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MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
133 MHz 150 MHz 166 MHz
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
133 MHz 150 MHz 166 MHz
Maximum Operating Frequency Support for MMX Technology Compatible with Large Software Base MS-DOS, Windows, OS / 2, UNIX 32-Bit CPU with 64-Bit Data Bus Superscalar Architecture Enhanced pipelines Two Pipelined Integer Units Capable of 2 Instructions / Clock Pipelined MMX Unit Pipelined Floating-Point Unit Separate Code and Data Caches 16-Kbyte Code, 16-Kbyte Write Back Data MESI Cache Protocol Low Voltage CMOS Silicon Technology 4-Mbyte Pages for Increased TLB Hit Rate
Advanced Design Features Deeper Write Buffers Enhanced Branch Prediction Feature Virtual Mode Extensions IEEE 1149.1 Boundary Scan Voltage Reduction Technology 2.45 VCC for core supply Internal Error Detection Features Power Management Features System Management Mode Clock Control Fractional Bus Operation 133-MHz Core / 66-MHz Bus 150-MHz Core / 60-MHz Bus 166-MHz Core / 66-MHz Bus
June 1997
Order Number: 243292-004
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
CONTENTS
PAGE 1.0. MICROPROCESSOR ARCHITECTURE OVERVIEW .......................... 4 2.0. MICROPROCESSOR ARCHITECTURE OVERVIEW .......................... 4 2.1. Mobile Pentium ® Processor Family Architecture ........................ 5 2.2. Mobile Pentium ® Processor with MMX Technology ......................... 7 2.3.1. Full support for Intel MMX technology ...................... 7 2.3.2. Doubled code and data caches to 16K each........................... 7 2.3.3. Improved branch prediction ......... 7 2.3.4. Enhanced pipeline ................ 8 3.0. MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY PINOUT .......... 8 3.1. Mobile Differences from Desktop ........ 8 3.2. TCP Pinout and Pin Descriptions ........ 9 3.2.1. TCP MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY PINOUT ........... 9 3.2.2. TCP MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY PIN CROSS REFERENCE ................... 10 3.3. PPGA Package ..................... 17 3.3.1. PPGA Pin Diagrams .............. 17 3.3.2 PPGA MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY PIN CROSS REFERENCE ................... 19 3.4. Design Notes ...................... 22 3.5. Quick Pin Reference ................. 22 3.6. Bus Frequency ..................... 30 PAGE 3.7. Pin Reference Tables ................ 31 3.8. Pin Grouping According to Function ..... 34 4.0. ELECTRICAL SPECIFICATIONS ........ 35 4.1. Maximum Ratings ................... 35 4.2. DC Specifications ................... 35 4.2.1. POWER SEQUENCING ........... 35 4.3. AC Specifications ................... 38 4.3.1. POWER AND GROUND .......... 38 4.3.2. DECOUPLING RECOMMENDATIONS 38 4.3.3. CONNECTION SPECIFICATIONS ... 39 4.3.4. AC TIMINGS FOR A 60-MHZ BUS .. 39 4.3.5. AC TIMINGS FOR A 66-MHZ BUS .. 45 4.4. I / O Buffer Models ................... 54 4.4.1. BUFFER MODEL PARAMETERS ... 57 4.4.2. SIGNAL QUALITY SPECIFICATIONS 60 CLOCK SIGNAL MEASUREMENT METHODOLOGY ................ 64 5.0. MECHANICAL SPECIFICATIONS ........ 66 5.1. TCP Mechanical Diagrams ............ 67 5.2. Plastic Pin Grid Array (PPGA) .......... 73 6.0. THERMAL SPECIFICATIONS ........... 75 6.1. Measuring Thermal Values for TCP ..... 75 6.1.1. TCP Thermal Equations ........... 75 6.1.2. TCP Thermal Characteristics ....... 75 6.1.3. TCP PC Board Enhancements ...... 75 6.1.3.1. TCP STANDARD TEST BOARD CONFIGURATION ............... 76 6.2. Measuring Thermal Values For PPGA ... 77 6.2.1. THERMAL EQUATIONS AND DATA . 78
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
2.0. 1.0. MICROPROCESSOR ARCHITECTURE OVERVIEW
MICROPROCESSOR ARCHITECTURE OVERVIEW
The mobile Pentium® processor with MMX technology is functionally similar to the mobile Pentium processor with voltage reduction technology (75-150) with the following differences: voltage supplies, maximum bus and core frequency and performance. This processor is socket compatible with the mobile Pentium processor voltage reduction technology (75-150) making it possible to design a flexible motherboard that supports both the mobile Pentium processor (75-150) and the mobile Pentium processor with MMX technology. It has all the advanced features of the desktop version of the Pentium processor with MMX technology except for the differences listed in Section 3.1. The mobile Pentium processor with MMX technology has several features which allow highperformance notebooks to be designed, including the following: · · · TCP dimensions are ideal for small form-factor designs. TCP has superior thermal resistance characteristics. 2.45V core and 3.3V I / O buffer VCC inputs reduce power consumption significantly, while maintaining 3.3V compatibility externally. The SL Enhanced feature set
The mobile Pentium processor with MMX technology extends the mobile Pentium family of microprocessors. It is binary compatible with the 8086 / 88, 80286, Intel386 DX, Intel386 SX, Intel486 DX, Intel486 SX, Intel486 DX2 and mobile Pentium processors with voltage reduction technology (75-150). The mobile Pentium processor family consists of the mobile Pentium processor with MMX technology described in this document and the mobile Pentium processor with voltage reduction technology (75-150). The mobile Pentium processor with MMX technology contains all of the features of previous Intel Architecture and provides significant enhancements and additions including the following: · · · · · · · · · · · · · · · · · · · Support for MMX Technology Superscalar Architecture Enhanced Branch Prediction Algorithm Pipelined Floating-Point Unit Improved Instruction Execution Time Separate 16K Code and 16K Data Caches Writeback MESI Protocol in the Data Cache 64-Bit Data Bus Enhanced Bus Cycle Pipelining Address Parity Internal Parity Checking Execution Tracing Performance Monitoring IEEE 1149.1 Boundary Scan System Management Mode Virtual Mode Extensions Voltage Reduction Technology SL Power Management Features Pool of four write buffers used by both pipes
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
Mobile Pentium ® Processor Family Architecture
The application instruction set of the mobile Pentium processor family includes the complete Intel486 CPU family instruction set with extensions to accommodate some of the additional functionality of the Pentium processors. All application software written for the Intel386 and Intel486 family microprocessors will run on the Pentium processors without modification. The onchip memory management unit (MMU) is completely compatible with the Intel386 and Intel486 families of processors. The Pentium processors implement several enhancements to increase performance. The two instruction pipelines and floating-point unit on Pentium processors are capable of independent operation. Each pipeline issues frequently used instructions in a single clock. Together, the dual pipes can issue two integer instructions in one clock, or one floating-point instruction (under certain circumstances, two floating-point instructions) in one clock. Branch prediction is implemented in the Pentium processors. To support this, Pentium processors implement two prefetch buffers, one to prefetch code in a linear fashion, and one that prefetches code according to the Branch Target Buffer (BTB) so the needed code is almost always prefetched before it is needed for execution. The floating-point unit has been completely redesigned over the Intel486 processor. Faster algorithms provide up to 10X speed-up for common operations including add, multiply and load. Pentium processors include separate code and data caches integrated on-chip to meet performance goals. Each cache has a 32-byte line size and is 2-way set associative. Each cache has a dedicated Translation Lookaside Buffer (TLB) to translate linear addresses to physical addresses. The data cache is configurable to be writeback or writethrough on a line-by-line basis and follows the MESI protocol. The data cache tags are triple ported to support two data transfers and an inquire cycle in the same clock. The code cache is an inherently write-protected cache. The code cache tags are also triple ported to support snooping and split line accesses. Individual pages can be configured as cacheable or non-cacheable by software or hardware. The caches can be enabled or disabled by software or hardware.
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
The separate code and data caches are shown, . The data cache has two ports, one for each of the two pipes (the tags are triple ported to allow simultaneous inquire cycles). The data cache has a dedicated Translation Lookaside Buffer (TLB) to translate linear addresses to the physical addresses used by the data cache.
TLB Branch Prefetch Code Cache Target 16 KBytes Buffer Address
Instruction Pointer
Branch Verif. & Target Addr
64-Bit Data Bus
Prefetch Buffers Instruction Decode
Control ROM
Control Unit
V-Pipeline Connection
32-Bit Address Bus
Bus Unit
Page Unit Generate
(U Pipeline) Address
U-Pipeline Connection
Floating Point Unit Control Register File
Address Generate
(V Pipeline)
MMX Unit
Control Integer Register File ALU ALU
(V Pipeline)
Divide
(U Pipeline)
Multiply
Barrel Shifter
64-Bit Data Bus
32-Bit Addr. Bus
Data Cache 16 KBytes TLB
PP0115
Figure 1. Mobile Pentium ® Processor with MMX Technology Block Diagram
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
CMOS process which allows voltage reduction technology for low power and high density. This enables the mobile Pentium processor with MMX technology to remain within the thermal envelope while providing a significant performance increase. In addition to the architecture described in the previous section for the mobile Pentium processor family, the mobile Pentium processor with MMX technology has several additional microarchitectural enhancements, which are described below: 2.3.1. Full support for Intel MMX
technology
MMX technology is based on SIMD technique (Single Instruction, Multiple Data) which enables increased performance on a wide variety of multimedia and communications applications. Fiftyseven new instructions and four new 64-bit data types are supported in the mobile Pentium processor with MMX technology. All existing operating system and application software are fullycompatible. 2.3.2. Doubled code and data caches to 16K each On-chip level-1 data and code cache sizes have been doubled to 16KB each and are 4-way set associative on the mobile Pentium processor with MMX technology. Larger separate internal caches improve performance by reducing average memory access time and providing fast access to recentlyused instructions and data. The instruction and data caches can be accessed simultaneously while the data cache supports two data references simultaneously. The data cache supports a writeback (or alternatively, write-through, on a line by line basis) policy for memory updates. 2.3.3. Improved branch prediction Dynamic branch prediction uses the Branch Target Buffer (BTB) to boost performance by predicting the most likely set of instructions to be executed. The BTB has been improved on the mobile Pentium processor with MMX technology to increase its accuracy. Further, this processor has four prefetch buffers that can hold up to four successive code streams.
Mobile Pentium ® Processor with MMX Technology
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY PINOUT Mobile Differences from Desktop
To better streamline the part for mobile applications, the following features have been eliminated: Upgrade, Dual Processing (DP), APIC and Master / Checker functional redundancy. Table 1 lists the corresponding pins which exist on the desktop Pentium processor with MMX technology but have been removed on the mobile Pentium processor with MMX technology.
Table 1. Signals Removed in Mobile Pentium Signal ADSC#
Processor with MMX Technology Function
BRDYC#
CPUTYP D / P# FRCMC# PBGNT# PBREQ# PHIT# PHITM# PICCLK PICD0 DPEN# PICD1 APICEN
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
TCP Pinout and Pin Descriptions
this section is not the actual text which will be marked on the packages). 3.2.1. TCP MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY PINOUT
The text orientation on the top side view drawings in this section represent the orientation of the ink mark on the actual packages (Note that the text shown in
Figure 2. TCP Mobile Pentium ® Processor with MMX Technology Pinout 9
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
3.2.2. TCP MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY PIN CROSS REFERENCE Table 2. TCP Pin Cross Reference by Pin Name Address A3 A4 A5 A6 A7 A8 219 222 223 227 228 231 A9 A10 A11 A12 A13 A14 234 237 238 242 245 248 A15 A16 A17 A18 A19 A20 Data D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 152 151 150 149 146 145 144 143 139 138 137 134 133 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 132 131 128 126 125 122 121 120 119 116 115 113 108 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 107 106 105 102 101 100 96 95 94 93 90 89 88 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 87 83 82 81 78 77 76 75 72 70 69 64 63 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 62 61 56 55 53 48 47 46 45 40 39 38 251 254 255 259 262 265 A21 A22 A23 A24 A25 A26 200 201 202 205 206 207 A27 A28 A29 A30 A31 208 211 212 213 214
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
Table 2. TCP Pin Cross Reference by Pin Name (Contd.) Control A20M# ADS# AHOLD AP APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BP2 BP3 BRDY# 286 296 14 308 315 285 284 283 282 279 278 277 276 9 28 25 10 BREQ BUSCHK# CACHE# D / C# DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 EADS# EWBE# FERR# FLUSH# HIT# 312 288 21 298 140 127 114 99 84 71 54 37 297 16 31 287 292 Clock Control BF0 BF1 CLK STPCLK# 186 185 272 181 HITM# HLDA HOLD IERR# IGNNE# INIT INTR / LINT0 INV KEN# LOCK# M / IO# NA# NMI / LINT1 PCD PCHK# PEN# 293 311 4 34 193 192 197 15 13 303 22 8 199 300 316 191 PM0 / BP0 PM1 / BP1 PRDY PWT R / S# RESET SCYC SMI# SMIACT# TCK TDI TDO TMS TRST# W / R# WB / WT# 30 29 318 299 198 270 273 196 319 161 163 162 164 167 289 5
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
Table 2. TCP Pin Cross Reference by Pin Name (Contd.) VCC21 1 6 11 17 27 33 41 49 57 65 111 153 157 165 168 170 172 174 177 180 VCC32 2 19 23 35 43 51 59 67 73 79 85 91 97 103 109 117 123 129 135 141 147 160 178 204 210 216 221 226 230 236 241 247 253 258 264 275 281 291 295 301 306 313 183 188 190 195 217 225 232 240 243 249 257 260 266 268 304 309 317
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
Table 2. TCP Pin Cross Reference by Pin Name (Contd.) VSS 3 7 12 18 20 24 26 32 36 42 44 50 52 58 60 66 68 74 80 86 92 98 104 110 112 118 124 130 136 142 148 154 159 166 169 171 NC 155 156 158 175 184 271 173 176 179 182 187 189 194 203 209 215 218 220 224 229 233 235 239 244 246 250 252 256 261 263 267 269 274 280 290 294 302 305 307 310 314 320
NOTE: 1. These VCC2 pins are 2.45V inputs to the core, but may change to a different voltage on future offerings of this microprocessor family. 2. All V CC3 pins are 3.3V I / O power inputs.
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
Table 3. TCP Pin Cross References by Pin Number (Pins 1-160) Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 14 Signal VCC2 VCC3 VSS HOLD WB / WT# VCC2 VSS NA# BOFF# BRDY# VCC2 VSS KEN# AHOLD INV EWBE# VCC2 VSS VCC3 VSS CACHE# M / IO# V CC3 VSS BP3 VSS VCC2 BP2 PM1 / BP1 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 Pin # Signal V CC2 VSS VCC3 VSS D60 D59 D58 D57 VCC2 VSS VCC3 VSS D56 DP6 D55 D54 VCC2 VSS VCC3 VSS D53 D52 D51 D50 VCC2 VSS VCC3 VSS D49 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 Pin # Signal D42 D41 D40 DP4 VCC3 VSS D39 D38 D37 D36 VCC3 VSS D35 D34 D33 D32 VCC3 VSS DP3 D31 D30 D29 V CC3 VSS D28 D27 D26 D25 V CC3 Pin # 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 Signal D19 D18 VCC3 VSS D17 D16 DP1 D15 VCC3 VSS D14 D13 D12 D11 VCC3 VSS D10 D9 D8 DP0 VCC3 VSS D7 D6 D5 D4 V CC3 VSS D3
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
Table 3. TCP Pin Cross References by Pin Number (Pins 1-160) Pin # 30 31 32 33 34 35 36 37 38 39 40 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 Signal PM0 / BP0 FERR# VSS VCC2 IERR# VCC3 VSS DP7 D63 D62 D61 TCK TDO TDI TMS VCC2 VSS TRST# VCC2 VSS V CC2 VSS V CC2 VSS V CC2 NC VSS V CC2 VCC3 VSS 70 71 72 73 74 75 76 77 78 79 80 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 Pin # Signal D48 DP5 D47 VCC3 VSS D46 D45 D44 D43 VCC3 VSS A22 A23 VSS V CC3 A24 A25 A26 A27 VSS VCC3 A28 A29 A30 A31 VSS V CC3 V CC2 VSS A3 Pin # 110 111 112 113 114 115 116 117 118 119 120 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 Signal VSS VCC2 VSS D24 DP2 D23 D22 VCC3 VSS D21 D20 V CC3 A12 VCC2 VSS A13 VSS VCC3 A14 VCC2 VSS A15 VSS V CC3 A16 A17 VSS V CC2 V CC3 A18 Pin # 150 151 152 153 154 155 156 157 158 159 160 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 Signal D2 D1 D0 VCC2 VSS NC NC VCC2 NC VSS VCC3 VCC3 BE3# BE2# BE1# BE0# A20M# FLUSH# BUSCHK# W / R# VSS V CC3 HIT# HITM# VSS V CC3 ADS# EADS# D / C# PWT 15
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
Table 3. TCP Pin Cross References by Pin Number (Pins 1-160) Pin # 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Signal V CC2 STPCLK# VSS VCC2 NC BF1 BF0 VSS V CC2 VSS V CC2 PEN# INIT IGNNE# VSS V CC2 SMI# Pin # 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 Signal VSS VCC3 A4 A5 VSS V CC2 V CC3 A6 A7 VSS V CC3 A8 V CC2 VSS A9 VSS V CC3 A10 A11 VSS V CC2 Pin # 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 Signal V CC2 VSS A19 VSS V CC3 A20 V CC2 VSS V CC2 VSS RESET NC CLK SCYC VSS V CC3 BE7# BE6# BE5# BE4# VSS Pin # 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 Signal PCD V CC3 VSS LOCK# V CC2 VSS V CC3 VSS AP V CC2 VSS HLDA BREQ V CC3 VSS APCHK# PCHK# V CC2 PRDY SMIACT# VSS
INTR / LINT0 237 R / S# NMI / LINT1 A21 238 239 240
NOTE: 1. VCC2 pins are 2.45V inputs to the core. 2. VCC3 pins are 3.3V inputs to the I / O.
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
PPGA Package
The text orientation on the top side view drawings in this section represent the orientation of the ink 3.3.1. PPGA Pin Diagrams
mark on the actual packages (Note that the text shown in this section is not the actual text which will be marked on the packages).
NOTE All INC and NC pins must remain unconnected. Connection of NC pins may result in component failure or incompatibility with processor steppings.
Figure 3. Mobile Pentium ® Processor with MMX Technology Pinout Top Side View 17
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
NOTE All INC and NC pins must remain unconnected. Connection of NC pins may result in component failure or incompatibility with processor steppings.
Figure 4. Mobile Pentium® Processor with MMX Technology Pinout Pin Side View
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
3.3.2 PPGA MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY PIN CROSS REFERENCE Table 4. PPGA Pin Cross Reference by Pin Name Address A3 A4 A5 A6 A7 A8 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 AL35 AM34 AK32 AN33 AL33 AM32 K34 G35 J35 G33 F36 F34 E35 E33 D34 C37 C35 B36 D32 A9 A10 A11 A12 A13 A14 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 AK30 AN31 AL31 AL29 AK28 AL27 B34 C33 A35 B32 C31 A33 D28 B30 C29 A31 D26 C27 C23 A15 A16 A17 A18 A19 A20 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 AK26 AL25 AK24 AL23 AK22 AL21 Data D24 C21 D22 C19 D20 C17 C15 D16 C13 D14 C11 D12 C09 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D10 D08 A05 E09 B04 D06 C05 E07 C03 D04 E05 D02 F04 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 E03 G05 E01 G03 H04 J03 J05 K04 L05 L03 M04 N03 A21 A22 A23 A24 A25 A26 AF34 AH36 AE33 AG35 AJ35 AH34 A27 A28 A29 A30 A31 AG33 AK36 AK34 AM36 AJ33
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
Table 4. PPGA Pin Cross Reference by Pin Name (Contd.) Control A20M# ADS# AHOLD AP APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BP2 BP3 BRDY# AK08 AJ05 V04 AK02 AE05 AL09 AK10 AL11 AK12 AL13 AK14 AL15 AK16 Z04 S03 S05 X04 BREQ BUSCHK# CACHE# D / C# DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 EADS# EWBE# FERR# FLUSH# HIT# AJ01 AL07 U03 AK04 D36 D30 C25 D18 C07 F06 F02 N05 AM04 W03 Q05 AN07 AK06 HITM# HLDA HOLD IERR# IGNNE# INIT INTR INV KEN# LOCK# M / IO# NA# NMI PCD PCHK# PEN# PM0 / BP0 Clock Control CLK BF0 BF1 STPCLK# AK18 Y33 X34 V34 AL05 AJ03 AB04 P04 AA35 AA33 AD34 U05 W05 AH04 T04 Y05 AC33 AG05 AF04 Z34 Q03 PM1 / BP1 R / S# PRDY PWT RESET SCYC SMI# SMIACT# TCK TDI TDO TMS TRST# VCC2DET# W / R# WB / WT# R04 AC35 AC05 AL03 AK20 AL17 AB34 AG03 M34 N35 N33 P34 Q33 AL01 AM06 AA05
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
Table 4. PPGA Pin Cross Reference by Pin Name (Contd.) VCC21 A17 A15 A13 A11 A09 A19 A21 A23 A25 A27 A29 E37 G37 A07 G01 J01 L01 N01 J37 L37 L33 N37 Q01 S01 U01 W01 Y01 VCC32 Q37 S37 T34 U33 VSS B06 B08 B10 B12 B14 B16 B18 B20 B22 B24 B26 B28 A37 H34 J33 L35 Q35 R34 S33 A03 B02 H02 H36 K02 K36 M02 M36 P02 P36 R02 R36 T02 T36 S35 Y03 Y35 W33 W35 AA03 AC03 INC C01 AN01 AN03 AN05
NOTE: 1. These VCC2 pins are 2.45V inputs to the core, but may change to a different voltage on future offerings of this microprocessor family. 2. All V CC3 pins are 3.3V power inputs to the I / O.
AA01 AC01 AE01 AG01 AN09 U37 W37 Y37 AA37 AC37 AE37 AG37 AN29
AN11 AN13 AN15 AN17 AN19 AN27 AN25 AN23 AN21
U35 V02 V36 X02 X36 Z02 NC
Z36 AB02 AB36 AD02 AD36 AF02
AF36 AH02 AJ37 AL37 AM08 AM10
AM12 AM14 AM16 AM18 AM20 AM22 AD04 AE03 AE35 AL01 AL19 AM02 AN35
AM24 AM26 AM28 AM30 AN37
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
Design Notes
For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to VCC3. Unused active HIGH inputs should be connected to GND (VSS). No Connect (NC) pins must remain unconnected. Connection of NC and INC pins may result in component failure or incompatibility with processor steppings.
Quick Pin Reference
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
A31-A3
ADS# AHOLD
APCHK#
BE7#-BE5# BE4#-BE0# BF0:1
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
BRDY#
BUSCHK#
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
DP7-DP0
EADS# EWBE#
FERR#
FLUSH#
HITM#
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
IERR#
IGNNE#
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
NMI PCD
PCHK#
PM / BP1:0
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
RESET
SMIACT# STPCLK#
TMS TRST# VCC2
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
Table 5. Quick Pin Reference (Contd.) Symbol VCC3 VCCDET# VSS W / R# Type I O I O Name and Function These pins are the 3.3V power inputs to the I / O. VCC2 detect is used in flexible motherboard implementations to configure the voltage output set-point appropriately for the VCC2 inputs of the processor. 1 These pins are the ground inputs. Write / read is one of the primary bus cycle definition pins. It is driven valid in the same clock as the ADS# signal is asserted. W / R# distinguishes between write and read cycles. The writeback / writethrough input allows a data cache line to be defined as writeback or writethrough on a line-by-line basis. As a result, it determines whether a cache line is initially in the S or E state in the data cache.
NOTE: 1. Only in PPGA package.
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
Bus Frequency
Core and bus frequencies can be set according to Table 6 below. Each mobile Pentium processor with MMX technology specified to operate within a single bus-to-core ratio and a specific minimum to
maximum bus frequency range (corresponding to a minimum to maximum core frequency range). Operation in other bus-to-core ratios or outside the specified operating frequency range is not supported.
Table 6. Bus Frequency Selections BF1 0 0 1 1 BF0 0 1 0 1 Bus / Core Ratio 2 / 5 1 / 32 1 / 2 1 Reserved Max Bus / Core Frequency (MHz) 60 / 150 66 / 166 N / A2 66 / 133 Reserved Min Bus / Core Frequency (MHz) 30 / 75 33 / 83 N / A2 33 / 66 Reserved
NOTES: 1. This is the default bus to core ratio for the mobile Pentium ® processor with MMX technology. If the BF pins are left floating, the processor will be configured for the 1 / 2 bus to core frequency ratio. 2. This bus ratio is currently not supported in mobile Pentium processors.
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
Pin Reference Tables
Table 7. Output Pins 1 Name Active Level Low Low Low High Low Low Low Low High Low Low n / a Low High High High High Low n / a All states except Shift-DR and Shift-IR Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# When Floated Bus Hold, BOFF#
ADS# APCHK# BE7#-BE4# BREQ CACHE# FERR# HIT# HITM# 2 HLDA IERR# LOCK# M / IO#, D / C#, W / R# PCHK# BP3-2, PM1 / BP1, PM0 / BP0 PRDY PWT, PCD SCYC SMIACT# TDO
NOTE: 1. All output and input / output pins are floated during tristate test mode (except TDO). 2. HITM# pin has an internal pull-up resistor.
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
Table 8. Input Pins Name A20M# AHOLD BF0 BF1 BOFF# BRDY# BUSCHK# CLK EADS# EWBE# FLUSH# HOLD IGNNE# INIT INTR INV KEN# NA# NMI PEN# R / S# RESET SMI# STPCLK# TCK TDI TMS TRST# WB / WT# Active Level LOW HIGH HIGH HIGH LOW LOW LOW n / a LOW LOW LOW HIGH LOW HIGH HIGH HIGH LOW LOW HIGH LOW n / a HIGH LOW LOW n / a n / a n / a LOW n / a Synchronous / TCK Synchronous / TCK Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Pullup Pullup Pullup Pullup Pullup Pullup First BRDY# / NA# TCK TCK Pullup BRDY# EADS# First BRDY# / NA# Bus State T2, TD, T2P BRDY# Synchronous / Asynchronous Asynchronous Synchronous Synchronous / RESET Synchronous / RESET Synchronous Synchronous Synchronous Pullup Pullup Bus State T2, T12, T2P BRDY# PullDown Pullup Internal resistor Qualified
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Table 9. Input / Output Pins 1 Name A31-A3 AP BE3#-BE0# D63-D0 DP7-DP0 Active Level n / a n / a Low n / a n / a When Floated Address Hold, Bus Hold, BOFF# Address Hold, Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Qualified (when an input) EADS# EADS# RESET BRDY# BRDY# Pulldown 2 Internal Resistor
NOTES: 1. All output and input / output pins are floated during tristate test mode (except TDO). 2. BE3#-BE0# have pulldowns during RESET only.
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
Pin Grouping According to Function
Table 10 organizes the pins with respect to their function. Table 10. Pin Functional Grouping Function Clock Initialization Address Bus Address Mask Data Bus Address Parity Data Parity Internal Parity Error System Error Bus Cycle Definition Bus Control Page Cacheability Cache Control Cache Snooping / Consistency Cache Flush Write Ordering Bus Arbitration Interrupts Floating-point Error Reporting System Management Mode TAP Port Breakpoint / Performance Monitoring Clock Control Debugging CLK RESET, INIT, BF1:0 A31-A3, BE7# - BE0# A20M# D63-D0 AP, APCHK# DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M / IO#, D / C#, W / R#, CACHE#, SCYC, LOCK# ADS#, BRDY#, NA# PCD, PWT KEN#, WB / WT# AHOLD, EADS#, HIT#, HITM#, INV FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA INTR, NMI FERR#, IGNNE# SMI#, SMIACT# TCK, TMS, TDI, TDO, TRST# PM0 / BP0, PM1 / BP1, BP3-2 STPCLK# R / S#, PRDY Pins
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ELECTRICAL SPECIFICATIONS Maximum Ratings
WARNING Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
The following values are stress ratings only. Functional operation at the maximum ratings is not implied nor guaranteed. Functional operating conditions are given in the AC and DC specification tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the mobile Pentium processor with MMX technology contains protective circuitry to resist damage from Electrostatic Discharge (ESD), always take precautions to avoid high static voltages or electric fields. Case temperature under bias ..... -65° to 110° C C Storage temperature............ -65° to 150° C C VCC3 Supply voltage with respect to V SS ............. -0.5V to +4.6V VCC2 Supply voltage with respect to V SS ............. -0.5V to +3.7V 3V Only Buffer DC Input Voltage ................... -0.5V to V CC3 and +0.5V not to exceed V
DC Specifications
Tables 11, 12 and 13 list the DC specifications which apply to the mobile Pentium processor with MMX technology. The processor core operates at 2.45V internally while the I / O interface operates at 3.3V. 4.2.1. POWER SEQUENCING
There is no specific sequence required for powering up or powering down the VCC2 and VCC3 power supplies. However, for compatibility with future mobile processors, it is recommended that the VCC2 and VCC3 power supplies be either both ON or both OFF within one second of each other.
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Table 12. 3.3V DC Specifications 1 Symbol VIL3 VIH3 VOL3 VOH3 Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 2.4 Min -0.3 2.0 Max 0.8 VCC3 +0.3 0.4 Unit V V V V Notes TTL Level 5 TTL Level 4 TTL Level 2 TTL Level 3
NOTES: 1. See Table 11 for V CC and TCASE assumptions. 2. Parameter measured at -4 mA. 3. Parameter measured at 3 mA. 4. Parameter measured at nominal V CC3 which is 3.3V. 5. VIL3, max for TCK is 0.6V.
Table 13. ICC Specifications Symbol ICC2 Parameter Power Supply Current Min Max 3.3 3.7 4.1 0.4 0.37 0.4 Unit A A A A A A Notes 133 MHz 1 150 MHz 1 166MHz1 133 MHz 1 150 MHz 1 166 MHz 1
Power Supply Current
NOTE: 1. This value should be used for power supply design. It was determined using a worst case instruction mix an d maximum VCC. Power supply transient response and decoupling capacitors must be sufficient to handle the instantaneous current changes occurring during transitions from Stop Clock to full Active modes.
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Table 14. Power Dissipation Requirements for Thermal Design Parameter Thermal Design Power Typical 1 N / A Max2 7.8 8.6 9.0 N / A Unit Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts Frequency 133 MHz 150 MHz 166 MHz 133 MHz 150 MHz 166 MHz 133 MHz 150 MHz 166 MHz 133 MHz 150 MHz 166 MHz Notes 6, 7
Active Power
Stop Grant / Auto Halt Power
Stop Clock Power
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NOTES: 1. This parameter is for inputs / outputs without an internal pull up or pull down. 2. This parameter is for inputs with an internal pull up. 3. This parameter is for inputs with an internal pull down. 4. Guaranteed by design. 5. This specification applies to the HITM# pin when it is driven as an input (e.g., in JTAG mode).
AC Specifications
DECOUPLING RECOMMENDATIONS
The AC specifications of the mobile Pentium processor with MMX technology consist of setup times, hold times, and valid delays at 0 pF. 4.3.1. POWER AND GROUND
Transient power surges can occur as the processor is executing instruction sequences or driving large loads. To mitigate these high frequency transients, liberal high frequency decoupling capacitors should be placed near the processor. Low inductance capacitors and interconnects are recommended for best high frequency electrical performance. Inductance can be reduced by shortening circuit board traces between the processor and decoupling capacitors as much as possible. These capacitors should be evenly distributed around each component on the power plane. Capacitor values should be chosen to ensure they eliminate both low and high frequency noise components. Power transients also occur as the processor rapidly transitions from a low level of power consumption to a much higher level (or high to low power). A typical example would be entering or
For clean on-chip power distribution, the TCP mobile Pentium processor with MMX technology has 37 VCC2 (core power), 42 VCC3 (3.3V power) and 72 VSS (ground) inputs. The PPGA mobile Pentium processor with MMX technology has 28 VCC3 (I / O power), 25 VCC2 (core power) and 53 VSS (ground) inputs. Power and ground connections must be made to all external V CC2, V CC3 and VSS pins. On the circuit board all VCC2 pins must be connected to a 2.45V V CC2 plane (or island) and all VCC3 pins must be connected to a 3.3V V CC3 plane. All VSS pins must be connected to a VSS plane. Please refer to Table 2 for the list of VCC2, VCC3 and VSS pins.
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exiting the Stop Grant state. Another example would be executing a HALT instruction, causing the processor to enter the Auto HALT Powerdown state, or transitioning from HALT to the Normal state. All of these examples may cause abrupt changes in the power being consumed by the processor. Note that the Auto HALT Powerdown feature is always enabled even when other power management features are not implemented. Bulk storage capacitors with a low ESR (Effective Series Resistance) in the 10 to 100 µ range are f required to maintain a regulated supply voltage during the interval between the time the current load changes and the point that the regulated power supply output can react to the change in load. In order to reduce the ESR, it may be necessary to place several bulk storage capacitors in parallel. These capacitors should be placed near the processor (on the 3.3V plane and the 2.45V plane) to ensure that the supply voltages stay within specified limits during changes in the supply current during operation. For more detailed information, please contact Intel or refer to the Mobile Pentium® Processor with MMX Technology: Power Supply Design Considerations application note (Order Number 243306). 4.3.3. CONNECTION SPECIFICATIONS
All NC pins must remain unconnected. For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to VCC3. Unused active high inputs should be connected to ground. 4.3.4. AC TIMINGS FOR A 60-MHZ BUS
The AC specifications given in Table 16 consists of output delays, input setup requirements and input hold requirements for a 60 MHz external bus. All AC specifications (with the exception of those for the TAP signals and APIC signals) are relative to the rising edge of the CLK input. All timings are referenced to 1.5V for both "0" and "1" logic levels unless otherwise specified. Within the sampling window, a synchronous input must be stable for correct operation. Each valid delay is specified for a 0 pF load. The system designer should use I / O buffer modeling to account for signal flight time delays. Do not select a bus fraction and clock speed which will cause the processor to exceed its internal maximum frequency.
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t6b t6c t6e
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
t8a t8b t9a t9b t10a t10b t11a t11b t12 t13 t14 t15 t16a t16b t17 t18a t18b t19 t20 t21 t22 t23 t24
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
t43a t43b t43c t43d t44 t45 t46 t47 t48 t49 t50 t51 t52 t53 t54 t55 t56 t57 t58
mS CLKs CLKs CLKs MHz nS nS nS nS nS nS nS nS nS nS nS nS nS nS
5 5 5 5 5 11 10 10 10 10 10 10 10 10 at 2V, (1) at 0.6V, (1) (2.0V-0.6V), (1, 7, 8) (0.6V-2.0V), (1, 5, 6) (1), Asynchronous 4 4 5 1, 5 3, 5, 16 1, 3, 5, 16 3, 4, 16 3, 4, 16
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4.3.5. AC TIMINGS FOR A 66-MHZ BUS The AC specifications given in Table 17 consist of output delays, input setup requirements and input hold requirements for a 66 MHz external bus. All AC specifications (with the exception of those for the TAP signals and APIC signals) are relative to the rising edge of the CLK input.
All timings are referenced to 1.5V for both "0" and "1" logic levels unless otherwise specified. Within the sampling window, a synchronous input must be stable for correct operation. Each valid delay is specified for a 0 pF load. The system designer should use I / O buffer modeling to account for signal flight time delays. Do not select a bus fraction and clock speed which will cause the processor to exceed its internal maximum frequency.
t6b t6c t6d t6e t6f t7
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MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
t43a t43b t43c t43d t44 t45 t46 t47 t48 t49 t50 t51 t52 t53 t54 t55 t56 t57 t58
mS CLKs CLKs CLKs MHz nS nS nS nS nS nS nS nS nS nS nS nS nS nS
5 5 5 5 5 1 10 10 10 10 10 10 10 10 2V(1) 0.6V(1) (2.0V- 0.6V) (1, 5, 6) (0.6V- 2.0V) (1, 5, 6) Asynchronous(1) 4 4 5 1, 5 3, 5, 7 1, 3, 5, 7 3, 4, 7 3, 4, 7
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MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
Figure 5. Clock Waveform
V ALID
P P0052
Figure 6. Valid Delay Timings
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S ignal
PP0053
Figure 7. Float Delay Timings
S ignal
VA LID
Figure 8. Setup and Hold Timings
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R ESET
C onfig
VA LID
PP0055
Figure 9. Reset and Configuration Timings
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Figure 10. Test Timings
Figure 11. Test Reset Timings
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I / O Buffer Models
The following model represents the input buffer model. Figure 12 represents all of the input buffers. In addition to the input and output buffer parameters, input protection diode models are provided for added accuracy. These diodes have been optimized to provide ESD protection and provide some level of clamping. Although the diodes are not required for simulation, it may be more difficult to meet specifications without them. Note, however, some signal quality specifications require that the diodes be removed from the input model. The series resistors (RS) are a part of the diode model. Remove these when removing the diodes from the input model. Figure 13 shows the structure of the output buffer model. This model is used for all of the output buffers of the mobile Pentium processor with MMX technology.
This section describes the I / O buffer models of the mobile Pentium processor with MMX technology. The first order I / O buffer model is a simplified representation of the complex input and output buffers used. Figure 12 shows the structure of the input buffer model and Figure 13 shows the output buffer model. Tables 18 and 19 show the parameters used to specify these models. Although simplified, these buffer models will accurately model flight time and signal quality. For these parameters, there is very little added accuracy in a complete transistor model. NOTE: CLK is not 5V tolerant. It is 3.3V tolerant only.
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Figure 12. Input Buffer Model
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Table 18. Parameters Used in the Specification of the First Order Input Buffer Model Parameter Cin Lp Cp Rs D1, D2 Description Minimum and Maximum value of the capacitance of the input buffer model Minimum and Maximum value of the package inductance Minimum and Maximum value of the package capacitance Diode Series Resistance Ideal Diodes
PP0061
Figure 13. First Order Output Buffer Model
Table 19. Parameters Used in the Specification of the First Order Output Buffer Model Parameter dV / dt RO CO LP CP Description Minimum and maximum value of the rate of change of the open circuit voltage source used in the output buffer model Minimum and maximum value of the output impedance of the output buffer model Minimum and Maximum value of the capacitance of the output buffer model Minimum and Maximum value of the package inductance Minimum and Maximum value of the package capacitance
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BUFFER MODEL PARAMETERS
This section gives the parameters for each input, output and bidirectional buffers. The input, output and bidirectional buffer values of the processor are listed in Table 21. These tables contain listings for all three types, do not get them confused during simulation. When a bidirectional pin is operating as an input, use the CIN, CP and LP
Table 20. TCP Signal to Buffer Type Signals CLK A20M#, AHOLD, BF, BOFF#, BRDY#, BUSCHK#, EADS#, EWBE#, FLUSH#, HOLD, IGNNE#, INIT, INTR, INV, KEN#, NA#, NMI, PEN#, R / S#, RESET, SMI#, STPCLK#, TCK, TDI, TMS, TRST#, WB / WT# APCHK#, BE7:5#, BP3:2, BREQ, FERR#, IERR#, PCD, PCHK#, PM0 / BP0, PM1 / BP1, PRDY, PWT, SMIACT#, TDO A31:21, AP, BE4:0#, CACHE#, D / C#, D63:0, DP8:0, HLDA, LOCK#, M / IO#, SCYC A20:3, ADS#, HITM#, W / R# HIT# Type I I Driver Buffer Type Receiver Buffer Type ER0 ER1
EB1 EB2 EB3
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Table 21. Input, Output and Bi-directional Buffer Model Parameters for TCP Buffer Type Transition dV / dt (V / nsec) Min ER0 (input) ER1 (input) ED1 Rising Falling Rising Falling Rising 3 / 3.0 3 / 2.8 3 / 3.0 3 / 2.8 3 / 3.0 3 / 2.8 3 / 3.0 3 / 2.8 3.7 / 0.9 3.7 / 0.8 3.7 / 0.9 3.7 / 0.8 3.7 / 0.9 3.7 / 0.8 3.7 / 0.9 3.7 / 0.8 21.6 17.5 21.6 17.5 21.6 17.5 21.6 17.5 53.1 50.7 53.1 50.7 53.1 50.7 53.1 50.7 Max RO (Ohms) Min Max CP (pF) Min 0.23 0.23 0.16 0.16 0.16 0.16 0.16 0.16 0.25 0.25 0.25 0.25 Max 0.23 0.23 0.38 0.38 0.40 0.40 0.36 0.36 0.43 0.43 0.25 0.25 Min 8.61 8.61 5.75 5.75 4.69 4.69 4.53 4.53 4.90 4.90 4.97 4.97 LP (nH) Max 8.61 8.61 10.22 10.22 10.68 10.68 9.21 9.21 8.51 8.51 4.97 4.97 CO / CIN (pF) Min 0.8 0.8 0.8 0.8 2.0 2.0 2.0 2.0 9.1 9.1 3.3 3.3 Max 1.2 1.2 1.2 1.2 2.6 2.6 2.6 2.6 9.7 9.7 3.9 3.9
(output) Falling EB1 (bidir) EB2 (bidir) EB3 (bidir) Rising Falling Rising Falling Rising Falling
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Table 22. Input, Output and Bi-directional Buffer Model Parameters for PPGA Package Buffer Type Transition dV / dt (V / nsec) Min ER0 (input) ER1 (input) ED1 (output) EB1 (bidir) EB2 (bidir) EB3 (bidir) Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling 3 / 3.0 3 / 2.8 3 / 3.0 3 / 2.8 3 / 3.0 3 / 2.8 3 / 3.0 3 / 2.8 3.7 / 0.9 3.7 / 0.8 3.7 / 0.9 3.7 / 0.8 3.7 / 0.9 3.7 / 0.8 3.7 / 0.9 3.7 / 0.8 21.6 17.5 21.6 17.5 21.6 17.5 21.6 17.5 53.1 50.7 53.1 50.7 53.1 50.7 53.1 50.7 Max RO (Ohms) Min Max Min 3.0 3.0 1.1 1.1 1.1 1.1 1.3 1.3 1.3 1.3 1.9 1.9 CP (pF) Max 5.0 5.0 6.1 6.1 8.2 8.2 8.7 8.7 8.3 8.3 7.5 7.5 Min 4.0 4.0 4.7 4.7 4.0 4.0 4.0 4.0 4.4 4.4 9.9 9.9 LP (nH) Max 7.2 7.2 15.3 15.3 17.7 17.7 18.7 18.7 16.7 16.7 14.3 14.3 CO / CIN (pF) Min 0.8 0.8 0.8 0.8 2.0 2.0 2.0 2.0 9.1 9.1 3.3 3.3 Max 1.2 1.2 1.2 1.2 2.6 2.6 2.6 2.6 9.7 9.7 3.9 3.9
Table 23. Input Buffer Model Parameters: D (Diodes) Symbol IS N RS TT VJ CJ0 M Parameter Saturation Current Emission Coefficient Series Resistance Transit Time PN Potential Zero Bias PN Capacitance PN Grading Coefficient D1 1.4e-14A 1.19 6.5 ohms 3 ns 0.983V 0.281 pF 0.385 D2 2.78e-16A 1.00 6.5 ohms 6 ns 0.967V 0.365 pF 0.376
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Signals driven by the system into the mobile Pentium processor with MMX technology must meet signal quality specifications to guarantee that the components read data properly and to ensure that incoming signals do not affect the reliability of the component. There are two signal quality parameters: Ringback and Settling Time. See Section 4.4.2.3 for CLK signal quality specification. 4.4.2.1. Ringback
Excessive ringback can contribute to long-term reliability degradation of the mobile Pentium processor with MMX technology, and can cause false signal detection. Ringback is simulated at the input pin of a component using the input buffer model. Ringback can be simulated with or without the diodes that are in the input buffer model. Ringback is the absolute value of the maximum voltage at the receiving pin below VCC3 (or above VSS) relative to VCC3 (or VSS) level after the signal
Figure 14. Overshoot / Undershoot and Ringback Guidelines
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Settling Time
The settling time is defined as the time a signal requires at the receiver to settle within 10 percent of VCC3 or VSS. Settling time is the maximum time allowed for a signal to reach within 10 percent of its final value. Most available simulation tools are unable to simulate settling time so that it accurately reflects silicon measurements. On a physical board, second-order effects and other effects serve to dampen the signal at the receiver. Because of all these concerns, settling time is a recommendation or a tool for layout tuning and not a specification. Settling time is simulated at the slow corner, to make sure that there is no impact on the flight times of the signals if the waveform has not settled. Settling time may be simulated with the diodes included or excluded from the input buffer model. If diodes are included, settling time recommendation will be easier to meet. Although simulated settling time has not shown good correlation with physical, measured settling time, settling time simulations can still be used as a tool to tune layouts.
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Figure 15. Settling Time UNDERSHOOT THRESHOLD DURATION SPECIFICATION: The undershoot threshold duration is defined as the sum of all time during which the CLK signal is below -0.5V within a single clock period. The undershoot threshold duration must not exceed 20 percent of the period. MAXIMUM RINGBACK SPECIFICATION: The maximum ringback of CLK associated with their high states (overshoot) must not drop below VCC3 0.8V as shown in Figure 17. Similarly, the maximum ringback of CLK associated with their low states (undershoot) must not exceed 0.8V as shown in Figure 19. Refer to Table 24 and Table 25 for a summary of the clock overshoot and undershoot specifications for the Pentium processor with MMX technology.
CLK Signal Quality Specifica tion
The maximum overshoot, maximum undershoot, overshoot threshold duration, undershoot threshold duration, and maximum ringback specifications for CLK are described below: MAXIMUM OVERSHOOT AND MAXIMUM UNDERSHOOT SPECIFICATION: The maximum overshoot of the CLK signals should not exceed VCC3, nominal + 0.9V. The maximum undershoot of the CLK signals must not drop below -0.9V. OVERSHOOT THRESHOLD DURATION SPECIFICATION: The overshoot threshold duration is defined as the sum of all time during which the CLK signal is above VCC3, nominal + 0.5V within a single clock period. The overshoot threshold duration must not exceed 20 percent of the period.
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Table 24. Overshoot Specification Summary Specification Name Maximum Ringback Value VCC3, nominal - 0.8 Units V Notes 1, 2
NOTES: 1. VCC3, nominal refers to the voltage measured at the bottom side of the V CC3 pins. See Section 7.1.2.1.1 for details. 2. See Figures 16 and 17.
Table 25. Undershoot Specification Summary Specification Name Threshold Level Minimum Undershoot Level Maximum Threshold Duration Maximum Ringback
NOTE: 1. See Figures 18 and Figure 19.
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CLOCK SIGNAL MEASUREMENT METHODOLOGY: The waveform of the clock signals should be measured at the bottom side of the processor pins using an oscilloscope with a 3 dB bandwidth of at least 20 MHz (100 MS / s digital sampling rate). There should be a short isolation ground lead attached to a processor pin on the bottom side of the board. An 1 MOhm probe with loading of less than 1 pF (e.g., Tektronics 6243 or Tektronics 6245) is recommended. The measurement should be taken at the CLK (AK18) pin and its nearest V SS pin (AM18). MAXIMUM OVERSHOOT, MAXIMUM UNDERSHOOT AND MAXIMUM RINGBACK SPECIFICATIONS: The display should show continuous sampling (e.g., infinite persistence) of the waveform at 500 mV / div and 5 nS / div for a recommended duration of approximately five seconds. Adjust the vertical position to measure the maximum overshoot and associated ringback with the largest possible granularity. Similarly, readjust the vertical position to measure the maximum undershoot and associated ringback. There is no allowance for crossing the maximum overshoot, maximum undershoot or maximum ringback specifications. OVERSHOOT THRESHOLD DURATION SPECIFICATION: A snapshot of the clock signal should be taken at 500 mV / div and 500 pS / div. Adjust the vertical position and horizontal offset position to view the threshold duration. The overshoot threshold duration is defined as the sum of all time during which the clock signal is above VCC3, nominal + 0.5V within a single clock period. The overshoot threshold duration must not exceed 20 percent of the period. UNDERSHOOT THRESHOLD DURATION SPECIFICATION: A snapshot of the clock signal should be taken at 500 mV / div and 500 pS / div. Adjust the vertical position and horizontal offset position to view the threshold duration. The undershoot threshold duration is defined as the sum of all time during which the clock signal is below 0.5V within a single clock period. The undershoot threshold duration must not exceed 20 percent of the period. These overshoot and undershoot specifications are illustrated graphically in Figures 16 through 19.
Maximum Overshoot Level Overshoot Threshold Level VCC3, nominal
Overshoot Threshold Duration
Figure 16. Maximum Overshoot Level, Overshoot Threshold Level, and Overshoot Threshold Duration 64
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VCC3, nominal Maximum Ringback
Figure 17. Maximum Ringback Associated with the Signal High State
Undershoot Threshold Duration
VSS, nominal Undershoot Threshold Level Maximum Undershoot Level
Figure 18. Maximum Undershoot Level, Undershoot Threshold Level, and Undershoot Threshold Duration
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Maximum Ringback VSS, nominal
Figure 19. Maximum Ringback Associated with the Signal Low State
MECHANICAL SPECIFICATIONS
be excised and lead formed at the customer manufacturing site. Recommendations for the manufacture of this package are included in the 1996 Packaging Databook (Order Number 240800). Figure 20 shows a cross-section view of the TCP as mounted on the Printed Circuit Board. Figures 21 and 22 show the TCP as shipped in its slide carrier, and key dimensions of the carrier and package. Figure 23 shows a cross-section detail of the package. Figure 24 shows an enlarged view of the outer lead bond area of the package.
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TCP Mechanical Diagrams
Encapsulant Gold Bump
Polyimide Support Ring
Polyimide TAB Lead Keeper (OFC Copper) Bar
PCB PCB 1 / 2 Cross-Section Thermally Conductive Adhesive Note: Thermal vias Ground plane Sketches Not to Scale
PCB Full Cross-Section
Figure 20. Cross-Sectional View of the Mounted TCP
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Figure 21. One TCP Site in Carrier (Bottom View of Die)
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Figure 22. One TCP Site in Carrier (Top View of Die)
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
Figure 23. One TCP Site (Cross-Sectional Detail)
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
Figure 24. Outer Lead Bond (OLB) Window Detail
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Table 26. TCP Key Dimensions Symbol N W L T e1 b D1, E1 A2 DL DW LT EL EW Description Leadcount Tape Width Site Length Test Pad Pitch Outer Lead Pitch Outer Lead Width Package Body Size Package Height Die Length Die Width Lead Thickness Encap Length Encap Width Dimension 320 leads 48.
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