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PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
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Support MMXTechnology Compatible with Large Software Base MS-DOS*, Windows*, OS/2*, UNIX* 32-Bit Processor with 64-Bit Data Superscalar Architecture Enhanced Pipelines Pipelined Integer Units Capable Instructions Clock Pipelined Unit Pipelined Floating-Point Unit Separate Code Data Caches 16-Kbyte Code, 16-Kbyte Write Back Data MESI Cache Protocol Advanced Design Features Deeper Write Buffers Enhanced Branch Prediction Feature Virtual Mode Extensions
Enhanced CMOS Silicon Technology 4-Mbyte Pages Increased Rate IEEE 1149.1 Boundary Scan Dual Processing Configuration Internal Error Detection Features Multi-Processor Support Multiprocessor Instructions Support Second Level Cache On-Chip Local APIC Controller Interrupt Management 8259 Compatible Power Management Features System Management Mode Clock Control Fractional Operation Core/66 Core/66 Core/66
Pentium® processor with MMXtechnology extends Pentium processor family, providing performance needed mainstream desktop applications well workstations. Pentium processor with technology compatible with entire installed base applications MS-DOS*, Windows*, OS/2* UNIX*. Pentium processor with technology first microprocessor support Intel technology. Furthermore, Pentium processor with technology superscalar architecture execute instructions clock cycle. Enhanced branch prediction separate caches also increase performance. pipelined floating-point unit delivers workstation level performance. Separate code data caches reduce cache conflicts while remaining software transparent. Pentium processor with technology million transistors built Intel's enhanced CMOS silicon technology. Pentium processor with technology contain design defects errors known errata that cause product deviate from published specifications. Current characterized errata available request.
June 1997
Order Number: 243185.004
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium® Processor with MMXtechnology contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature, obtained from: Intel Corporation P.O. 7641 Prospect, 60056-7641 call 1-800-879-4683 visit Intel's website http\\:www.intel.com *Third-party brands names property their respective owners.
COPYRIGHT INTEL CORPORATION, 1997
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
CONTENTS
PAGE PAGE 2.2. Design Notes.13 2.3. Quick Reference.13 2.4. Reference Tables.24 2.5. Grouping According Function.27 3.0. ELECTRICAL SPECIFICATIONS.28 3.1. Electrical Characteristics Differences between Pentium® Processor with MMXTechnology Pentium Processor 133/150/166/200.28 3.1.1. POWER SUPPLIES.28 3.1.2. CONNECTION SPECIFICATIONS 3.1.3. BUFFER MODELS.30 3.2. Absolute Maximum Ratings.30 3.3. Specifications.30 3.4. Specifications.34 4.0. MECHANICAL SPECIFICATIONS 5.0. THERMAL SPECIFICATIONS.46 5.1. Measuring Thermal Values.46 5.1.1. THERMAL EQUATIONS DATA.46
1.0. MICROPROCESSOR ARCHITECTURE OVERVIEW 1.1. Pentium® Processor Family Architecture. 1.2. Pentium® Processor with MMXTechnology. 1.2.1. FULL SUPPORT INTEL MMXTECHNOLOGY 1.2.2. DOUBLE CODE DATA CHACHES EACH 1.2.3. IMPROVED BRANCH PREDICTION. 1.2.4. ENHANCED PIPELINE 1.2.5. DEEPER WRITE BUFFERS. Processor with MMX1.3. Mobile Technology. 2.0. PINOUT. 2.1. Pinout Descriptions. 2.1.1. PENTIUM® PROCESSOR WITH MMXTECHNOLOGY PINOUT 2.1.2. CROSS-REFERENCE TABLE PENTIUM® PROCESSOR WITH MMXTM. Pentium®
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
1.0.
MICROPROCESSOR ARCHITECTURE OVERVIEW
Improved Instruction Execution Time Separate Code Data Caches
Pentium® processor with MMXtechnology extends Intel Pentium family microprocessors. binary compatible with 8086/88, 80286, Intel386DX, Intel386 Intel486DX, Intel486 Intel486 Pentium processors Pentium processor family currently includes following products.
Writeback MESI Protocol Data Cache 64-Bit Data Cycle Pipelining Address Parity Internal Parity Checking Execution Tracing Performance Monitoring IEEE 1149.1 Boundary Scan System Management Mode Virtual Mode Extensions Dual processing support On-chip local APIC device
Pentium processor with technology: Pentium processor with technology MHz, iCOMP® Index rating Pentium processor with technology MHz, iCOMP Index rating Pentium processor with technology MHz, iCOMP Index rating
Pentium processor 133/150/166/200. name "Pentium processor 133/150/166/200" will used this document refer Pentium processor with 133, 150, versions Pentium processor: Pentium processor MHz, iCOMP Index rating Pentium processor MHz, iCOMP Index rating Pentium processor MHz, iCOMP Index rating Pentium processor MHz, iCOMP Index rating Pentium processor MHz, iCOMP Index rating Pentium processor MHz, iCOMP Index rating Pentium processor MHz, iCOMP Index rating Pentium processor MHz, iCOMP Index rating
addition features listed above, Pentium processor with technology offers following enhancements over Pentium processor 133/150/ 166/200:
Support Intel technology Doubled code data cache sizes each Improved branch prediction Enhanced pipeline Deeper write buffers
following features supported Pentium processor 133/150/166/200, these features supported Pentium processor with technology:
Functional redundancy check Lock Step operation. Support Intel 82498/82493 82497/82492 cache chipset products Split line accesses code cache
Pentium processor family supports features previous Intel Architecture processors, provides significant enhancements additions including following:
Superscalar Architecture Dynamic Branch Prediction Pipelined Floating-Point Unit
1.1.
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
inquire cycle same clock. code cache inherently write-protected cache. code cache tags multi-ported support snooping. Individual pages configured cacheable noncacheable software hardware. caches enabled disabled software hardware. Pentium processors have increased data bits improve data transfer rate. Burst read burst write back cycles supported Pentium processors. addition, cycle pipelining been added allow cycles progress simultaneously. Pentium processors' Memory Management Unit contains optional extensions architecture which allow 4Kbyte 4-Mbyte page sizes. Pentium processors have added significant data integrity error detection capability. Data parity checking still supported byte-by-byte basis. Address parity checking internal parity checking features have been added along with exception, machine check exception. more more functions integrated chip, complexity board level testing increased. address this, Pentium processors have increased test debug capability. Pentium processors implement IEEE Boundary Scan (Standard 1149.1). addition, Pentium processors have specified breakpoint pins that correspond each debug registers externally indicate breakpoint match. Execution tracing provides external indications when instruction completed execution either internal pipelines, when branch been taken. System Management Mode (SMM) been implemented along with some extensions architecture. Enhancements virtual 8086 mode have been made increase performance reducing number times necessary trap virtual 8086 monitor. Figure shows block diagram Pentium processor with technology representative Pentium processor family. block diagram shows instruction pipelines, pipe pipe. u-pipe execute integer floating-point instructions. v-pipe execute simple integer instructions FXCH floating-point instructions.
more detailed description Pentium processor family products, please refer Pentium® Processor Family Developer's Manual (Order Number 241428).
Pentium® Processor Family Architecture
application instruction Pentium processor family includes complete Intel486 processor family instruction with extensions accommodate some additional functionality Pentium processors. application software written Intel386 Intel486 family microprocessors will Pentium processors without modification. on-chip memory management unit (MMU) completely compatible with Intel386 family Intel486 family processors. Pentium processors implement several enhancements increase performance. instruction pipelines floating-point unit Pentium processors capable independent operation. Each pipeline issues frequently used instructions single clock. Together, dual pipes issue integer instructions clock, floating-point instruction (under certain circumstances, floating-point instructions) clock. Branch prediction implemented Pentium processors. support this, Pentium processors implement prefetch buffers, prefetch code linear fashion, that prefetches code according needed code almost always prefetched before needed execution. floating-point unit been completely redesigned over Intel486 processor. Faster algorithms provide speed-up common operations including add, multiply load. Pentium processors include separate code data caches integrated on-chip meet performance goals. Each cache 32-byte line size. Each cache dedicated Translation Lookaside Buffer (TLB) translate linear addresses physical addresses. data cache configurable write back write through line-by-line basis follows MESI protocol. data cache tags triple ported support data transfers
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Control
V-Pipeline Connection U-Pipeline Connection
Control
Logic
Branch Prefetch Target Address Buffer
Code Cache KBytes
Instruction Pointer
Branch Verif. Target Addr
64-Bit Data
Prefetch Buffers Instruction Decode
Control Unit Floating Point Unit Control Register File
32-Bit Address
Unit
Page Unit Generate
Pipeline) Address
Address Generate
Pipeline)
Control Integer Register File
Unit
Divide
Pipeline)
Pipeline)
Multiply
Barrel Shifter
64-Bit Data Data APIC
32-Bit Addr.
Control
Data Cache KBytes
Figure Pentium® Processor with MMXTechnology Block Diagram separate code data caches shown. data cache ports, each pipes (the tags triple ported allow simultaneous inquire cycles). data cache dedicated Translation Lookaside Buffer (TLB) translate linear addresses physical addresses used data cache. code cache, branch target buffer prefetch buffers responsible getting instructions into execution units Pentium processor. Instructions fetched from code cache from external bus. Branch addresses remembered branch target buffer. code cache translates linear addresses physical addresses used code cache. decode unit decodes prefetched instructions Pentium processors execute instruction. control contains microcode which controls sequence operations that must performed implement Pentium processor architecture. control unit direct control over both pipelines. Pentium processors contain pipelined floatingpoint unit that provides significant floating-point performance advantage over previous generations processors. Symmetric dual processing system supported with Pentium processors. processors appear system single Pentium processor. Operating systems with dual processing support properly schedule computing tasks between processors. This scheduling tasks transparent software applications end-user. Logic built into processors support "glueless" interface
easy system design. Through private bus, Pentium processors arbitrate external maintain cache coherency. Dual processing supported system only both processors operating identical core frequencies. this document, order distinguish between Pentium processors dual processing mode, processor will designated "Primary" processor other "Dual" processor. Pentium processors produced enhanced 0.35 CMOS process which allows high device density lower power dissipation. addition features described above, Pentium processor supports clock control. When clock Pentium processor stopped, power dissipation virtually eliminated. combination these improvements makes Pentium processor good choice energy-efficient desktop designs. Pentium processor supports fractional operation. This allows internal processor core operate high frequencies, while communicating with external lower frequencies. Pentium processor contains on-chip Advanced Programmable Interrupt Controller (APIC). This APIC implementation supports multiprocessor interrupt management (with symmetric interrupt distribution across processors), multiple subsystem support, 8259A compatibility, interprocessor interrupt support. architectural features introduced this chapter more fully described Pentium® Processor Family Developer's Manual (Order Number 241428).
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
envelope original Pentium processor while providing significant performance increase. addition architecture described previous section Pentium processor family, Pentium processor with technology several additional micro-architectural enhancements, compared Pentium processor 133/150/166/200, which described below: 1.2.1. FULL SUPPORT INTEL MMXTECHNOLOGY
technology based Single Instruction Multiple Data (SIMD) technique which enables increased performance wide variety multimedia communications applications. Fiftyseven instructions four 64-bit data types supported Pentium processor with technology. existing operating system application software fully-compatible with Pentium processor with technology. 1.2.2. DOUBLE CODE DATA CACHES EACH
1.2.
Pentium® Processor with MMXTechnology
On-chip level-1 data code cache sizes have been doubled each 4-way associative Pentium processor with technology. Larger separate internal caches improve performance reducing average memory access time providing fast access recently-used instructions data. instruction data caches accessed simultaneously while data cache supports data references simultaneously. data cache supports writeback alternatively, write-through, line line basis) policy memory updates. 1.2.3. IMPROVED BRANCH PREDICTION
Pentium processor with technology significant addition Pentium processor family. Available 166, MHz, first microprocessor support Intel's technology. Pentium processor with technology both software compatible with previous members Pentium processor family. contains million transistors manufactured lntel's enhanced 0.35 micron CMOS process which allows voltage reduction technology power high density. This enables Pentium processor with technology remain within thermal
Dynamic branch prediction uses Branch Target Buffer (BTB) boost performance predicting most likely instructions executed. been improved Pentium processor with technology increase accuracy. Further, Pentium processor with technology four prefetch buffers that hold four successive code streams. 1.2.4. ENHANCED PIPELIN
additional pipeline stage been added pipeline been enhanced improve performance.
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
integration pipeline with integer pipeline very similar that floating-point pipeline. Under some circumstances, instructions integer instruction paired issued clock cycle increase throughput. enhanced pipeline described more detail Pentium® Processor Family Developer's Manual (Order Number 241428). 1.2.5. DEEPER WRITE BUFFERS
1.3.
Mobile Pentium Processor with MMXTechnology
Currently, Intel's Mobile Pentium processor with technology family consists three products. Detailed information Mobile Pentium processors with technology based enhanced CMOS process technology available datasheet Mobile Pentium® Processor with MMXTechnology (Order Number 243292). Please reference datasheet correct pinout, mechanical, thermal electrical specifications.
pool four write buffers shared between dual pipelines improve memory write performance.
2.0. 2.1.
2.1.1.
VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
PINOUT Pinout Descriptions
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY PINOUT
INTR VCC3 VCC3 VCC3 VCC3 VCC3 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 FLUSH# W/R# ADS# HLDA BREQ LOCK# SMIACT# VCC2 PCHK#
APCHK# PBREQ# VCC2
EADS# ADSC#
VCC2 DET#
SCYC
BE6#
BE4#
BE2#
BE0# BUSCHK# HITM# A20M# HIT#
RESET
BE7#
BE5#
BE3#
BE1#
D/C#
D/P#
PBGNT# PRDY PHITM# VCC2 HOLD
R/S#
SMI#
IGNNE# INIT PEN#
WB/WT# PHIT# VCC2 BOFF#
VCC3 FRCMC#1
BRDYC# VCC2 BRDY#
KEN# EWBE# VCC2
STPCLK# VCC3
Side View
AHOLD
CACHE# VCC2
VCC3
MI/O#
VCC2
PM1BP1
FERR# PM0BP0 VCC2
VCC3 CPUTYP TRST# VCC3
IERR# VCC3
VCC2
VCC2
PICD1 VCC3 PICD0
VCC2
PICCLK
VCC2
VCC3
VCC3
VCC3
VCC3 VCC3
VCC2 VCC2
VCC2
VCC2
VCC2
VCC2
NOTE: FRCMC# defined Pentium® processor with MMXtechnology. should left "NC" tied VCC3 external pull-up resistor.
PP0008a
Figure
Pentium®
Processor with MMXTechnology SPGA PPGA Package Pinout (Top Side View)
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
VCC2 EWBE# KEN# VCC2 VCC2 VCC2 VCC3 VCC2 VCC2 VCC2 CACHE# MI/O# AHOLD VCC2 VCC2 VCC2 VCC2 VCC3 VCC3 VCC3
VCC3 VCC3 INTR
VCC3 D/P# VCC3 VCC3 R/S# VCC3
FLUSH# VCC2 VCC2
ADSC# EADS# W/R#
VCC2 DET#
HITM# BUSCHK# BE0# D/C# HIT# A20M#
BE2#
BE4#
BE6#
SCYC
BE1#
BE3#
BE5#
BE7#
RESET
BREQ HLDA
ADS#
LOCK#
VCC2 SMIACT# PCHK#
VCC2 PBREQ#APCHK# PBGNT#
VCC2 PHITM# PRDY VCC2 HOLD
SMI#
PHIT# WB/WT# BOFF#
INIT IGNNE# VCC3 PEN#
VCC2 BRDYC# BRDY#
FRCMC# VCC3
Side View
STPCLK# VCC3 VCC3 VCC3 VCC3
VCC3
PM1BP1
VCC2 PM0BP0 FERR# IERR#
TRST# CPUTYP
VCC3
VCC3
PICD1 VCC3
PICD0 VCC3 PICCLK VCC3 VCC2 VCC3 VCC2 VCC2 VCC2 VCC2 VCC2 VCC3 VCC3 VCC3 VCC3 VCC3
NOTE: FRCMC# defined Pentium® processor with MMXtechnology. should left "NC" tied VCC3 external pull-up resistor.
PP0009a
Figure
Pentium®
Processor with MMXTechnology SPGA PPGA Package Pinout (Pin Side View)
2.1.2.
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
CROSS-REFERENCE TABLE PENTIUM® PROCESSOR WITH MMXTable Cross-Reference Name (xPGA Package) Address AL35 AM34 AK32 AN33 AL33 AM32 AK30 AN31 AL31 AL29 AK28 AL27 AK26 AL25 AK24 AL23 AK22 AL21 AF34 AH36 AE33 AG35 AJ35 AH34 AG33 AK36 AK34 AM36 AJ33
Data
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
AK06 AL05 AJ03 AB04 AA35 AA33 PRDY R/S# RESET SCYC SMI# SMIACT# TRST# AC05 AL03 AC35 AK20 AL17 AB34 AG03 AH04 AC33 AG05 AF04
Table Cross-Reference Name (xPGA Package) (Cont'd) Control A20M# ADS# ADSC# AHOLD APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BRDY# BRDYC# AK08 AJ05 AM02 AK02 AE05 AL09 AK10 AL11 AK12 AL13 AK14 AL15 AK16 BREQ BUSCHK# CACHE# CPUTYP D/C# D/P# EADS# EWBE# FERR# FLUSH# FRCMC#1 AJ01 AL07 AK04 AE35 AM04 AN07 HIT# HITM# HLDA HOLD IERR# IGNNE# INIT
INTR/LINT0 AD34 KEN# LOCK# M/IO# NMI/LINT1 PCHK# PEN# PM0/BP0 PM1/BP1
VCC2DET# AL01 W/R# WB/WT# AM06 AA05
APIC PICCLK PICD0 [DPEN#] PICD1 [APICEN] [BF0] [BF1]
Clock Control AK18
Dual Processor Private Interface PBGNT# PBREQ# PHIT# PHITM# AD04 AE03 AA03 AC03
STPCLK#
VCC2 AA01 AC01 AE01 AG01 AN09 AN11 AN13 AN15 AN17 AN19
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Table Cross-Reference Name (xPGA Package) (Cont'd) VCC3 AA37 AC37 AE37 AG37 AN29 AN27 AN25 AN23 AN21
AB02 AB36 AD02 AD36 AF02 AF36 AH02 AJ37 AL37 AM08 AM10 AM12 AM14 AM16 AM18 AM20 AM22 AM24 AM26 AM28 AM30 AN37
AL19 AN35
AN01 AN03 AN05
NOTES: FRCMC# defined Pentium® processor with MMXtechnology. This should left "NC" tied VCC3 external pull-up resistor Pentium processor with technology. PICCLK 3.3V-tolerant-only Pentium processor with technology. Please refer Pentium® Processor Family Developer's Manual (Order Number 241428) PICCLK signal quality specification.
2.2.
Design Notes
2.3.
Quick Reference
reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected VCC3. Unused active high inputs should connected GND. Connect (NC) pins must remain unconnected. Connection pins result component failure incompatibility with processor steppings.
This section gives brief functional description each pins. detailed description, Hardware Interface chapter Pentium® Processor Family Developer's Manual (Order Number 241428). NOTE input pins must meet their AC/DC specifications guarantee proper functional behavior.
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
symbol signal name indicates that active, asserted state occurs when signal voltage. When symbol present after signal name, signal active, asserted high voltage level. Square brackets around signal name indicate that signal defined only RESET.
following pins become pins when Pentium processors with technology operating dual processing environment: ADS#, CACHE#, HIT#, HITM#, HLDA#, LOCK#, M/IO#, D/C#, W/R#, SCYC, BE#4
Table Quick Reference Symbol A20M# Type Name Function When address mask asserted, Pentium® processor with MMXtechnology emulates address wraparound Mbyte which occurs 8086 masking physical address (A20) before performing lookup internal caches driving memory cycle bus. effect A20M# undefined protected mode. A20M# must asserted only when processor real mode. A20M# internally masked Pentium processor with technology when configured Dual processor. A31-A3 outputs, address lines processor along with byte enables define physical area memory accessed. external system drives inquire address processor A31-A5. address strobe indicates that valid cycle currently being driven Pentium processor with technology. address strobe (copy) functionally identical ADS#. response assertion address hold, Pentium processor with technology will stop driving address lines (A31-A3) next clock. rest will remain active data returned driven previously issued cycles. Address parity driven Pentium processor with technology with even parity information Pentium processor with technology generated cycles same clock that address driven. Even parity must driven back Pentium processor with technology during inquire cycles this same clock EADS# ensure that correct parity check status indicated Pentium processor with technology. address parity check status asserted clocks after EADS# sampled active Pentium processor with technology detected parity error address during inquire cycles. APCHK# will remain active clock each time parity error detected (including during dual processing private snooping). Advanced Programmable Interrupt Controller Enable enables disables on-chip APIC interrupt controller. sampled high falling edge RESET, APIC enabled. APICEN shares with PICD1 signal.
ADS# ADSC# AHOLD
APCHK#
[APICEN] PICD1
Symbol BE7#-BE4# BE3#-BE0# Type BF[1:0] BOFF#
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Table Quick Reference (Cont'd) Name Function byte enable pins used determine which bytes must written external memory which bytes were requested current cycle. byte enables driven same clock address lines (A31-3). Additionally, lower 4-byte enables (BE3#-BE0#) used Pentium processor with technology APIC inputs sampled RESET. dual processing mode, BE4# used input during Flush cycles. frequency pins determine bus-to-core frequency ratio. BF[1:0] sampled RESET, cannot changed until another non-warm assertion RESET. Additionally, BF[1:0] must change values while RESET active. Table Frequency Selections. backoff input used abort outstanding cycles that have completed. response BOFF#, Pentium processor with technology will float pins normally floated during hold next clock. processor remains hold until BOFF# negated, which time Pentium processor with technology restarts aborted cycle(s) their entirety. breakpoint pins (BP3-0) correspond debug registers, DR3-DR0. These pins externally indicate breakpoint match when debug registers programmed test breakpoint matches. multiplexed with performance monitoring pins (PM1 PM0). bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring. BRDY# burst ready input indicates that external system presented valid data data pins response read that external system accepted Pentium processor with technology data response write request. This signal sampled states. burst ready (copy) functionally identical BRDY#. request output indicates external system that Pentium processor with technology internally generated request. This signal always driven whether Pentium processor with technology driving bus.
BP[3:2] PM/BP[1:0]
BRDYC# BREQ
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Table Quick Reference (Cont'd) Symbol BUSCHK# Type Name Function check input allows system signal unsuccessful completion cycle. this sampled active, Pentium processor with technology will latch address control signals machine check registers. addition, set, Pentium processor with technology will vector machine check exception. NOTE: assure that BUSCHK# will always recognized, STPCLK# must deasserted time BUSCHK# asserted system, before system allows another external cycle. BUSCHK# asserted system snoop cycle while STPCLK# remains asserted, usually MCE=1) processor will vector exception after STPCLK# deasserted. another snoop same line occurs during STPCLK# assertion, processor lose BUSCHK# request. CACHE# Pentium processor with technology-initiated cycles thecache indicates internal cacheability cycle read), indicates burst write back cycle write). this driven inactive during read cycle, Pentium processor with technology will cache returned data, regardless state KEN# pin. This also used determine cycle length (number transfers cycle). clock input provides fundamental timing Pentium processor with technology. frequency operating frequency Pentium processor with technology external bus, requires levels. external timing parameters except TDI, TDO, TMS, TRST#, PICD0-1 specified with respect rising edge CLK. This 3.3V-tolerant-only Pentium processor with technology. Please refer Pentium® Processor Family Developer's Manual (Order Number 241428) PICCLK signal quality specification. NOTE: recommended that begin toggling within after reaches proper operating level. This recommendation ensure long-term reliability device. CPUTYP type distinguishes Primary processor from Dual processor. single processor environment, when Pentium processor with technology acting Primary processor dual processing system, CPUTYP should strapped VSS. Dual processor should have CPUTYP strapped VCC3. data/code output primary cycle definition pins. driven valid same clock ADS# signal asserted. D/C# distinguishes between data code special cycles.
D/C#
Symbol D/P# Type D63-D0 DP7-DP0
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Table Quick Reference (Cont'd) Name Function dual/primary processor indication. Primary processor drives this when driving bus, otherwise drives this high. D/P# always driven. D/P# sampled current cycle with ADS# (like status pin). This defined only Primary processor. Dual processing supported system only both processors operating identical core frequencies. Within these restrictions, processors different steppings operate together system. These data lines processor. Lines D7-D0 define least significant byte data bus; lines D63-D56 define most significant byte data bus. When driving data lines, they driven during T12, clocks that cycle. During reads, samples data when BRDY# returned. These data parity pins processor. There each byte data bus. They driven Pentium processor with technology with even parity information writes same clock write data. Even parity information must driven back Pentium processor with technology these pins same clock data ensure that correct parity check status indicated Pentium processor with technology. applies D63-56, applies D7-0. Dual processing enable output Dual processor input Primary processor. Dual processor drives DPEN# Primary processor RESET indicate that Primary processor should enable dual processor mode. DPEN# sampled system falling edge RESET determine dual-processor socket occupied. DPEN# multiplexed with PICD0. This signal indicates that valid external address been driven onto Pentium processor with technology address pins used inquire cycle. external write buffer empty input, when inactive (high), indicates that write cycle pending external system. When Pentium processor with technology generates write, EWBE# sampled inactive, Pentium processor with technology will hold subsequent writes Mstate lines data cache until write cycles have completed, indicated EWBE# being active. floating-point error driven active when unmasked floating-point error occurs. FERR# similar ERROR# Intel387math coprocessor. FERR# included compatibility with systems using type floating-point error reporting. FERR# never driven active Dual processor.
[DPEN#] PICD0
EADS#
EWBE#
FERR#
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Table Quick Reference (Cont'd) Symbol FLUSH# Type Name Function When asserted, cache flush input forces Pentium processor with technology write back modified lines data cache invalidate internal caches. Flush Acknowledge special cycle will generated Pentium processor with technology indicating completion write back invalidation. FLUSH# sampled when RESET transitions from high low, tristate test mode entered. Pentium processors with technology operating dual processing mode FLUSH# asserted, Dual processor will perform flush first (without flush acknowledge cycle), then Primary processor will perform flush followed flush acknowledge cycle. NOTE: FLUSH# signal asserted dual processing mode, must deasserted least clock prior BRDY# FLUSH Acknowledge cycle avoid arbitration problems. FRCMC# Functional Redundancy Checking supported thePentium processor with technology. FRCMC# defined Pentium processor with technology. This should left a"NC" tied VCC3 external pull-up resistor. indication driven reflect outcome inquire cycle. inquire cycle hits valid line either Pentium processor with technology data instruction cache, this asserted clocks after EADS# sampled asserted. inquire cycle misses Pentium processor with technology cache, this negated clocks after EADS#. This changes value only result inquire cycle retains value between cycles. modified line output driven reflect outcome inquire cycle. asserted after inquire cycles which resulted modified line data cache. used inhibit another master from accessing data until line completely written back. hold acknowledge goes active response hold request driven processor HOLD pin. indicates that Pentium processor with technology floated most output pins relinquished another local master. When leaving hold, HLDA will driven inactive Pentium processor with technology will resume driving bus. Pentium processor with technology cycle pending, will driven clock cycle after HLDA de-asserted. response hold request, Pentium processor with technology will float most output input/output pins assert HLDA after completing outstanding cycles. Pentium processor with technology will maintain this state until HOLD de-asserted. HOLD recognized during LOCK cycles. Pentium processor with technology will recognize HOLD during reset.
HIT#
HITM#
HLDA
HOLD
Symbol IERR# Type IGNNE#
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Table Quick Reference (Cont'd) Name Function internal error used indicate internal parity errors. parity error occurs read from internal array, Pentium processor with technology will assert IERR# clock then shutdown. This ignore numeric error input. This effect when When CR0.NE IGNNE# asserted, Pentium processor with technology will ignore pending unmasked numeric exception continue executing floating-point instructions entire duration that this asserted. When CR0.NE IGNNE# asserted, pending unmasked numeric exception exists (SW.ES floating-point instruction FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, FSETPM, Pentium processor with technology will execute instruction spite pending exception. When CR0.NE IGNNE# asserted, pending unmasked numeric exception exists (SW.ES floating-point instruction other than FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, FSETPM, Pentium processor with technology will stop execution wait external interrupt. IGNNE# internally masked when Pentium processor with technology configured Dual processor. INIT Pentium processor with technology initialization input forces Pentium processor with technology begin execution known state. processor state after INIT same state after RESET except that internal caches, write buffers, floating-point registers retain values they prior INIT. INIT used lieu RESET after power-up. INIT sampled high when RESET transitions from high low, thePentium processor with technology will perform built-in self test prior start program execution. INTR/LINT0 active maskable interrupt input indicates that external interrupt been generated. EFLAGS register set, thePentium processor with technology will generate locked interrupt acknowledge cycles vector interrupt handler after current instruction execution completed. INTR must remain active until first interrupt acknowledge cycle generated assure that interrupt recognized. local APIC enabled, this becomes LINT0. invalidation input determines final cache line state case inquire cycle hit. sampled together with address inquire cycle clock EADS# sampled active. cache enable used determine whether current cycle cacheable consequently used determine cycle length. When Pentium processor with technology generates cycle that cached (CACHE# asserted) KEN# active, cycle will transformed into burst line fill cycle.
KEN#
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Table Quick Reference (Cont'd) Symbol LINT0/INTR LINT1/NMI LOCK# Type Name Function APIC enabled, this local interrupt APIC disabled, this INTR. APIC enabled, this local interrupt APIC disabled, this NMI. lock indicates that current cycle locked. ThePentium processor with technology will allow hold when LOCK# asserted (but AHOLD BOFF# allowed). LOCK# goes active first clock first locked cycle goes inactive after BRDY# returned last locked cycle. LOCK# guaranteed de-asserted least clock between back-to-back locked cycles. memory/input-output primary cycle definition pins. driven valid same clock ADS# signal asserted. M/IO# distinguishes between memory cycles. active next address input indicates that external memory system ready accept cycle although data transfers current cycle have completed. Pentium processor with technology will issue ADS# pending cycle clocks after asserted. Pentium processor with technology supports outstanding cycles. non-maskable interrupt request signal indicates that external non-maskable interrupt been generated. local APIC enabled, this becomes LINT1. PBGNT# Private grant grant line that used when Pentium processors with technology configured dual processing mode, order perform private arbitration. PBGNT# should left unconnected only Pentium processor with technology exists system. Private request request line that used when Pentium processor with technology configured dual processing mode, order perform private arbitration. PBREQ# should left unconnected only Pentium processor with technology exists system. page cache disable reflects state CR3, Page Directory Entry, Page Table Entry. purpose provide external cacheability indication page page basis. parity check output indicates result parity check data read. driven with parity status clocks after BRDY# returned. PCHK# remains clock each clock which parity error detected. Parity checked only bytes which valid data returned. When Pentium processors with technology operating dual processing mode, PCHK# driven three clocks after BRDY# returned.
M/IO#
NMI/LINT1
PBREQ#
PCHK#
Symbol PEN# Type PHIT# PHITM#
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Table Quick Reference (Cont'd) Name Function parity enable input (along with CR4.MCE) determines whether machine check exception will taken result data parity error read cycle. this sampled active clock data parity error detected, Pentium processor with technology will latch address control signals cycle with parity error machine check registers. addition, machine check enable "1", Pentium processor with technology will vector machine check exception before beginning next instruction. Private indication used when Pentium processors with technology configured dual processing mode, order maintain local cache coherency. PHIT# should left unconnected only Pentium processor with technology exists system. Private modified modified cache line indication used when Pentium processors with technology configured dual processing mode, order maintain local cache coherency. PHITM# should left unconnected only Pentium processor with technology exists system. APIC interrupt controller serial data clock driven into programmable interrupt controller clock input Pentium processor with technology. This 3.3V-tolerant-only Pentium processor with technology. Please refer Pentium® Processor Family Developer's Manual (Order Number 241428) PICCLK signal quality specification. PICD0-1 [DPEN#] [APICEN] PM/BP[1:0] Programmable interrupt controller data lines Pentium processor with technology comprise data portion APIC 3-wire bus. They open-drain outputs that require external pull-up resistors. These signals multiplexed with DPEN# APICEN respectively. These pins function part performance monitoring feature. breakpoint pins multiplexed with theperformance monitoring pins. bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring. PRDY probe ready output provided with Intel debug port. Please refer Pentium® Processor Family Developer's Manual (Order Number 241428) more details. page write through reflects state CR3, page directory entry, page table entry. used provide external write back indication page-by-page basis. run/stop input provided with Intel debug port. Please refer Pentium® Processor Family Developer's Manual (Order Number 241428) more details.
PICCLK
R/S#
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Table Quick Reference (Cont'd) Symbol RESET Type Name Function RESET forces Pentium processor with technology begin execution known state. Pentium processor with technology internal caches will invalidated upon RESET. Modified lines data cache written back. FLUSH# INIT sampled when RESET transitions from high determine tristate test mode checker mode will entered, Built-In Self-Test (BIST) will run. split cycle output asserted during misaligned LOCKed transfers indicate that more than cycles will locked together. This signal defined locked cycles only. undefined cycles which locked. system management interrupt causes system management interrupt request latched internally. When latched SMI# recognized instruction boundary, processor enters System Management Mode. active system management interrupt active output indicates that processor operating System Management Mode. Assertion stop clock input signifies request stop internal clock Pentium processor with technology, thereby causing core consume less power. When recognizes STPCLK#, processor will stop execution next instruction boundary, unless superseded higher priority interrupt, generate stop grant acknowledge cycle. When STPCLK# asserted, Pentium processor with technology will still respond interprocessor external snoop requests. testability clock input provides clocking function Pentium processor with technology boundary scan accordance with IEEE Boundary Scan interface (Standard 1149.1). used clock state information data into Pentium processor with technology during boundary scan. test data input serial input test logic. instructions data shifted into Pentium processor with technology rising edge when controller appropriate state. test data output serial output test logic. instructions data shifted Pentium processor with technology TCK's falling edge when controller appropriate state. value test mode select input signal sampled rising edge controls sequence controller state changes. When asserted, test reset input allows controller asynchronously initialized. Pentium processor with technology 2.8Vpower inputs. Pentium processor with technology 3.3Vpower inputs. VCC2 detect used flexible motherboard implementations configure voltage output set-point appropriately inputs processor.
SCYC
SMI#
SMIACT# STPCLK#
TRST# VCC2 VCC3 VCC2DET#
Symbol W/R# Type WB/WT#
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Table Quick Reference (Cont'd) Name Function Pentium processor with technology 53ground inputs. Write/read primary cycle definition pins. driven valid same clock ADS# signal asserted. W/R# distinguishes between write read cycles. write back/write through input allows data cache line defined write back write through line-by-line basis. result, determines whether cache line initially state data cache.
Core frequencies according Table below. Each Pentium processor with technology specified operate within single bus-to-core ratio specific minimum maximum frequency range (corresponding minimum maximum core frequency range). Operation other bus-to-core ratios outside specified operating frequency range supported. example, Pentium processor with technology does operate beyond frequency only supports bus-to-core ratio; does support 1/3, 1/2, bus-to-core ratios. Table clarifies summarizes these specifications. Table Frequency Selections Bus/Core Ratio Bus/Core Frequency (MHz) 66/200 66/166 66/233 Bus/Core Frequency (MHz) 33/100 33/83 33/117
NOTES: This default core ratio Pentium® processor with MMXtechnology. pins left floating, processor will configured core frequency ratio. Currently, there products that support these fractions.
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
2.4.
Reference Tables
Table Output Pins Name Active Level High High High High High High Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# When Floated Hold, BOFF# Hold, BOFF#
ADS#
ADSC# APCHK# BE7#-BE4# BREQ CACHE# D/P# FERR# HIT# HITM# HLDA IERR# LOCK# M/IO# (1), D/C# (1), W/R# PCHK# BP3-2, PM1/BP1, PM0/BP0 PRDY PWT, SCYC SMIACT# VCC2DET#
states except Shift-DR Shift-IR
NOTES: output input/output pins floated during tristate test mode (except IERR#). These signals when Pentium® processor with MMXtechnology operating dual processing mode. These signals undefined when processor configured Dual processor. internal pull-up resistor.
Name A20M# AHOLD APICEN BOFF# BRDY# BRDYC# BUSCHK# CPUTYP EADS# EWBE# FLUSH# HOLD IGNNE# INIT INTR LINT[1:0] KEN# PEN# PICCLK R/S# RESET SMI# STPCLK# TRST# WB/WT# Active Level High High High High High High High High High High High
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Table Input Pins Synchronous/ Asynchronous Asynchronous Synchronous Synchronous/RESET Synchronous/RESET Synchronous/RESET Synchronous Synchronous Synchronous Synchronous Synchronous/RESET Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Asynchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Synchronous/TCK Synchronous/TCK Asynchronous Synchronous Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up First BRDY#/NA# Pull-up Pull-up BRDY# EADS# APICEN RESET First BRDY#/NA# State BRDY# Pull-up Pull-up Pull-up Pull-down State T12, State T12, BRDY# Pull-up Pull-down Pull-up Internal Resistor Qualified
NOTES: Undefined when processor configured Dual processor.
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Table Input/Output Pins Name A31-A3 BE3#-BE0# D63-D0 DP7-DP0 DPEN# PICD0 PICD1 Active Level When Floated Address Hold, Hold, BOFF# Address Hold, Hold, BOFF# Address Hold, Hold, BOFF# Hold, BOFF# Hold, BOFF#
Qualified (when input) EADS# EADS# RESET BRDY# BRDY# RESET
Internal Resistor
Pull-down
Pull-up Pull-up Pull-down
NOTES: output input/output pins floated during tristate test mode (except TDO, IERR# TDO). BE3#-BE0# have Pull-downs during RESET only.
Table Inter-Processor Input/Output Pins Name PHIT# PHITM# PBGNT# PBREQ# Active Level Internal Resistor Pull-up Pull-up Pull-up Pull-up
NOTES: proper inter-processor operation, system cannot load these signals.
2.5.
Clock
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Grouping According Function
Table organizes pins with respect their function. Table Functional Grouping Function RESET, INIT, BF1-BF0 A31-A3, BE7#-BE0# A20M# D63-D0 APCHK# PICCLK, PICD0-1 DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# ADS#, ADSC#, BRDY#, BRDYC#, PCD, KEN#, WB/WT# AHOLD, EADS#, HIT#, HITM#, FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA PBGNT#, PBREQ#, PHIT#, PHITM# INTR, FERR#, IGNNE# SMI#, SMIACT# TCK, TMS, TDI, TDO, TRST# PM0/BP0, PM1/BP1, BP3-2 STPCLK# CPUTYP, D/P# R/S#, PRDY VCC2DET# Initialization Address Address Mask Data Address Parity APIC Support Data Parity Internal Parity Error System Error Cycle Definition Control Page Cacheability Cache Control Cache Snooping/Consistency Cache Flush Write Ordering Arbitration Dual Processing Private Control Interrupts Floating-Point Error Reporting System Management Mode Port Breakpoint/Performance Monitoring Power Management Miscellaneous Dual Processing Debugging Voltage Detection Pins
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3.0.
ELECTRICAL SPECIFICATIONS
This section describes electrical differences between Pentium processor with technology Pentium processor 133/150/166/200, well specifications Pentium processor with technology.
Pentium processor 133/150/166/200 designs easily converted support Pentium processor with technology. order maintain compatibility with Pentium processor 133/150/166/200-based platforms, Pentium processor with technology supports standard 3.3V specification VCC3 pins. 3.1.1.1. Power Supply Sequencing
3.1.
Electrical Characteristics Differences between Pentium® Processor with MMXTechnology Pentium Processor 133/150/166/200
There specific power sequence required powering powering down separate VCC2 VCC3 supplies Pentium processor with technology. recommended that VCC2 VCC3 supplies either both both within second each other. 3.1.2. CONNECTION SPECIFICATIONS
When designing Pentium processor with technology system from Pentium processor 133/150/166/200 system, there number electrical differences that require attention. Designing single motherboard that supports various members Pentium processor family including Pentium processor with technology, Pentium processor 133/150/166/200, Pentium OverDrive® processor, future Pentium OverDrive processor easily accomplished. Refer Pentium® Processor Flexible Motherboard Design Guidelines application note (Order Number 243187) more information specific implementation examples. following sections highlight electrical issues pertaining Pentium processor with technology power supplies, connection specifications buffer models. 3.1.1. POWER SUPPLIES
Connection specifications power ground inputs, 3.3V inputs outputs, NC/INC unused inputs discussed following sections. 3.1.2.1. Power Ground
clean on-chip power distribution, Pentium processor with technology PPGA SPGA packages VCC3 (I/O power), VCC2 (core power) (ground) inputs. Power ground connections must made external pins Pentium processor with technology. circuit board VCC3 pins must connected 3.3V plane. VCC2 pins must connected 2.8V plane. pins must connected plane. 3.1.2.1.1. VCC2 VCC3 Measurement Specification
main electrical difference between Pentium processor with technology Pentium processor 133/150/166/200 operating voltage. Pentium processor with technology requires separate voltage inputs, VCC2 VCC3. VCC2 pins supply power Pentium processor with technology core, while VCC3 pins supply power processor pins. Pentium processor 133/150/166/200, other hand, requires single voltage supply pins. This single supply powers both core pins Pentium processor 133/150/166/200. connecting VCC2 pins together VCC3 pins together separate power islands,
values VCC2 VCC3 should measured bottom side processor pins using oscilloscope with bandwidth least (100 MS/s digital sampling rate). There should short isolation ground lead attached processor bottom side board. measurement should taken following VCC/VSS pairs: AN13/AM10, AN21/AM18, AN29/ AM26, AC37/Z36, U37/R36, L37/H36, A25/B28, A17/B20, A7/B10, G1/K2, S1/V2, AC1/Z2. One-half these pins VCC2 while others VCC3; operating ranges VCC2 VCC3 pins
3.1.2.1.2.
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supply output react change load. order reduce ESR, necessary place several bulk storage capacitors parallel. These capacitors should placed near Pentium processor with technology both VCC2 VCC3 plane ensure that supply voltage stays within specified limits during changes supply current during operation. Detailed decoupling recommendations provided Flexible Motherboard Design Guidelines application note (Order Number 243187) 3.1.2.2. 3.3V Inputs Outputs
specified different voltages. Table specification. display should show continuous sampling voltage line, mV/div, ns/div with trigger point center point range. Slowly move trigger high ends specification, verify that excursions beyond these limits observed. There allowances crossing high limits voltage specification. more information measurement techniques, Voltage Guidelines Pentium® Processors with MMXTechnology application note (Order Number 243186). Decoupling Recommendations
Liberal decoupling capacitance should placed near Pentium processor with technology. Pentium processor with technology, when driving large address data buses high frequencies, cause transient power surges, particularly when driving large capacitive loads. inductance capacitors interconnects recommended best high frequency electrical performance. Inductance reduced shortening circuit board traces between Pentium processor with technology decoupling capacitors much possible. These capacitors should evenly distributed around each component power plane. Capacitor values should chosen ensure they eliminate both high frequency noise components. Pentium processor with technology, power consumption transition from level power much higher level high power) very rapidly. typical example would entering exiting Stop Grant State. Another example would executing HALT instruction, causing Pentium processor with technology enter AutoHALT Power Down State, transitioning from HALT Normal State. these examples cause abrupt changes power being consumed Pentium processor with technology. Note that AutoHALT Power Down feature always enabled even when other power management features implemented. Bulk storage capacitors with Effective Series Resistance (ESR) range required maintain regulated supply voltage during interval between time current load changes point that regulated power
inputs outputs Pentium processor with technology comply with 3.3V JEDEC standard levels. Both inputs outputs also TTL-compatible, although inputs cannot tolerate voltage swings above VIN3 (max) specification. System support components which TTLcompatible inputs will interface Pentium processor with technology without extra logic. This because Pentium processor drives according specification (but beyond 3.3V). Pentium processor with technology inputs, voltage must exceed 3.3V VIN3 (max) specification. System support components consist 3.3V devices open-collector devices. open-collector configuration, external resistor should biased VCC3. pins, including PICCLK Pentium processor with technology, 3.3Vtolerant-only. 8259A interrupt controller used, example, system must provide level converters between 8259A Pentium processor with technology. 3.1.2.3. NC/INC Unused Inputs
pins must remain unconnected. reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected VCC3. Unused active high inputs should connected (ground).
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3.1.2.4. Private
When Pentium processors with technology operating dual processor mode, "private bus" exists arbitrate processor maintain local cache coherency. private consists pinout changes: Five pins added: PBREQ#, PBGNT#, PHIT#, PHITM#, D/P#. output pins become pins: ADS#, D/C#, W/R#, M/IO#, CACHE#, LOCK#, HIT#, HITM#, HLDA, SCYC, BE#4.
values components have changed reflect minor manufacturing process package differences between processors. system should insignificant differences between behavior Pentium processor with technology Pentium processor 133/150/166/200. Simulation timings using Pentium processor with technology buffer models recommended ensure robust system designs. specific attention signal quality restrictions imposed 3.3V buffers.
pins given specifications valid delays setup times hold times. Simulate with these parameters their respective buffer models guarantee that proper timings met. specification gives input setup hold times signals that become pins. These setup hold times must only when dual processor present system. 3.1.3. BUFFER MODELS
3.2.
Absolute Maximum Ratings
Table provides stress ratings only. Functional operation Absolute Maximum Ratings implied guaranteed. Functional operating conditions given specification tables. Extended exposure maximum ratings affect device reliability. Furthermore, although Pentium processor with technology contains protective circuitry resist damage from electrostatic discharge, always take precautions avoid high static voltages electric fields.
structure buffer models Pentium processor with technology Pentium processor 133/150/166/200 identical. Some
Table Absolute Maximum Ratings Symbol Parameter Storage Temperature Case Temperature Under Bias VCC3 VCC2 VIN3 VCC3 Supply Voltage with respect VCC2 Supply Voltage with respect Only Buffer Input Voltage -0.5 -0.5 -0.5 VCC3 +0.5 (not exceed VCC3 max) WARNING Stressing device beyond Absolute Maximum Ratings cause permanent damage. These stress ratings only. Operation beyond specifications recommended guaranteed extended exposure beyond specifications affect device reliability. Unit Notes
3.3. Specifications
Symbol TCASE VCC2 VCC3 Parameter Case Temperature VCC2 Voltage VCC3 Voltage
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Table Table list Specifications Pentium processor with technology. Table TCASE Specifications 3.135 Unit Range 3.57% Range -5%, +9.09% Notes
NOTES: measurement specification section earlier this chapter.
Table 3.3V Specifications (See Table TCASE assumptions.) Symbol VIL3 VIH3 VOL3 VOH3 Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage -0.3 VCC3 +0.3 Unit Notes Level Level Level Level
NOTES: Parameter measured Parameter measured Parameter measured nominal VCC3 which 3.3V. dual processing systems, load from second processor observed PCHK# signal. Based silicon characterization data, VOL3 PCHK# will remain less than even with load. PCHK# will increase approximately with load (worst case system with system load).
Table Specifications (Measured VCC2=2.9V VCC3=3.6V.) Symbol ICC2 Parameter Power Supply Current 6500 5700 4750 Unit Notes
ICC3
Power Supply Current
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NOTES: This value should used power supply design. determined using worst case instruction maximum VCC. Power supply transient response decoupling capacitors must sufficient handle instantaneous current changes occurring during transitions from Stop Clock full Active modes.
Notes
Table Power Dissipation Requirements Thermal Design (Measured VCC2=2.8V VCC3=3.3V.) Parameter Active Power Typical
Unit Watts Watts Watts Watts Watts Watts Watts
17.0 15.7 13.1 2.61 2.41 2.05
frequencies
Stop Grant Auto Halt Powerdown Power Stop Clock Power 0.03
NOTES: This typical power dissipation system. This value expected average value that will measured system using typical device VCC2 2.8V running typical applications. This value highly dependent upon specific system configuration. Typical power specifications tested. Systems must designed thermally dissipate maximum active power dissipation. determined using worst case instruction with VCC2 2.8V VCC3 also takes into account thermal time constants package. Stop Grant/Auto Halt Power Down Power Dissipation determined asserting STPCLK# executing HALT instruction. Stop Clock Power Dissipation determined asserting STPCLK# then removing external input. Active Power (typ) average power measured system using typical device running typical applications under normal operating conditions nominal room temperature. Active Power (max) maximum power dissipation under normal operating conditions nominal CC2, worst-case temperature, while executing worst case power instruction mix. Active power (max) equivalent Thermal Design Power (max).
Symbol CI/O CCLK CTIN CTOUT CTCK Parameter Input Capacitance Output Capacitance Capacitance Input Capacitance Test Input Capacitance Test Output Capacitance Test Clock Capacitance Input Leakage Current Output Leakage Current Input Leakage Current Input Leakage Current
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Table Input Output Characteristics -400 Unit
Notes
VIL, VIL, 2.4V 0.4V
NOTES: This parameter inputs/outputs without internal pull-up pull-down. This parameter inputs with internal pull-up. This parameter inputs with internal pull-down. Guaranteed design. This specification applies HITM# when driven input (e.g., JTAG mode).
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
3.4.
Specifications
specifications consist output delays, input setup requirements input hold requirements. specifications (with exception those signals APIC signals) relative rising edge input. timings referenced volts both logic levels unless otherwise specified. Within sampling window, synchronous input must stable correct Pentium processor with technology operation. Each valid delay specified load. system designer should buffer modeling account signal flight time delays.
Each Pentium processor with technology specified operate within single bus-to-core ratio specific minimum maximum frequency range (corresponding minimum maximum core frequency range). Operation other bus-tocore ratios outside specified operating frequency range supported. example, Pentium processor with technology does operate beyond frequency only supports bus-to-core ratio; does support 1/3, 1/2, bus-to-core ratios. Table clarifies summarizes these specifications.
Table Pentium® Processor with MMXTechnology Specifications 66-MHz Operation (See Table TCASE specifications, pF.) Symbol Frequency Period Period Stability High Time Time Fall Time Rise Time PWT, PCD, CACHE# Valid Delay Valid Delay BE0-7#, LOCK# Valid Delay ADS# Valid Delay ADSC#, D/C#, W/R#, SCYC, Valid Delay M/IO# Valid Delay A3-A16 Valid Delay A17-A31 Valid Delay 0.15 0.15 Parameter 33.33 15.0 66.6 30.0 ±250 Unit
Figure
Notes
Adjacent Clocks 0.8V (2.0V-0.8V) (0.8V-2.0V)
Symbol Parameter ADS#, ADSC#, A3-A31, PWT, PCD, BE0-7#, M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# Float Delay t10a t10b t11a t11b t16a t16b t18a t18b t24a PCHK# Valid Delay BREQ Valid Delay SMIACT# Valid Delay HLDA Valid Delay HIT# Valid Delay HITM# Valid Delay PM0-1, BP0-3 Valid Delay PRDY Valid Delay
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Table Pentium® Processor with MMXTechnology Specifications 66-MHz Operation (Cont'd) (See Table TCASE specifications, pF.) 10.0 Unit Figure
Notes
APCHK#, IERR#, FERR# Valid Delay
10.0 10.0
D0-D63, DP0-7 Write Data Valid Delay D0-D63, DP0-3 Write Data Float Delay A5-A31 Setup Time A5-A31 Hold Time INV, Setup Time EADS# Setup Time EADS#, INV, Hold Time KEN# Setup Time NA#, WB/WT# Setup Time KEN#, WB/WT#, Hold Time BRDY#, BRDYC# Setup Time BRDY#, BRDYC# Hold Time AHOLD, BOFF# Setup Time AHOLD, BOFF# Hold Time BUSCHK#, EWBE#, HOLD Setup Time
(26)
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Unit
(12, (13) (17)
Table Pentium® Processor with MMXTechnology Specifications 66-MHz Operation (Cont'd) (See Table TCASE specifications, pF.) Symbol t24b t25a t25b t42a Parameter PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time A20M#, INTR, STPCLK# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R/S# Setup Time R/S# Hold Time R/S# Pulse Width, Async. D0-D63, DP0-7 Read Data Setup Time D0-D63, DP0-7 Read Data Hold Time RESET Setup Time RESET Hold Time RESET Pulse Width, Stable RESET Active After Stable Reset Configuration Signals (INIT, FLUSH#) Setup Time Reset Configuration Signals (INIT, FLUSH#) Hold Time Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. Reset Configuration Signals 15.0 Figure
(12,
Notes
(13)
(12,
(13)
(15,
(12, (13)
Power
(12,
(13)
RESET falling edge
(16)
t42b
RESET falling edge
Symbol Parameter (INIT, FLUSH#, BRDYC#, BUSCHK#) Hold Time, Async. t42c Reset Configuration Signals (BRDYC#, BUSCHK#) Setup Time, Async. t43a t43b t43c t43d BF0, BF1, CPUTYP Hold Time APICEN, BE4# Setup Time APICEN, BE4# Hold Time Frequency Period High Time Time Fall Time Rise Time TRST# Pulse Width TDI, Setup Time TDI, Hold Time Valid Delay Float Delay
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Table Pentium® Processor with MMXTechnology Specifications 66-MHz Operation (Cont'd) (See Table TCASE specifications, pF.) Unit Figure
(27)
Notes
RESET falling edge
(27)
BF0, BF1, CPUTYP Setup Time
16.0 62.5 25.0 25.0 40.0 13.0 20.0 25.0 20.0 25.0 13.0
RESET falling edge
(22)
RESET falling edge
(22)
RESET falling edge RESET falling edge
0.8V (2.0V-0.8V) (0.8V-2.0V) Asynchronous
Non-Test Outputs Valid Delay Non-Test Outputs Float Delay Non-Test Inputs Setup Time Non-Test Inputs Hold Time
APIC Specifications t60a t60b t60c t60d PICCLK Frequency PICCLK Period PICCLK High Time PICCLK Time 60.0 15.0 15.0 16.66 500.0
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Unit Figure PICCLK PICCLK From PICCLK (28) From PICCLK (28) Notes
Table Pentium® Processor with MMXTechnology Specifications 66-MHz Operation (Cont'd) (See Table TCASE specifications, pF.) Symbol t60e t60f t60g t60h t60i t60j Parameter PICCLK Rise Time PICCLK Fall Time PICD0-1 Setup Time PICD0-1 Hold Time PICD0-1 Valid Delay (LtoH) PICD0-1 Valid Delay (HtoL) 0.15 0.15 38.0 22.0
NOTES: Please refer Table footnotes.
Symbol t80a t80b t83a t83b t83c t83d t83e t84a t84b Parameter PBREQ#, PBGNT#, PHIT# Flight Time PHITM# Flight Time A5-A31 Setup Time D/C#, W/R#, CACHE#, LOCK#, SCYC Setup Time ADS#, M/IO# Setup Time HIT#, HITM# Setup Time HLDA Setup Time CACHE#, HIT# Hold Time ADS#, D/C#, W/R#, M/IO#, A5-A31, HLDA, SCYC Hold Time LOCK# Hold Time HITM# Hold Time DPEN# Valid Time DPEN# Hold Time APIC (BE0#-BE3#) Setup Time APIC (BE0#-BE3#) Hold Time D/P# Valid Delay
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Table Pentium® Processor with MMXTechnology Dual Processor Mode Specifications 66-MHz Operation (See Table TCASE assumptions.) Unit Figure
(11,
Notes
(11, (18) (18,
(18, (18, (18, (18, (18,
t84c t84d
10.0
(18, (18, (18, (18,
falling Edge RESET (23) From Falling Edge RESET (23) Primary Processor Only
NOTES: Notes general apply standard signals used with Pentium processor family. Each valid delay specified load. system designer should buffer models account signal flight time delays. 100% tested. Guaranteed design/characterization. input test waveforms assumed transitions with V/ns rise fall times. Non-test outputs inputs normal output input signals (besides TCK, TRST#, TDI, TMS). These timings correspond response these signals boundary scan operations. APCHK#, FERR#, HLDA, IERR#, LOCK# PCHK# glitch-free outputs. Glitch-free signals monotonically transition without false transitions (i.e., glitches). 0.8V/ns input rise/fall time 8V/ns. 0.3V/ns input rise/fall time 5V/ns. Referenced rising edge. Referenced falling edge. added maximum rise fall times every frequency below MHz. During debugging, boundary scan timings (t55 t58).
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
This flight time specification, that includes both flight time clock skew. flight time time from where unloaded driver crosses 1.5V (50% VCC), where receiver crosses 1.5V level (50% VCC). Figure minimum flight time minus clock skew must greater than zero. Setup time required guarantee recognition specific clock. Pentium processor with MMXtechnology must meet this specification dual processor operation FLUSH# RESET signals. Hold time required guarantee recognition specific clock. Pentium processor with technology must meet this specification dual processor operation FLUSH# RESET signals. timings referenced from 1.5V. guarantee proper asynchronous recognition, signal must have been de-asserted (inactive) minimum clocks before being returned active must meet minimum pulse width. This input driven asynchronously. However, when operating processors dual processing mode, FLUSH# RESET must asserted synchronously both processors. When driven asynchronously, RESET, NMI, FLUSH#, R/S#, INIT SMI# must de-asserted (inactive) minimum clocks before being returned active. Timings valid only when dual processor present. Maximum time DPEN# valid from rising edge RESET. Minimum time DPEN# valid after falling edge RESET. D/C#, M/IO#, W/R#, CACHE# A5-A31 signals sampled only that ADS# active. order override internal defaults guarantee that BF[1:0] inputs remain stable while RESET active, these pins should strapped directly through pull-up/pull-down resistor VCC3 ground. Driving these pins with active logic recommended unless stability duringt RESET guaranteed. Similarly, CPUTYP should also strapped directly through pull-up/pull-down resistor VCC3 ground. RESET synchronous dual processing mode. signals which have setup hold time with respect falling rising edge RESET mode, should measured with respect first processor clock edge which RESET sampled either active inactive dual processing mode. PHIT# PHITM# signals operate core frequency. These signals measured rising edge adjacent CLKs 1.5V. ensure relationship between amplitude input jitter internal external clocks, jitter frequency spectrum should have power spectrum peaking between operating frequency. amount jitter present must accounted component skew between devices. internal clock generator requires constant frequency input within ±250 Therefore, input cannot changed dynamically. dual processing mode, timing replaced t83a Timing required external snooping (e.g., address setup which EADS# sampled active) both uniprocessor dual processor modes. BRDYC# BUSCHK# used reset configuration signals select buffer size. This assumes external pull-up resistor lumped capacitive load. pull-up resistor must between ohms ohms, capacitance must between product must between PICD0-1 0.55V.
2.0V 0.8V
t49, t60e t48, t60f t47, t60d t45, t60b t46, t60c
1.5V
Figure Clock Waveform
1.5V max. Signal
t10, t11, t12, t60i, t60j, t80a,
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
min.
1.5V
VALID
Figure Valid Delay Timings
t13; t6min, t12min
Figure Float Delay Timings
t14, t16, t18, t20, t22, t24, t26, t28, t31, t34, t60g PICCLK),t81, t15, t17, t19, t21, t23, t25, t27, t29, t32, t35, t60h PICCLK), t82,
Figure Setup Hold Timings
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
t40, t41, t37, =t42, t43a, t43c, t87, t43b, t43d, t43f, t88, t38, t39,
Figure Reset Configuration Timings
t57, t58, t54, t51, t52, t53, t55,
Figure Test Timings
Figure Test Reset Timings
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Figure Percent Measurement Flight Time
4.0.
MECHANICAL SPECIFICATIONS
Pentium processor with technology packaged 296-pin staggered grid array ceramic (SPGA) plastic (PPGA) packages. pins arranged matrix package dimensions 1.95" 1.95" (Table 17). 1.25" 1.25" copper tungsten heat spreader attached some ceramic packages. This package design with spreader been replaced with package which attached
spreader. this section, both ceramic (spreader non-spreader) well plastic packages shown. Package summary information provided Table mechanical specifications Pentium processor with technology provided Table Table Figure Figure show package dimensions.
Table Package Information Summary Pentium® Processor with MMXTechnologty Package Type Ceramic Staggered Grid Array (SPGA) Plastic Staggered Grid Array (PPGA) Total Pins Array Package Size 1.95" 1.95" 4.95 4.95 1.95" 1.95" 4.95 4.95
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
SEATING PLANE
1.65 REF.
2.29 REF. 1.52 INDEX CHAMFER (INDEX CORNER)
Figure SPGA Package Dimensions
Table SPGA Package Dimensions Millimeters Symbol 1.52 2.62 0.69 3.31 0.43 49.28 45.59 2.29 3.05 2.54 2.97 0.84 3.81 0.51 49.78 45.85 2.79 3.30 Lead Count 0.060 Ceramic Ceramic Notes 0.103 0.027 0.130 0.017 1.940 1.795 0.090 0.120 0.100 Inches 0.117 0.033 0.150 0.020 1.960 1.805 0.110 0.130 Lead Count Ceramic Ceramic Notes
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Figure PPGA Package Dimensions
Table PPGA Package Dimensions Millimeters Symbol 3.05 0.40 49.43 45.59 23.44 2.29 17.56 23.04 3.30 Lead Count 0.120 2.72 1.83 1.00 0.51 49.63 45.85 23.95 2.79 0.016 1.946 1.795 0.923 0.090 0.692 0.907 0.130 Lead Count 3.33 2.23 Notes 0.107 0.072 0.039 0.020 1.954 1.805 0.943 0.110 Inches 0.131 0.088 Notes
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Inches 0.060 0.100 Notes THERMAL EQUATIONS DATA
Table PPGA Package Dimensions Millimeters Symbol 1.52 2.54 Notes
5.0.
THERMAL SPECIFICATIONS
5.1.1.
Pentium processor with technology specified proper operation when case temperature, TCASE, (TC) within specified range 70°C.
Pentium processor with technology, ambient temperature, (air temperature around processor), specified directly. only restriction that met. calculate values, following equations used:
5.1.
Measuring Thermal Values
Where:
verify that proper maintained, should measured center package surface (opposite pins). measurement made same with without heatsink attached. When heatsink attached, hole (smaller than 0.150" diameter) should drilled through heatsink allow probing center package. Figure illustration measure minimize measurement errors, recommended following approach:
Ambient case temperature. (°C)
Case-to-ambient thermal resistance. Junction-to-ambient thermal resistance. Junction-to-case thermal resistance. Maximum power consumption (Watt)
36-gauge finer diameter type thermocouples. laboratory testing done using thermocouple made Omega* (part number 5TC-TTK-36-36). Attach thermocouple bead junction center package surface using high thermal conductivity cements. laboratory testing done using Omega Bond (part number OB-100). thermocouple should attached 90degree angle shown Figure hole size should smaller than 0.150' diameter. Make sure there contact between thermocouple cement heatsink base. contact will affect thermocouple reading.
Table Table list values Pentium processor with technology with passive heatsinks. thermal resistance from package case. values shown these tables typical values. actual values depend actual thermal conductivity process attach. thermal resistance from package case ambient. values shown these tables typical values. actual values depend heatsink design, interface between heatsink package, flow system, thermal interactions between processor surrounding components through ambient. Figure Figure show Table Table graphical format.
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
PPGA
SPGA Figure Technique fore Measuring PPGA SPGA Packages
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
12.1
Table Thermal Resistance SPGA Packages Heatsink Height (inches) 0.25 0.35 0.45 0.55 0.65 0.80 1.00 1.20 1.40 Without Heatsink
(°C/Watt) 14.4
(°C/Watt) Laminar Airflow (linear ft/min)
13.4
NOTES: Heatsinks omni directional aluminum alloy. Features were based standard extrusion practices given height: size ranged from mils spacing ranged from mils Based thickness ranged from mils Heatsink attach 0.005" thermal grease. Attach thickness 0.002" will improve performance approximately
Theta [C/W]
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Flow Rate [LFM]
Heat Sink Height [in]
Figure Thermal Resistance Heatsink Height, SPGA Packages
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
11.2
Table Thermal Resistances PPGA Packages Heat Sink Height (inches) 0.25 0.35 0.45 0.55 0.65 0.80 1.00 1.20 1.40 None
(°C/Watt) 12.9
(°C/Watt) Laminar Airflow (linear ft/min)
12.2
NOTES: Heatsinks omni directional aluminum alloy. Features were based standard extrusion practices given height: size ranged from mils spacing ranged from mils Based thickness ranged from mils Heatsink attach 0.005" thermal grease. Attach thickness 0.002" will improve performance approximately
Theta [C/W]
PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Flow Rate [LFM]
Heat Sink Height [in]
Figure Thermal Resistance Heatsink Height, PPGA Packages
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