PENTIUM® PROCESSOR iCOMP® INDEX 815\100 PENTIUM PROCESSOR iCOMP INDEX
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PENTIUM® PROCESSOR iCOMP® INDEX 815\100 PENTIUM PROCESSOR iCOMP INDEX 735\90 PENTIUM PROCESSOR iCOMP INDEX 610\75 WITH VOLTAGE REDUCTION TECHNOLOGY
MS-DOS, Windows, OS/2, UNIX
32-Bit with 64-Bit Data Superscalar Architecture Pipelined Integer Units Capable Instructions/Clock Pipelined Floating Point Unit Separate Code Data Caches Code, Writeback Data MESI Cache Protocol Advanced Design Features Branch Prediction Virtual Mode Extensions Voltage BiCMOS Silicon Technology
Compatible with Large Software Base
Pages Increased Rate IEEE 1149.1 Boundary Scan Internal Error Detection Features Enhanced Power Management Features System Management Mode Clock Control Voltage Reduction Technology 2.9V core supply 3.3V buffer supply Fractional Operation 75-MHz Core 50-MHz 90-MHz Core 60-MHz 100-MHz Core 66-MHz
Pentium® processor fully compatible with entire installed base applications DOS, Windows, OS/2, UNIX, other software that runs earlier Intel 8086 family product. Pentium processor's superscalar architecture execute instructions clock cycle. Branch prediction separate caches also increase performance. pipelined floating-point unit delivers workstation level performance. Separate code data caches reduce cache conflicts while remaining software transparent. Pentium processor with voltage reduction technology million transistors. built Intel's advanced voltage BiCMOS silicon technology, full Enhanced power management features, including System Management Mode (SMM) clock control. additional Enhanced features, 2.9V core operation along with 3.3V buffer operation, option TCP, which available desktop version Pentium processor, make Pentium processor with voltage reduction technology ideal enabling mobile Pentium processor designs. Pentium processor contain design defects errors known errata. Current characterized errata available upon request.
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Information this document provided connection with Intel products. Intel assumes liability whatsoever, including infringement patent copyright, sale Intel products except provided Intel's Terms Conditions Sale such products. Intel retains right make changes these specifications time, without notice. Microcomputer Products have minor variations this specification known errata.
COPYRIGHT INTEL CORPORATION 1996 March 1996 Order Number 242973-001
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
CONTENTS
PAGE 1.0. INTRODUCTION 2.0. MICROPROCESSOR ARCHITECTURE OVERVIEW_3 2.1. Pentium® Processor Family Architecture 3.0. PINOUT 3.1. Pentium® Processor with Voltage Reduction Technology Differences from SPGA 3.3V Pentium Processor 3.2. Pinout Descriptions 3.2.1. PENTIUM® PROCESSOR PINOUT 3.2.2. CROSS REFERENCE TABLE PENTIUM® PROCESSOR_9 3.3. Design Notes_13 3.4. Quick Reference 3.5. Reference Tables 3.6. Grouping According Function 4.0. PENTIUM® PROCESSOR ELECTRICAL SPECIFICATIONS 4.1. Maximum Ratings 4.2. Specifications 4.2.1. POWER SEQUENCING 4.3. Specifications 4.3.1. POWER GROUND 4.3.2. DECOUPLING RECOMMENDATIONS 4.3.3. CONNECTION SPECIFICATIONS 4.3.4. TIMINGS 50-MHZ 4.3.5. TIMINGS 60-MHZ 4.3.6. TIMINGS 66-MHZ 4.4. Buffer Models_47 4.4.1. BUFFER MODEL PARAMETERS_51 4.4.2. SIGNAL QUALITY SPECIFICATIONS_52 4.4.2.1. Ringback 4.4.2.2. Settling Time
5.0. PENTIUM® PROCESSOR MECHANICAL SPECIFICATIONS_ 5.1. Mechanical Diagrams_ 6.0. PENTIUM® PROCESSOR THERMAL SPECIFICATIONS 6.1. Measuring Thermal Values_ 6.2. Thermal Equations 6.3. Thermal Characteristics 6.4. Board Enhancements_ 6.4.1. STANDARD TEST BOARD CONFIGURATION 7.0. SPGA PENTIUM® PROCESSOR SPECIFICATIONS_ 7.1. SPGA Pentium® Processor with Voltage Reduction Technology Differences from 3.3V Pentium Processor_ 7.1.1. Features Removed 7.1.2. Maximum Rating 7.1.3. Specifications 7.1.3.1 Power Sequencing_ 7.1.4. Specifications 7.1.4.1. Power Ground 7.1.4.2. Decoupling Recommendations_ 7.1.4.3. Connection Specifications 7.1.4.4. Timings 7.1.5. Thermal Specifications 7.1.6. SPGA Package Differences 7.1.6.1 Pinout_ 7.1.6.2. Package Dimensions 7.1.7. Buffer Models_
1.0.
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
INTRODUCTION
2.0.
MICROPROCESSOR ARCHITECTURE OVERVIEW
Intel manufacturing reduced power version latest Pentium® processor, Pentium processor with voltage reduction technology, targeting mobile market. Voltage reduction technology allows processor "talk" industry standard 3.3-volt components while inner core, operating volts, consumes less power promote longer battery life. Pentium processor with voltage reduction technology offered Tape Carrier Package (TCP) Staggered Grid Array (SPGA) package. advanced features 3.3V Pentium except differences listed sections 7.1.1. Pentium processor with voltage reduction technology several features which allow highperformance notebooks designed with Pentium processor, including following: dimensions ideal small form-factor designs. superior characteristics. thermal resistance
Pentium processor with voltage reduction technology extends Intel Pentium family microprocessors. compatible with host other Intel products. Pentium processor family consists Pentium processor with voltage reduction technology described this document, original mobile Pentium processor various desktop Pentium processors. "Pentium processor" will used this document refer entire Pentium processor family general. mobile Pentium processor family architecture contains features Intel486 family, provides significant enhancements additions including following: Superscalar Architecture Dynamic Branch Prediction Pipelined Floating-Point Unit Improved Instruction Execution Time Separate Code Data Caches Writeback MESI Protocol Data Cache 64-Bit Data Cycle Pipelining Address Parity Internal Parity Checking Execution Tracing Performance Monitoring IEEE 1149.1 Boundary Scan System Management Mode Virtual Mode Extensions Voltage Reduction Technology Power Management Features
2.9V core 3.3V buffer inputs reduce power consumption significantly, while maintaining 3.3V compatibility externally. Enhanced feature set, which initially implemented Intel486CPU. architecture internal features Pentium processor with voltage reduction technology identical desktop version Pentium processor specifications provided Pentium® Processor Family Developer's Manual, Volume Pentium Processors., except several features used mobile applications have been eliminated streamline mobile applications. This document should used conjunction with following related Pentium processor documents.
Pentium® Processor Family Developer's Manual, Volume Pentium Processors (Order Number: 241428) Pentium® Processor Family Developer's Manual, Volume Architecture Programming Manual (Order Number: 241430)
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
2.1.
Mobile Pentium® Processor Family Architecture
application instruction Pentium processor family includes complete Intel486 family instruction with extensions accommodate some additional functionality Pentium processors. application software written Intel386 Intel486 family microprocessors will Pentium processors without modification. on-chip memory management unit (MMU) completely compatible with Intel386 family Intel486 family CPUs. Pentium processors implement several enhancements increase performance. instruction pipelines floating-point unit Pentium processors capable independent operation. Each pipeline issues frequently used instructions single clock. Together, dual pipes issue integer instructions clock, floating point instruction (under certain circumstances, floating-point instructions) clock. Branch prediction implemented Pentium processors. support this, Pentium processors implement prefetch buffers, prefetch code linear fashion, that prefetches code according Branch Target Buffer (BTB) needed code almost always prefetched before needed execution. floating-point unit been completely redesigned over Intel486 CPU. Faster algorithms provide speed-up common operations including add, multiply load. Pentium processors include separate code data caches integrated on-chip meet performance goals. Each cache Kbytes size, with 32-byte line size 2-way associative. Each cache dedicated Translation Lookaside Buffer (TLB) translate linear addresses physical addresses. data cache configurable writeback writethrough line-by-line basis follows MESI protocol. data cache tags triple-ported support data transfers inquire
cycle same clock. code cache inherently write-protected cache. code cache tags also triple ported support snooping split line accesses. Individual pages configured cacheable non-cacheable software hardware. caches enabled disabled software hardware. Pentium processors have increased data bits improve data transfer rate. Burst read burst writeback cycles supported Pentium processors. addition, cycle pipelining been added allow cycles progress simultaneously. Pentium processors' contains optional extensions architecture which allow 2-Mbyte 4-Mbyte page sizes. Pentium processors have added significant data integrity error detection capability. Data parity checking still supported byte-by-byte basis. Address parity checking internal parity checking features have been added along with exception, machine check exception. more more functions integrated chip, complexity board level testing increased. address this, Pentium processors have increased test debug capability. Pentium processors implement IEEE Boundary Scan (Standard 1149.1). addition, Pentium processors have specified four breakpoint pins that correspond each debug registers externally indicate breakpoint match. Execution tracing provides external indications when instruction completed execution either internal pipelines, when branch been taken. System Management Mode (SMM) been implemented along with some extensions architecture. Enhancements virtual 8086 mode have been made increase performance reducing number times necessary trap virtual 8086 monitor.
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
255702
Figure Pentium® Processor Block Diagram
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Figure shows block diagram Pentium processor. block diagram shows instruction pipelines, pipe pipe. u-pipe execute integer floating point instructions. v-pipe execute simple integer instructions FXCH floating-point instructions. separate caches shown, code cache data cache. data cache ports, each pipes (the tags triple ported allow simultaneous inquire cycles). data cache dedicated Translation Lookaside Buffer (TLB) translate linear addresses physical addresses used data cache. code cache, branch target buffer prefetch buffers responsible getting instructions into execution units Pentium processor. Instructions fetched from code cache from external bus. Branch addresses remembered branch target buffer. code cache translates linear addresses physical addresses used code cache. decode unit decodes prefetched instructions Pentium processor execute instruction. control contains microcode which controls sequence operations that must performed implement Pentium processor
architecture. control unit direct control over both pipelines. Pentium processors contain pipelined floatingpoint unit that provides significant floating-point performance advantage over previous generations processors. architectural features introduced this section more fully described Pentium® Processor Family Developer's Manual, Volume
3.0. 3.1.
PINOUT Pentium® Processor with Voltage Reduction Technology Differences from SPGA 3.3V Pentium Processor
better streamline part mobile applications, following features have been eliminated from SPGA Pentium processor with voltage reduction technology: Upgrade, Dual Processing (DP), APIC Master/Checker functional redundancy. Table lists corresponding pins which exist SPGA 3.3V Pentium processor have been removed SPGA Pentium processor with voltage reduction technology.
ADSC# BRDYC# CPUTYP D/P# FRCMC# PBGNT# PBREQ# PHIT# PHITM# PICCLK PICD0 [DPEN#] PICD1 [APICEN]
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table Signals Removed Pentium® Processor with Voltage Reduction Technology Signal Function Additional Address Status. This signal mainly used large standalone cache memory subsystem support required high-performance desktop server models. Additional Burst Ready. This signal mainly used large standalone cache memory subsystem support required high-performance desktop server models. Type. This signal used dual processing systems. Dual/Primary processor identification. This signal only used upgrade processor. Functional Redundancy Checking. This signal only used error detection processor redundancy, requires Pentium processors (master/checker). Private Grant. This signal only used dual processing systems. Private Request. This signal used only dual processing systems. Private Hit. This signal only used dual processing systems. Private Modified Hit. This signal only used dual processing systems. APIC Clock. This signal APIC interrupt controller serial data clock. APIC's Programmable Interrupt Controller Data line PICD0 shares with DPEN# (Dual Processing Enable). APIC's Programmable Interrupt Controller Data line PICD1 shares with APICEN (APIC Enable RESET)).
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
3.2.
3.2.1.
Pinout Descriptions
PENTIUM® PROCESSOR PINOUT
VCC2 VCC3 VCC2 VCC3 VCC3 VCC2 VCC3 VCC2 VCC3 VCC3 VCC3 R/S# INTR SMI# VCC2 IGNNE# INIT PEN# VCC2 VCC2 VCC2 STPCLK# VCC2 VCC3 VCC2 VCC2 VCC2 VCC2 VCC2 TRST# VCC2
VCC2 VCC3 HOLD WB/WT# VCC2 BOFF# BRDY# VCC2 KEN# AHOLD EWBE# VCC2 VCC3 CACHE# M/IO# VCC3 VCC2 PM1/BP1 PM0/BP0 FERR# VCC2 IERR# VCC3 VCC2 VCC3 VCC2 VCC3 VCC2 VCC3 VCC2 VCC3 VCC3 VCC3
VCC3 VCC3 VCC3 VCC3 VCC3 VCC2 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2 VCC2 VCC3
SMIACT# PRDY VCC2 PCHK# APCHK# VCC3 BREQ HLDA VCC2 VCC3 VCC2 LOCK# VCC3 D/C# EADS# ADS# VCC3 HITM# HIT# VCC3 W/R# BUSCHK# FLUSH# A20M# BE0# BE1# BE2# BE3# VCC3 BE4# BE5# BE6# BE7# VCC3 SCYC RESET VCC2 VCC2 VCC3 VCC2 VCC3 VCC2 VCC3 VCC2 VCC3 VCC2 VCC3
Figure Pentium® Processor Pinout
Pentium® Processor with Voltage Reduction Technology Pinout
255701
3.2.2.
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
PENTIUM® PROCESSOR CROSS REFERENCE TABLE Table Cross Reference Name Address Data
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table Cross Reference Name (Contd.) Control A20M# ADS# AHOLD APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BRDY# BREQ BUSCHK# CACHE# D/C# EADS# EWBE# FERR# FLUSH# HIT# HITM# HLDA HOLD IERR# IGNNE# INIT INTR/LINT0 KEN# LOCK# M/IO# NMI/LINT1 PCHK# PEN# PM0/BP0 Clock Control STPCLK# PM1/BP1 PRDY R/S# RESET SCYC SMI# SMIACT# TRST# W/R# WB/WT#
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table Cross Reference Name (Contd.) VCC2* VCC3**
NOTE: These VCC2 pins 2.9V inputs Pentium processor with voltage reduction technology, change different voltage future offerings this microprocessor family. VCC3 pins will remain 3.3V power inputs Pentium processor.
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table Cross Reference Name (Contd.)
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table Cross Reference Number (Pins 1-160)
Signal VCC2 VCC3 HOLD WB/WT# VCC2 Signal VCC2 VCC3 VCC2 VCC3 VCC2 VCC3 VCC2 VCC3 VCC3 VCC3 Signal VCC3 VCC3 VCC3 VCC3 VCC3 VCC2 VCC3 Signal VCC3 VCC3 VCC3 VCC3 VCC3 VCC2 VCC2 VCC3
BOFF# BRDY# VCC2 KEN# AHOLD EWBE# VCC2 VCC3 CACHE# M/IO# VCC3 VCC2 PM1/BP1 PM0/BP0 FERR# VCC2 IERR# VCC3
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Signal VCC3 BE3# BE2# BE1# BE0# A20M# FLUSH# BUSCHK# W/R# VCC3 HIT# HITM# VCC3 ADS# EADS# D/C# VCC3 LOCK# VCC2 VCC3 VCC2 HLDA BREQ VCC3 APCHK# PCHK# VCC2 PRDY SMIACT#
Table Cross Reference Number (Pins 161-320) (Contd.)
NOTE: VCC2 pins 2.9V power inputs core. VCC3 pins 3.3V power inputs core. Signal VCC2 TRST# VCC2 VCC2 VCC2 VCC2 VCC2 VCC3 VCC2 STPCLK# VCC2 VCC2 VCC2 PEN# INIT IGNNE# VCC2 SMI# INTR R/S# Signal VCC3 VCC3 VCC3 VCC2 VCC3 VCC2 VCC3 VCC3 VCC2 VCC3 VCC2 Signal VCC3 VCC2 VCC3 VCC2 VCC3 VCC2 VCC3 VCC2 VCC3 VCC2 VCC2 RESET SCYC VCC3 BE7# BE6# BE5# BE4#
3.3. 3.4.
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Design Notes
"Hardware Interface" chapter Pentium® Processor Family Developer's Manual, Volume Note that input pins must meet their AC/DC specifications guarantee proper functional behavior. symbol signal name indicates that active asserted state occurs when signal voltage. When symbol present after signal name, signal active, asserted high voltage level. pins classified Input Output based their function Master Mode. Error Detection chapter Pentium Processor Family Developer's Manual, Volume Pentium Processors, further information.
reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected VCC3. Unused active HIGH inputs should connected (VSS). Connect (NC) pins must remain unconnected. Connection pins result component failure incompatibility with processor steppings.
Quick Reference
This section gives brief functional description each pins. detailed description,
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table Quick Reference Symbol A20M# Type Name Function When address mask asserted, Pentium processor emulates address wraparound Mbyte which occurs 8086. When A20M# asserted, processor masks physical address (A20) before performing lookup internal caches driving memory cycle bus. effect A20M# undefined protected mode. A20M# must asserted only when processor real mode. outputs, address lines processor along with byte enables define physical area memory accessed. external system drives inquire address processor A31-A5. address status indicates that valid cycle currently being driven processor. response assertion address hold, processor will stop driving address lines (A31-A3), next clock. rest will remain active data returned driven previously issued cycles. Address parity driven processor with even parity information processor generated cycles same clock that address driven. Even parity must driven back processor during inquire cycles this same clock EADS# ensure that correct parity check status indicated. address parity check status asserted clocks after EADS# sampled active processor detected parity error address during inquire cycles. APCHK# will remain active clock each time parity error detected. byte enable pins used determine which bytes must written external memory, which bytes were requested current cycle. byte enables driven same clock address lines (A31-3). Frequency determines bus-to-core ratio. sampled RESET, cannot changed until another non-warm assertion RESET. Additionally, must change values while RESET active. proper operation processor, this should strapped high low. When strapped VCC, processor will operate bus/core frequency ratio. When strapped VSS, processor will operate bus/core frequency ratio. left floating, processor defaults bus/core ratio. backoff input used abort outstanding cycles that have completed. response BOFF#, processor will float pins normally floated during hold next clock. processor remains hold until BOFF# negated, which time Pentium processor restarts aborted cycle(s) their entirety. breakpoint pins (BP3-0) correspond debug registers, DR3-DR0. These pins externally indicate breakpoint match when debug registers programmed test breakpoint matches. multiplexed with performance monitoring pins (PM1 PM0). bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring.
A31-A3
ADS# AHOLD
APCHK#
BE7#-BE5# BE4#-BE0#
BOFF#
BP[3:2] PM/BP[1:0]
Symbol BRDY# Type BREQ BUSCHK# CACHE#
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table Quick Reference (Contd.) Name Function burst ready input indicates that external system presented valid data data pins response read that external system accepted processor data response write request. This signal sampled states. request output indicates external system that processor internally generated request. This signal always driven whether processor driving bus. check input allows system signal unsuccessful completion cycle. this sampled active, processor will latch address control signals machine check registers. addition, set, processor will vector machine check exception. processor-initiated cycles, cache indicates internal cacheability cycle read), indicates burst writeback cycle write). this driven inactive during read cycle, processor will cache returned data, regardless state KEN# pin. This also used determine cycle length (number transfers cycle). clock input provides fundamental timing processor. frequency operating frequency processor external requires levels. external timing parameters except TDI, TDO, TMS, TRST# PICD0-1 specified with respect rising edge CLK. NOTE: recommended that begin after reaches proper operating level. This recommendation only assure long term reliability device. D/C# data/code output primary cycle definition pins. driven valid same clock ADS# signal asserted. D/C# distinguishes between data code special cycles. These data lines processor. Lines D7-D0 define least significant byte data bus; lines D63-D56 define most significant byte data bus. When driving data lines, they driven during clocks that cycle. During reads, samples data when BRDY# returned. These data parity pins processor. There each byte data bus. They driven processor with even parity information writes same clock write data. Even parity information must driven back Pentium processor with voltage reduction technology these pins same clock data ensure that correct parity check status indicated processor. applies D63-D56; applies D7-D0. This signal indicates that valid external address been driven onto processor address pins used inquire cycle.
D63-D0
DP7-DP0
EADS#
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table Quick Reference (Contd.) Symbol EWBE# Type Name Function external write buffer empty input, when inactive (high), indicates that write cycle pending external system. When processor generates write EWBE# sampled inactive, processor will hold subsequent writes M-state lines data cache until write cycles have completed, indicated EWBE# being active. floating point error driven active when unmasked floating point error occurs. FERR# similar ERROR# Intel387math coprocessor. FERR# included compatibility with systems using DOS-type floating point error reporting. When asserted, cache flush input forces processor write back modified lines data cache invalidate internal caches. Flush Acknowledge special cycle will generated processor indicating completion writeback invalidation. NOTE: FLUSH# sampled when RESET transitions from high low, tristate test mode entered. HIT# indication driven reflect outcome inquire cycle. inquire cycle hits valid line either data instruction cache, this asserted clocks after EADS# sampled asserted. inquire cycle misses cache, this negated clocks after EADS#. This changes value only result inquire cycle retains value between cycles. modified line output driven reflect outcome inquire cycle. asserted after inquire cycles which resulted modified line data cache. used inhibit another master from accessing data until line completely written back. hold acknowledge goes active response hold request driven processor HOLD pin. indicates that processor floated most output pins relinquished another local master. When leaving hold, HLDA will driven inactive processor will resume driving bus. processor cycle pending, will driven same clock that HLDA de-asserted. response hold request, processor will float most output input/output pins assert HLDA after completing outstanding cycles. processor will maintain this state until HOLD de-asserted. HOLD recognized during LOCK cycles. processor will recognize HOLD during reset. internal error used indicate internal parity errors. parity error occurs read from internal array, processor will assert IERR# clock then shutdown.
FERR#
FLUSH#
HITM#
HLDA
HOLD
IERR#
Symbol IGNNE# Type INIT
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table Quick Reference (Contd.) Name Function This ignore numeric error input. This effect when When CR0.NE IGNNE# asserted, processor will ignore pending unmasked numeric exception continue executing floating-point instructions entire duration that this asserted. When CR0.NE IGNNE# asserted, pending unmasked numeric exception exists (SW.ES floating-point instruction FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, FSETPM, processor will execute instruction spite pending exception. When CR0.NE IGNNE# asserted, pending unmasked numeric exception exists (SW.ES floating-point instruction other than FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, FSETPM, processor will stop execution wait external interrupt. processor initialization input forces processor begin execution known state. processor state after INIT same state after RESET except that internal caches, write buffers, floating point registers retain values they prior INIT. INIT used lieu RESET after power INIT sampled high when RESET transitions from high low, processor will perform built-in self test prior start program execution. INTR active maskable interrupt input indicates that external interrupt been generated. EFLAGS register set, processor will generate locked interrupt acknowledge cycles vector interrupt handler after current instruction execution completed. INTR must remain active until first interrupt acknowledge cycle generated assure that interrupt recognized. invalidation input determines final cache line state case inquire cycle hit. sampled together with address inquire cycle clock EADS# sampled active. cache enable used determine whether current cycle cacheable consequently used determine cycle length. When processor generates cycle that cached (CACHE# asserted) KEN# active, cycle will transformed into burst line fill cycle. lock indicates that current cycle locked. processor will allow hold when LOCK# asserted (but AHOLD BOFF# allowed). LOCK# goes active first clock first locked cycle goes inactive after BRDY# returned last locked cycle. LOCK# guaranteed de-asserted least clock between back-to-back locked cycles. memory/input-output primary cycle definition pins. driven valid same clock ADS# signal asserted. M/IO# distinguishes between memory cycles.
KEN#
LOCK#
M/IO#
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table Quick Reference (Contd.) Symbol Type Name Function active next address input indicates that external memory system ready accept cycle although data transfers current cycle have completed. processor will issue ADS# pending cycle clocks after asserted. processor supports outstanding cycles. non-maskable interrupt request signal indicates that external nonmaskable interrupt been generated. page cache disable reflects state CR3; Page Directory Entry Page Table Entry. purpose provide external cacheability indication page-by-page basis. parity check output indicates result parity check data read. driven with parity status clocks after BRDY# returned. PCHK# remains clock each clock which parity error detected. Parity checked only bytes which valid data returned. parity enable input (along with CR4.MCE) determines whether machine check exception will taken result data parity error read cycle. this sampled active clock, data parity error detected. processor will latch address control signals cycle with parity error machine check registers. addition, machine check enable "1", processor will vector machine check exception before beginning next instruction. These pins function part performance monitoring feature. breakpoint pins multiplexed with performance monitoring pins. bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring. PRDY probe ready output indicates that processor stopped normal execution response R/S# going active Probe Mode being entered. page writethrough reflects state CR3, page directory entry, page table entry. used provide external writeback indication page-by-page basis. stop input asynchronous, edge-sensitive interrupt used stop normal execution processor place into idle state. high transition R/S# will interrupt processor cause stop execution next instruction boundary. RESET forces processor begin execution known state. processor internal caches will invalidated upon RESET. Modified lines data cache written back. FLUSH# INIT sampled when RESET transitions from high determine tristate test mode will entered BIST will run. split cycle output asserted during misaligned LOCKed transfers indicate that more than cycles will locked together. This signal defined locked cycles only. undefined cycles which locked.
PCHK#
PEN#
PM/BP[1:0]
R/S#
RESET
SCYC
Symbol SMI# Type SMIACT# STPCLK#
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table Quick Reference (Contd.) Name Function system management interrupt causes system management interrupt request latched internally. When latched SMI# recognized instruction boundary, processor enters System Management Mode. active system management interrupt active output indicates that processor operating System Management Mode. Assertion stop clock input signifies request stop internal clock Pentium processor with voltage reduction technology thereby causing core consume less power. When recognizes STPCLK#, processor will stop execution next instruction boundary, unless superseded higher priority interrupt, generate Stop Grant Acknowledge cycle. When STPCLK# asserted, processor will still respond external snoop requests. testability clock input provides clocking function processor boundary scan accordance with IEEE Boundary Scan interface (Standard 1149.1). used clock state information data into processor during boundary scan. test data input serial input test logic. instructions data shifted into processor rising edge when controller appropriate state. test data output serial output test logic. instructions data shifted processor TCK's falling edge when controller appropriate state. value test mode select input signal sampled rising edge controls sequence controller state changes. When asserted, test reset input allows controller asynchronously initialized. These pins 2.9V power inputs Pentium processor with voltage reduction technology. These pins 3.3V power inputs Pentium processor with voltage reduction technology. These pins ground inputs Pentium processor with voltage reduction technology. Write/read primary cycle definition pins. driven valid same clock ADS# signal asserted. W/R# distinguishes between write read cycles. writeback/writethrough input allows data cache line defined writeback writethrough line-by-line basis. result, determines whether cache line initially state data cache.
TRST# VCC2 VCC3 W/R#
WB/WT#
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
3.5.
Reference Tables
Table Output Pins Name Active Level High High High High High High Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF#
When Floated Hold, BOFF#
ADS# APCHK# BE7#-BE5# BREQ CACHE# FERR# HIT# HITM# HLDA IERR# LOCK# M/IO#, D/C#, W/R# PCHK# BP3-2, PM1/BP1, PM0/BP0 PRDY PWT, SCYC SMIACT#
states except Shift-DR Shift-IR
NOTE: output input/output pins floated during tristate test mode (except TDO).
Name A20M# AHOLD BOFF# BRDY# BUSCHK# EADS# EWBE# FLUSH# HOLD IGNNE# INIT INTR KEN# PEN# R/S# RESET SMI# STPCLK# TRST# WB/WT#
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table Input Pins Active Level High High High High High High High High Synchronous/TCK Synchronous/TCK Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Pullup Pullup Pullup Pullup Pullup Pullup First BRDY#/NA# Pullup BRDY# EADS# First BRDY#/NA# State T2,TD,T2P BRDY# Synchronous/ Asynchronous Asynchronous Synchronous Synchronous/RESET Synchronous Synchronous Synchronous Pullup Pullup State T12, BRDY# Pullup Internal resistor Qualified
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table Input/Output Pins Name A31-A3 BE4#-BE0# D63-D0 DP7-DP0 Active Level When Floated Address Hold, Hold, BOFF# Address Hold, Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Qualified (when input) EADS# EADS# RESET BRDY# BRDY#
Internal Resistor Pulldown*
NOTES: output input/output pins floated during tristate test mode (except TDO). *BE3#-BE0# have pulldowns during RESET only.
3.6.
Clock Initialization Address Data Data Parity
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Grouping According Function
Table organizes pins with respect their function. Table Functional Grouping Function RESET, INIT, A31-A3, BE7# BE0# A20M# D63-D0 APCHK# DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# ADS#, BRDY#, PCD, KEN#, WB/WT# AHOLD, EADS#, HIT#, HITM#, FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA INTR, FERR#, IGNNE# SMI#, SMIACT# TCK, TMS, TDI, TDO, TRST# PM0/BP0, PM1/BP1, BP3-2 STPCLK# R/S#, PRDY Pins
Address Mask
Address Parity
Internal Parity Error System Error Cycle Definition Control Page Cacheability Cache Control Cache Snooping/Consistency Cache Flush Write Ordering Arbitration Interrupts Floating Point Error Reporting System Management Mode Port Breakpoint/Performance Monitoring Clock Control Probe Mode
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4.0.
PENTIUM® PROCESSOR ELECTRICAL SPECIFICATIONS Maximum Ratings
WARNING Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only. Operation beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" affect device reliability.
4.1.
following values stress ratings only. Functional operation maximum ratings implied guaranteed. Functional operating conditions given specification tables. Extended exposure maximum ratings affect device reliability. Furthermore, although Pentium processor with voltage reduction technology contains protective circuitry resist damage from static electric discharge, always take precautions avoid high static voltages electric fields. Case temperature under bias_-65°C 110°C Storage temperature_-65°C 150°C Supply voltage with respect -0.5V +4.6V 2.9V Supply voltage with respect -0.5V +4.1V Only Buffer Input Voltage -0.5V VCC3 +0.5; exceed 4.6V Safe Buffer Input Voltage -0.5V 6.5V (1,3)
NOTES: Applies CLK. Applies Pentium processors with voltage reduction technology inputs except CLK. Table
4.2.
Specifications
Tables list specifications which apply Pentium processor with voltage reduction technology. Pentium processor with voltage reduction technology core operates 2.9V internally while interface operates 3.3V. input 3.3V Since 3.3V safe) input levels defined Table same levels, input compatible with existing clock drivers. power dissipation specification Table provided design thermal solutions during operation sustained maximum level. This worst-case power device would dissipate system sustained period time. This number used design thermal solution device. 4.2.1. POWER SEQUENCING
There specific sequence required powering powering down VCC2 VCC3 power supplies. However, compatibility with future mobile processors, recommended that VCC2 VCC3 power supplies either both both within second each other.
Symbol VIL3 VIH3 VOL3 VOH3 ICC2 ICC3
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Table 3.3V Specifications
TCASE 95°C; VCC2 2.9V ±165mV; VCC3 3.3V ±165mV Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage Power Supply Current from 2.9V core supply Power Supply Current from 3.3V buffer supply 2096 2515 2800 -0.3 VCC3+0.3 Unit Notes Level Level Level Level @100 @100
NOTES: Parameter measured Parameter measured 3.3V levels apply signals except CLK. This value should used power supply design. determined using worst-case instruction VCC+165mV. Power supply transient response decoupling capacitors must sufficient handle instantaneous current changes occurring during transitions from stop clock full active modes. more information, refer section 4.3.2. lower power number process improvement. Refer document 242557 process specification.
Table 3.3V Safe) Specifications Symbol VIL5 VIH5 Parameter Input Voltage Input High Voltage -0.3 5.55 Unit Notes Level Level
NOTES: Applies only.
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Table Input Output Characteristics Symbol CI/O CCLK CTIN CTOUT CTCK Parameter Input Capacitance Output Capacitance Capacitance Input Capacitance Test Input Capacitance Test Output Capacitance Test Clock Capacitance Input Leakage Current Output Leakage Current Input Leakage Current Input Leakage Current -400 Unit
Notes
VCC3 VCC3 2.4V 0.4V
NOTES: This parameter input without pull pull down. This parameter input with pull This parameter input with pull down. Guaranteed design.
Table Power Dissipation Requirements Thermal Solution Design Parameter Active Power Dissipation Typical(1) 2.0-3.0 2.5-3.5 2.8-3.9 Max(2) 0.05 Unit Watts Watts Watts Watts Watts Watts Watts Notes @100 @100
Stop Grant Auto Halt Powerdown Power Dissipation Stop Clock Power Dissipation
NOTES: This typical power dissipation system. This value average value measured system using typical device VCC2 2.9V VCC3 3.3V running typical applications. This value highly dependent upon specific system configuration. Systems must designed thermally dissipate maximum active power dissipation. determined using worstcase instruction with VCC2 2.9V VCC3 3.3V. nominal this measurement takes into account thermal time constant package. Stop Grant/Auto Halt Powerdown Power Dissipation determined asserting STPCLK# executing HALT instruction. Stop Clock Power Dissipation determined asserting STPCLK# then removing external input. Refer document 242557 process specification.
4.3.
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performance. Inductance reduced shortening circuit board traces between processor decoupling capacitors much possible. These capacitors should evenly distributed around each component 3.3V plane 2.9V plane island). Capacitor values should chosen ensure they eliminate both high frequency noise components. Power transients also occur processor rapidly transitions from level power consumption much higher level high power). typical example would entering exiting Stop Grant state. Another example would executing HALT instruction, causing processor enter Auto HALT Powerdown state, transitioning from HALT Normal state. these examples cause abrupt changes power being consumed processor. Note that Auto HALT Powerdown feature always enabled even when other power management features implemented. Bulk storage capacitors with (Effective Series Resistance) range required maintain regulated supply voltage during interval between time current load changes point that regulated power supply output react change load. order reduce ESR, necessary place several bulk storage capacitors parallel. These capacitors should placed near processor 3.3V plane 2.9V plane island)) ensure that these supply voltages stay within specified limits during changes supply current during operation. more detailed information, please contact Intel refer Pentium® Processor with Voltage Reduction Technology: Power Supply Design Considerations Mobile Systems application note (Order Number 242558). 4.3.3. CONNECTION SPECIFICATIONS
Specifications
specifications Pentium processor with voltage reduction technology consist setup times, hold times, valid delays Pentium processor with voltage reduction technology specifications valid VCC2 2.9V ±165mV, VCC3 3.3V ±165mV Tcase 95°C. WARNING exceed 75-MHz Pentium processor with voltage reduction technology internal maximum frequency either selecting fraction providing clock greater than MHz. exceed 90-MHz Pentium processor with voltage reduction technology internal maximum frequency either selecting fraction providing clock greater than MHz. 4.3.1. POWER GROUND
clean on-chip power distribution, Pentium processor with voltage reduction technology VCC2 (2.9V power), VCC3 (3.3V power) (ground) inputs. Power ground connections must made external VCC2, VCC3 pins Pentium processor with voltage reduction technology. circuit board VCC2 pins must connected 2.9V VCC2 plane island) VCC3 pins must connected 3.3V VCC3 plane. pins must connected plane. Please refer Table list VCC2, VCC3 pins. 4.3.2. DECOUPLING RECOMMENDATIONS
Transient power surges occur processor executing instruction sequences driving large loads. mitigate these high frequency transients, liberal high frequency decoupling capacitors should placed near processor. inductance capacitors interconnects recommended best high frequency electrical
pins must remain unconnected. reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected VCC3. Unused active high inputs should connected ground.
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4.3.4. TIMINGS 50-MHZ
signals) relative rising edge input. timings referenced 1.5V both logic levels unless otherwise specified. Within sampling window, synchronous input must stable correct operation.
Notes
specifications given Table consist output delays, input setup requirements input hold requirements 50-MHz external bus. specifications (with exception those
Table Mobile Pentium® Processor Specifications 50-MHz Operation
VCC2 2.9V ±165mV, VCC3 3.3V ±165mV, TCASE 95°C, SPGA TCASE 85°C,
Symbol Frequency Period
Parameter
25.0 20.0
50.0 40.0 ±250
Unit
Figure
(1), (19) @2V, @0.8V, (2.0V-0.8V), (1), (0.8V-2.0V), (1), (22)
Period Stability High Time Time Fall Time Rise Time ADS#, PWT, PCD, BE0-7#, M/IO#, D/C#, CACHE#, SCYC, W/R# Valid Delay Valid Delay A3-A31, LOCK# Valid Delay 0.15 0.15
(22) (22)
Symbol t10a t10b t11a t11b t16a t16b t18a t18b t22a
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Table Mobile Pentium® ProcessorAC Specifications 50-MHz Operation (Contd.)
VCC2 2.9V ±165mV, VCC3 3.3V ±165mV, TCASE 95°C, SPGA TCASE 85°C,
Parameter ADS#, A3-A31, PWT, PCD, BE0-7#, M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# Float Delay APCHK#, IERR#, FERR#, PCHK# Valid Delay BREQ, HLDA, SMIACT# Valid Delay HIT# Valid Delay HITM# Valid Delay PM0-1, BP0-3 Valid Delay PRDY Valid Delay D0-D63, DP0-7 Write Data Valid Delay D0-D63, DP0-3 Write Data Float Delay A5-A31 Setup Time A5-A31 Hold Time INV, Setup Time EADS# Setup Time EADS#, INV, Hold Time KEN# Setup Time NA#, WB/WT# Setup Time KEN#, WB/WT#, Hold Time BRDY# Setup Time BRDY# Hold Time BOFF# Setup Time AHOLD Setup Time AHOLD, BOFF# Hold Time
10.0
Unit
Figure
Notes (1), (22)
10.0 10.0
(4), (22) (4), (22) (22) (22) (22) (22) (22) (20)
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Notes (11), (15) (12) (11), (15), (16)
Table Mobile Pentium® Processor Specifications 50-MHz Operation (Contd.)
VCC2 2.9V ±165mV, VCC3 3.3V ±165mV, TCASE 95°C, SPGA TCASE 85°C,
Symbol t25a
Parameter BUSCHK#, EWBE#, HOLD, PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time A20M#, INTR, STPCLK# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R/S# Setup Time R/S# Hold Time R/S# Pulse Width, Async. D0-D63, DP0-7 Read Data Setup Time D0-D63, DP0-7 Read Data Hold Time RESET Setup Time RESET Hold Time RESET Pulse Width, Stable RESET Active After Stable Reset Configuration Signals (INIT, FLUSH#) Setup Time Reset Configuration Signals (INIT, FLUSH#) Hold Time
Unit
Figure
CLKs CLKs CLKs
(12) (14), (16) (11), (15), (16) (12) (14), (16)
(11), (15) (12) (16) Power (11), (15), (16) (12)
Symbol t42a t42b t42c t42d
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Table Mobile Pentium® Processor Specifications 50-MHz Operation (Contd.)
VCC2 2.9V ±165mV, VCC3 3.3V ±165mV, TCASE 95°C, SPGA TCASE 85°C,
Parameter Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. Reset Configuration Signals (INIT, FLUSH#, BRDY#, BUSCHK#) Hold Time, Async. Reset Configuration Signal (BRDY#, BUSCHK#) Setup Time, Async. Reset Configuration Signal BRDY# Hold Time, RESET driven synchronously Setup Time Hold Time Frequency Period High Time Time Fall Time Rise Time TRST# Pulse Width TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Non-Test Outputs Valid Delay
Unit CLKs CLKs
Figure
Notes RESET falling edge (15) RESET falling edge (21) RESET falling edge (21) RESET falling edge (1), (21)
CLKs
t43a t43b
62.5 25.0 25.0 40.0 13.0 20.0 25.0 20.0 16.0
CLKs
(18) RESET falling edge (18) RESET falling edge
@2V, @0.8V, (2.0V-0.8V), (1), (8), (0.8V-2.0V), (1), (8), (1), Asynchronous (1), (3), (8), (10)
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Notes (1), (3), (8), (10) (3), (7), (10) (3), (7), (10)
Table Mobile Pentium® Processor Specifications 50-MHz Operation (Contd.)
VCC2 2.9V ±165mV, VCC3 3.3V ±165mV, TCASE 95°C, SPGA TCASE 85°C,
Symbol
Parameter Non-Test Outputs Float Delay Non-Test Inputs Setup Time Non-Test Inputs Hold Time
25.0
Unit
Figure
13.0
4.3.5.
TIMINGS 60-MHZ
signals) relative rising edge input. timings referenced 1.5V both logic levels unless otherwise specified. Within sampling window, synchronous input must stable correct operation.
specifications given Table consists output delays, input setup requirements input hold requirements 60-MHz external bus. specifications (with exception those signals APIC
Table Mobile Pentium® Processor with Voltage Reduction Technology Specifications 60-MHz Operation
VCC2 2.9V ±165mV, VCC3 3.3V ±165mV, TCASE 95°C, SPGA TCASE 85°C,
Symbol Frequency Period
Parameter
30.0 16.67
60.0 33.33 ±250
Unit
Figure
Notes
(1), (19) @2V, @0.8V, (2.0V-0.8V), (1), (0.8V-2.0V), (1), (22)
Period Stability High Time Time Fall Time Rise Time ADS#, PWT, PCD, BE0-7#, M/IO#, D/C#, CACHE#, SCYC, W/R# Valid Delay Valid Delay LOCK# Valid Delay A3-A31 Valid Delay 0.15 0.15
(22) (22) (22)
Symbol t10a t10b t11a t11b t16a t16b t18a t18b
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Table Mobile Pentium® Processor Specifications 60-MHz Operation (Contd.)
VCC2 2.9V ±165mV, VCC3 3.3V ±165mV, TCASE 95°C, SPGA TCASE 85°C,
Parameter ADS#, A3-A31, PWT, PCD, BE0-7#, M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# Float Delay APCHK#, IERR#, FERR# Valid Delay PCHK# Valid Delay BREQ, HLDA Valid Delay SMIACT# Valid Delay HIT# Valid Delay HITM# Valid Delay PM0-1, BP0-3 Valid Delay PRDY Valid Delay D0-D63, DP0-7 Write Data Valid Delay D0-D63, DP0-3 Write Data Float Delay A5-A31 Setup Time A5-A31 Hold Time INV, Setup Time EADS# Setup Time EADS#, INV, Hold Time KEN# Setup Time NA#, WB/WT# Setup Time KEN#, WB/WT#, Hold Time BRDY# Setup Time BRDY# Hold Time AHOLD, BOFF# Setup Time AHOLD, BOFF# Hold Time
10.0
Unit
Figure
Notes (1), (22)
10.0 10.0
(4), (22) (4), (22) (4), (22) (22) (22) (22) (22) (22) (22) (20)
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Table Mobile Pentium® Processor Specifications 60-MHz Operation (Contd.)
Notes
VCC2 2.9V ±165mV, VCC3 3.3V ±165mV, TCASE 95°C, SPGA TCASE 85°C,
Symbol t25a t25b
Parameter BUSCHK#, EWBE#, HOLD, PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time A20M#, INTR, STPCLK# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R/S# Setup Time R/S# Hold Time R/S# Pulse Width, Async. D0-D63, DP0-7 Read Data Setup Time D0-D63, DP0-7 Read Data Hold Time RESET Setup Time RESET Hold Time RESET Pulse Width, Stable RESET Active After Stable Reset Configuration Signals (INIT, FLUSH#) Setup Time Reset Configuration Signals (INIT, FLUSH#) Hold Time
Unit CLKs CLKs CLKs
Figure
(11), (15) (12) (11), (15), (16) (12) (14), (16)
(11), (15), (16) (12) (14), (16)
(11), (15) (12) (16) Power (11), (15), (16) (12)
Symbol t42a t42b t42c t42d t43a t43b
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Table Mobile Pentium® Processor Specifications 60-MHz Operation (Contd.)
VCC2 2.9V ±165mV, VCC3 3.3V ±165mV, TCASE 95°C, SPGA TCASE 85°C,
Parameter Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. Reset Configuration Signals (INIT, FLUSH#, BRDY#, BUSCHK#) Hold Time, Async. Reset Configuration Signal (BRDY#, BUSCHK#) Setup Time, Async. Reset Configuration Signal BRDY# Hold Time, RESET driven synchronously Setup Time Hold Time Frequency Period High Time Time Fall Time Rise Time TRST# Pulse Width TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Non-Test Outputs Valid Delay Non-Test Outputs Float Delay Non-Test Inputs Setup Time Non-Test Inputs Hold Time
Unit CLKs CLKs
Figure
Notes RESET falling edge (15) RESET falling edge (21) RESET falling edge (21) RESET falling edge (1), (21)
CLKs
62.5 25.0 25.0 40.0 13.0 20.0 25.0 20.0 25.0 13.0 16.0
CLKs
(18) RESET falling edge (18) RESET falling edge
@2V, @0.8V, (2.0V-0.8V), (1), (8), (0.8V-2.0V), (1), (8), (1), Asynchronous (1), (3), (8), (10) (1), (3), (8), (10) (3), (7), (10) (3), (7), (10)
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Notes
4.3.6.
TIMINGS 66-MHZ
signals) relative rising edge input. timings referenced 1.5V both logic levels unless otherwise specified. Within sampling window, synchronous input must stable correct operation.
specifications given Table consist output delays, input setup requirements input hold requirements 66-MHz external bus. specifications (with exception those signals APIC
Table Mobile Pentium® Processor Specifications 66-MHz Operation
VCC2 2.9V ±165mV, VCC3 3.3V ±165mV, TCASE 95°C, SPGA TCASE 85°C,
Symbol Frequency Period
Parameter
33.33 15.0
66.6 30.0 ±250
Unit
Figure
(1), (19) @2V, @0.8V, (2.0V-0.8V), (1), (0.8V-2.0V), (1),
Period Stability High Time Time Fall Time Rise Time PWT, PCD, BE0-7#, D/C#, W/R#, CACHE#, SCYC Valid Delay Valid Delay LOCK# Valid Delay ADS# Valid Delay A3-A31 Valid Delay M/IO# Valid Delay ADS#, A3-A31, PWT, PCD, BE0-7#, M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# Float Delay APCHK#, IERR#, FERR# Valid Delay PCHK# Valid Delay BREQ Valid Delay SMIACT# Valid Delay 0.15 0.15
10.0
Symbol t10a t10b t11a t11b t16a t16b t18a t18b t24a t24b t25a t25b
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Table Mobile Pentium® Processor Specifications 66-MHz Operation (Contd.)
VCC2 2.9V ±165mV, VCC3 3.3V ±165mV, TCASE 95°C, SPGA TCASE 85°C,
Parameter HLDA Valid Delay HIT# Valid Delay HITM# Valid Delay PM0-1, BP0-3 Valid Delay PRDY Valid Delay D0-D63, DP0-7 Write Data Valid Delay D0-D63, DP0-3 Write Data Float Delay A5-A31 Setup Time A5-A31 Hold Time INV, Setup Time EADS# Setup Time EADS#, INV, Hold Time KEN# Setup Time NA#, WB/WT# Setup Time KEN#, WB/WT#, Hold Time BRDY# Setup Time BRDY# Hold Time AHOLD, BOFF# Setup Time AHOLD, BOFF# Hold Time BUSCHK#, EWBE#, HOLD, Setup Time PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time A20M#, INTR, STPCLK# Hold Time
10.0 10.0
Unit
Figure (20)
Notes
(11), (15) (12)
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Table Mobile Pentium® Processor Specifications 66-MHz Operation (Contd.)
Notes
VCC2 2.9V ±165mV, VCC3 3.3V ±165mV, TCASE 95°C, SPGA TCASE 85°C,
Symbol t42a
Parameter INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R/S# Setup Time R/S# Hold Time R/S# Pulse Width, Async. D0-D63, DP0-7 Read Data Setup Time D0-D63, DP0-7 Read Data Hold Time RESET Setup Time RESET Hold Time RESET Pulse Width, Stable RESET Active After Stable Reset Configuration Signals (INIT, FLUSH#, FRCMC#) Setup Time Reset Configuration Signals (INIT, FLUSH#, FRCMC#) Hold Time Reset Configuration Signals (INIT, FLUSH#, FRCMC#) Setup Time, Async. Reset Configuration Signals (INIT, FLUSH#, FRCMC#, BRDY#, BUSCHK#) Hold Time, Async. Reset Configuration Signal (BRDY#, BUSCHK#) Setup Time, Async. Reset Configuration Signal BRDY# Hold Time, RESET driven synchronously
15.0
Unit CLKs CLKs CLKs CLKs
Figure
(11), (15), (16) (12) (14), (16)
(11), (15), (16) (12) (14), (16)
(11), (15) (12) (16) Power (11), (15), (16) (12) RESET falling edge (15) RESET falling edge (21) RESET falling edge (21) RESET falling edge (1), (21)
t42b
CLKs
t42c
CLKs
t42d
Symbol t43a t43b t43c t43d
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Table Mobile Pentium® Processor Specifications 66-MHz Operation (Contd.)
VCC2 2.9V ±165mV, VCC3 3.3V ±165mV, TCASE 95°C, SPGA TCASE 85°C,
Parameter CPUTYP Setup Time CPUTYP Hold Time APICEN, BE4# Setup Time APICEN, BE4# Hold Time Frequency Period High Time Time Fall Time Rise Time TRST# Pulse Width TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Non-Test Outputs Valid Delay Non-Test Outputs Float Delay Non-Test Inputs Setup Time Non-Test Inputs Hold Time
62.5 25.0 25.0
Unit CLKs CLKs CLKs
Figure
Notes (18) RESET falling edge (18) RESET falling edge RESET falling edge RESET falling edge
16.0
@2V, @0.8V, (2.0V-0.8V), (1), (8), (0.8V-2.0V), (1), (8), (1), Asynchronous (1), (3), (8), (10) (1), (3), (8), (10) (3), (7), (10) (3), (7), (10)
40.0 13.0 20.0 25.0 20.0 25.0 13.0
NOTES: Notes general apply standard signals used with Pentium processor family. percent tested. Guaranteed design. input test waveforms assumed transitions with 1V/nS rise fall times. Non-test outputs inputs normal output input signals (besides TCK, TRST#, TDI, TDO, TMS). These timings correspond response these signals boundary scan operations. APCHK#, FERR#, HLDA, IERR#, LOCK#, PCHK# glitch-free outputs. Glitch-free signals monotonically transition without false transitions (i.e., glitches). 0.8V/ns input rise/fall time 8V/ns. 0.3V/ns input rise/fall time 5V/ns. Referenced rising edge.
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Referenced falling edge. added maximum rise fall times every frequency below MHz. During probe mode operation, boundary scan timings (t55-58). Setup time required guarantee recognition specific clock. Hold time required guarantee recognition specific clock. timings referenced from 1.5V. guarantee proper asynchronous recognition, signal must have been de-asserted (inactive) minimum clocks before being returned active must meet minimum pulse width. This input driven asynchronously. When driven asynchronously, RESET, NMI, FLUSH#, R/S#, INIT, SMI# must de-asserted (inactive) minimum clocks before being returned active. D/C#, M/IO#, W/R#, CACHE#, A5-A31 signals sampled only that ADS# active. should strapped VCC3 left floating. These signals measured rising edge adjacent CLKs 1.5V. ensure relationship between amplitude input jitter internal external clocks, jitter frequency spectrum should have power spectrum peaking between operating frequency. amount jitter present must accounted component skew between devices. Timing (t14) required external snooping (e.g., address setup which EADS# sampled active). BUSCHK# used reset configuration signal select buffer size. Each valid delay specified load. system designer should buffer modeling account signal flight time delays.
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PP0051
Figure Clock Waveform
PP0052
Figure Valid Delay Timings
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PP0053
Figure Float Delay Timings
PP0054
Figure Setup Hold Timings
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PP0055
Figure Reset Configuration Timings
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Output Signals Input Signals
PP0056
Figure Test Timings
PP0059
Figure Test Reset Timings
4.4.
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input buffers except special group input buffers. second model, Figure represents these special buffers. These buffers inputs: AHOLD, EADS#, KEN#, WB/WT#, INV, NA#, EWBE#, BOFF# CLK. addition input output buffer parameters, input protection diode models provided added accuracy. These diodes have been optimized provide protection provide some level clamping. Although diodes required simulation, more difficult meet specifications without them. Note, however, some signal quality specifications require that diodes removed from input model. series resistors (Rs) part diode model. Remove these when removing diodes from input model.
Buffer Models
This section describes buffer models Pentium processor with voltage reduction technology. first order buffer model simplified representation complex input output buffers used Pentium processor with voltage reduction technology. Figures show structure input buffer model Figure shows output buffer model. Tables show parameters used specify these models. Although simplified, these buffer models will accurately model flight time signal quality. these parameters, there very little added accuracy complete transistor model. following models represent input buffer models. first model, Figure represents
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Note: Figure refers buffer VCC3.
PP0059
Figure Input Buffer Model, Except Special Group
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Vcc2
PP0060
Figure Input Buffer Model Special Group
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Table Parameters Used Specification First Order Input Buffer Model Parameter Description Minimum Maximum value capacitance input buffer model Minimum Maximum value package inductance Minimum Maximum value package capacitance Diode Series Resistance Ideal Diodes
Figure shows structure output buffer model. This model used output buffers Pentium processor with voltage reduction technology.
PP0061
Figure First Order Output Buffer Model
Table Parameters Used Specification First Order Output Buffer Model Parameter dV/dt Description Minimum maximum value rate change open circuit voltage source used output buffer model Minimum maximum value output impedance output buffer model Minimum Maximum value capacitance output buffer model Minimum Maximum value package inductance Minimum Maximum value package capacitance
4.4.1.
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ringback occur. There other selection choices; configurable buffers same size same time. input, output bidirectional buffer values Pentium processor with voltage reduction technology listed Table This table contains listings three types, them confused during simulation. When bidirectional operating input, Cin, values; operating driver, data parameters. Please refer Table groupings buffers.
BUFFER MODEL PARAMETERS
This section gives parameters each Pentium processor with voltage reduction technology input, output bidirectional signal, well settings configurable buffers. Some pins Pentium processor with voltage reduction technology have selectable buffer sizes. These pins configurable output buffer EB2. Table shows drive level BRDY# required falling edge RESET select buffer strength. buffer sizes selected should appropriate size required; otherwise timings might met, much overshoot
Table Buffer Selection Chart Environment Typical Stand Alone Component Loaded Component BRDY# Buffer Selection EB2A
NOTES: correct buffer selection, BUSCHK# signal must held inactive (high) falling edge RESET.
Table Signal Buffer Type Signals A20M#, AHOLD, BOFF#, BRDY#, BUSCHK#, EADS#, EWBE#, FLUSH#, HOLD, IGNNE#, INIT, INTR, INV, KEN#, NA#, NMI, PEN#, R/S#, RESET, SMI#, STPCLK#, TCK, TDI, TMS, TRST#, WB/WT# APCHK#, BE[7:5]#, BP[3:2], BREQ, FERR#, IERR#, PCD, PCHK#, PM0/BP0, PM1/BP1, PRDY, PWT, SMIACT#, TDO, U/O# A[31:21], BE[4:0]#, CACHE#, D/C#, D[63:0], DP[8:0], HLDA, LOCK#, M/IO#, SCYC A[20:3], ADS#, HITM#, W/R# HIT# Type Driver Buffer Type Receiver Buffer Type
EB2/EB2A
EB2/EB2A
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table Pentium® ProcessorInput, Output Bidirectional Buffer Model Parameters Buffer Type Transition (input) (input) (output) (bidir) (bidir) EB2A (bidir) (bidir) (bidir) Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling 3/3.0 3/2.8 3/3.0 3/2.8 3/3.0 3/2.8 3/2.4 3/2.4 3/3.0 3/2.8 3/3.0 3/2.8 3.7/0.9 3.7/0.8 3.7/0.9 3.7/0.8 3.7/0.9 3.7/0.8 3.7/0.9 3.7/0.9 3.7/0.9 3.7/0.8 3.7/0.9 3.7/0.8 21.6 17.5 21.6 17.5 21.6 17.5 10.1 21.6 17.5 21.6 17.5 53.1 50.7 53.1 50.7 53.1 50.7 22.4 21.2 53.1 50.7 53.1 50.7 dV/dt (V/nsec) (Ohms) (pF) (nH)
Co/Cin (pF)
Table Input Buffer Model Parameters: (Diodes) Symbol Parameter Saturation Current Emission Coefficient Series Resistance Transit Time Potential Zero Bias Capacitance Grading Coefficient 1.4e-14A 1.19 ohms 0.983V 0.281 0.385 2.78e-16A 1.00 ohms 0.967V 0.365 0.376
4.4.2. 4.4.2.1.
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Maximum Ringback Inputs 0.8V (with diodes) simulated without input diodes, follow Maximum Overshoot/Undershoot specification. meeting overshoot/undershoot specification, signal guaranteed ringback excessively. simulated with diodes present input model, follow maximum ringback specification. Overshoot (Undershoot) absolute value maximum voltage above VCC3 (below VSS). guideline assumes absence diodes input. Maximum Overshoot/Undershoot 82497 Cache Controller, 82492 Cache SRAM Inputs (CLK PICCLK only) 1.6V above VCC5 (without diodes)
SIGNAL QUALITY SPECIFICATIONS
Signals driven system into Pentium processor with voltage reduction technology must meet signal quality specifications guarantee that components read data properly ensure that incoming signals affect reliability component. There signal quality parameters: Ringback Settling Time. Ringback
Excessive ringback contribute long-term reliability degradation Pentium processor with voltage reduction technology, cause false signal detection. Ringback simulated input component using input buffer model. Ringback simulated with without diodes that input buffer model. Ringback absolute value voltage receiving below VCC3 VSS) relative VCC3 VSS) level after reached maximum voltage level. diodes assumed present. maximum above signal input
Maximum Overshoot/Undershoot 3.3V Pentium processor with voltage reduction technology Inputs (not CLK) 1.4V above VCC3 (without diodes)
PP0110
Figure Overshoot/Undershoot Ringback Guidelines
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
4.4.2.2. Settling Time
following procedure verify board simulation tuning with concerns settling time. Simulate settling time slow corner particular signal. settling time violations occur, simulate signal trace with D.C. diodes place receiver pin. D.C. diode behaves almost identically actual (non-linear) diode part long excessive overshoot does occur. settling time violations still occur, simulate flight times five consecutive cycles that particular signal. flight time values consistent over five simulations, settling time should concern. however, flight times consistent over five simulations, tuning layout required. Note that, signals that allocated cycles flight time, recommended settling time doubled. typical design method would include settling time that ensures signal within percent VCC3 least prior period.
settling time defined time signal requires receiver settle within percent VCC3 VSS. Settling time maximum time allowed signal reach within percent final value. Most available simulation tools unable simulate settling time that accurately reflects silicon measurements. physical board, second-order effects other effects serve dampen signal receiver. Because these concerns, settling time recommendation tool layout tuning specification. Settling time simulated slow corner, make sure that there impact flight times signals waveform settled. Settling time simulated with diodes included excluded from input buffer model. diodes included, settling time recommendation will easier meet. Although simulated settling time shown good correlation with physical, measured settling time, settling time simulations still used tool tune layouts.
PP0111
Figure Settling Time
5.0.
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
body size polyimide pick-andplace handling. components shipped with leads flat slide carriers, designed excised lead formed customer manufacturing site. Recommendations manufacture this package included Chapter 1996 Packaging Data Book. Figure shows cross-sectional view mounted Printed Circuit Board. Figures show shipped slide carrier, dimensions carrier package. Figure shows cross-section detail package. Figure shows enlarged view outer lead bond area package. Tables provide Pentium processor with voltage reduction technology dimensions.
PENTIUM® PROCESSOR MECHANICAL SPECIFICATIONS
Today's portable computers face challenge meeting desktop performance environment that constrained thermal, mechanical electrical design considerations. These considerations have driven development implementation Intel's Tape Carrier Package (TCP). Intel been designed offer high count, profile, reduced footprint package with uncompromised thermal electrical performance. Intel continues provide packaging solutions that meet rigorous criteria quality performance, this entry into Intel package portfolio exception. features include: surface mount technology design, lead pitch 0.25 polyimide
5.1.
Mechanical Diagrams
Encapsulant Gold Bump
Polyimide Support Ring
Polyimide Lead Keeper (OFC Copper)
X-Section Thermally Electrically Conductive Adhesive (Silver Filled Thermoplastic) Note: Thermal vias Ground plane Sketches Scale
Full X-Section
255703
Figure Cross-Sectional View Mounted
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
255705
Figure Site Carrier (Bottom View Die)
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
255706
Figure Site Carrier (Top View Die)
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
255707
Figure Site (Cross-Sectional Detail)
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
255708
Figure Outer Lead Bond (OLB) Window Detail
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table Dimensions Symbol D1,E1 Leadcount Tape Width Site Length Outer Lead Pitch Outer Lead Width Package Body Size Package Height Length Width Lead Thickness Encap Length Encap Width Description leads 48.18 ±0.12 (43.94) reference only 0.25 nominal 0.10 ±0.01 24.0 ±0.1 min-0.605 ±0.030 max-0.615 ±0.030 min-9.929 ±0.015 max-13.302 ±0.015 min-9.152 ±0.015 max-12.235 ±0.015 min-0.025 max-0.035
Dimension
min-(10.56) reference only max-(13.94) reference onlly min-(9.78) reference only max-(12.87) reference only
NOTES: Dimensions millimeters unless otherwise noted. Dimensions parentheses reference only.
Table Mounted Dimensions Description Package Height Terminal Dimension Package Weight 0.75 maximum 29.5 nominal maximum Dimension
NOTE: Dimensions millimeters unless otherwise noted. Package terminal dimension (lead tip-to-lead tip) assumes keeper bar.
6.0. 6.1.
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
ambient case temperatures (°C) Case-to-Ambient thermal resistance (°C/W) Junction-to-Ambient thermal resistance (°C/W) Junction-to-Case thermal resistance (°C/W) maximum power consumption (Watts)
PENTIUM® PROCESSOR THERMAL SPECIFICATIONS
Pentium processor with voltage reduction technology specified proper operation when case temperature, TCASE, (TC) within specified range
(maximum power consumption) specified section 4.2.
Measuring Thermal Values 6.3. Thermal Characteristics
verify that proper (case temperature) maintained Pentium processor, should measured center package surface (encapsulant). minimize measurement errors, following techniques recommended: gauge finer diameter type thermocouples. Intel's laboratory testing done using thermocouple made Omega (part number: 5TC-TTK-36-36). Attach thermocouple bead junction center package surface using highly thermally conductive cements. Intel's laboratory testing done using Omega Bond (part number: OB-100). thermocouple should attached angle shown Figure
6.2.
Thermal Equations
primary heat transfer path from through back side into board. There thermal paths traveling from board ambient air. spread heat within board dissipation heat board ambient air. other transfer heat through board opposite side where thermal enhancements (e.g., heat sinks, pipes) attached. Solder-side heat sinking, compared component-side heat sinking, preferred method reduced risk damage, easier mechanical implementation larger surface area attachment. However, component-side heat sinking possible. design requirements component-side thermal solution are: direct loading inner lead bonds TCP, maximum force center clean TCP, direct loading tape outer lead bonds controlled board deflection.
Pentium processor with voltage reduction technology, ambient temperature (TA) specified directly. only requirement that case temperature (TC) met. ambient temperature calculated from following equations:
where,
6.4.
Board Enhancements
Copper planes, thermal pads, vias design options that used improve heat transfer from board ambient air. Tables present thermal resistance data copper plane thickness effects. should noted that although thicker copper planes will reduce system without thermal enhancements, they have less effect system with thermal enhancements. However, placing vias under will reduce system with without thermal enhancements.
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
255704
Figure Technique Measuring Case Temperature (TC)
Table Thermal Resistance Copper Plane Thickness with without Enhancements Copper Plane Thickness*
NOTES: *225 vias underneath mil)
(°C/W) Enhancements
(°C/W) With Heat Pipe
Table Thermal Resistance Thermal Vias underneath Thermal Configuration thermal vias drill pitch (°C/W) Enhancements
Table Pentium® Processor Thermal Resistance without Enhancements (°C/W) Thermal Resistance without Enhancements (°C/W) 13.9
Heat sink Plate
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table Pentium® Processor Thermal Resistance with Enhancements (without Airflow) Thermal Enhancements (°C/W) 11.7 Table Pentium® Processor Thermal Resistance with Enhancements (with Airflow) Thermal Enhancements (°C/W) Notes 1.2"x1.2"x.35" Notes
Plate with Heat Pipe
Heat sink with Heat sink with Airflow Heat sink with Airflow
heat sink Linear Feet/Minute Cubic Feet/Minute
6.4.1.
STANDARD TEST BOARD CONFIGURATION
7.0.
thermal measurements provided tables were taken with component soldered test board outline. This six-layer board contains 13.5 drill pitch vias (underneath die) attach which connected copper planes located layers five. Pentium processor with voltage reduction technology, vias attach should connected without thermal reliefs ground plane(s). attached attach using thermally electrically conductive adhesive. This test board designed optimize heat spreading into board heat transfer through opposite side board. NOTE Thermal resistance values should used guidelines only, highly system dependent. Final system verification should always refer case temperature specification.
SPGA PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY SPECIFICATIONS SPGA Pentium® Processor with Voltage Reduction Technology Differences from 3.3V Pentium Processor
7.1.
SPGA Pentium processor with voltage reduction technology specifications, except differences described this section, identical those 3.3V Pentium processor. 7.1.1. Features Removed
following features have been removed Pentium processor with voltage reduction technology: Upgrade, Dual Processing (DP), APIC Master/Checker functional redundancy. Table lists corresponding pins which exist 3.3V Pentium processor have been removed Pentium processor with voltage reduction technology.
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
7.1.2. Maximum Rating WARNING
following values stress ratings only. Functional operation maximum ratings implied guaranteed. Functional operating conditions given specification tables. Extended exposure maximum ratings affect device reliability. Furthermore, although SPGA Pentium processor with voltage reduction technology contains protective circuitry resist damage from static electric discharge, always take precautions avoid high static voltages electric fields. Case temperature under bias.-65°C 110°C Storage temperature.-65°C 150°C Supply voltage with respect -0.5V +4.6V 2.9V Supply voltage with respect -0.5V +4.1V Only Buffer Input Voltage. -0.5V VCC3 +0.5; exceed 4.6V Safe Buffer Input Voltage .-0.5V 6.5V (1,3)
NOTES: Applies CLK. Applies SPGA Pentium processor with voltage reduction technology inputs except CLK. Table
Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only. Operation beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" affect device reliability. 7.1.3. Specifications
Tables list specifications which apply SPGA Pentium processor with voltage reduction technology. SPGA Pentium processor with voltage reduction technology core operates 2.9V internally while interface operates 3.3V. input 3.3V Since 3.3V safe) input levels defined Table same levels, input compatible with existing clock drivers. power dissipation specification Table provided design thermal solutions during operation sustained maximum level. This worst-case power device would dissipate system sustained period time. This number used design thermal solution device.
Symbol VIL3 VIH3 VOL3 VOH3 ICC2 ICC3
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table SPGA 3.3V Specifications TCASE 85°C; VCC2 2.9V ±165mV; VCC3 3.3V ±165mV Parameter -0.3 VCC3+0.3 2096 2515 2800 Unit Notes Level Level Level Level @100 @100
Input Voltage Input High Voltage Output Voltage Output High Voltage Power Supply Current from 2.9V core supply Power Supply Current from 3.3V buffer supply
NOTES: Parameter measured Parameter measured 3.3V levels apply signals except CLK. This value should used power supply design. estimated worst-case instruction VCC2 2.9V 165mV VCC3 3.3V± 165mV. Power supply transient response decoupling capacitors must sufficient handle instantaneous current changes occurring during transitions from stop clock full active modes. lower power number process improvement.
Table SPGA 3.3V Safe) Specifications Symbol VIL5 VIH5 Parameter Input Voltage Input High Voltage -0.3 5.55 Unit Notes Level Level
NOTES: Applies only.
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table Input Output Characteristics Symbol CI/O CCLK CTIN CTOUT CTCK Parameter Input Capacitance Output Capacitance Capacitance Input Capacitance Test Input Capacitance Test Output Capacitance Test Clock Capacitance Input Leakage Current Output Leakage Current Input Leakage Current Input Leakage Current -400 Unit
Notes
VCC3 VCC3 2.4V 0.4V
NOTES: This parameter input without pull pull down. This parameter input with pull This parameter input with pull down. Guaranteed design.
Table SPGA Power Dissipation Requirements Thermal Solution Design Parameter Active Power Dissipation Typical(1) 2.0-3.0 2.5-3.5 2.8-3.9 Max(2) 0.05 Unit Watts Watts Watts Watts Watts Watts Watts @100 @100 Notes
Stop Grant Auto Halt Powerdown Power Dissipation Stop Clock Power Dissipation
NOTES: This typical power dissipation system. This value average value measured system using typical device VCC2 2.9V VCC3 3.3V running typical applications. This value highly dependent upon specific system configuration. Systems must designed thermally dissipate maximum active power dissipation. determined using worstcase instruction with VCC2 2.9V VCC3 3.3V. nominal this measurement takes into account thermal time constant package. Stop Grant/Auto Halt Powerdown Power Dissipation determined asserting STPCLK# executing HALT instruction. Stop Clock Power Dissipation determined asserting STPCLK# then removing external input. lower power number process improvement.
7.1.3.1. 7.1.4.
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
inductance capacitors interconnects recommended best high frequency electrical performance. Inductance reduced shortening circuit board traces between processor decoupling capacitors much possible. These capacitors should evenly distributed around each component 3.3V plane 2.9V plane island). Capacitor values should chosen ensure they eliminate both high frequency noise components. Power transients also occur processor rapidly transitions from level power consumption much higher level high power). typical example would entering exiting Stop Grant state. Another example would executing HALT instruction, causing processor enter Auto HALT Powerdown state, transitioning from HALT Normal state. these examples cause abrupt changes power being consumed processor. Note that Auto HALT Powerdown feature always enabled even when other power management features implemented. Bulk storage capacitors with (Effective Series Resistance) range required maintain regulated supply voltage during interval between time current load changes point that regulated power supply output react change load. order reduce ESR, necessary place several bulk storage capacitors parallel. These capacitors should placed near processor 3.3V plane 2.9V plane island)) ensure that these supply voltages stay within specified limits during changes supply current during operation. more detailed informations, please contact Intel refer Pentium® Processor with Voltage Reduction Technology: Power Supply Design Considerations Mobile Systems application note (Order Number 242558). 7.1.4.3. Connection Specifications
Power Sequencing
There specific sequence required powering powering down VCC2 VCC3 power supplies. However, compatibility with future mobile processors, recommended that VCC2 VCC3 power supplies either both both within second each other. Specifications
specifications SPGA Pentium processor with voltage reduction technology consist setup times, hold times, valid delays SPGA Pentium processor with voltage reduction technology specifications valid VCC2 2.9V 165mV, VCC3 3.3V 165mV, TCASE WARNING exceed 75-MHz Pentium processor with voltage reduction technology internal maximum frequency either selecting fraction providing clock greater than MHz. exceed 90-MHz Pentium processor with voltage reduction technology internal maximum frequency either selecting fraction providing clock greater than MHz. 7.1.4.1. Power Ground
clean on-chip power distribution, SPGA Pentium processor with voltage reduction technology VCC2 (2.9V power), VCC3 (3.3V power) (ground) inputs. Power ground connections must made external VCC2, VCC3 pins SPGA Pentium processor with voltage reduction technology. circuit board VCC2 pins must connected 2.9V VCC2 plane island) VCC3 pins must connected 3.3V VCC3 plane. pins must connected plane. Refer Table listing VCC2 VCC3. 7.1.4.2. Decoupling Recommendations
Transient power surges occur processor executing instruction sequences driving large loads. mitigate these high frequency transients, liberal high frequency decoupling capacitors should placed near processor.
pins must remain unconnected. Refer Table listing pins. RESERVED pins must remain unconnected.
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected VCC3. Unused active high inputs should connected ground. 7.1.4.4. Timings
Table contains SPGA Pentium processor with voltage reduction technology timing changes 50-MHz operation. Table contains SPGA Pentium processor with voltage reduction technology timing changes 60-MHz operation. Table contains SPGA Pentium processor with voltage reduction technology timing changes 66-MHz operation. 7.1.5. Thermal Specifications
from SPGA 3.3V Pentium processor. Figure depicts side SPGA pinout diagram. VCC2 pins 3.3V pins 3.3V Pentium processor, will 2.9V VCC2 pins SPGA Pentium processor with voltage reduction technology. pins correspond unused (for mobile) functions listed Table They should left unconnected. Connection these pins result component failure incompatibility with processor steppings. brief functional description remaining pins, please refer Tables Input Output pins reference, please refer Table 7.1.6.2. Package Dimensions
SPGA Pentium processor with voltage reduction technology specified proper operation when case temperature, TCASE (TC) within specified range 7.1.6. SPGA Package Differences
Pentium processor with voltage reduction technology implements SPGA package that removes Heat spreader from package. package mechanically equivalent package used 3.3V Pentium processor stepping except that SPGA Pentium processor with voltage reduction technology will metal instead ceramic lid, dimensions shown Figure 7.1.7. Buffer Models
SPGA Pentium processor with voltage reduction technology package array that mechanically identical SPGA version 3.3V Pentium, some pins need connected differently. Also, there small differences package dimensions. 7.1.6.1. Pinout
Table lists SPGA Pentium processor with voltage reduction technology pins that different
buffer models provided section this document apply both SPGA Pentium processor with voltage reduction technology packages, although capacitance (Cp) inductance (Lp) parameter values differ between packages. SPGA Pentium processor with voltage reduction technology values, refer Pentium® Processor Family Developer's Manual, Volume Pentium Processors.
Symbol t10b
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table SPGA Pentium® Processor Timing Changes 50-MHz Operation VCC2 2.9V +165mV, VCC3 3.3V +165mV, TCASE 85°C, Parameter W/R# Valid Delay BE0-7# Valid Delay LOCK# Valid Delay Valid Delay CACHE# Valid Delay A3-A31 Valid Delay ADS# Valid Delay HITM# Valid Delay DBUS Valid Delay Unit
Table SPGA Pentium® Processor Timing Changes 60-MHz Operation VCC2 2.9V +165mV, VCC3 3.3V +165mV, TCASE 85°C, Symbol A3-A31 Valid Delay DBUS Valid Delay Parameter Unit
Table SPGA Pentium® Processor Timing Changes 66-MHz Operation VCC2 2.9V ±165mV, VCC3 3.3V ±165mV, SPGA TCASE 85°C, Symbol BE0-7# Valid Delay A3-A31 Valid Delay M/IO# Valid Delay HLDA Valid Delay D0-D63, DP0-7 Write Data Valid Delay Parameter 7.25 Unit
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
AN11 AN13 AN15 AN17 AN19
Table SPGA Pentium® Processor with Voltage Reduction Technology VCC2 VCC3 Pins
VCC2*
AA01 AC01 AE01 AG01 AN09
VCC3
AA37 AC37 AE37 AG37 AN21 AN23 AN25 AN27 AN29
NC**
AA03 AC03 AD04 AE03 AE35 AL19 AM02 AN35
NOTE: *These VCC2 pins 3.3V pins SPGA 3.3V Pentium® processor. SPGA Pentium processor with voltage reduction technology, these pins 2.9V VCC2 supplies SPGA core. **These pins should left unconnected. Connection these pins result component failure incompatibility with processor steppings.
VCC2 FLUSH# W/R# HIT# EADS# LOCK# BREQ HLDA ADS# VCC2 SMIACT# PCHK# APCHK#
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
VCC2
VCC2 BE4# BE3# BE2# BE1# VCC2 BE6# BE7# BE5# VCC2
VCC2 SCYC
VCC2 RESET VCC3 VCC3
VCC3
VCC3 VCC3 INTR VCC3 VCC3
A20M#
HITM# BUSCHK# BE0#
VCC3 PRDY VCC2 HOLD SMI# INIT IGNNE# VCC3 VCC2 WB/WT# PEN# BOFF# VCC3 VCC2 BRDY# VCC3 VCC2 EWBE# KEN# STPCLK# AHOLD VCC3 VCC2 CACHE# VCC3 VCC3 MI/O# VCC3 VCC2 PM1BP1 TRST# VCC3 VCC2 PM0BP0 FERR# IERR# VCC2 VCC3 VCC3 VCC3 VCC2 VCC3 VCC2 VCC3 VCC2 VCC3 VCC2 VCC2 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2 VCC2 VCC2 VCC2
PENTIUM PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY SIDE VIEW
255701
Figure SPGA Pentium® Processor with Voltage Reduction Technology Pinout
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Seating Plane
1.65
2.29 1.52 REF. Index Chamfer (Index Corner)
Bottom View (Pin Side
Figure 296-Pin Ceramic Grid Array Package
Side View
Symbol 1.52 3.27 0.66 2.62 0.43 49.28 45.59 24.00 2.29 3.05
PENTIUM® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table 296-Pin Ceramic Grid Array: Package Dimensional Specification Millimeters 3.83 0.86 2.97 0.51 49.78 45.85 24.25 2.79 3.30 2.54 Total Pins 0.060 Includes Fillet Notes Ceramic Ceramic 0.129 0.026 0.103 0.017 1.940 1.795 0.945 0.090 0.120 0.100 Inches 0.151 0.034 0.117 0.020 1.960 1.805 0.955 0.110 1.130 Total Pins Includes Fillet Notes Ceramic Ceramic
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