Full 32-Bit Internal Architecture 32-Bit Data Types General Purpose 32
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HIGH PERFORMANCE 32-BIT EMBEDDED PROCESSOR
Full 32-Bit Internal Architecture 32-Bit Data Types General Purpose 32-Bit Registers Extensive 32-Bit Instruction High Performance 16-Bit Data Clock Two-Clock Cycles Mbytes Bandwidth Mbyte Physical Memory Size High Speed Numerics Support with 80387SX System Cost with 82370 Integrated System Peripheral On-Chip Debugging Support Including Break Point Registers
Complete Intel Development Support Assembler -376 In-Circuit Emulator iRMK Real Time Kernel iSDM Debug Monitor Based Debug Extensive Third-Party Support Languages Pascal FORTRAN BASIC Hosts UNIX MS-DOS Others Real-Time Kernels High Speed CHMOS Technology Available Plastic Quad FlatPack Package 88-Pin Grid Array
(See Packaging Outlines Dimensions 231369)
INTRODUCTION
32-bit embedded processor designed high performance embedded systems provides performance benefits highly pipelined 32-bit internal architecture with system cost associated with 16-bit hardware systems 80376 processor based 80386 offers high degree compatibility with 80386 80386 32-bit programs dependent paging executed 80376 80376 programs executed 80386 32-bit 80386 language translators used software development With proper support software 80386-based computer used develop test 80376 programs addition 80386-based PC-AT compatible computer used hardware prototyping designs based 80376 companion product 82370
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80376 Microarchitecture
Intel iRMK Intel386 iSDM Intel1376 trademarks Intel Corp UNIX registered trademark registered trademark Government Joint Program Office PC-AT registered trademark Corporation trademark Digital Equipment Corporation MS-DOS trademark MicroSoft Corporation
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COPYRIGHT
INTEL CORPORATION 1995
December 1990
Order Number 240182-004
EMBEDDED PROCESSOR
DESCRIPTION
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Figure 80376 100-Pin Quad Flat-Pack (Top View) Table 100-Pin Plastic Quad Flat-Pack Assignments
Address Data Control BUSY CLK2 ERROR HLDA HOLD INTR LOCK PEREQ READY RESET
EMBEDDED PROCESSOR
View (Component Side)
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Bottom View (Pin Side)
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Figure 80376 88-Pin Grid Array
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Table 88-Pin Grid Array Assignments Label CLK2 Label Label LOCK READY HOLD HLDA PEREQ BUSY ERROR INTR RESET Label
EMBEDDED PROCESSOR
following table lists brief description each 80376 following definitions used these descriptions named signal active Input signal Output signal Input Output signal electrical connection Symbol CLK2 RESET Type Name Function CLK2 provides fundamental timing 80376 additional information Clock Section RESET suspends operation progress places 80376 known reset state Interrupt Signals Section additional information DATA inputs data during memory interrupt acknowledge read cycles outputs data during memory write cycles Data Section additional information ADDRESS outputs physical memory port addresses Address Section additional information WRITE READ cycle definition that distinguishes write cycles from read cycles Cycle Definition Signals Section additional information DATA CONTROL cycle definition that distinguishes data cycles either memory from control cycles which interrupt acknowledge halt instruction fetching Cycle Definition Signals Section additional information MEMORY cycle definition that distinguishes memory cycles from input output cycles Cycle Definition Signals Section additional information LOCK cycle definition that indicates that other system masters denied access system while active Cycle Definition Signals Section additional information ADDRESS STATUS indicates that valid cycle definition address -A1) being driven 80376 pins Control Signals Section additional information NEXT ADDRESS used request address pipelining Control Signals Section additional information READY terminates cycle Control Signals Section additional information BYTE ENABLES indicate which data bytes data take part cycle Address Section additional information HOLD REQUEST input allows another master request control local Arbitration Signals Section additional information
LOCK
READY
HOLD
EMBEDDED PROCESSOR
Symbol HLDA INTR
Type
BUSY ERROR PEREQ
Name Function HOLD ACKNOWLEDGE output indicates that 80376 surrendered control local another master Arbitration Signals Section additional information INTERRUPT REQUEST maskable input that signals 80376 suspend execution current program execute interrupt acknowledge function Interrupt Signals Section additional information NON-MASKABLE INTERRUPT REQUEST non-maskable input that signals 80376 suspend execution current program execute interrupt acknowledge function Interrupt Signals Section additional information BUSY signals busy condition from processor extension Coprocessor Interface Signals Section additional information ERROR signals error condition from processor extension Coprocessor Interface Signals Section additional information PROCESSOR EXTENSION REQUEST indicates that processor extension data transferred 80376 Coprocessor Interface Signals Section additional information FLOAT when active forces bidirectional output signals including HLDA float condition FLOAT available package Float additional information CONNECT should always remain unconnected Connection cause processor malfunction incompatible with future steppings 80376 SYSTEM POWER provides nominal supply input SYSTEM GROUND provides connection from which inputs outputs measured sists execution unit instruction unit execution unit contains eight 32-bit general registers which used both address calculation data operations 64-bit barrel shifter used speed shift rotate multiply divide operations instruction unit decodes instruction opcodes stores them decoded instruction queue immediate execution unit Memory Management Unit (MMU) consists segmentation protection unit Segmentation allows managing logical address space providing extra addressing component that allows easy code data relocatability efficient sharing protection unit provides four levels protection isolating protecting applications operating system from each other hardware enforced protection allows design systems with high degree integrity simplifies debugging Finally facilitate high performance system hardware designs 80376 interface offers address pipelining direct Byte Enable signals each byte data
ARCHITECTURE OVERVIEW
80376 supports protection mechanisms needed sophisticated multitasking embedded systems real-time operating systems these protection mechanisms completely optional embedded applications needing protection 80376 easily configured provide Mbyte physical address space Instruction pipelining high bandwidth very high performance ensure short average instruction execution times high system throughput 80376 capable execution sustained rates million instructions second 80376 offers on-chip testability debugging features Four break point registers allow conditional unconditional break point traps code execution data accesses powerful debugging even based systems Other testability features include self-test tri-stating output buffers during RESET Intel 80376 embedded processor consists central processing unit memory management unit interface central processing unit con6
EMBEDDED PROCESSOR
Register
80376 twenty-nine registers shown Figure These registers grouped into following categories
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Figure 80376 Base Architecture Registers
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General Registers eight 32-bit general purpose registers used contain arithmetic logical operands Four these (EAX EDX) used either their entirety 32-bit registers 16-bit registers split into pairs separate 8-bit registers Segment Registers 16-bit special purpose registers select given time segments memory that immediately addressable code stack data Flags Instruction Pointer Registers These 32-bit special purpose registers Figure record control certain aspects 80376 processor state EFLAGS register includes status control bits that used reflect outcome many instructions modify semantics some instructions Instruction Pointer called bits wide Instruction Pointer controls instruction fetching processor automatically increments after executing instruction Control Register 32-bit control register used control Coprocessor Emulation System Address Registers These four special registers reference tables segments supported 80376 80386 protection model These tables segments GDTR (Global Descriptor Table Register) IDTR (Interrupt Descriptor Table Register) LDTR (Local Descriptor Table Register) (Task State Segment Register) Debug Registers programmer accessible debug registers provide on-chip support debugging debug registers described Section Debugging Support EFLAGS REGISTER flag Register 32-bit register named EFLAGS defined bits fields within EFLAGS shown Figure control certain operations indicate status 80376 processor function flag bits given Table
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Figure Status Control Register Functions
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Table Flag Definitions Position Name IOPL Function Carry Flag high-order carry borrow cleared otherwise Parity Flag low-order bits result contain even number 1-bits cleared otherwise Auxiliary Carry Flag carry from borrow order four bits cleared otherwise Zero Flag result zero cleared otherwise Sign Flag equal high-order result positive negative) Single Step Flag Once single step interrupt occurs after next instruction executes cleared single step interrupt Interrupt-Enable Flag When external interrupts signaled INTR will cause transfer control interrupt vector specified location Direction Flag Causes string instructions auto-increment (default) appropriate index registers when cleared Setting causes autodecrement Overflow Flag operation resulted carry borrow into sign (high-order bit) result result carry borrow high-order vice-versa Privilege Level Indicates maximum permitted execute instructions without generating exception fault consulting permission also indicates maximum value allowing alteration Nested Task Indicates that execution current task nested within another task (see Task Switching) Resume Flag Used conjunction with debug register breakpoints checked instruction boundaries before breakpoint processing debug fault ignored next instruction reset successful completion instruction except IRET POPF those instructions causing task switches
CONTROL REGISTER 80376 32-bit control register called that used control coprocessor emulation This register shown Figures defined bits described Table Bits have fixed values 80376 These values cannot changed Programs that load should always load bits with values previously there compatible with 80386 Table Definitions Position Name Function Monitor Coprocessor Extension Allows WAIT instructions cause processor extension present exception (number Emulate Processor Extension When this causes processor extension present exception (number instructions allow processor extension emulation Task Switched When this indicates next instruction using processor extension will cause exception allowing software test whether current processor extension context belongs current task (see Task Switching)
EMBEDDED PROCESSOR
Instruction
instruction divided into nine categories operations Data Transfer Arithmetic Shift Rotate String Manipulation Manipulation Control Transfer High Level Language Support Operating System Support Processor Control These 80376 processor instructions listed Table 80376 Instruction Clock Count Summary 80376 processor instructions operate either operands operand resides register instruction itself memory Most zero operand instructions STI) take only byte operand instructions generally bytes long average instruction bytes long Since 80376 16-byte prefetch instruction queue average instructions prefetched operands permits following types common instructions Register Register Memory Register Immediate Register Memory Memory Register Memory Immediate Memory operands either 32-bit long
Memory Organization
Memory 80376 divided into 8-bit quantities (bytes) 16-bit quantities (words) 32-bit quantities (dwords) Words stored consecutive bytes memory with low-order byte lowest address Dwords stored four consecutive bytes memory with low-order byte lowest address address word Dword byte address low-order byte maximum performance word dword values should even physical addresses addition these basic data types 80376 processor supports segments Memory divided into more variable length segments which shared between programs ADDRESS SPACES 80376 three types address spaces logical linear physical logical address (also known virtual address) consists selector offset selector contents segment register offset formed summing addressing components (BASE INDEX DISPLACEMENT) discussed Section Addressing Modes into effective address Every selector logical base address associated with that bits length This 32bit logical base address added either 32-bit offset address 16-bit offset address using address length prefix form final 32-bit linear address This final linear address then truncated that only lower bits this address used address Mbytes physical memory address space logical base address stored operating system tables Local Descriptor Table Global Descriptor Table) Figure shows relationship between various address spaces
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Figure Address Translation SEGMENT REGISTER USAGE main data structure used organize memory segment 80376 segments variable sized blocks linear addresses which have certain attributes associated with them There main types segments code data simplest segments have code data segment Each segment Mbytes size overlapping each other This allows code data directly addressed same offset order provide compact instruction encoding increase processor performance instructions need explicitly specify which segment register used segment register automatically chosen according rules Table (Segment Register Selection Rules) general data references selector contained register stack references register instruction fetches register contents Instruction Pointer provide offset Special segment override prefixes allow explicit given segment register override implicit rules listed Table override prefixes also allow segment registers There restrictions regarding overlapping base addresses segments Thus segments could have base address zero Further details segmentation discussed Section Architecture
EMBEDDED PROCESSOR
Table Segment Register Selection Rules Type Memory Reference Code Fetch Destination PUSH PUSHF CALL PUSHA Instructions Source POPA POPF IRET Instructions Destination STOS MOVS STOS MOVS Instructions Base Register) Other Data References with Effective Address Using Base Register Implied (Default) Segment Segment Override Prefixes Possible None None None
None
Addressing Modes
80376 provides total addressing modes instructions specify operands addressing modes optimized allow efficient execution high level languages such FORTRAN they cover vast majority data references needed high-level languages addressing modes provide instructions that operate register immediate operands Register Operand Mode operand located 32-bit general registers Immediate Operand Mode operand included instruction part opcode remaining modes provide mechanism specifying effective address operand linear address consists components seg-
ment base address effective address effective address calculated summing combination following three address elements (see Figure DISPLACEMENT 32-bit immediate value following instruction BASE contents general purpose register base registers generally used compilers point start local variable area Note that Address Length Prefix used only used BASE register INDEX contents general purpose register except index registers used access elements array string characters index register's value multiplied scale factor either scaled index especially useful accessing arrays structures Note that Address Length Prefix used Scaling available only registers used INDEX
EMBEDDED PROCESSOR
Combinations these components make additional addressing modes There performance penalty using these addressing combinations since effective address calculation pipelined with execution other instructions exception simultaneous BASE INDEX components which requires additional clock shown Figure effective address (EA) operand calculated according following formula BASERegister (INDEXRegister scaling) DISPLACEMENT Direct Mode operand's offset contained part instruction 32-bit DISPLACEMENT Register Indirect Mode BASE register contains address operand Based Mode BASE register's contents added DISPLACEMENT form operand's offset Scaled Index Mode INDEX register's contents multiplied SCALING factor which added DISPLACEMENT form operand's offset Based Scaled Index Mode contents INDEX register multiplied SCALING factor result added contents BASE register obtain operand's offset Based Scaled Index Mode with Displacement contents INDEX register multiplied SCALING factor result added contents BASE register DISPLACEMENT form operand's offset
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Figure Addressing Mode Calculations
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blers Operand Length Address Length Prefixes applied separately combination instruction 80376 normally executes 32-bit code uses either 32-bit displacements register used based index registers When executing 16-bit code prefix overrides) displacements either bits base index register conform 16-bit model Table illustrates differences
GENERATING 16-BIT ADDRESSES 80376 executes code with default length operands addresses bits 80376 also able execute operands addresses bits This specified through override prefixes prefixes Operand Length Prefix Address Length Prefix override default 32-bit length individual instruction basis These prefixes automatically added assem-
Table BASE INDEX Registers 32-Bit Addresses 16-Bit Addressing BASE REGISTER INDEX REGISTER SCALE FACTOR DISPLACMENT None Bits 32-Bit Addressing 32-Bit Register 32-Bit Register except Bits
Data Types
80376 supports data types commonly used high level languages Field String Byte Unsigned Byte Integer (Word) Long Integer (Double Word) Unsigned Integer (Word) Unsigned Long Integer (Double Word) Signed Quad Word Unsigned Quad Word Pointer Long Pointer Char String Packed single quantity group contiguous bits which spans maximum four bytes contiguous bits 80376 strings Mbits long signed 8-bit quantity unsigned 8-bit quantity signed 16-bit quantity signed 32-bit quantity operations assume complement representation unsigned 16-bit quantity unsigned 32-bit quantity signed 64-bit quantity unsigned 64-bit quantity 32-bit offset only quantity which indirectly references another memory location full pointer which consists 16-bit segment selector either 32-bit offset byte representation ASCII Alphanumeric control character contiguous sequence bytes words dwords string contain between byte Mbytes byte (unpacked) representation decimal digits byte (packed) representation decimal digits storing digit each nibble
EMBEDDED PROCESSOR
When 80376 coupled with numerics Coprocessor such 80387SX then following common Floating Point types supported Floating Point signed 80-bit real number representation Floating point numbers supported 80387SX numerics coprocessor
Figure illustrates data types supported 80376 processor 80387SX coprocessor
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Figure 80376 Supported Data Types
EMBEDDED PROCESSOR
struction immediately following interrupted instruction other hand return address from exception fault routine will always point instruction causing exception include leading instruction prefixes Table summarizes possible interrupts 80376 shows where return address points 80376 ability handle different interrupts exceptions order service interrupts table with interrupt vectors must defined interrupt vectors simply pointers appropriate interrupt service routine interrupt vectors 8-byte quantities which Interrupt Descriptor Table possible interrupts reserved Intel remaining free used system designer INTERRUPT PROCESSING When interrupt occurs following actions happen First current program address Flags saved stack allow resumption interrupted program Next 8-bit vector supplied 80376 which identifies appropriate entry interrupt table table contains either Interrupt Gate Trap Gate Task Gate that will point interrupt procedure task user supplied interrupt service routine executed Finally when IRET instruction executed processor state restored program execution resumes appropriate instruction 8-bit interrupt vector supplied 80376 several different ways exceptions supply interrupt vector internally software instructions contain imply vector maskable hardware interrupts supply 8-bit vector interrupt acknowledge sequence Non-Maskable hardware interrupts assigned interrupt vector Maskable Interrupt Maskable interrupts most common respond asynchronous external hardware events hardware interrupt occurs when INTR pulled HIGH Interrupt Flag (IF) enabled processor only responds interrupts between instructions (string instructions have ``interrupt window'' between memory moves which allows interrupts during long string moves) When interrupt occurs processor reads 8-bit vector supplied hardware which identifies source interrupt (one user defined interrupts)
Space
80376 distinct physical address spaces physical memory Generally peripherals placed space although 80376 also supports memory-mapped peripherals space consists Kbytes which divided into 8-bit ports 16-bit ports combination ports which more than Kbytes acts additional address line thus allowing system designer easily determine which address space processor accessing Note that address refers physical address ports accessed instructions with port address supplied immediate 8-bit constant instruction register 8-bit 16-bit port addresses zero extended upper address lines instructions cause driven port addresses 00F8H through 00FFH reserved Intel
Interrupts Exceptions
Interrupts exceptions alter normal program flow order handle external events report errors exceptional conditons difference between interrupts exceptions that interrupts used handle asynchronous external events while exceptions handle instruction faults Although program generate software interrupt instruction processor treats software interrupts exceptions Hardware interrupts occur result external event classified into types maskable non-maskable Interrupts serviced after execution current instruction After interrupt handler finished servicing interrupt execution proceeds with instruction immediately after interrupted instruction Exceptions classified faults traps aborts depending they reported whether restart instruction causing exception suported Faults exceptions that detected serviced before execution faulting instruction Traps exceptions that reported immediately after execution instruction which caused problem Aborts exceptions which permit precise location instruction causing exception determined Thus when interrupt service routine been completed execution proceeds from
EMBEDDED PROCESSOR
Table Interrupt Vector Assignments Interrupt Number 14-15 17-32 0-255 TRAP WAIT FAULT Instruction Which Cause Exception IDIV Instruction INTO BOUND Illegal Instruction WAIT Instruction That Generate Exception CALL IRET Segment Register Instructions Stack References Memory Reference Return Address Points Faulting Instruction
Function
Type
Divide Error Debug Exception Interrupt One-Byte Interrupt Interrupt Overflow Array Bounds Check Invalid OP-Code Device Available Double Fault Coprocessor Segment Overrun Invalid Segment Present Stack Fault General Protection Fault Intel Reserved Coprocessor Error Intel Reserved Two-Byte Interrupt
FAULT TRAP TRAP TRAP FAULT FAULT FAULT ABORT ABORT FAULT FAULT FAULT FAULT
Some debug exceptions report both traps previous instruction faults next instruction
Interrupts through Interrupt Gates automatically reset disabling INTR requests Interrupts through Trap Gates leave state unchanged Interrupts through Task Gate change according image EFLAGs register task's Task State Segment (TSS) When IRET instruction executed original state restored Non-Maskable Interrupt Non-maskable interrupts provide method servicing very high priority interrupts When input pulled HIGH causes interrupt with internally supplied vector value Unlike normal hardware interrupt interrupt acknowledgement sequence performed While executing servicing procedure 80376 will service further request requests until interrupt return (IRET) instruc-
tion executed processor reset occurs while currently servicing presence will saved servicing after executing first IRET instruction disabling INTR requests depends gate location Software Interrupts third type interrupt exception 80376 software interrupt instruction causes processor execute interrupt service routine pointed vector interrupt table special case byte software interrupt byte breakpoint interrupt inserting this byte instruction program user breakpoints program debugging tool
EMBEDDED PROCESSOR
final type software interrupt single step interrupt discussed Single-Step Trap (page INTERRUPT EXCEPTION PRIORITIES Interrupts externally-generated events Maskable Interrupts INTR input) Non-Maskable Interrupts input) recognized instruction boundaries When maskable INTR both recognized same instruction boundary 80376 invokes service routine first after service routine been invoked maskable interrupts still enabled then 80376 will invoke appropriate interrupt service routine 80376 executes instructions follows consistent cycle checking exceptions shown Table This cycle repeated each instruction executed occurs parallel with instruction decoding execution INSTRUCTION RESTART 80376 fully supports restarting instructions after faults exception detected instruction executed (exception categories through Table 80376 device invokes appropriate exception service routine 80376 state that permits restart instruction
DOUBLE FAULT Double fault (exception results when processor attempts invoke exception service routine segment exceptions process doing detects exception
Reset Initialization
When processor Reset registers have values shown Table 80376 will then start executing instructions near physical memory location 0FFFFF0H short should executed within segment defined power-up (see Table should then initialized start-up data code segment followed that will load segment descriptor cache with descriptor values table after reset located physical address with limit entries RESET forces 80376 terminate execution local activity instruction execution activity will occur long Reset active Between CLK2 periods after Reset becomes inactive 80376 will start executing instructions physical memory
Table Sequence Exception Checking Consider case 80376 having just completed instruction then performs following checks before reaching point where next instruction completed Check Exception Traps from instruction just completed (single-step Trap Flag Data Breakpoints Debug Registers) Check external INTR Check Exception Faults next instruction (Instruction Execution Breakpoint Debug Registers next instruction) Check Segmentation Faults that prevented fetching entire next instruction (exceptions Check Faults decoding next instruction (exception illegal opcode exception instruction longer than bytes privilege violation IOPL WAIT opcode check (exception both ESCape opcode numeric coprocessor check (exception either WAIT opcode ESCape opcode numeric coprocessor check ERROR input signal (exception ERROR input asserted) Check Segmentation Faults that prevent transferring entire memory quantity (exceptions
EMBEDDED PROCESSOR
Table Register Values after Reset Flag Word (EFLAGS) Machine Status Word (CR0) Instruction Pointer (EIP) Code Segment (CS) Data Segment (DS) Stack Segment (SS) Extra Segment (ES) Extra Segment (FS) Extra Segment (GS) Register Register Other Registers uuuu0002H uuuuuuu1H 0000FFF0H F000H 0000H 0000H 0000H 0000H 0000H 0000H Component Stepping Undefined (Note (Note (Note (Note (Note (Note (Note (Note
NOTES EFLAG Register upper bits EFLAGS register undefined defined flag bits zero defined bits equal Code Segment Register (CS) will have Base Address 0FFFF0000H Limit 0FFFFH Data Extra Segment Registers will have their Base Address 000000000H Limit 0FFFFH self-test selected should contain value value found self-test detected flaw part register always holds component stepping identifier unidentified bits Intel Reserved should used
Initialization
Because 80376 processor starts executing protected mode certain precautions need taken during initialization Before jumps take place tables need setup their respective registers loaded Before interrupts initialized table must setup IDTR must loaded example code shown below This example startup code either 80376 80386SX 80386 into flat mode memory treated simple linear There interrupt routines Builder creates GDT-alias IDT-alias places them default Other entries specified Build file After initialization jumps startup routine this template change this address that your code make label your code startup` This code assembled built using version Intel utilities Intel 386ASM assembler This code tested
EMBEDDED PROCESSOR
NAME FLAT EXTRN startup near name object module this label jmped after init assume code data
flag data selc INIT CODE
SEGMENT PUBLIC USE32
Segment base 0ffffff80h
PUBLIC DESC desc PUBLIC START clear direction flag check processor (80376) reset SMSW rather than speed 80386 real mode force next operand into 32-bit mode move address descriptor into clear load bits address into load bits address into 32-bit form LGDT load 32-bits address into GDTR into protected mode (set bit)
start smsw test pestart realstart offset desc move lgdt smsw flag lmsw next pestart offset desc lgdt data selc pejump next data selc pejump startup short start INIT CODE ENDS
flush prefetch queue
lower portion address only initialize data selectors
initialize data selectors
80386
need make 32-bit jump
80376 already 32-bit only segment base 0ffffff80h
EMBEDDED PROCESSOR
This code should linked into your application boot loadable code following build file illustrates this accomplished FLAT build program Give user segments These segments created builder when FLAT control used startup code reset vector area trap gate disables interrupts interrupt gates doesn't
SEGMENT *segments (dpl40) phantom code (dpl40) phantom data (dpl40) init code (base40ffffff80h) GATE (entry413 (entry432 TABLE create (LOCATION DESC dpl40 dpl40 trap) interrupt)
ENTRY phantom code phantom data code32 data init code) TASK MAIN TASK DATA DATA CODE main STACKS (DATA) INTENABLED PRESENT
buffer starting DESC BLD386 places base limit values Buffer must bytes long base limit values places this buffer bytes limit plus four bytes base format required LGDT instruction Explicitly place segment entries into
Task privilege level Points segment that indicates initial value Entry point main which must public Segment points stack segment Sets initial Disable interrupts Present
MEMORY (RANGE (EPROM ROM(0ffff8000h 0ffffffffh) DRAM RAM(0 0ffffh)) ALLOCATE (EPROM (MAIN TASK))) asm386 asm386 bnd386 bld386 flatsim application application application debug debug flatsim nolo debug (application bnd) (flatsim bld) flat
Commands assemble build boot-loadable application named ``application a38'' initialization code called ``flatsim a38'' build file called ``application bld''
EMBEDDED PROCESSOR
Self-Test
80376 capability perform self-test self-test checks function Control most non-random logic part Approximately one-half 80376 tested during self-test Self-Test initiated 80376 when RESET transitions from HIGH BUSY self-test takes about clocks approximately with 80376 processor completion self-test processor performs reset begins normal operation part successfully passed self-test contents register zero register zero then self-test detected flaw part self-test selected after reset non-zero after reset DEBUG REGISTERS
Debugging Support
80376 provides several features which simplify debugging process three categories onchip debugging aids code execution breakpoint opcode (0CCH) single-step capability provided flag register code data breakpoint capability provided Debug Registers BREAKPOINT INSTRUCTION single-byte software interrupt (Int breakpoint instruction available software debuggers breakpoint opcode 0CCh generates exception trap when executed
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Figure Debug Registers
EMBEDDED PROCESSOR
SINGLE-STEP TRAP single-step flag EFLAG register found instruction single-step exception occurs single-step exception auto vectored exception number Debug Registers advanced debugging feature 80376 They allow data access breakpoints well code execution breakpoints Since breakpoints indicated on-chip registers instruction execution breakpoint placed code code shared several tasks neither which supported breakpoint opcode 80376 contains Debug Registers consisting four breakpoint address registers breakpoint control registers Initially after reset breakpoints disabled state therefore breakpoints will occur unless debug registers programmed Breakpoints Debug Registers auto-vectored exception Figure shows breakpoint status control registers
ARCHITECTURE
Intel 80376 Embedded Processor physical address space Mbytes (224 bytes) allows running virtual memory programs almost unlimited size Kbytes Mbytes Gbytes (238 bytes)) addition 80376 provides sophisticated memory management hardware-assisted protection mechanism
Addressing Mechanism
80376 uses components form logical address 16-bit selector which determines linear base address segment 32-bit effective address selector used specify index into operating system defined table (see Figure table contains 32-bit base address given segment linear address formed adding base address obtained from table 32-bit effective address This value truncated bits form physical address which then placed address
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Figure Address Calculation
EMBEDDED PROCESSOR
Each tables have register associated with GDTR LDTR IDTR Figure LGDT LLDT LIDT instructions load base limit Global Local Interrupt Descriptor Tables into appropriate register SGDT SLDT SIDT store these base limit values These privileged instructions
Segmentation
Segmentation method memory management provides basis protection 80376 Segments used encapsulate regions memory which have common attributes example code given program could contained segment operating system table reside segment information about each segment stored 8-byte data structure called descriptor descriptors system contained tables recognized hardware TERMINOLOGY following terms used throughout discussion descriptors privilege levels protection Privilege Level four hierarchical privilege levels Level most privileged level level least privileged Requestor Privilege Level privilege level original supplier selector determined least significant bits selector Descriptor Privilege Level This least privileged level which task access that descriptor (and segment associated with that descriptor) Descriptor Privilege Level determined bits Access Right Byte descriptor Current Privilege Level privilege level which task currently executing which equals privilege level code segment being executed also determined examining lowest bits register except conforming code segments Effective Privilege Level effective privilege level least privileged numerical maximum
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Figure Descriptor Table Registers Global Descriptor Table Global Descriptor Table (GDT) contains descriptors which possibly available tasks system contain type segment descriptor except interrupt trap descriptors Every 80376 system contains simple 80376 system contains only entries code data descriptor maximum performance descriptor tables should begin even addresses first slot Global Descriptor Table corresponds null selector used null selector defines null pointer value Local Descriptor Table LDTs contain descriptors which associated with given task Generally operating systems designed that each task separate contain only code data stack task gate call gate descriptors LDTs provide mechanism isolating given task's code data segments from rest operating system while contains descriptors segments which common tasks segment cannot accessed task segment descriptor does exist either current This pro-
Task instance execution program Tasks also referred processes DESCRIPTOR TABLES descriptor tables define segments which used 80376 system There three types tables 80376 which hold descriptors Global Descriptor Table Local Descriptor Table Interrupt Decriptor Table tables variable length memory arrays they range size between bytes Kbytes Each table hold 8192 8-byte descriptors upper bits selector used index into descriptor table tables have registers associated with them which hold 32-bit linear base address 16-bit limit each table
EMBEDDED PROCESSOR
vides both isolation protection task's segments while still allowing global data shared among tasks Unlike 6-byte registers which contain base address limit visible portion register contains only 16-bit selector This selector refers Local Descriptor Table descriptor (see Figure ment 20-bit length granularity segment protection level read write execute privileges type segment attribute information about segment contained bits segment descriptor Figure shows general format descriptor segments 80376 have three attribute fields common Present Descriptor Privilege Level bits (DPL) Segment segment loaded physical memory then attempt access segment causes present exception (exception two-bit field which specifies protection level associated with segment 80376 main categories segments system segments non-system segments (for code data) segment determines given segment system segment code segment data segment then segment either code data segment then segment system segment Note that although 80376 limited 16-Mbyte Physical address space (224) base address allows segment placed anywhere 4-Gbyte linear address space When writing code 80376 users should keep code portability 80386 processor other processors with larger physical address space) mind segment base address placed anywhere this 4-Gbyte linear address space physical address will BYTE ADDRESS
INTERRUPT DESCRIPTOR TABLE
third table needed 80376 systems Interrupt Descriptor Table contains descriptors which point location interrupt service routines contain only task gates interrupt gates trap gates should least bytes size order hold descriptors Intel Reserved Interrupts Every interrupt used system must have entry entries referenced instructions external interrupt vectors exceptions DESCRIPTORS object which segment selector points called descriptor Descriptors eight-byte quantities which contain attributes about given region linear address space These attributes include 32-bit logical base address seg31
SEGMENT BASE SEGMENT LIMIT BASE LIMIT TYPE
BASE LIMIT TYPE
BASE
Base Address segment length segment Present Present Present Descriptor Privilege Level Code Data Descriptor Segment Descriptor System Descriptor Type Segment Accessed Granularity Segment length Kbyte Granular Segment length byte granular must zero compatibility with future processors Available field user
Figure Segment Descriptors SEGMENT BASE SEGMENT LIMIT ACCESS BASE LIMIT RIGHTS BYTE BASE
Granularity Segment length Kbyte granular Segment length byte granular must zero compatibility with future processors Available field user
Figure Code Data Descriptors
EMBEDDED PROCESSOR
Table Access Rights Byte Definition Code Data Descriptors Position Name Present Function Segment mapped into physical memory mapping physical memory exits Segment privilege attribute used privilege tests
Descriptor Privilege Level (DPL) Segment Code Data (includes stacks) segment descriptor Descriptor System Segment Descriptor Gate Descriptor Executable Expansion Direction (ED) Writable Executable Conforming Readable Accessed Descriptor type data segment Expand segment offsets must limit Expand down segment offsets must limit Data segment written into Data segment written into Descriptor type code segment Code segment only executed when remains unchanged Code segment read Code segment read Data Segment Code Segment
Segment been accessed Segment selector been loaded into segment register used selector test instructions 80376 system descriptors (which same 80386 descriptor types contain 32-bit logical base address 20-bit segment limit Selector Fields
generated that truncated version this linear address Truncation will maximum number address bits recommended place EPROM highest physical address DRAM lowest physical addresses Code Data Descriptors Figure shows general format code data descriptor Table illustrates bits Access Right Byte interpreted Code data segments have several descriptor fields common accessed whenever processor accesses descriptor granularity specifies segment length 1-bytegranular 4-Kbyte-granular Base address bits 31-24 which normally found 80386 descriptors made externally available 80376 They affect operation 80376 -A24 field should allow 80386 correctly execute with EPROM upper 4096 Mbytes physical memory System Descriptor Formats System segments describe information about operating system tables tasks gates Figure shows general format system segment descriptors various types system segments
selector three fields Local Global Descriptor Table Indicator (TI) Descriptor Entry Index (Index) Requestor selector's) Privilege Level (RPL) shown Figure selects either Global Descriptor Table Local Descriptor Table Index selects descriptors appropriate descriptor table bits allow high speed testing selector's privilege attributes Segment Descriptor Cache addition selector value every segment register segment descriptor cache register associated with Whenever segment register's contents changed 8-byte descriptor associated with that selector automatically loaded (cached) chip Once loaded references that segment cached descriptor information instead reaccessing descriptor contents descriptor cache visible programmer Since descriptor caches only change when segment register changed programs which modify descriptor tables must reload appropriate segment registers after changing descriptor's value
EMBEDDED PROCESSOR
SEGMENT BASE
SEGMENT LIMIT
Type
TYPE BASE
BASE LIMIT
Type Defines Invalid Reserved Reserved Reserved Task Gate (80376 80386 Task) Reserved Reserved
Defines Invalid Available 80376 80386 Undefined (Intel Reserved) Busy 80376 80386 80376 80386 Call Gate Undefined (Intel Reserved) 80376 80386 Interrupt Gate 80376 80386 Trap Gate
Figure System Descriptors
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Figure Example Descriptor Selection
Protection
80376 offers extensive protection features These protection features particularly useful sophisticated embedded applications which multitasking real-time operating systems simpler embedded applications these protection capabilities easily bypassed making applications privilege level (PL) RULES PRIVILEGE 80376 controls access both data procedures between levels task according following rules
Data stored segment with privilege level accessed only code executing privilege level least privileged code segment procedure with privilege level only called task executing same lesser privilege level than PRIVILEGE LEVELS point time task 80376 always executes four privilege levels Current Privilege Level (CPL) specifies what task's privilege level task's only changed
EMBEDDED PROCESSOR
control transfers through gate descriptors code segment with different privilege level Thus application program running call operating system routine (via gate) which would cause task's until operating system routine finished Selector Privilege (RPL) privilege level selector specified field selector's only used establish less trusted privilege level than current privilege level task segment This level called task's effective privilege level (EPL) defined being least privileged (numerically larger) level task's selector's most commonly used verify that pointers passed operating system procedure access data that higher privilege than procedure that originated pointer Since originator selector specify value Adjust (ARPL) instruction provided force bits originator's Privilege privilege level (IOPL) lets operating system code executing define least privileged level which instructions used exception (General Protection Violation) generated instruction attempted when task less privileged than IOPL IOPL stored bits EFLAGS register following instructions cause exception greater than IOPL OUTS LOCK prefix Descriptor Access There basically types segment accessess those involving code segments such control transfers those involving data accesses Determining ability task access segment involves type segment accessed instruction used type descriptor used described above time instruction loads data segment register 80376 makes protection validation checks Selectors loaded registers must refer only data segment readable code segments Finally privilege validation checks performed compared more privileged than exception (general protection fault) generated rules regarding stack segment slightly different than those involving data segments Instructions that load selectors into must refer data segment descriptors writeable data segments must equal other descriptor types privilege level violation will cause exception stack present fault causes exception PRIVILEGE LEVEL TRANSFERS Inter-segment control transfers occur when selector loaded register typical system most these transfers simply result call jump another routine There five types control transfers which summarized Table Many these transfers result privilege level transfer Changing privilege levels done only control transfers using gates task switches interrupt trap gates Control transfers only occur operation which loaded selector references correct descriptor type violation these descriptor usage rules will cause exception CALL GATES Gates provide protected indirect CALLs major uses gates provide secure method privilege transfers within task Since operating system defines gates system ensure that gates only allow entry into trusted procedures
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Table Descriptor Types Used Control Transfer Control Transfer Types Intersegment within same privilege level Intersegment same higher privilege level Interrupt within task change Operation Types CALL IRET CALL Interrupt Instruction Exception External Interrupt IRET CALL Task Switch CALL IRET Interrupt Instruction Exception External Interrupt
(Nested Task flag register) (Nested Task flag register)
Descriptor Referenced Code Segment Call Gate Trap Interrupt Gate Code Segment Task State Segment Task Gate Task Gate
Descriptor Table
Intersegment lower privilege level (changes task CPL)
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NOTE OFFSET must DFFFH
Type Available 80376 Type Busy 80376
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Figure 80376 Registers
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interrupted current executing task's state saved task state restored from Several bits flag register register give information about state task which useful operating system Nested Task controls function IRET instruction IRET instruction performs regular return IRET performs task switch operation back previous task reset following fashion When CALL instruction initiates task switch will marked busy back link field selector task CALL initiated task switches interrupt that does cause task switch will clear (The will restored after execution interrupt handler) also cleared POPF IRET instructions 80376 task state segment marked busy changing descriptor type field from TYPE TYPE selector that references busy task state segment causes exception coprocessor's state automatically saved when task switch occurs Task Switched register helps deal with coprocessor's state multi-tasking environment Whenever 80376 switches tasks sets 80376 detects first processor extension instruction after task switch causes processor extension available exception exception handler exception then decide whether save state coprocessor 80376 indicates that processor should generate debug exception when switching task then upon entry task debug exception will generated
TASK SWITCHING very important attribute multi-tasking operating system ability rapidly switch between tasks processes 80376 directly supports this operation providing task switch instruction hardware 80376 task switch operation saves entire state machine (all registers address space link previous task) loads execution state performs protection checks commences execution task Like transfer control gates task switch operation invoked executing inter-segment CALL instruction which refers Task State Segment (TSS) task gate descriptor instruction exception trap external interrupt also invoke task switch operation there task gate descriptor associated descriptor slot simple applications task switching used task switch will used occur task gates present descriptor points segment (see Figure containing entire 80376 execution state task gate descriptor contains selector limit 80376 must greater than large Mbytes additional space operating system free store additional information reason task inactive time task spent running open files belonging task maximum performance should start even address Each Task must have associated with current identified special register 80376 called Task State Segment Register (TR) This register contains selector referring task state segment descriptor that defines current hidden base limit register associated with descriptor loaded whenever loaded with selector Returning from task accomplished IRET instruction When IRET executed control returned task which
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Figure Sample Permission
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necessary permission represent addresses addresses spanned treated they onebits base should least byte less than limit last byte beyond mapping information must contain Because permission segment different tasks have different maps Thus operating system allocate ports task changing permission task's IMPORTANT IMPLEMENTATION NOTE Beyond last byte mapping information permission must byte containing byte must within limit 80376's segment (see Figure
PROTECTION PERMISSION instructions that directly refer addresses processor's space OUTS 80376 ability selectively trap references specific addresses structure that enables selective trapping Permission segment (see Figures permission vector size location segment variable processor locates permission means base field fixed portion base field bits wide contains offset beginning permission instruction OUTS) encountered processor first checks whether IOPL this condition true operation proceed true processor checks permission Each corresponds port byte address example port found base linearly offset processor tests bits that correspond addresses spanned operation example double word operation tests four bits corresponding four adjacent byte addresses tested processor signals general protection exception tested bits zero operations proceed
FUNCTIONAL DATA
Intel 80376 embedded processor features straightforward functional interface external hardware 80376 separate parallel buses data address data bits width bidirectional address outputs 24-bit address values using address lines two-byte enable signals 80376 selectable address cycles pipelined non-pipelined pipelining option allows much time possible data access
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Figure Functional Signal Groups
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starting pending cycle before present cycle finished non-pipelined cycle gives highest performance executing every cycle processor clock cycles maximum design flexibility address pipelining option selectable cycle-by-cycle basis processor's cycle basic mechanism information transfer either from system processor from processor system 80376 cycles perform data transfer minimum only clock periods 16-bit data maximum 80376 transfer bandwidth therefore Mbytes However cycle will extended more than clock periods external hardware withholds acknowledgement cycle 80376 relinquish control local buses allow mastership other devices such direct memory access (DMA) channels When relinquished HLDA only output driven 80376 providing near-complete isolation processor from system (all other output pins float condition)
Signal Description Overview
Ahead brief description 80376 input output signals arranged functional groups signal descriptions sometimes refer timing parameters such ``t25 Reset Setup Time'' ``t26 Reset Hold Time values these parameters found Tables CLOCK (CLK2) CLK2 provides fundamental timing 80376 divided internally generate internal processor clock used instruction execution internal clock comprised
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Figure CLK2 Signal Internal Processor Clock
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phases ``phase one'' ``phase two'' Each CLK2 period phase internal clock Figure illustrates relationship desired phase internal processor clock synchronized known phase ensuring falling edge RESET signal meets applicable setup hold times DATA (D15 -D0) These three-state bidirectional signals provide general purpose data path between 80376 other devices data outputs active HIGH will float during hold acknowledge Data reads require that read-data setup hold times relative CLK2 correct operation ADDRESS (BHE -A1) These three-state outputs provide physical memory addresses port addresses -A16 during transfers except transfers automatically generated coprocessor instructions During coprocessor transfers -A16 driven driven HIGH that this address line used external logic generate coprocessor select signal Thus address driven 80376 coprocessor commands 8000F8H address driven 80376 processor coprocessor data 8000FCH 8000FEH address capable addressing Mbytes physical memory space (000000H through 0FFFFFFH) Kbytes address space (000000H through 00FFFFH) programmed address active HIGH will float during hold acknowledge Byte Enable outputs directly indicate which bytes 16-bit data involved with current transfer applies applies both asserted then bits data being transferred Table complete decoding these signals byte enables active will float during hold acknowledge
Table Byte Enable Definitions Word Transfer Byte Transfer Upper Byte Data Byte Transfer Lower Byte Data Never Occurs Function
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CYCLE DEFINITION SIGNALS LOCK) These three-state outputs define type cycle being performed distinguishes between write read cycles distinguishes between data control cycles distinguishes between memory cycles LOCK distinguishes between locked unlocked cycles these signals active will float during acknowledge primary cycle definition signals since these signals driven valid (Address Status output) becomes active LOCK signal driven valid same time cycle begins which address pipelining could after becomes active Exact cycle definitions function given Table LOCK indicates that other system masters gain control system while active LOCK activated CLK2 edge that begins first locked cycle active same time other cycle definition pins) deactivated when ready returned last cycle which locked beginning cycle determined when READY returned previous cycle another pending (ADS active) clock which driven active idle This means that follows more closely with write data rules when valid cause locked longer than desired LOCK signal explicitly activated LOCK prefix certain instructions LOCK always asserted when executing XCHG instruction during descriptor updates during interrupt acknowledge sequence
CONTROL SIGNALS (ADS READY following signals allow processor indicate when cycle begun allow other system hardware control address pipelining cycle termination Address Status (ADS) This three-state output indicates that valid cycle definition address -A1) being driven 80376 pins active output Once driven active valid address byte enables definition signals will change addition will remain active until associated cycle begins (when READY returned previous cycle when running pipelined cycles) will float during hold acknowledge sections NonPipelined Cycles Pipelined Cycles additional information asserted different states Transfer Acknowledge (READY) This input indicates current cycle complete active bytes indicated accepted provided When READY sampled active during read cycle interrupt acknowledge cycle 80376 latches input data terminates cycle When READY sampled active during write cycle processor terminates cycle
Table Cycle Definition Cycle Type INTERRUPT ACKNOWLEDGE Does Occur DATA READ DATA WRITE MEMORY CODE READ HALT Address SHUTDOWN Address Locked
MEMORY DATA READ MEMORY DATA WRITE
Some Cycles Some Cycles
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READY ignored first state cycles sampled each state thereafter until asserted READY must eventually asserted acknowledge every cycle including Halt Indication Shutdown Indication cycles When being sampled READY must always meet setup hold times correct operation Next Address Request (NA) This used request pipelining This input indicates system prepared accept values from 80376 even current cycle being acknowledged READY this input active when sampled next cycle's address status signals driven onto provided next request already pending internally ignored clock cycles which READY activated This signal active must satisfy setup hold times correct operation Pipelined Cycles Read Write Cycles additional information ARBITRATION SIGNALS (HOLD HLDA) This section describes mechanism which processor relinquishes control local buses when requested another master device Entering Exiting Hold Acknowledge additional information Hold Request (HOLD) This input indicates some device other than 80376 requires mastership When control granted 80376 floats LOCK then activates HLDA thus entering hold acknowledge state local will remain granted requesting master until HOLD becomes inactive When HOLD becomes inactive 80376 will deactivate HLDA drive local same time) thus terminating hold acknowledge condition HOLD must remain asserted long other device local master External pull-up resistors required when hold acknowledge state since none 80376 floated outputs have internal pull-up resistors Resistor Recommendations additional information HOLD recognized while RESET active recognized during time between high-to-low transistion RESET first instruction fetch RESET asserted while HOLD asserted RESET priority places into idle state rather than hold acknowledge (high-impedance) state When HOLD signal made inactive 80376 will deactivate HLDA drive rising edge input remembered processing after HOLD input negated Table Output State during HOLD Value Float Names HLDA LOCK HOLD level-sensitive active HIGH synchronous input HOLD signals must always meet setup hold times correct operation Hold Acknowledge (HLDA) When active (HIGH) this output indicates 80376 relinquished control local response asserted HOLD signal Hold Acknowledge state Hold Acknowledge state offers near-complete signal isolation Hold Acknowledge state HLDA only signal being driven 80376 other output signals bidirectional signals (D15 LOCK ADS) high-impedance state requesting master control them These pins remain throughout time that HLDA remains active (see Table Pull-up resistors desired several signals avoid spurious activity when master driving them Resistor Recommendations additional information
Hold Latencies maximum possible HOLD latency depends software being executed actual HOLD latency time depends current activity state LOCK signal (internal CPU) activated LOCK prefix interrupts 80376 will honor HOLD request until current operation complete 80376 breaks 32-bit data accesses into internally locked 16-bit cycles LOCK signal asserted 80376 breaks unaligned 16-bit 32-bit data accesses into internally locked 16-bit cycles Again LOCK signal asserted HOLD request will recognized until entire transfer
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Wait states affect HOLD latency 80376 will honor HOLD request until current operation matter many wait states required Systems with where data transfer critical must insure that READY returns sufficiently soon F(N)INIT F(N)CLEX coprocessor instructions allowed execute even BUSY active since these instructions used coprocessor initialization exception-clearing BUSY active level-sensitive asynchronous signal Setup hold times relative CLK2 signal must guarantee recognition particular clock edge This provided with weak internal pull-up resistor around that will float active when left unconnected BUSY serves additional function BUSY sampled falling edge RESET 80376 processor performs internal self-test (see Activity During Following Reset BUSY sampled HIGH self-test performed Coprocessor Error (ERROR) When asserted (HIGH) this input signal indicates coprocessor request data operand transferred from memory 80376 response 80376 transfers information between coprocessor memory Because 80376 internally stored coprocessor opcode being executed performs requested data transfer with correct direction memory address PEREQ level-sensitive active HIGH asynchronous signal Setup hold times relative CLK2 signal must guarantee recognition particular clock edge This signal provided with weak internal pull-down resistor around ground that will float active when left unconnected Coprocessor Busy (BUSY) When asserted (LOW) this input indicates coprocessor still executing instruction able accept another When 80376 encounters coprocessor instruction which operates numerics stack load arithmetic operation) WAIT instruction this input first automatically sampled until seen inactive This sampling BUSY input prevents overrunning execution previous coprocessor instruction When asserted (LOW) this input signal indicates that previous coprocessor instruction generated coprocessor error type masked coprocessor's control register This input automatically sampled 80376 when coprocessor instruction encountered active 80376 generates exception access error-handling software Several coprocessor instructions generally those which clear numeric error flags coprocessor save coprocessor state execute without 80376 generating exception even ERROR active These instructions FNINIT FNCLEX FNSTSW FNSTSWAX FNSTCW FNSTENV FNSAVE ERROR active level-sensitive asynchronous signal Setup hold times relative CLK2 signal must guarantee recognition particular clock edge This provided with weak internal pull-up resistor around that will float active when left unconnected
COPROCESSOR INTERFACE SIGNALS (PEREQ BUSY ERROR) following sections descriptions signals dedicated numeric coprocessor interface addition data address cycle definition signals these following signals control communication between 80376 80387SX processor extension Coprocessor Request (PEREQ)
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INTERRUPT SIGNALS (INTR RESET) following descriptions cover inputs that interrupt suspend execution processor's current instruction stream Maskable Interrupt Request (INTR) When asserted this input indicates request interrupt service which masked 80376 Flag Register When 80376 responds INTR input performs interrupt acknowledge cycles second latches 8-bit interrupt vector identify source interrupt INTR active HIGH level-sensitive asynchronous signal Setup hold times relative CLK2 signal must guarantee recognition particular clock edge assure recognition INTR request INTR should remain active until first interrupt acknowledge cycle begins INTR sampled beginning every instruction order recognized particular instruction boundary INTR must active least eight CLK2 clock periods before beginning execution instruction recognized 80376 will begin execution interrupt Non-Maskable Interrupt Request (NMI) This input indicates request interrupt service which cannot masked software nonmaskable interrupt request always processed according pointer gate slot interrupt table Because fixed slot assignment interrupt acknowledge cycles performed when processing active HIGH rising edge-sensitive asynchronous signal Setup hold times relative CLK2 signal must guarantee recognition particular clock edge assure recognition must inactive least eight CLK2 periods then active least eight CLK2 periods before beginning execution instruction Once processing begun additional NMI's processed until after next IRET instruction which typically service routine re-asserted prior that time however rising edge will remembered processing after executing next IRET instruction
Interrupt Latency time that elapses before interrupt request serviced (interrupt latency) varies according several factors This delay must taken into account interrupt source following factors affect interrupt latency interrupts masked INTR request will recognized until interrupts reenabled currently being serviced incoming request will recognized until 80376 encounters IRET instruction interrupt request recognized only instruction boundary 80376 Execution Unit except following cases Repeat string instructions interrupted after each iteration instruction loads Stack Segment register interrupt processed until after following instruction which should load This allows entire stack pointer loaded without interruption instruction sets interrupt flag (enabling interrupts) interrupt processed until after next instruction longest latency occurs when interrupt request arrives while 80376 processor executing long instruction such multiplication division task-switch Saving Flags register registers interrupt service routine requires task switch time must allowed task switch interrupt service routine saves registers that automatically saved 80376 RESET This input signal suspends operation progress places 80376 known reset state 80376 reset asserting RESET more CLK2 periods more CLK2 periods before requesting self-test) When RESET active other input pins except ignored other pins driven idle state shown Table RESET HOLD both active point time RESET takes priority even 80376 Hold Acknowledge state prior RESET active RESET active HIGH level-sensitive synchronous signal Setup hold times must order assure proper operation 80376
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Each cycle composed least states Each state requires processor clock period Additional states added single cycle called wait states Functional Description additional information
Table State (Bus Idle) during RESET Name LOCK HLDA Signal Level during RESET Float
Memory Spaces
cycles access physical memory space space Peripheral devices system either memory-mapped O-mapped both shown Figure physical memory addresses range from 000000H 0FFFFFFH Mbytes) addresses from 000000H 00FFFFH Kbytes) Note addresses used automatic cycles coprocessor communication 8000F8H 8000FFH beyond address range programmed allow easy generation coprocessor chip select signal using signals OPERAND ALIGNMENT With flexibility memory addressing 80376 possible transfer logical operand that spans more than physical Dword word memory Examples 32-bit Dword 16-bit word operands beginning addresses evenly divisible Operand alignment size dictate when multiple cycles required Table describes transfer cycles generated combinations logical operand lengths alignment Table Transfer Cycles Bytes Words Dwords
Byte-Length Logical Operand Physical Byte Address Memory (Low-Order Bits) Transfer Cycles
Transfer Mechanism
data transfers occur result more cycles Logical data operands byte word lengths transferred without restrictions physical address alignment byte boundary used although physical cycles performed required unaligned operand transfers 80376 processor address signals designed simplify external system hardware provide linear selects bytes 16-bit data Byte Enable outputs asserted when their associated data bytes involved with present cycle listed Table Table Byte Enables Associated Data Operand Bytes Byte Enable Associated Data Signals (Byte Most Significant) (Byte Least Significant)
byte transfer word transfer low-order portion mid-order portion don't care high-order portion
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NOTE Since HIGH during automatic communication with coprocessor HIGH used easily generate coprocessor select signal
Figure Physical Memory Spaces
Functional Description
80376 separate parallel buses data address data bits width bidirectional address provides 24-bit value using signals upper-order address bits Byte Enable signals directly indicate active bytes These buses interpreted controlled several definition signals definition each cycle given three signals same time valid address present byte enable signals other address signals status signal indicates when 80376 issues cycle definition address Collectively address data associated control signals referred simply ``the bus'' When active performs cycles below Read from memory space Locked read from memory space Write memory space Locked write memory space
Read from space coprocessor) Write space coprocessor) Interrupt acknowledge (always locked) Indicate halt indicate shutdown Table shows encoding cycle definition signals each cycle Cycle Definition Signals additonal information When 80376 performing activities listed above either Idle Hold Acknowledge state which detected external circuitry idle state identified 80376 giving further assertions address strobe output (ADS) since beginning most recent cycle most recent cycle having been terminated hold acknowledge state identified 80376 asserting hold acknowledge (HLDA) output shortest time unit activity state state processor clock period (two CLK2 periods) duration complete data transfer occurs during cycle composed more states
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Figure Fastest Read Cycles with Non-Pipelined Timing fastest 80376 cycle requires only states example three consecutive read cycles each consisting states shown Figure states each cycle named memory address accessed such two-state cycle external hardware fast enough Every cycle continues until acknowledged external system hardware using 80376 READY input Acknowledging cycle first results shortest cycle requiring only READY immediately asserted however states repeated indefinitely until READY input sampled active pipelining option provides choice cycle timings Pipelined non-pipelined cycles selectable cycle-by-cycle basis with Next Address (NA) input When pipelining selected address (BHE -A1) definition LOCK) next cycle available before current cycle signal their availability 80376 address status output (ADS) asserted Figure illustrates fastest read cycles with pipelined timing Note from Figure fastest cycles using pipelining require only states named Therefore pipelined cycles allow same data bandwidth non-pipelined cycles address-to-data access time increased T-state time compared that non-pipelined cycle
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Figure Fastest Read Cycles with Pipelined Timing READ WRITE CYCLES Data transfers occur result cycles classified read write cycles During read cycles data transferred from external device processor During write cycles data transferred from processor external device choices cycle timing dynamically selectable non-pipelined pipelined After idle state processor always uses non-pipelined timing However (Next Address) input asserted select pipelined timing next cycle When pipelining selected 80376 request pending internally address definition next cycle made available even before current cycle acknowledged READY Terminating read write cycle like cycle requires acknowledging cycle asserting READY input Until acknowledged processor inserts wait states into cycle allow adjustment speed external device External hardware which decoded address cycle type asserts READY input appropriate time second state within cycle READY sampled that time external hardware acknowledges cycle asserting READY cycle terminates shown Figure READY negated Figure 80376 executes another state wait state) READY sampled again that state This continues indefinitely until cycle acknowledged READY asserted When current cycle acknowledged 80376 terminates When read cycle acknowledged 80376 latches information present data pins When write cycle acknowledged write data 80376 remains valid throughout phase next state provide write data hold time
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Idle states shown here diagram variety only Write cycles always followed idle state active cycle immediately follow write cycle
Figure Various Non-Pipelined Cycles (Zero Wait States) Non-Pipelined Cycles cycle performed with non-pipelined timing example Figure shows mixture non-pipelined read write cycles Figure shows that fastest possible non-pipelined cycles have states cycle states named phase address signals cycle definition signals driven valid signal their availability address strobe (ADS) simultaneously asserted During read write cycles data behaves follows cycle read 80376 floats data signals allow driving external device being addressed 80376 requires that data pins valid logic state (HIGH LOW) each read cycle when READY asserted system MUST designed meet this requirement cycle write data signals driven 80376 beginning phase until phase state following cycle acknowledgement
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Idle states shown here diagram variety only Write cycles always followed idle state active cycle immediately follow write cycle
Figure Various Non-Pipelined Cycles (Various Number Wait States) Figure illustrates non-pipelined cycles with wait state added Cycles READY sampled inactive first Cycles Therefore Cycles have repeated again second READY sampled active When address pipelining used address cycle definition remain valid during wait states When wait states added desirable maintain non-pipelined timing necessary negate during each state except last shown Figure Cycles sampled active during other than last next state would instead another When address pipelining used states transitions completely illustrated Figure transitions between four possible states cycles consist with being repeated wait states Otherwise idle hold acknowledge state
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States first clock non-pipelined cycle (80376 drives address asserts ADS) subsequent clocks cycle when been sampled asserted current cycle idle state hold acknowledge state (80376 asserts HLDA) fastest cycle consists states Four basic states describe operation when using pipelined address
Figure 80376 States (Not Using Pipelined Address) cycles always begin with always leads cycle acknowledged during inactive repeated When cycle acknowledged during following state will next cycle request pending internally there request pending HOLD input being asserted pipelining allows 80376 enter three additional states shown Figure Figure complete state diagram including pipelined cycles Pipelined Cycles Pipelining option requesting address cycle definition next internally pending cycle before current cycle acknowledged with READY asserted asserted 80376 when next address issued pipelining option controlled cycleby-cycle basis with input signal Once cycle progress current address been valid least entire state input sampled every phase until cycle acknowledged During non-pipelined cycles sampled phase every example Cycle Figure during which sampled phase every asserted once during first further effect during that cycle)
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Following idle state (Ti) cycles non-pipelined Within non-pipelined cycles only sampled during wait states Therefore begin pipelining during group non-pipelined cycles requires non-pipelined cycle with least wait state (Cylcle above)
Figure Transitioning Pipelining during Burst Cycles sampled active 80376 free drive address cycle definition next cycle assert soon request internally pending drive next address early next state whether current cycle acknowledged that time Regarding details pipelining 80376 following characteristics next address status appear early state after sampled active (see Figures that case state entered immediately However when there internal request already pending next address status will available immediately after asserted entered instead (see Figure Cycle Provided current cycle isn't acknowledged READY asserted will entered soon 80376 does drive next address status External hardware should therefore observe output confirmation next address status actually being driven address status which validated pulse 80376 output will remain stable address pins least processor clock periods 80376 cannot produce address status more frequently than every processor clock periods (see Figures Only address cycle definition very next cycle available pipelining capability cannot look further than cycle ahead (see Figure Cycle
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Following idle state (Ti) cycle always non-pipelined only sampled during wait states start address pipelining after idle state requires non-pipelined cycle with least wait state (cycle above) pipelined cycles above) shown with various numbers wait states
Figure Fastest Transition Pipelined Cycle Following Idle State complete state transition diagram including pipelining given Figure Note superset diagram non-pipelined only three additional states pipelining drawn bold fastest cycle with pipelining consists just states (recall non-pipelined first state pipelined cycle Initiating Maintaining Pipelined Cycles Using state diagram Figure observe transitions from idle state beginning pipelined cycle From idle state first cycle must begin with therefore non-pipelined cycle next cycle will pipelined however provided asserted first cycle ends state (the address status next cycle driven during T2P) fastest path from idle state pipelined cycle shown bold below idle states non-pipelined cycle pipelined cycle
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Figure Details Address Pipelining during Cycles with Wait States T1-T2-T2P states cycle that establishes address pipelining next cycle which begins with same true after hold state shown below T1-T2-T2P T1P-T2P pipelined cycle transition pipelined address shown functionally Figure Cycle Note that Cycle used transition into pipelined address timing subsequent Cycles which pipelined input asserted appropriate time select address pipelining Cycles Once cycle progress current address status been valid entire state input sampled every phase until cycle acknowledged
hold aknowledge non-pipelined states cycle
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States first clock non-pipelined cycle (80376 drives address status asserts ADS) subsequent clocks cycle when been sampled asserted current cycle subsequent clocks cycle when been sampled asserted current cycle there internal request pending (80376 will drive address status assert ADS) subsequent clocks cycle when been sampled asserted current cycle there internal request pending (80376 drives address status asserts ADS) first clock pipelined cycle idle state hold acknowledge state (80376 asserts HLDA) Asserting pipelined cycles gives access three more states Using pipelining fastest cycle consists
Figure 80376 Processor Complete States (Including Pipelining)
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Sampling begins during Cycle Figure Once sampled active during current cycle 80376 free drive address cycle definition early next state Figure Cycle example next address status driven during state Thus Cycle makes transition pipelined timing since begins with ends with Because address Cycle available before Cycle begins Cycle called pipelined cycle begins with Cycle begins soon READY asserted terminates Cycle Examples transition cycles Figure Cycle Figure Cycle Figure shows transition during very first cycle after idle state which fastest possible transition into address pipelining Figure Cycle shows transition cycle occurring during burst cycles case transition cycle same whenever occurs consists least asserted that time) (provided 80376 internal request already pending which almost always has) states repeated wait states added cycle Note that only three states T2P) required cycle performing transition from non-pipelined into pipelined timing example Figure Cycle Figure Cycles show that pipelining maintained with twostate cycles consisting only Once pipelined cycle progress pipelined timing maintained next cycle asserting detecting that 80376 enters during current cycle current cycle must state pipelining maintained next cycle identified assertion Figures however each show pipelining ending after Cycle because Cycle ends This indicates 80376 didn't have internal request prior acknowledgement Cycle cycle ends with next cycle will pipelined Realistically pipelining almost always maintained long sampled asserted This because absence other request code prefetch request always internally pending until instruction decoder code prefetch queue completely full Therefore pipelining maintained long bursts cycles available HOLD inactive) sampled active each cycles INTERRUPT ACKNOWLEDGE (INTA) CYCLES repsonse interrupt request INTR input when interrupts enabled 80376 performs interrupt acknowledge cycles These cycles similar read cycles that definition signals define type activity taking place each cycle continues until acknowledged READY sampled active state distinguishes first second interrupt acknowledge cycles byte address driven during first interrupt acknowledge cycle (A23 HIGH) byte address driven during second interrupt acknowledge cycle (A23 HIGH) LOCK output asserted from beginning first interrupt acknowledge cycle until second interrupt acknowledge cycle Four idle states inserted 80376 between interrupt acknowledge cycles compatibility with interrupt specification TRHRL 8259A Interrupt Controller 82370 Integrated Peripheral
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Interrupt Vector (0-255) read D0-D7 second Interrupt Acknowledge cycle Because each Interrupt Acknowledge cycle followed idle states asserting practical effect Choose approach which simplest your system hardware design
Figure Interrupt Acknowledge Cycles During both interrupt acknowledge cycles float data read first interrupt acknowledge cycle second interrupt acknowledge cycle 80376 will read external interrupt vector from data vector indicates specific interrupt number (from 0-255) requiring service HALT INDICATION CYCLE 80376 execution unit halts result executing instruction Signaling entrance into halt state halt indication cycle performed halt indication cycle identified state definition signals byte address Cycle Definition Signals section halt indication cycle must acknowledged READY asserted halted 80376 resumes execution when INTR interrupts enabled) RESET asserted
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Figure Example Halt Indication Cycle from Non-Pipelined Cycle SHUTDOWN INDICATION CYCLE 80376 shuts down result protection fault while attempting process double fault Signaling entrance into shutdown state shutdown indication cycle performed shutdown indication cycle identified state definition signals shown Cycle Definition Signals byte address shutdown indication cycle must acknowledged READY asserted shutdown 80376 resumes execution when RESET asserted ENTERING EXITING HOLD ACKNOWLEDGE hold acknowledge state entered response HOLD input being asserted hold acknowledge state 80376 floats outputs bidirectional signals except HLDA HLDA asserted long 80376 remains hold acknowledge state hold acknowledge state inputs except HOLD RESET ignored
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Figure Example Shutdown Indication Cycle from Non-Pipelined Cycle entered from idle state Figure after acknowledgement current physical cycle LOCK signal asserted Figures exited response HOLD input being negated following state will Figure request pending following state will request internally pending Figures exited response RESET being asserted rising edge occurs edge-triggered input while event remembered nonmaskable interrupt serviced when exited unless 80376 reset before exited
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NOTE maximum design flexibility 80376 internal pull-up resistors outputs Your design require external pullup other 80376 outputs keep them negated during float periods
Figure Requesting Hold from Idle RESET DURING HOLD ACKNOWLEDGE RESET being asserted takes priority over HOLD being asserted RESET asserted while HOLD remains asserted 80376 drives pins defined states during reset Table State During Reset performs internal reset activity usual HOLD remains asserted when RESET inactive 80376 enters hold acknowledge state before performing first cycle provided HOLD still asserted when 80376 processor would otherwise perform first cycle HOLD remains asserted when RESET inactive BUSY input still sampled usual determine whether self test being requested FLOAT Activating input floats 80376 bidirectional output signals including HLDA Asserting isolates 80376 from surrounding circuitry When 80376 PQFP surface-mount package used without socket cannot removed from printed circuit board input allows 80376 electrically isolated allow testing external circuitry This technique known ONCE ``ON-Circuit Emulation'' ENTERING EXITING FLOAT asynchronous active-low input recognized rising edge CLK2 When recognized aborts current cycle floats outputs 80376 (Figure must held minimum CLK2 cycles Reset should asserted held asserted until after deasserted This will ensure that 80376 will exit float valid state Asserting input unconditionally aborts current cycle forces 80376 into FLOAT mode Since activating unconditionally forces 80376 into FLOAT mode 80376
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NOTE HOLD synchronous input asserted CLK2 edge provided setup hold (t23 t24) requirements This waveform useful determining Hold Acknowledge latency
Figure Requesting Hold from Active Inactive) guaranteed enter FLOAT valid state After deactivating 80376 guaranteed exit FLOAT mode valid state This problem meant used only during ONCE After exiting FLOAT 80376 must reset return valid state Reset should asserted before deasserted This will ensure that 80376 will exit float valid state internal pull-up resistor used should unconnected ACTIVITY DURING FOLLOWING RESET RESET highest priority input signal capable interrupting processor activity when asserted cycle progress aborted stage idle states hold acknowledge states discontinued that reset state established RESET should remain asserted least CLK2 periods ensure recognized throughout 80376 least CLK2 periods 80376 selftest going requested falling edge RESET asserted pulses less than CLK2 periods recognized RESET pulses less than CLK2 periods followed self-test cause selftest report failure when true failure exists Provided RESET falling edge meets setup hold times internal processor clock phase defined that time illustrated Figure Figure
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NOTE HOLD synchronous input asserted CLK2 edge provided setup hold (t23 t24) requirements This waveform useful determining Hold Acknowledge latency
Figure Requesting Hold from Idle Active) 80376 self-test requested time RESET goes inactive having BUSY input level shown Figure self-test requires (220 approximately CLK2 periods complete self-test duration affected test results Even self-test indicates problem 80376 attempts proceed with reset sequence afterwards After RESET falling edge (and after self-test requested) 80376 performs internal initialization sequence approximately CLK2 periods
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NOTES BUSY should held stable CLK2 periods before after CLK2 period which RESET falling edge occurs self-test requested 80376 outputs remain their reset state shown here
Figure Activity from Reset until First Code Fetch
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Figure Entering Exiting FLOAT
EMBEDDED PROCESSOR
80376 begins supporting coprocessor instruction tests BUSY ERROR signals determine coprocessor accept next instruction Thus BUSY ERROR inputs eliminate need ``preamble'' cycles communication between processor coprocessor 80387SX given command opcode immediately dedicated signals provide instruction synchronization eliminate need using 80376 WAIT opcode (9BH) 80387SX instruction synchronization (the WAIT opcode required when 8086 8088 used with 8087 coprocessor) Custom coprocessors included 80376 based systems memory-mapped O-mapped interfaces Such coprocessor interfaces allow completely custom protocol limited coprocessor protocol ``primitives'' Instead memory-mapped O-mapped interfaces applicable 80376 instructions high-speed coprocessor communication BUSY ERROR inputs 80376 also used custom coprocessor interface such hardware assist desired These signals tested 80376 WAIT opcode (9BH) WAIT instruction will wait until BUSY input inactive (interruptable enabled INTR input) generates exception fault ERROR active when BUSY goes inactive custom coprocessor interface memory-mapped protection addresses used interface provided with segmentation mechanism 80376 custom interface O-mapped protection interface provided with 80376 IOPL Privilege Level) mechanism 80387SX numeric coprocessor interface mapped shown Table Note that 80387SX coprocessor interface addresses beyond 0H-0FFFFH range programmed When 80376 supports 80387SX coprocessor 80376 automatically generates cycles coprocessor interface addresses Table Numeric Coprocessor Port Addresses Address 80376 Space 8000F8H 8000FCH 8000FEH 80387SX Coprocessor Register Opcode Register Operand Register Operand Register
Self-Test Signature
Upon completion self-test self-test requested driving BUSY falling edge RESET) register will contain signature 00000000H indicating 80376 passed self-test microcode major contents with problems detected passing signature 00000000H applies 80376 revision levels non-zero signature indicates 80376 unit faulty
Component Revision Identifiers
assist 80376 users 80376 after reset holds component identifier revision identifier register upper bits hold identification 80376 component (The lower nibble refers Intel386 architecture upper nibble refers third member Intel386 family) lower bits hold 8-bit unsigned binary number related component revision level revision identifier will general chronologically track those component steppings which intended have certain improvements distinction from previous steppings 80376 revision identifier will track that 80386 where possible revision identifier intended assist 80376 users practical extent However revision identifier value guaranteed change with every stepping revision follow completely uniform numerical sequence depending type intention revision manufacturing materials required changed Intel sole discretion over these characteristics component Table Component Revision Identifier History 80376 Stepping Name Revision Identifier
Coprocessor Interfacing
80376 provides automatic interface Intel 80387SX numeric floating-point coprocessor 80387SX coprocessor uses mapped interface driven automatically 80376 assisted three dedicated signals BUSY ERROR PEREQ
EMBEDDED PROCESSOR
SOFTWARE TESTING COPROCESSOR PRESENCE When software used test coprocessor (80387SX) presence should only following coprocessor opcodes FNINIT FNSTCW FNSTSW other coprocessor opcodes when coprocessor known present first 80376 register
Table 80376 Maximum Allowable Ambient Temperature Various Airflows Airflow-ft sec) Package 1000 100-Lead Fine Pitch 88-Pin
PACKAGE THERMAL SPECIFICATIONS
Intel 80376 embedded processor specified operation when case temperature within range C-115 both ceramic 88-pin package plastic 100-pin PQFP package case temperature measured environment determine whether 80376 within specified operating range case temperature should measured center surface ambient temperature guaranteed long violated ambient temperature calculated from from following equations
ELECTRICAL SPECIFICATIONS
following sections describe recommended electrical connections 80376 electrical specifications
Power Grounding
80376 implemented CHMOS technology modest power requirements However high clock frequency output buffers (address data control HLDA) cause power surges multiple output buffers drive signal levels simultaneously clean on-chip power distribution high frequency pins separately feed functional units 80376 Power ground connections must made external pins 80376 circuit board pins should connected plane pins should connected plane POWER DECOUPLING RECOMMENDATIONS Liberal decoupling capacitors should placed near 80376 80376 driving 24-bit address 16-bit data high frequencies cause transient power surges particularly when driving large capacitive loads inductance capacitors interconnects recommended best high frequency electrical performance Inductance reduced shortening circuit board traces between 80376 decoupling capacitors much possible RESISTOR RECOMMENDATIONS
Values given Table 100-lead fine pitch given various airflows Table shows maximum allowable (without exceeding various airflows Note that improved further attaching ``fins'' ``heat sink'' package calculated using maximum cold maximum both packages Table 80376 Package Thermal Characteristics Thermal Resistances Watt)
Versus Airflow-ft sec) Package 1000
100-Lead Fine Pitch 88-Pin
ERROR BUSY inputs have internal pull-up resistors approximately PEREQ input internal pull-down resistor approximately built into 80376 keep these signals inactive when 80387SX present system temporarily removed from socket)
EMBEDDED PROCESSOR
typical designs external pull-up resistors shown Table recommended However particular design have reason adjust resistor values recommended here alter pull-up resistors other ways Table Recommended Resistor Pull-Ups Signal Pull-Up Value Purpose using address pipelining connect pull-up resistor range
Absolute Maximum Ratings
Table Maximum Ratings Parameter Storage Temperature Case Temperature under Bias Supply Voltage with Respect Voltage Other Pins Maximum Rating
(VCC
Lightly Pull Inactive during 80376 Hold Acknowledge States
LOCK Lightly Pull LOCK Inactive during 80376 Hold Acknowledge States
OTHER CONNECTION RECOMMENDATIONS reliable operation always connect unused inputs appropriate signal level pins should always remain unconnected Connection pins will result incompatibility with future steppings 80376 Particularly when using interrupts hold when first prototyping) prevent chance spurious activity connecting these associated inputs INTR HOLD
Table gives stress ratings only functional operation maximums guaranteed Functional operating conditions given Section Specifications Section Specifications Extended exposure Maximum Ratings affect device reliability Furthermore although 80376 contains protective circuitry resist damage from static electric discharge always take precautions avoid high static voltages electric fields
EMBEDDED PROCESSOR
Specifications ADVANCE INFORMATION SUBJECT CHANGE
Table 80376 Characteristics Functional Operating Range TCASE 88-pin 100-pin PQFP Symbol VILC VIHC Parameter Input Voltage Input HIGH Voltage CLK2 Input Voltage CLK2 Input HIGH Voltage Output Voltage LOCK HLDA Output High Voltage LOCK HLDA LOCK HLDA Input Leakage Current (For Pins except PEREQ BUSY ERROR) Input Leakage Current (PEREQ Pin) Input Leakage Current (BUSY ERROR Pins) Output Leakage Current Supply Current CLK2 CLK2 Input Capacitance Output Capacitance CLK2 Capacitance V(1) V(1) V(1) V(1) V(1)
Unit V(1) V(1)
V(1)
V(1)
V(1)
VCC(1)
4V(1 45V(3) VOUT VCC(1) mA(4) mA(4) MHz(5) MHz(5) MHz(5)
COUT CCLK
NOTES Tested minimum operating frequency device PEREQ input internal pull-down resistor BUSY ERROR inputs each have internal pull-up resistor measurement worse case load temperature 100% tested
EMBEDDED PROCESSOR
specifications given Table consist output delays input setup requirements input hold requirements specifications relative CLK2 rising edge crossing level specification measurement defined Figure Inputs must driven voltage levels indicated Figure when specifications measured 80376 output delays specified with minimum maximum limits measured shown minimum 80376 delay times hold times provided external circuitry 80376 input setup hold times specified minimums defining smallest acceptable sampling window Within sampling window synchronous input signal must stable correct 80376 processor operation Outputs LOCK HLDA only change beginning phase (write cycles) only change beginning phase READY HOLD BUSY ERROR PEREQ (read cycles) inputs sampled beginning phase INTR inputs sampled beginning phase
240182 LEGEND Maximum Output Delay Spec Minimum Output Delay Spec Minimum Input Setup Spec Minimum Input Hold Spec
Figure Drive Levels Measurement Points Specifications
EMBEDDED PROCESSOR
Specifications
Table 80376 Characteristics Functional Operating Range TCASE 88-pin 100-pin PQFP Symbol Parameter Operating Frequency CLK2 Period CLK2 HIGH Time CLK2 HIGH Time CLK2 Time CLK2 Time CLK2 Fall Time CLK2 Rise Time Valid Delay Float Delay LOCK Valid Delay LOCK Float Delay Valid Delay Float Delay Write Data Valid Delay Write Data Float Delay HLDA Valid Delay Setup Time Hold Time READY Setup Time READY Hold Time Setup Time Read Data Hold Time Read Data HOLD Setup Time HOLD Hold Time RESET Setup Time RESET Hold Time Unit 2(3) (VCC 8)V(3) 2V(3) 8V(3) (VCC 8V(3) (VCC 8)(3) pF(4)
Figure
Notes Half CLK2 Freq
pF(4)
pF(4)
pF(4)
pF(4)
EMBEDDED PROCESSOR
Table 80376 Characteristics (Continued) Functional Operating Range TCASE 88-pin 100-pin PQFP Symbol Parameter INTR Setup Time INTR Hold Time PEREQ ERROR BUSY Setup Time PEREQ ERROR BUSY Hold Time Unit Figure Notes
NOTES Float condition occurs when maximum output current becomes less than magnitude Float delay 100% tested These inputs allowed asynchronous CLK2 setup hold specifications given testing purposes assure recognition within specific CLK2 period These tested They guaranteed design characterization Tested with derated support indicated distributed capacitive load Figures through capacitive derating curves 80376 does have timing specifications
Table 80376 Characteristics Functional Operating Range TCASE 88-pin 100-pin PQFP Symbol Parameter Operating Frequency t10a t10b CLK2 Period CLK2 HIGH Time CLK2 HIGH Time CLK2 Time CLK2 Time CLK2 Fall Time CLK2 Rise Time Valid Delay Float Delay LOCK Valid Delay LOCK Float Delay Valid Delay Valid Delay Float Delay Write Data Valid Delay Write Data Float Delay Unit 2V(3) (VCC 8)V(3) 2V(3) 8V(3) (VCC 8V(3) (VCC 8)(3) pF(4)
Figure
Notes Half CLK2 Frequency
pF(4)
pF(4) pF(4)
EMBEDDED PROCESSOR
Table 80376 Characteristics (Continued) Functional Operating Range TCASE 88-pin 100-pin PQFP Symbol Parameter HLDA Valid Delay Setup Time Hold Time READY Setup Time READY Hold Time Read Data Setup Time Read Data Hold Time HOLD Setup Time HOLD Hold Time RESET Setup Time RESET Hold Time INTR Setup Time INTR Hold Time PEREQ ERROR BUSY Setup Time PEREQ ERROR BUSY Hold Time Unit Figure
Notes pF(4)
NOTES Float condition occurs when maximum output current becomes less than magnitude Float delay 100% tested These inputs allowed asynchronous CLK2 setup hold specifications given testing purposes assure recognition within specific CLK2 period These tested They guaranteed design characterization Tested with derated support indicated distributed capacitive load Figures through capacitive derating curves 80376 does have timing specifications
TEST LOADS
TIMING WAVEFORMS
240182
240182
Figure Test Loads
Figure CLK2 Waveform
EMBEDDED PROCESSOR
240182
Figure Timing Waveforms
Input Setup Hold Timing
240182
Figure Timing Waveforms
Output Valid Delay Timing
EMBEDDED PROCESSOR
240182
Figure Timing Waveforms
Output Float Delay HLDA Valid Delay Timing
240182
second internal processor phase following RESET high-to-low transition (provided met)
Figure Timing Waveforms
RESET Setup Hold Timing Internal Phase
EMBEDDED PROCESSOR
240182
240182
Figure Typical Output Valid Delay versus Load Capacitance Maximum Operating Temperature
Figure Typical Output Valid Delay versus Load Capacitance Maximum Operating Temperature
240182
Figure Typical Output Rise Time versus Load Capacitance Maximum Operating Temperature
240182
Figure Typical Frequency
EMBEDDED PROCESSOR
emulation processor receives RESET signal CLK2 cycles later than 80376 would responds RESET later Correct phase response guaranteed addition above considerations ICE-376 emulator processor module several electrical mechanical characteristics that should taken into consideration when designing 80376 system Capacitive Loading ICE-376 adds each 80376 signal Drive Requirements ICE-376 adds FAST load CLK2 control address data lines These loads within processor module driven 80376 emulation processor which standard drive loading capability listed Tables Power Requirements noise immunity CMOS latch-up protection ICE-376 emulator processor module powered user system circuitry processor module draws including maximum 80376 from user 80376 socket 80376 Location Orientation ICE-376 emulator processor module require lateral clearance Figure shows clearance requirements adapter Figure shows clearance requirements 88-pin adapter
Designing -376 Emulator
embedded processor in-circuit emulator product ICE-376 emulator emulator requires target system provide socket that compatible with ICE-376 emulator 80376 offers different probes emulating user systems 88-pin probe 100-pin fine pitch flat-pack probe 100-pin fine pitch flatpack probe requires socket called 100-pin PQFP which available from Textool (part number 2-0100-07243-000) ICE-376 emulator probe attaches target system adapter which replaces 80376 component target system Because high operating frequency 80376 systems ICE-376 emulator there buffering between 80376 emulation processor ICE-376 emulator probe target system direct result non-buffered interconnect that ICE-376 emulator shares address data with user's system RESET signal intercepted emulator hardware order ICE-376 emulator functional user's system without Optional Isolation Board (OIB) designer must aware following conditions controller must only enable data transceivers onto data during valid read cycles 80376 other local devices other masters Before another master drives local processor address other master must gain control address asserting HOLD receiving HLDA response
240182
Figure Preliminary -376 Emulator User Cable with PQFP Adapter
EMBEDDED PROCESSOR
240182
Figure -376 Emulator User Cable with 88-Pin Adapter optional isolation board (OIB) which provides extra electrical buffering same lateral clearance requirements Figures adds additional inches vertical clearance requirement This illustrated Figure Optional Isolation Board (OIB) CLK2 speed reduction unbuffered probe design ICE-376 emulator susceptible errors user's allows ICE-376 emulator function user systems with faults (shorted signals After electrical verification removed When installed user system must have maximum CLK2 frequency
240182
Figure -376 Emulator User Cable with PQFP Adapter
EMBEDDED PROCESSOR
80376 paging mechanism 80376 starts executing code what corresponds 80386 protected mode 80386 starts execution real mode which then used enter protected mode 80386 virtual-86 mode that allows execution real mode 8086 program task protected mode 80376 virtual-86 mode 80386 maps 48-bit logical address into 32-bit physical address segmentation paging 80376 maps 48-bit logical address into 24-bit physical address segmentation only 80376 uses 80387SX numerics coprocessor floating point operations while 80386 uses 80387 coprocessor 80386 execute from 16-bit code segments 80376 only execute from 32-bit code Segments 80376 input called which threestates bidirectional output pins including HLDA when asserted used with Circuit Emulation (ONCE)
DIFFERENCES BETWEEN 80376 80386
following major differences between 80376 80386 80376 generates byte selects (like 8086 80286 microprocessors) distinguish upper lower bytes 16-bit data 80386 uses four-byte selects BE0-BE3 distinguish between different bytes 32-bit 80376 sizing option 80386 select between either 32-bit 16-bit BS16 input 80376 16-bit size operation 80376 identical that 80386 with exception 80386 cannot activated 16-bit cycles (where BS16 80386 case) whereas activated 80376 cycle contents 80376 registers reset identical contents 80386 registers reset except register register contains component-stepping identifier reset 80386 after reset indicates 80386 revision number 80376 after reset indicates 80376 revision number 80386 uses select numerics coprocessor 80376 uses select numerics coprocessor 80386 prefetch unit fetches code fourbyte units 80376 prefetch unit reads bytes unit (like 80286 microprocessor) BS16 mode 80386 takes consecutive cycles complete prefetch request there data read write request after prefetch starts 80386 will fetch four bytes before addressing request
INSTRUCTION
This section describes embedded processor instruction Table lists instructions along with instruction encoding diagrams clock counts Further details instruction encoding then provided following sections which completely describe encoding structure definition fields occurring within 80376 instructions
80376 Instruction Encoding Clock Count Summary
calculate elapsed time instruction multiply instruction clock count listed Table below processor clock period 80376 operating MHz) actual clock count 80376 program will average more
EMBEDDED PROCESSOR
than calculated clock count instruction sequences which execute faster than they fetched from memory Instruction Clock Count Assumptions instruction been prefetched decoded ready execution cycles require wait states There local HOLD requests delaying processor acess exceptions detected during instruction execution effective address calculated does general register components register scaling displacement used within clock counts showns However effective address calculation uses general register components clock clock count shown Memory reference instruction accesses byte aligned 16-bit operands Instruction Clock Count Notation clock counts given smaller refers register operand larger refers memory operand number times repeated number components next instruction executed where entire displacement any) counts component entire immediate data any) counts component other bytes instruction prefix(es) each count component Misaligned 32-Bit Operand Accesses instructions accesses misaligned 16-bit operand 32-bit operand even address clocks read write clocks read write instructions accesses 32-bit operand address clocks read write clocks read write
Wait States Wait states clock wait state instruction execution each data access
EMBEDDED PROCESSOR
Table 80376 Instruction Clock Count Summary
Instruction GENERAL DATA TRANSFER Move Register Register Memory Register Memory Register Immediate Register Memory Immediate Register (Short Form) Memory Accumulator (Short Form) Accumulator Memory (Short Form) Register Memory Segment Register Segment Register Register Memory MOVSX Move with Sign Extension Register from Register Memory MOVZX Move with Zero Extension Register from Register Memory PUSH Push Register Memory Register (Short Form) Segment Register Segment Register Immediate PUSHA Push Register Memory Register (Short Form) Segment Register Segment Register POPA XCHG Exchange Register Memory with Register Register with Accumulator (Short Form) Input from Fixed Port 1110010w port number Variable Port 1110110w Output Fixed Port 1110011w port number Variable Port 1110111w Load Register 10001101 1000011w 10010 10001111 01011 sreg 11111111 01010 sreg3 immediate data 00001111 1011011w 00001111 1011111w 1000100w 1000101w 1100011w 1011 immediate data Format Clock Counts Number Data Cycles Notes
immediate data
full displacement full displacement
1010000w 1010001w 10001110 10001100
sreg3 sreg3
s
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