Mbit CMOS 3.3Volt-only Count Flash Memory Preliminary Document Ti
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A49LF040
Mbit CMOS 3.3Volt-only Count Flash Memory Preliminary
Document Title Mbit CMOS Volt-only Count Flash Memory Revision History
History
Initial issue Pb-Free package type
Issue Date
February 2004 August 2004
Remark
Preliminary
PRELIMINARY
(August, 2004, Version 0.1)
AMIC Technology, Corp.
A49LF040
Mbit CMOS 3.3Volt-only Count Flash Memory Preliminary
FEATURES
Single Power Supply Operation voltage range: Read Write Operations Standard Intel Count Interface Read compatible Intel® Count (LPC) interface Memory Configuration 512K Mbit) Block Architecture 4Mbit: eight uniform 64KByte blocks Supports full chip erase Address/Address Multiplexed (A/A Mux) mode Automatic Erase Program Operation Embedded Byte Program Block/Chip Erase algorithms Typical µs/byte programming time Typical block erase time Operational Modes Count Interface (LPC) Mode in-system operation Address/Address Multiplexed (A/A Mux) Interface Mode programming equipment Count (LPC) Mode synchronous operation with 5-signal communication interface in-system read write operations Standard Command Data# Polling (I/O7) Toggle (I/O6) features pins multi-chip selection pins General Purpose Input Register TBL# hardware write protection Boot Block hardware write protection whole memory array except Boot Block
Address/Address Multiplexed (A/A Mux) Mode 11-pin multiplexed address 8-pin data interface Supports fast programming EPROM programmers Standard Command Data# Polling (I/O7) Toggle (I/O6) features Lower Power Consumption Typical 12mA active read current Typical 24mA program/erase current High Product Endurance Guarantee 100,000 program/erase cycles each block Minimum years data retention Compatible Pin-out Packaging 32-pin TSOP (TYPE 32-pin PLCC
GENERAL DESCRIPTION
A49LF040 flash memory device designed readcompatible with Intel Count (LPC) Interface Specification 1.1. This device designed single voltage, range from Volt Volt power supply perform in-system off-system read write operations. provides protection storage update code data addition adding system design flexibility through five general-purpose inputs. interface modes supported A49LF040: Count (LPC) Interface mode In-System programming Address/Address Multiplexed (A/A Mux) mode fast factory programming PC-BIOS applications. memory divided into eight uniform 64Kbyte blocks that erased independently without affecting data other blocks. Blocks also protected individually prevent accidental Program Erase commands from modifying memory. Program Erase operations executed issuing Program/Erase commands into command interface which activating internal control logic automatically process Program/Erase procedures. device programmed byte-bybyte basis after performing Erase operation. addition Block Erase operation, Chip Erase feature provided mode that allows whole memory erased single Erase operation. A49LF040 provides status detection such Data# Polling Toggle Functions both modes. process completion Program Erase operations detected reading status bits. A49LF040 offered 32-lead TSOP 32-lead PLCC packages. Figures assignments Table descriptions.
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A49LF040
CONFIGURATIONS
RST# (RST#)
R/C# (LCLK)
(VDD)
(GPI3)
(GPI1) (GPI0) (WP#) (TBL#) (ID3) (ID2) (ID1) (ID0) I/O0 (LAD0)
(GPI4)
(GPI2)
MODE (MODE) (VSS) (VDD) (INIT#) (LFRAME#) (RES) I/O7 (RES)
32-lead PLCC View
(VSS)
(RES)
(RES)
(LAD1)
(LAD2)
Designates Mode
FIGURE Assignments 32-Lead PLCC
(LAD3)
(RES)
(VSS) MODE (MODE) (GPI4) R/C# (LCLK) (VDD) RST# (RST#) (GPI3) (GPI2) (GPI1) (GPI0) (WP#) (TBL#)
Designates Mode
32-lead TSOP (8MM 14MM) View
(INIT#) (LFRAME#) (VDD) I/O7 (RES) I/O6 (RES) I/O5 (RES) I/O4 (RES) I/O3 (LAD3) (VSS) I/O2 (LAD2) I/O1 (LAD1) I/O0 (LAD0) (ID0) (ID1) (ID2) (ID3)
FIGURE Assignments 32-Lead TSOP
PRELIMINARY
(August, 2004, Version 0.1)
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A49LF040
BLOCK DIAGRAM
TBL# INIT#
LAD[3:0] LCLK LFRAME# ID[3:0] GPI[4:0] A[10:0] I/O7 I/O0 R/C# MODE RST#
Address Latch
Mode Interface
Control Logic
Input/Output Buffers
Mode Interface High Voltage Generator Data Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
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(August, 2004, Version 0.1)
AMIC Technology, Corp.
A49LF040
Table Description
Interface Symbol Name Type Descriptions Inputs addresses during Read Write operations mode. column addresses latched R/C# pin. output data during Read cycle receive input data during Write cycle mode. outputs tri-state when high. control data output buffers. control Write operations. determine which interface operational. When held high, mode enabled when held low, mode enabled. This must setup power-up before return from reset change during device operation. This internally pulled down with resistor between 20-100 This second reset in-system use. INIT# RST# pins internally combined initialize device reset when driven low. These four pins part mechanism that allows multiple devices attached same bus. identify component, correct strapping these pins must set. boot device must have ID[3:0]=0000 recommended that subsequent devices should sequential up-count strapping. These pins internally pulled down with resistor between 20100 These individual inputs used additional board flexibility. state these pins read immediately boot, through internal registers. These inputs should their desired state before start clock cycle during which read attempted, should remain place until Read cycle. Unused pins must floated. prevent write operations Boot Block when driven low, regardless state block lock registers. When TBL# high disables hardware write protection Boot Block. This cannot left unconnected. Communications mode. provide clock input device. This same that clock adheres specifications. indicate start data transfer operation; also used abort cycle progress. reset operation device When low, prevents write operations highest addressable block. When high disables hardware write protection these blocks. This cannot left unconnected. This determines whether address pins pointing addresses column addresses mode. determine device busy write operations. Valid only mode. Reserved. These pins must left unconnected. provide power supply (3.0-3.6Volt). Circuit ground. pins must grounded. Unconnected pins.
A10-A0 I/O7-I/O0
Address Data Output Enable Write Enable Interface Configuration
MODE
INIT#
Initialize
ID[3:0]
Identification Inputs
GPI[4:0]
General Purpose Inputs
TBL# LAD[3:0] LCLK LFRAME# RST# R/C#
Block Lock I/Os Clock Frame Reset Write Protect Row/Column Select Ready/Busy# Reserved Power Supply Ground
Connection IN=Input, OUT=output, I/O=Input/Output, PWR=Power
PRELIMINARY
(August, 2004, Version 0.1)
AMIC Technology, Corp.
A49LF040
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias -55°C 125°C Storage Temperature -65°C 125°C D.C. Voltage Pins with Respect Ground -0.5V 0.5V Package Power Dissipation Capability (Ta=25°C) -0.5V 0.5V Output Short Circuit Current 50mA
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections these specifications implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability.
Operating Ranges
Commercial Devices Ambient Temperature (TA) +85°C Supply Voltages devices +3.0V +3.6V Operating ranges define those limits between which functionally device guaranteed.
Notes:
Minimum voltage input pins -0.5V. During voltage transitions, input pins undershoot -2.0V periods 20ns. Maximum voltage input pins 0.5V. During voltage transitions, input pins overshoot 2.0V periods 20ns. more than output shorted time. Duration short circuit should greater than second.
MODE SELECTION
A49LF040 flash memory devices operate distinct interface modes: Count Interface (LPC) mode Address/Address Multiplexed (A/A Mux) mode. Mode used interface mode selection. Mode logic High, device mode; while Mode Low, device mode. Mode must configured prior device operation. Mode internally pulled down connected. mode, device configured interface with host using Intel's Count proprietary protocol. Communication between Host A49LF040 occurs 4-bit communication signals, LAD[3:0] LFRAME#. mode, device programmed 11-bit address A10-A0 8bit data I/O7-I/O0 parallel signals. address inputs multiplexed column selected control signal R/C# pin. column addresses mapped higher internal addresses, addresses mapped lower internal addresses. Device Memory Maps Figure address assignment.
Read Operation
Read operations read from memory cells specific registers device. valid Read operation starts when LFRAME# LCLK rises START value "0000b" LAD[3:0] then next nibble "010X" LAD[3:0]. Addresses data transferred from device decided series "fields". Field sequences contents strictly defined Read operations. Refer Table Read Cycle Definition.
Write Operation
Write operations write Interface registers. valid Write operation starts when LFRAME# LCLK rises START value "0000b" LAD[3:0] then next nibble "011X" LAD[3:0]. Addresses data transferred from device decided series "fields". Field sequences contents strictly defined Write operations. Refer Table write Cycle Definition.
Abort Operation
LFRAME# driven more clock cycles during cycle, cycle will terminated device will wait ABORT command. host drive LAD[3:0] with `1111b' (ABORT command) return device Ready mode. abort occurs during Write operation such checking operation status with Data# Polling (I/O7) Toggle (I/O6) pins, read status cycle will aborted internal write operation will affected. this case, only reset operation initiated RST# INIT# terminate Write operation.
MODE OPERATION
interface consists four data signals (LAD[3:0]), control signal (LFRAME#) clock (LCLK). data signals, control signal clock comply with specifications. Operations such Memory Read Memory Write Intel propriety protocol. JEDEC Standard (Software Data Protection) Byte-Program Block-Erase command sequences incorporated into memory cycles. Chip-Erase command only available mode. addresses data transferred through LAD[3:0] synchronized with input clock LCLK during memory cycle. pulse LFRAME# inserted least clock period indicate start memory cycle. address data LAD[3:0] latched rising edge LCLK. device enters standby mode when LFRAME# high internal operation progress. device ready mode when LFRAME# activity bus.
Response Invalid Fields
During operations, will explicitly indicate that received invalid field sequences. response specific invalid fields sequences follows: Address range: A49LF040 will only response address range specified Table Address special function directing reads writes flash memory (A22=1) register space (A22=0).
PRELIMINARY
(August, 2004, Version 0.1)
AMIC Technology, Corp.
A49LF040
Table Read Cycle
Clock Cycle Field Name START CYCTYPE ADDRESS Field Contents LAD[3:0]1 0000 010X LAD[3:0] Direction Comments LFRAME# must active (low) part respond. Only last start field (before LFRAME# transitioning high) should recognized. Indicates type cycle. Bits must "01b" memory cycle. indicates type transfer Read. reserved. Address Phase Memory Cycle. protocol supports 32-bit address phase. YYYY nibble entire address. Addresses transferred most-significant nibble first. Table address bits definition Table valid memory address range. this clock cycle, host driven then floats bus. This first part "turnaround cycle." A49LF040 takes control during this cycle. A49LF040 outputs value 0000b indicating that data will available during next clock cycle. This field least-significant nibble data byte. This field most-significant nibble data byte. this clock, host driven then floats bus. This first part "turnaround cycle." A49LF040 takes control during this cycle.
3-10
YYYY
then Float Float then then Float Float then
TAR0 TAR1 SYNC DATA DATA TAR0 TAR1
1111 1111(float) 0000 ZZZZ ZZZZ 1111 1111(float)
Field contents valid rising edge present clock cycle.
Single-Byte Read Waveforms
LCLK
LFRAME#
LAD[3:0]
START CYCTYPE
ADDRESS
TAR0
TAR1
SYNC
DATA
TAR0
TAR1
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A49LF040
Table Write Cycle
Clock Cycle Field Name START CYCTYPE Field Contents LAD[3:0]1 LAD[3:0] Direction Comments LFRAME# must active (low) part respond. Only last start field (before LFRAME# transitioning high) should recognized. Indicates type cycle. Bits must "01b" memory cycle. indicates type transfer Write. reserved. Address Phase Memory Cycle. protocol supports 32-bit address phase. YYYY nibble entire address. Addresses transferred most-significant nibble first. Table address bits definition Table valid memory address range. This field least-significant nibble data byte. This field most-significant nibble data byte. this clock cycle, host driven `1's then floats bus. This first part "turnaround cycle." A49LF040 takes control during this cycle. A49LF040 outputs values 0000, indicating that received data flash command. this clock cycle, A49LF040 driven `1's then floats bus. This first part "turnaround cycle." Host resumes control during this cycle.
0000 010X
3-10
ADDRESS
YYYY
DATA DATA TAR0 TAR1 SYNC TAR0 TAR1
ZZZZ ZZZZ 1111 1111(float) 0000 1111 1111(float)
then Float Float then then Float Float then
Field contents valid rising edge present clock cycle.
Write Waveforms
LCLK
LFRAME#
LAD[3:0]
START CYCTYPE
ADDRESS
DATA
TAR0
TAR1
SYNC
TAR0
TAR1
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A49LF040
mismatch: A49LF040 will compare bits address field with hardware strapping. there mismatch, device will ignore cycle. Refer Table Multiple Device Selection Configuration detail. Data# Polling (I/O7) When A49LF040 device internal Program operation, attempt read I/O7 will produce complement true data. Once Program operation completed, I/O7 will produce true data. Note that even though I/O7 have valid data immediately following completion internal Write operation, remaining data outputs still invalid: valid data entire data will appear subsequent successive Read cycles after interval During internal Erase operation, attempt read I/O7 will produce `0'. Once internal Erase operation completed, I/O7 will produce `1'. Proper status will given using Data# Polling address invalid range. Toggle (I/O6) During internal Program Erase operation, consecutive attempts read I/O6 will produce alternating `0's `1's, i.e., toggling between When internal Program Erase operation completed, toggling will stop.
Device Memory Hardware Write Protection
Boot Lock (TBL#) Write Protect (WP#) pins provided hardware write protection device memory A49LF040. TBL# used write protect boot block Kbytes) highest flash memory address range A49LF040. write protects remaining blocks flash memory. active signal TBL# prevents Program Erase operations boot block. serves same function remaining blocks device memory. TBL# pins write protection functions operate independently another. Both TBL# pins must their required protection states prior starting Program Erase operation. logic level change occurring TBL# during Program Erase operation could cause unpredictable results. TBL# pins cannot left unconnected. Clearing Write-Lock register when will have functional effect, even though register indicate that block longer locked.
Multiple Device Selection
four pins, ID[3:0], allow multiple devices attached same using different strapping system. When A49LF040 used boot device, ID[3:0] must strapped 0000, subsequent devices should sequential up-count strapping (i.e. 0001, 0010, 0011, etc.). bits address field inverse hardware strapping. address bits [A23, A21:A19] A49LF004 used select device with proper IDs. Table IDs. A49LF040 will compare strapping values, there mismatch, device will ignore remainder cycle into standby mode. Since there support mode, program multiple devices stand-alone PROM programmer recommended.
Reset
INIT# RST# initiates device reset. INIT# RST# pins have same function internally. required drive INIT# RST# pins during system reset ensure proper initialization. During Read operation, driving INIT# RST# pins deselects device places output drivers, LAD[3:0], high-impedance state. reset signal must held minimal duration time TRSTP. reset latency will occur reset procedure performed during Program Erase operation. Table Reset Timing Parameters more information. device reset during active Program Erase will abort operation memory contents become invalid data being altered corrupted from incomplete Erase Program operation. this case, device take TRSTE abort Program Erase operation.
REGISTERS
There types registers available A49LF040, General Purpose Inputs Register, JEDEC Registers. These registers appear their respective address location GByte system memory map. Unused register locations will read 00H. attempt read write register during internal Write operation will ignored. Refer Table register memory map. General Purpose Inputs Register GPI_REG (General Purpose Inputs Register) passes state GPI[4:0] pins power-up A49LF040. recommended that GPI[4:0] pins desired state before LFRAME# brought beginning next cycle, remain that state until cycle. There default value since this pass-through register. Table GPI_REG bits function, Table memory address locations respective device strapping.
Write Operation Status Detection
A49LF040 device provides software means detect completion Write (Program Erase) cycle, order optimize system Write cycle time. software detection includes status bits: Data# Polling (I/O7) Toggle (I/O6). End-of-Write detection mode incorporated into Read cycle. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either I/O7 I/O6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid.
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A49LF040
Table Address Definition
A31:A23 1111 1111b ID[3] Memory access Register access A21:A19 ID[2:0] A18:A0 Device memory address
Table Address Decoding Range
Strapping Device Device Device Access Memory Access Register Access Memory Access Register Access A21:A19 FFFF FFFFH: FFC0 0000H FFBF FFFFH: FF80 0000H FF7F FFFFH: FF40 0000H FF3F FFFFH: FF00 0000H Memory Size MByte MByte MByte MByte
Table Multiple Device Selection Configuration
Device# (Boot device) Hardware Strapping ID[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Address Bits Decoding
Table Register Memory
Memory Address FFBC0100h FFBC0000h FFBC0001h FFBC0003h Mnemonic GPI_REG MANUF_REG DEV_REG CONT_REG Register Name General Purpose Input Register Manufacturer Register Device Register Continuation Register Default Type
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A49LF040
JEDEC Registers JEDEC registers identify device A49LF040 manufacturer mode. Table memory address locations respective JEDEC location.
Table General Purpose Inputs Register
GPI[4] GPI[3] GPI[2] GPI[1] GPI[0] Function Reserved GPI_REG GPI_REG GPI_REG GPI_REG GPI_REG Number 32-PLCC 32-TSOP
Table Memory Register Addresses A49LF040
Device# (Boot device) Hardware Strapping ID[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 GPI_REG Manufacturer FFBC 0100H FFB4 0100H FFAC 0100H FFA4 0100H FF9C 0100H FF94 0100H FF8C 0100H FF84 0100H FF3C 0100H FF34 0100H FF2C 0100H FF24 0100H FF1C 0100H FF14 0100H FF0C 0100H FF04 0100H FFBC 0000H FFB4 0000H FFAC 0000H FFA4 0000H FF9C 0000H FF94 0000H FF8C 0000H FF84 0000H FF3C 0000H FF34 0000H FF2C 0000H FF24 0000H FF1C 0000H FF14 0000H FF0C 0000H FF04 0000H JEDEC Continuation FFBC 0003H FFB4 0003H FFAC 0003H FFA4 0003H FF9C 0003H FF94 0003H FF8C 0003H FF84 0003H FF3C 0003H FF34 0003H FF2C 0003H FF24 0003H FF1C 0003H FF14 0003H FF0C 0003H FF04 0003H Device FFBC 0001H FFB4 0001H FFAC 0001H FFA4 0001H FF9C 0001H FF94 0001H FF8C 0001H FF84 0001H FF3C 0001H FF34 0001H FF2C 0001H FF24 0001H FF1C 0001H FF14 0001H FF0C 0001H FF04 0001H
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A49LF040
ADDRESS/ADDRESS MULTIPLEXED (A/A MUX) MODE
Device Operation
Commands used initiate memory operation functions device. data portion software command sequence latched rising edge WE#. During software command sequence address latched falling edge R/C# column address latched rising edge R/C#. Refer Table Table operation modes command sequence.
Reset
RST# initiates device reset. Byte-Program Operation A49LF040 device programmed byte-by-byte basis. Before programming, must ensure that block, which byte which being programmed exists, fully erased. Byte-Program operation initiated executing four-byte command load sequence Software Data Protection with address data last byte sequence. During Byte-Program operation, address (A10-A0) latched falling edge R/C# column Address (A18-A11) latched rising edge R/C#. data latched rising edge WE#. Figure Program operation timing diagram, Figure timing waveforms, Figure flowchart. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands written during internal Program operation will ignored.
Read
Read operation A49LF040 device controlled OE#. output control used gate data from output pins. Refer Read cycle timing diagram, Figure further details.
Table Mode Operation Selection Mode Read Write Standby Output Disable Reset Product Identification RST# Address VIL, VIL, VIH, DOUT High High High Manufacturer Device Continuation
Block-Erase Operation
Block-Erase Operation allows system erase device KByte uniform block size A49LF040. Block-Erase operation initiated executing six-byte command load sequence Software Data Protection with Block-Erase command (30H 50H) block address. internal Block-Erase operation begins after sixth pulse. End-of-Erase determined using either Data# Polling Toggle methods. Figure timing waveforms. commands written during BlockErase operation will ignored.
Write Operation Status Detection
A49LF040 device provides software means detect completion Write cycle, order optimize system Write cycle time. software detection includes status bits: Data# Polling (I/O7) Toggle (I/O6). End-of-Write detection mode enabled after rising edge which initiates internal Write operation. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either I/O7 I/O6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid. Data# Polling (I/O7) When A49LF040 device internal Program operation, attempt read I/O7 will produce complement true data. Once Program operation completed, I/O7 will produce true data. Note that even though I/O7 have valid data immediately following completion internal Write operation, remaining data outputs still invalid: valid data entire data will appear subsequent successive Read cycles after interval During internal Erase operation, attempt
Chip-Erase
A49LF040 device provides Chip-Erase operation only mode, which allows user erase entire memory array `1's state. This useful when entire device must quickly erased. Chip-Erase operation initiated executing six-byte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H last byte sequence. internal Erase operation begins with rising edge sixth WE#. During internal Erase operation, only valid read Toggle Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands written during Chip-Erase operation will ignored.
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A49LF040
read I/O7 will produce `0'. Once internal Erase operation completed, I/O7 will produce `1'. Data# Polling valid after rising edge fourth pulse Program operation. Block- Chip-Erase, Data# Polling valid after rising edge sixth pulse. Figure Data# Polling timing diagram. Proper status will given using Data# Polling address invalid range. Toggle (I/O6) During internal Program Erase operation, consecutive attempts read I/O6 will produce alternating `0's `1's, i.e., toggling between When internal Program Erase operation completed, toggling will stop. device then ready next operation. Toggle valid after rising edge fourth pulse Program operation. Block- Chip-Erase, Toggle valid after rising edge sixth pulse. Figure Toggle timing diagram. Software Data Protection (SDP) A49LF040 provides JEDEC approved Software Data Protection scheme data alteration operation, i.e., Program Erase. Program operation requires inclusion series three-byte sequences. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte load sequence. A49LF040 device shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device Read mode, within TRC.
Electrical Specifications
specifications Interface signals (LAD[3:0], LCLK, LFRAME#, RST#) defined Section 4.2.2 Local Specification, Rev. 2.1. Refer Table voltage current specifications. Refer specifications Table Table Clock, Read/Write, Reset operations.
Data Protection
A49LF040 device provides both hardware software features protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: pulse less than will initiate Write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down.
Product Identification
product identification mode identifies Manufacturer Continuation Device A49LF040. Table detail information.
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A49LF040
Figure System Memory Device Memory A49LF040
A49LF040 Block (64K Bytes) Block (64K Bytes) Block (64K Bytes) Block (64K Bytes) Block (64K Bytes) Block (64K Bytes) Block (64K Bytes) Block (64K Bytes)
Device Memory 07FFFF TBL# 070000 06FFFF 060000 05FFFF 050000 04FFFF 040000 03FFFF 030000 02FFFF 020000 01FFFF 010000 00FFFF 000000
Block
Table Software Data Protection Command Definition
Command Cycles Cycle Addr
Cycle Data
Cycle Addr
YYYY 5555H YYYY 5555H YYYY 5555H YYYY 5555H
Cycle Addr
YYYY 5555H YYYY 5555H PA(6)
Cycle Addr
YYYY 2AAAH YYYY 2AAAH
Cycle Addr
BA(4) YYYY 5555H
Data
Addr
YYYY 2AAAH YYYY 2AAAH YYYY 2AAAH YYYY 2AAAH
Data
Data
PD(6)
Data
Data
30H/50H(5)
Block Erase Chip Erase
YYYY 5555H YYYY 5555H YYYY 5555H YYYY 5555H XXXX XXXXH YYYY 5555H
Byte Program Product Entry Product Exit Product Exit
YYYY 2AAAH
YYYY 5555H
Notes: Mode uses consecutive Write cycles complete command sequence; Mode uses consecutive cycles complete command sequence. YYYY A[31:16]. mode, during command sequence, YYYY must within memory address range specified Table mode, YYYY VIH, other value. Chip erase available Mode only. Block Erase Address. Either acceptable Block Erase. Program Byte Address; Byte data programmed. Both Product Exit commands equivalent.
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Operating Range Conditions Test Input Rise/Fall Time Output Load 30pF
Range Commercial
Ambient Temperature +85°C
3.0-3.6V
Table Operating Characteristics (All Interfaces)
Symbol Parameter Active Current: Read Active Current: Write IRY(2) VIHI(3) VILI(3)
Limits -0.5 0.5VDD -0.5 0.9VDD VDD+0.5 VDD+0.5 0.3VDD 0.1VDD Units
Test Conditions Address Input=VIL/VIH, F=1/TRCMin, VDD=VDDMax(A/A Mode) OE#=VIH, WE#=VIH other inputs 0.9VDD 0.1VDD LFRAME#=VIL,f=33MHz,VDD=VDDMax, other inputs 0.9VDD 0.1VDD VIN=GND VDD, VDD=VDDMax VIN=GND VDD, VDD=VDDMax VOUT=GND VDD, VDD=VDDMax VDD=VDDMax VDD=VDDMin VDD=VDDMax VDD=VDDMin IOL=1500µA, VDD=VDDMin IOH=-500µA, VDD=VDDMin
Standby Current (LPC Mode) Ready Mode Current (LPC Mode) Input Current Mode ID[3:0] Pins Input Leakage Current Output Leakage Current INIT# Input High Voltage INIT# Input Voltage Input High Voltage Input Voltage Output Voltage Output High Voltage
Notes: active while Erase Program progress. device Ready Mode when activity bus. violate processor chipset specification regarding INIT# voltage.
Table Recommended System Power-Up Timings
Symbol TPU-READ(1) TPU-WRITE
Parameter Power-up Read Operation Power-up Write Operation
Units
Notes: This parameter measured only initial qualification after design process change that could affect this parameter.
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Table Impedance (VDD=3.3V, Ta=25°C, f=1MHz, other pins open)
Parameter CI/O LPIN
Description Capacitance Input Capacitance Inductance
Test Condition VI/O
12pF 12pF 20nH
Notes: This parameter measured only initial qualification after design process change that could affect this parameter. Refer specifications.
Table Clock Timing Parameters
Symbol TCYC THIGH TLOW Parameter LCLK Cycle Time LCLK High Time LCLK Time LCLK Slew Rate (peak-to-peak) Units V/ns
Figure LCLK Waveform
TCYC THIGH Peak-to-Peak (Min) TLOW
Table Mode Read/Write Cycle Timing Parameters, VDD=3.0-3.6V
Symbol
TVAL TOFF
Parameter
Input Time LCLK Rising LCLK Rising Data Hold Time LCLK Rising Data Valid LCLK Rising Active (Float Active Delay) LCLK Rising Inactive (Active Float Delay)
Units
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Table Mode Interface Measurement Condition Parameters
Symbol
VTEST VMAX Input Signal Edge Rate
Value
1V/ns
Units
Figure Input Timing Parameters
LCLK VTEST LAD[3:0] (Valid Input Data) Valid Inputs VMAX
Figure Output Timing Parameters
LCLK VTEST TVAL LAD[3:0] (Valid Output Data)
LAD[3:0] (Float Output Data) TOFF
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Table Mode Interface Input/Output Characteristics
Symbol Parameter Test Conditions
VOUT 0.3VDD (AC) Switching Current High (Test Point) (AC) Switching Current (Test Point) slewr slewf Clamp Current High Clamp Current Output Rise Slew Rate Output Fall Slew Rate 0.3VDD VOUT 0.9VDD 0.7VDD VOUT VOUT 0.7VDD VOUT 0.6VDD 0.6VDD VOUT 0.1VDD 0.18VDD VOUT VOUT=0.18VDD VDD+4 VDD+1 0.2VDD-0.6VDD load 0.6VDD-0.2VDD load -25+(VIN+1)/0.015 25+(VIN-VDD-1)/0.015 16VDD 26.7VOUT Equation 38VDD
-17.1(VDD-VOUT)
Units
Equation
V/ns V/ns
Notes: specification. specification output load used.
Table Mode Interface Reset Timing Parameters, VDD=3.0-3.6V
Symbol
TPRST TKRST TRSTP TRSTF TRST(1) TRSTE
Parameter
Stable Reset Clock Stable Reset RST# Pulse Width RST# Output Float RST# High LFRAME# RST# Reset During Erase Program RST# INIT# Slew Rate
Units
mV/ns
Notes: There will latency TRSTE reset procedure performed during Program Erase operation.
Figure Reset Timing Diagram
LCLK TKRST RST#/INIT# TRSTF LAD[3:0] TRSTE TRST
Program Erase Operation Aborted
TPRST
TRSTP
LFRAME#
PRELIMINARY
(August, 2004, Version 0.1)
AMIC Technology, Corp.
A49LF040
Figure Mode Input/Output Reference Waveforms
VIHT INPUT VILT test inputs driven VIHT (0.9VDD) logic HIGH VILT (0.1VDD) logic LOW. Measurement reference points inputs outputs (0.5VDD) (0.5VDD). Input rise fall times (10% 90%) Note: VINPUT Test VOUTPUT Test IHT: VINPUT HIGH Test ILT: VINPUT Test Reference Points OUTPUT
Figure Mode Test Load Condition
TESTER
CL=30pF
PRELIMINARY
(August, 2004, Version 0.1)
AMIC Technology, Corp.
A49LF040
MODE CHARACTERISTICS Table Read Cycle Timing Parameters VDD=3.0-3.6V
Symbol
TRST TOLZ TOHZ
Parameter
Read Cycle Time RST# High Address Setup R/C# Address Set-up Time R/C# Address Hold Time Address Access Time Output Enable Access Time Active Output High High-Z Output Output Hold from Address Change
Units
Table Program/Erase Cycle Timing Parameters, VDD=3.0-3.6V
Symbol
TRST TCWH TOES TOEH TOEP TOET TWPH TIDA TSCE
Parameter
RST# High Address Setup R/C# Address Setup Time R/C# Address Hold Time R/C# Write Enable High Time High Setup Time High Hold Time Data# Polling Delay Toggle Delay Pulse Width Pulse Width High Data Setup Time Data Hold Time Product Access Exit Time Byte Programming Time Block Erase Time Chip Erase Time
Units
Table Reset Timing Parameters, VDD=3.0-3.6V
Symbol
TPRST TRSTP TRSTF TRST(1) TRSTE
Parameter
Stable Reset RST# Pulse Width RST# Output Float RST# High LFRAME# RST# Reset During Erase Program
Units
There will reset latency TRSTE reset procedure performed during Program Erase operation.
PRELIMINARY
(August, 2004, Version 0.1)
AMIC Technology, Corp.
A49LF040
Figure Mode Read Cycle Timing Diagram
TRSTP RST#
TRST
Address
Column Address Address Column Address
Address
R/C#
High-Z TOLZ
Data Valid
TOHZ High-Z
I/O7-I/O0
Figure Mode Write Cycle Timing Diagram
TRSTP RST#
TRST
Address Column Address
Address
R/C#
TCWH TOES
TOEH TWPH
I/O7-I/O0 High-Z
Data Valid
PRELIMINARY
(August, 2004, Version 0.1)
AMIC Technology, Corp.
A49LF040
Figure Mode Data# Polling Timing Diagram
Address
Address Column Address Address Column Address Address Column Address Address Column Address
R/C#
TOEP High-Z
I/O7
Data
Data#
Data#
Data
Final Input Command
Status
Status
Data
Command Input
Write Operation Progress
Write Operation Complete
Figure Mode Toggle Timing Diagram
Address
Address Column Address Address Column Address Address Column Address Address Column Address
R/C#
TOET High-Z
I/O6
Data
Data
Final Input Command
Status
Status
Data
Command Input
Write Operation Progress
Write Operation Complete
PRELIMINARY
(August, 2004, Version 0.1)
AMIC Technology, Corp.
A49LF040
Figure Mode Byte Program Timing Diagram
Four-Byte Byte Program Command Sequence 5555 Address 2AAA 5555
R/C#
TWPH
High-Z
I/O7-I/O0
Byte Program Command Input Byte Program Address Byte Program Data
Byte Program Operation Progress
Figure Mode Block Erase Timing Diagram
Six-Byte Block Erase Command Sequence 5555 Address 2AAA 5555 5555 2AAA
R/C#
TWPH
High-Z
30/50
I/O7-I/O0
Block Erase Command Input Block Address
Block Erase Operation Progress
PRELIMINARY
(August, 2004, Version 0.1)
AMIC Technology, Corp.
A49LF040
Figure Mode Chip Erase Timing Diagram
Six-Byte Chip Erase Command Sequence 5555 Address 2AAA 5555 5555 2AAA 5555
R/C#
TWPH
TSCE
High-Z
I/O7-I/O0
Chip Erase Command Input
Chip Erase Operation Progress
Figure Mode Product Entry Read Timing Diagram
Three-Byte Product Entry Command Sequence 5555 Address 2AAA 5555 0000 0001 0003
R/C#
TWPH
TIDA
High-Z
I/O7-I/O0
Figure Mode Product Exit Reset Timing Diagram
Three-Byte Product Exit Reset Command Sequence 5555 Address 2AAA 5555
R/C#
TWPH
High-Z
I/O7-I/O0
PRELIMINARY
(August, 2004, Version 0.1)
AMIC Technology, Corp.
A49LF040
Figure Automatic Byte Program Algorithm
Start
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
Write Command Address: 5555H Data:
Write Command Address: Data:
I/O7 Data I/O6 Stop Toggle?
Byte Program Completed
Byte Program Address Byte Program Data
PRELIMINARY
(August, 2004, Version 0.1)
AMIC Technology, Corp.
A49LF040
Figure Automatic Block Erase Algorithm
Start
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
Write Command Address: 5555H Data:
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
I/O7 Data I/O6 Stop Toggle?
Write Command Address: Data:
Block Erase Completed
Block Address
PRELIMINARY
(August, 2004, Version 0.1)
AMIC Technology, Corp.
A49LF040
Figure Automatic Chip Erase Algorithm
Start
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
Write Command Address: 5555H Data:
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
I/O7 Data I/O6 Stop Toggle?
Write Command Address: 5555H Data:
Chip Erase Completed
PRELIMINARY
(August, 2004, Version 0.1)
AMIC Technology, Corp.
A49LF040
Figure Product Command Flowchart
Start
Start
Write Command Address: 5555H Data:
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
Write Command Address: 2AAAH Data:
Write Command Address: 5555H Data:
Write Command Address: 5555H Data:
Write Command Address: XXXXH Data:
Enter Product Mode
Exit Product Mode
PRELIMINARY
(August, 2004, Version 0.1)
AMIC Technology, Corp.
A49LF040
Ordering Information
A49LF040T
Temperature Range
Commercial (0°C +85°C)
Clock Frequency
33MHz
Package Type
PLCC TSOP (8mmX14mm)
Device Number
Mbit Flash Memory
Part
Clock Frequency (MHz)
Boot Block Location
Temperature Range
+85°C
Package Type
A49LF040TL-33
32-pin PLCC
A49LF040TL-33F
+85°C +85°C +85°C
32-pin Pb-Free PLCC 32-pin TSOP (8mm 32-pin Pb-Free TSOP (8mm
A49LF040TX-33
A49LF040TX-33F
PRELIMINARY
(August, 2004, Version 0.1)
AMIC Technology, Corp.
A49LF040
Package Information PLCC Outline Dimension
unit: inches/mm
Dimensions inches
Dimensions 0.47 2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91 2.80 0.71 0.46 0.254 13.97 11.43 1.27 12.95 10.41 14.99 12.45 2.29 3.40 2.93 0.81 0.54 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.075
Symbol
0.0185 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075
0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.510 0.410 0.590 0.490 0.090
0.134 0.115 0.032 0.021 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.003
Notes: Dimensions include resin fins. Dimensions Board surface mount pitch design reference only.
PRELIMINARY
(August, 2004, Version 0.1)
AMIC Technology, Corp.
A49LF040
Package Information
TSOP TYPE 14mm) Outline Dimensions unit: inches/mm
Pin1
0.254 Gage Plane Detail
Detail
Dimensions inches Symbol 0.002 0.037 0.0067 0.004 0.311 0.543 0.484 0.020 0.000 0.039 0.0087 0.315 0.0197 0.551 0.488 0.024 0.047 0.006 0.041 0.0106 0.0083 0.319 0.559 0.492 0.028 0.003
Dimensions 0.05 0.95 0.17 0.10 7.90 13.80 12.30 0.50 0.00 1.00 0.22 8.00 0.50 14.00 12.40 0.60 1.20 0.15 1.05 0.27 0.21 8.10 14.20 12.50 0.70 0.076
Notes: Dimension does include mold flash. Dimension does include interlead flash. Dimension does include dambar protrusion.
PRELIMINARY
(August, 2004, Version 0.1)
AMIC Technology, Corp.
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