Mbit CMOS 3.3Volt-only Firmware Hub/LPC Flash Memory Preliminary

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Mbit CMOS 3.3Volt-only Firmware Hub/LPC Flash Memory Preliminary

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A49FL004
Mbit CMOS 3.3Volt-only Firmware Hub/LPC Flash Memory Preliminary
Document Title Mbit CMOS Volt-only Firmware Hub/LPC Flash Memory Revision History
History
Initial issue
Issue Date
September 2005
Remark
Preliminary
PRELIMINARY
(September, 2005, Version 0.0)
AMIC Technology, Corp.
A49FL004
Mbit CMOS 3.3Volt-only Firmware Hub/LPC Flash Memory Preliminary
FEATURES
Single Power Supply Operation voltage range: Standard Intel Firmware Hub/LPC Interface Read compatible Intel® 82802 Firmware devices Conforms Intel Interface Specification Revision Memory Configuration 512K Mbit) Block Architecture Uniform KBytes Sectors Uniform KByte overlay blocks Support full chip erase Address/Address Multiplexed (A/A Mux) mode Automatic Erase Program Operation Build-in automatic program verification extended product endurance Typical µs/byte programming time Typical sector erase time Typical block erase time Typical chip erase time Configurable Interfaces In-System hardware interface: Auto detection Firmware (FWH) Count (LPC) Interface in-system read write operations Address/Address Multiplexed (A/A Mux) Interface programming EPROM Programmers during manufacturing Firmware (FWH)/Low Count (LPC) Mode synchronous operation with 5-signal communication interface in-system read write operations Standard Command Data Polling Toggle features Block Locking Register blocks Register-based read write protection each block pins multiple chips selection pins General Purpose Input Register
hardware write protection Boot Block hardware write protection whole memory array except Boot Block
Address/Address Multiplexed (A/A Mux) Mode 11-pin multiplexed address 8-pin data interface Supports fast programming EPROM programmers Standard Command Data Polling Toggle features Lower Power Consumption Typical 12mA active read current Typical 17mA program/erase current High Product Endurance Guarantee 100,000 program/erase cycles single sector (preliminary) Minimum years data retention Compatible Pin-out Packaging 32-pin TSOP 32-pin PLCC Optional lead-free (Pb-free) package Hardware Data Protection
PRELIMINARY
(September, 2005, Version 0.0)
AMIC Technology, Corp.
A49FL004
GENERAL DESCRIPTION
A49FL004 Mbit Volt-only Flash Memories used BIOS storage Notebooks. This device designed single voltage, ranging from Volt Volt, power supply perform in-system off-system read, erase program operations. device conforms Intel® Count (LPC) Interface specification revision also compatible with Intel 82802 Firmware (FWH) most Notebook applications. A49FL004 supports configurable interfaces: In-system hardware interface which automatic detect memory cycle in-system read write operations, Address/Address Multiplexed (A/A Mux) interface fast manufacturing EPROM Programmers. This device designed work with both Intel Family chipset Non-Intel Family Chipset, will provide Notebook manufacturers great flexibility simplicity design, procurement, material inventory. memory array A49FL004 divided into uniform KByte sectors uniform KByte blocks (sector group consists sixteen adjacent sectors). sector block erase feature A49FL004 allows user flexibly erase memory area 4Kbyte KByte single erase operation without affecting data others. chip erase feature allows whole memory erased single erase operation. device programmed byteby-byte basis after performing erase operation. program operation A49FL004 executed issuing program command code into command register. internal control logic automatically handles programming voltage ramp-up timing. erase operation device also executed issuing sector, block, chip erase command code into command register. internal control logic automatically handles erase voltage rampup timing. device offer Data Polling Toggle functions FWH/LPC modes, progress completion program erase operation detected reading Data Polling I/O7 Toggle I/O6. A49FL004 KByte boot block. boot block write protected hardware method controlled register-based protection turned on/off Block Locking Registers (FWH mode only). rest blocks except boot block device also write protected Block Locking Registers (FWH mode only). A49FL004 manufactured AMIC advanced nonvolatile technology. device offered 32-pin TSOP PLCC packages with optional environmental friendly lead-free package.
PRELIMINARY
(September, 2005, Version 0.0)
AMIC Technology, Corp.
A49FL004
CONFIGURATIONS
Figure 32-Pin PLCC
GPI2 GPI3 GPI4 GPI4
GPI2
GPI3
GPI1 GPI0 FWH0
GPI1 GPI0 LAD0
I/O0
I/O7
INIT
INIT
32-pin PLCC
LFRAME FWH4
I/O5
I/O4
I/O2
I/O3
LAD1
LAD2
LAD3
FWH1
FWH2
FWH3
Figure 32-Pin TSOP
GPI4 GPI3 GPI2 GPI1 GPI0 GPI4 GPI3 GPI2 GPI1 GPI0 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 INIT LFRAME LAD3 LAD2 LAD1 LAD0 INIT LFRAME LAD3 LAD2 LAD1 LAD0
I/O6
I/01
32-lead TSOP View
PRELIMINARY
(September, 2005, Version 0.0)
AMIC Technology, Corp.
A49FL004
Figure BLOCK DIAGRAM
INIT FWH[3:0] LAD[3:0] FWH4 LFRAME GPI[4:0] A[10:0] I/O[7:0] Address Latch Y-Decoder X-decoder Gating Memory Array Control Logic Mode Interface
Erase/Program Voltage Generator
Buffers
FWH/LPC Mode Interface
High Voltage Switch
Data Latch
Sense
PRELIMINARY
(September, 2005, Version 0.0)
AMIC Technology, Corp.
A49FL004
Table Description
Symbol Type Interface Addresses Inputs: inputting multiplex address mode. A[10:0] column address latched during read write cycle controlled pin. Data Inputs/Outputs: Used mode only, input command/data during write operation output data during Read operation. data pins float tri-state when high.
Descriptions
I/O[7:0]
Output Enable: Control device's output buffers during read cycle. active low. Write Enable: Active device write operation. active low. Interface Configuration Select: This determines which mode selected. When pulls high, device enters into mode. When pulls low, FWH/LPC mode selected. This must setup during power-up system reset, stays change during operation. This internally pulled down with resistor between 20-100 Initialize: This second reset in-system use. INIT internally combined initialize device reset when driven low. These four pins part mechanism that allows multiple devices attached same bus. strapping these pins used identify component. boot device must have ID[3:0]=0000b recommended that subsequent devices should sequential up-count strapping. These pins internally pulled-down with resistor between 20-100 FWH/LPC General Purpose Inputs: Used GPI_REG system design purpose only. value GPI_REG read through interface. state these pins read immediately boot, through FWH/LPC internal registers. These pins should desired state before start clock cycle read operation should remain change until Read cycle. Unused pins must floated.
INIT
ID[3:0]
GPI[4:0]
FWH[3:0] FWH4
Block Lock: When pulls low, enables hardware write protection state boot block. When pulls high, disables hardware write protection. Address Data: major pins transmitting data, address command code mode.
FWH/LPC Clock: provide synchronous clock mode operations. Input: indicate start memory cycle operation. Also used abort memory cycle progress.
Reset: reset operation device return standby mode. Write Protect: When pulls low, enables hardware write protection memory array except boot block. When pulls high, disables hardware write protection except boot block. Row/Column Select: indicate column address mode. When this goes low, address latched. When this goes high, column address latched.
LAD[3:0] LFRAME
Address Data: major pins transmitting data, addresses command code mode. Frame: indicate start memory cycle operation. Also used abort memory cycle progress. Reserved. Reserved function pins future use. Device power supply. Ground. Connection.
Notes: IN=Input, I/O=Input/Output. PRELIMINARY (September, 2005, Version 0.0)
AMIC Technology, Corp.
A49FL004
MODE SELECTION
A49FL004 operate configurable interfaces: In-System Hardware interface Address/Address Multiplexed (A/A Mux) interface controlled pin. logic high (VIH), devices enter into interface mode. logic (VIL), device will in-system hardware interface mode. During insystem hardware interface mode, device automatically detect Firmware (FWH) Count (LPC) memory cycle sent from host system response command accordingly. must setup during power-up system reset, stays change during device operation. When working in-system, typically Notebook Intel Platform, A49FL004 enters into mode automatically. device configured interface with host using Intel's Firmware proprietary protocol. Communication between host (Intel ICH) A49FL004 occurs 4-bit communication signal, FWH[3:0] FWH4. mode, device programmed 11-bit address A[10:0] 8-pin data I/O[7:0] interfaces. address inputs multiplexed column selected column control signal column addresses mapped higher internal addresses, addresses mapped lower internal addresses.
Write Operation
Write operations write Interface registers. valid Write operation starts when FWH4 rises START value "1110b" FWH[3:0]. Addresses data transferred from device decided series "fields". Field sequences contents strictly defined Write operations. Refer Table Write Cycle Definition.
Abort Operation
FWH4 signal indicates start memory cycle termination cycle mode. Asserting FWH4 more clock cycle with valid START value FWH[3:0] will initiate memory read memory write cycle. FWH4 driven again more clock cycles during this cycle, this cycle will terminated device will wait ABORT command "1111b" release FWH[3:0] bus. abort occurs during program erase operation such checking operation status with Data Polling (I/O7) Toggle (I/O6) pins, read status cycle will aborted internal program erase operation will affected. Only reset operation initiated INIT terminate program erase operation.
Response Invalid Fields
MODE OPERATION
mode, A49FL004 connected through 5-pin communication interface FWH[3:0] FWH4 pins work with Intel® Family Controller Hubs (ICH) chipset platforms. mode also supports JEDEC standard Software Data Protection (SDP) product entry, byte program, sector erase, block erase command sequences. chip erase command sequence only available mode. addresses data transmitted through 4-bit FWH[3:0] synchronized with input clock during memory cycle operation. address data FWH[3:0] latched rising edge clock. device enters standby mode when FWH4 high internal operation progress. device ready mode when FWH4 activity bus.
Read Operation
During operations, device will explicitly indicate that received invalid field sequences. response specific invalid fields sequences follows:
Address range: address sequence fields long bits), only last five address fields bits) will decoded A49FL004. Address special function directing reads writes flash memory (A22=1) register space (A22=0). Invalid IMSIZE Field: device receives invalid size field during Read Write operation, device will reset operation will attempted. A49FL004 will generate kind response this situation. Invalid size field Read/Write cycles anything "0000b".
Read Operations read from memory cells specific registers device. valid Read operation starts when FWH4 rises START value "1101b" FWH[3:0]. Addresses data transferred from device decided series "fields". Field sequences contents strictly defined Read Operations. Refer Table Read Cycle definition.
PRELIMINARY
(September, 2005, Version 0.0)
AMIC Technology, Corp.
A49FL004
Table Read Cycle
Clock Cycle Field FWH[3:0] Direction Descriptions
START
1101
Start Cycle: "1101b" indicate start memory read cycle. FWH4 must active (low) part respond. Only last start field (before FWH4 transition high) should recognized. start field contents indicate read cycle. Select Cycle: Indicates which device should respond. IDSEL field matches value ID[3:0] pins, then particular device will respond subsequent commands. Address Cycle: This 28-bit memory address. addressed transfer most-significant nibble first least-significant nibble last. (i.e., a27-24 FWH[3:0] first, A3-A0 FWH[3:0] last). Memory Size Cycle: Indicates many bytes will transferred during multi-byte operations. A49FL004 only support "0000b" byte operation. Turn-Around cycle master (Intel ICH) driven all"1"s then float bus. Turn-Around cycle device takes control during this cycle. Ready Sync: device indicates least-significant nibble data byte will ready next clock cycle. Data Cycles: 8-bits data transferred with least-significant nibble first most-significant nibble last. (i.e., I/O3 I/O0 FWH[3:0] first, then I/O7 I/O4 FWH[3:0] last). Turn-Around cycle device driven "1"s then float bus. Turn-Around cycle master (Intel ICH) resumes control during this cycle.
IDSEL
0000 1111
IMADDR
YYYY
14-15
IMSIZE TAR0 TAR1 RSYNC DATA TAR0 TAR1
0000 1111 1111 (Float) 0000 (READY) YYYY 1111 1111 (Float)
then Float Float then then Float Float then
Figure Memory Read Cycle Waveforms
FWH4
FWH[3:0]
START
IDSEL
IMADDR
IMSIZE
TAR0
TAR1
RSYNC
DATA
TAR0
TAR1
PRELIMINARY
(September, 2005, Version 0.0)
AMIC Technology, Corp.
A49FL004
Table Write Cycle
Clock Cycle Field FWH[3:0] Direction Descriptions
START
1101
Start Cycle: "1101b" indicate start memory write cycle. FWH4 must active (low) part respond. Only last start field (before FWH4 transitioning high) should recognized. START field contents indicate write cycle. Select Cycle: Indicates which device should respond. IDSEL field matches value ID[3:0] pins, then particular device will respond subsequent commands. Address Cycle: This 28-bit memory address. addressed transfer most-significant nibble first least-significant nibble last. (i.e., a27-24 FWH[3:0] first, A3-A0 FWH[3:0] last). Memory Size Cycle: Indicates many bytes will transferred during multi-byte operations. A49FL004 only supports "0000b" byte operation. Data Cycles: 8-bits data transferred with least-significant nibble first most-significant nibble last. (i.e., I/O3 I/O0 FWH[3:0] first, then I/O7 I/O4 FWH[3:0] last).
IDSEL
0000 1111
IMADDR
YYYY
IMSIZE
0000
11-12
DATA TAR0 TAR1 RSYNC TAR0 TAR1
YYYY 1111 1111 (Float) 0000 (Ready) 1111 1111 (Float)
Turn-Around cycle master (Intel ICH) driven then Float all"1"s then float bus. Float Turn-Around cycle device takes control during this then cycle. Ready Sync: device indicates that received data command.
Turn-Around cycle device driven "1"s then Float then float bus. Float then Turn-Around cycle master (Intel ICH) resumes control during this cycle.
Figure Write Waveforms
FWH4
FWH[3:0]
START
IDSEL
IMADDR
IMSIZE
DATA
TAR0
TAR1
RSYNC
TAR0
TAR1
PRELIMINARY
(September, 2005, Version 0.0)
AMIC Technology, Corp.
A49FL004
MODE SELECTION
A49FL004 operate configurable interfaces: In-System Hardware interface Address/Address Multiplexed (A/A Mux) interface controlled pin. logic high (VIH), devices enter into interface mode. logic (VIL), devices will in-system hardware interface mode. During insystem hardware interface mode, devices automatically detect Firmware (FWH) Count (LPC) memory cycle sent from host system response command accordingly. must setup during power-up system reset, stays change during device operation. When working in-system, typically Notebook Intel Platform, A49FL004 connected host system through 5-pin communication interface operated based 33-MHz synchronous clock. 5-pin interface defined LAD[3:0] LFRAME pins under mode easy understanding those existing compatible products. When working off-system, typically EPROM Programmer, device operated through 11-pin multiplexed address A[10:0] 8-pin data I/O[7:0] interfaces. memory addresses device input through cycles column addresses controlled pin. rising edge clock. pulse LFRAME signal inserted more clocks indicates start memory read write cycle. Once memory cycle started, asserted LFRAME START value "0000b" expected device valid command cycle. Then CYCTYPE value ("010xb" memory read cycle "011xb" memory write cycle) used indicates type memory cycle. Refer Table Memory Read Write Cycle Definition. There clock fields memory cycle that gives memory address through LAD[3:0] with most-significant nibble first. memory space A49FL004 mapped directly Gbyte system memory space. Figure System Memory Map. A49FL004 mapped address location (FFFFFFFFh FFF80000h), A31- must loaded with select activate device during memory operation. Only used decode access KByte memory.
Abort Operation
LFRAME driven more clock cycles during cycle, cycle will terminated device will wait ABORT command. host drive LAD[3:0] with "1111b" (ABORT command) return device ready mode. abort occurs during Write operation such checking operation status with Data Polling (I/O7) Toggle (I/O6) pins, read status cycle will aborted internal program erase operation will affected. this case, only reset operation initiated INIT terminate write operation.
Response Invalid Fields
MODE OPERATION
mode, A49FL004 connected through 5-pin communication interface LAD[3:0] LFRAME pins work with Intel® Family South Bridge chipset platforms. mode also supports JEDEC standard Software Data Protection (SDP) product entry, byte program, sector erase, block erase command sequences. chip erase command sequence only available mode. addresses data transmitted through 4-bit LAD[3:0] synchronized with input clock during memory cycle operation. address data LAD[3:0] latched rising edge clock. pulse LFRAME inserted clock indicates start memory read memory write cycle. address data LAD[3:0] latched rising edge CLK. device enters standby mode when LFRAME high internal operation progress. device ready mode when LFRAME activity bus.
Mode Memory Read/Write Operation
During operations, A49FL004 will explicitly indicate that received invalid field sequences. responses specific invalid fields sequence follows:
Address range: A49FL004 will only response address range specified Table Address special function directing reads writes flash memory (A22=1) register space (A22=0). mismatch: A49FL004 will compare bits address field with hardware strapping. there mismatch, device will ignore cycle.
mode, A49FL004 uses 5-pin interface includes 4-bit LAD[3:0] LFRAME pins communicate with host system. addresses data transmitted through 4-bit LAD[3:0] synchronized with input clock during memory cycle operation. address data LAD[3:0] latched
PRELIMINARY
(September, 2005, Version 0.0)
AMIC Technology, Corp.
A49FL004
Table Memory Read Cycle Definition
Clock Cycle Field LAD[3:0] Direction Descriptions
START
0000
Start Cycle: "0000b" indicates start memory cycle. LFRAME must active (low) part respond. Only last field latched before LFRAME transitions high will recognized. Cycle Type: Indicates type memory read cycle. CYCTYPE: Bits must "01b" memory cycle. DIR: "0b" indicates type cycle Read. reserved. Address Cycles: This 32-bit memory address. addressed transfer most-significant nibble first least-significant nibble last. (i.e., a31-28 LAD[3:0] first, A3-A0 LAD[3:0] last). Turn-Around cycle host driven all"1"s then float bus. Turn-Around cycle A49FL004 takes control during this cycle. Sync: device indicates least-significant nibble data byte will ready next clock cycle. Data Cycles: 8-bits data transferred with least-significant nibble first most-significant nibble last. (i.e., I/O3 I/O0 LAD[3:0] first, then I/O7 I/O4 LAD[3:0] last). Turn-Around cycle host driven "1"s then float bus. Turn-Around cycle A49FL004 resumes control during this cycle.
CYCTYPE
010x
3-10
ADDR
YYYY
Then Float Float then then Float Float then
14-15
TAR0 TAR1 SYNC DATA TAR0 TAR1
1111 1111 (Float) 0000 1111 1111 1111 (Float)
Figure Single-Byte Read Waveforms
LCLK
LFRAME
LAD[3:0]
START CYCTYPE
ADDRESS
TAR0
TAR1
SYNC
DATA
TAR0
TAR1
PRELIMINARY
(September, 2005, Version 0.0)
AMIC Technology, Corp.
A49FL004
Table Memory Write Cycle Definition
Clock Cycle Field LAD[3:0] Direction Descriptions
START
0000
Start Cycle: "0000b" indicate start memory cycle. LFRAME must active (low) part respond. Only last field latched before LFRAME transitions high will recognized. Cycle Type: Indicates type memory write cycle. CYCTYPE: Bits must "01b" memory cycle. DIR: "1b" indicates type cycle Write. reserved. Address Cycles: This 32-bit memory address. addressed transfer most-significant nibble first least-significant nibble last. (i.e., a31-28 LAD[3:0] first, A3-A0 LAD[3:0] last). Data Cycles: 8-bits data transferred with least-significant nibble first most-significant nibble last. (i.e., I/O3 I/O0 LAD[3:0] first, then I/O7 I/O4 LAD[3:0] last). Turn-Around cycle host driven all"1"s then float bus. Turn-Around cycle A49FL004 takes control during this cycle. Sync: device indicates least-significant nibble data byte will ready next clock cycle. Turn-Around cycle A49FL004 driven "1"s then float bus. Turn-Around cycle host resumes control during this cycle.
CYCTYPE
011x
3-10
ADDR
YYYY
11-12
DATA TAR0 TAR1 SYNC TAR0 TAR1
YYYY 1111 1111 (Float) 0000 1111 1111 (Float)
then Float Float then then Float Float then
Figure Write Waveforms
LCLK
LFRAME LAD[3:0]
START CYCTYPE ADDRESS DATA TAR0 TAR1 SYNC TAR0 TAR1
PRELIMINARY
(September, 2005, Version 0.0)
AMIC Technology, Corp.
A49FL004
Multiple Device Selection Multiple A49FL004 devices strapped increase memory densities system. four pins, ID[3:0], allow devices attached same using different strapping system, BIOS support, loading, attaching bridge limit this number. boot device must have "0000b" (determined ID[3:0]); subsequent devices incremental numbering, equal density must used with multiple devices. Multiple Device Selection Memory Cycle Memory Read/Write cycles, information included address bits every cycle. bits address field reverse hardware strapping. Table multiple device selection configurations. A49FL004 will compare these bits with ID[3:0]'s strapping values. there mismatch, device will ignore remainder cycle. Table Configuration Device (Boot Device) Multiple Device Selection
Multiple Device Selection Firmware Memory Cycle Firmware Memory Read/Write cycles, hardware strapping values ID[3:0] must match values IDSEL field. Table multiple device selection configurations. A49FL004 will compare IDSEL field with ID[3:0] strapping values. there mismatch, device will ignore reminder cycle. Table Configuration Device (Boot Device) Multiple Device Selection
ID[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
IDSEL 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
ID[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Address Range 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
PRELIMINARY
(September, 2005, Version 0.0)
AMIC Technology, Corp.
A49FL004
Register
A49FL004 registers include General Purpose Inputs Register (GPI_REG) Block Locking Register (BL_REG). Both registers available mode only. GPI_REG read FFBC0100h GByte system memory map. BL_REG read through FFBx0002h where x=F-0h. Refer table BL_REG.
General Purpose Inputs Register Table General Purpose Inputs Register Name Function Number 32-PLCC 32-TSOP
GPI[4] GPI[3] GPI[2] GPI[1] GPI[0]
Reserved GPI_REG GPI_REG GPI_REG GPI_REG GPI_REG
A49FL004 contains 8-bit General Purpose Inputs Register (GPI_REG) available modes. Only used current version, reserved future use. GPI_REG pass-through register with value GPI[4:0] during power-up. GPI_REG used system design purpose only, device does this register. This register read only read address location FFBC0100h Gbyte system memory through memory read cycle. Refer Table General Purpose Input Register Definition.
Block Locking Registers
A49FL004 supports block read-lock, write-lock, lockdown features through Block Locking Registers. Each memory block associated 8-bit read/writable block locking register. Only used current version reserved future use. default value BL_REG "01h" power definition BL_REG listed Table FWH/LPC Register Configuration A49FL004 shown Table Unused register will read
Table A49FL004 Block Locking Register Address Memory Address Protected Block Address Range
Mnemonic
Register Name
FFBF0002h FFBE0002h FFBD0002h FFBC0002h FFBB0002h FFBA0002h FFB90002h FFB80002h
T_BLOCK_LK T_MINUS01_LK T_MINUS02_LK T_MINUS03_LK T_MINUS04_LK T_MINUS05_LK T_MINUS06_LK T_MINUS07_LK
Block Lock Register (Block Block [-1] Lock Register (Block Block [-2] Lock Register (Block Block [-3] Lock Register (Block Block [-4] Lock Register (Block Block [-5] Lock Register (Block Block [-6] Lock Register (Block Block [-7] Lock Register (Block
70000h 7FFFFh 60000h 6FFFFh 50000h 5FFFFh 40000h 4FFFFh 30000h 3FFFFh 20000h 2FFFFh 10000h 1FFFFh 00000h 0FFFFh
PRELIMINARY
(September, 2005, Version 0.0)
AMIC Technology, Corp.
A49FL004
Table Block Lock Register Definition
Reserved Read-Lock Lock-Down Write-Lock
Data
Function
00000 00000 00000 00000 00000 00000 00000 00000
Full Access. Write locked. Default state power-up. Locked open (full access locked down). Write-locked down. Read locked. Read Write locked. Read-locked down Read-locked Write-locked down
Data
Function Reserved Read-Lock
Prevents read operations block where Normal operation reads block where clear. This default state.
Lock-Down
Prevents further clear operations Write-Lock Read-Lock bits. Lock-Down only clear. block will remain lock-down until reset (with INIT until device power-on reset. Normal operation Write-Lock Read-Lock altering block where clear. This default state.
Write-Lock
Prevents program erase operations block where set. This default state. Normal operation programming erase block where clear.
PRELIMINARY
(September, 2005, Version 0.0)
AMIC Technology, Corp.
A49FL004
ADDRESS/ADDRESS MULTIPLEXED (A/A MUX) MODE
Read/Write Operation
A49FL004 offers Address/Address Multiplexed (A/A Mux) mode off-system operation, typically EPROM Programmer, similar traditional Flash memory except address input multiplexed. mode, programmer must drive (VIL) read
pins write operation. devices have
multiplex address pins A[10:0] used load column addresses target memory location. addresses (internal address latched falling edge pin. column addresses (internal address A11) latched rising edge pin. A49FL004 respectively. During read operation, signal used control output data pins I/O[7:0]. During write operation, signal used latch input data from I/O[7:0]. Table Operation Modes.
Chip Enable chip selection activation traditional Flash memory. pins used activate device control power.
Table Mode Operation Selection
Mode
Address
Read Write Standby Output Disable Reset
VIL, VIL,
DOUT High High High Manufacturer Device
Product Identification
VIH,
A21= VIL, Notes: VIH. Refer Table Manufacturer Device devices. A49FL004 provides three levels data protection critical BIOS code Notebook. includes memory hardware write protection, hardware data protection software data protection.
six-byte command sequence through consecutive write memory cycles with Block Erase Command (50h), Block address (BA) last cycle. mode, erase operation activated writing six-byte command consecutive cycles. Preprograms block required prior erase operation.
Sector-Erase Operation
A49FL004 contains uniform KByte sectors. sector erase command used erase individual sector. Table Sector/Block Address Table. FWH/LPC mode, erase operation activated writing six-byte command sequence through consecutive write memory cycles with Sector Erase Command (30h), sector address (SA) last cycle. mode, erase operation activated writing six-byte command consecutive cycles. Preprograms sector required prior erase operation.
Chip-Erase
entire memory array erased chip erase operation available under mode operated EPROM Programmer only. Pre-programs device required prior chip erase operation. Chip erase starts immediately after six-bus-cycle chip erase command sequence. commands will ignored once chip erase operation started. Data Polling I/O7 Toggle I/O6 used detect progress completion erase operation. device will return back standby mode after completion chip erase.
Block-Erase Operation
A49FL004 contains eight uniform KByte blocks. block erase command used erase individual block. Table Sector/Block Address Table. FWH/LPC mode, erase operation activated writing
Write Operation Status Detection
program operation, data programmed into devices logical "0") byte-by-byte basis. mode, program operation activated writing three-byte command sequence program address/data
PRELIMINARY
(September, 2005, Version 0.0)
AMIC Technology, Corp.
A49FL004
through four consecutive memory write cycles. mode, program operation activated writing threebyte command sequence program address/data through four consecutive cycles. address (A10 latched falling edge column address (A21 A11) latched rising edge data latched rising edge Once program operation started, internal control logic automatically handles internal programming voltages timing. data programmed back "1". Only erase operation convert "0"s "1"s. Data Polling I/O7 Toggle I/O6 used detect when programming operation completed FWH, LPC, modes. protected. attempt erase program sector block within this area will ignored. Both pins must (VIL) protection high (VIH) un-protection prior program erase operation. logic level change during program erase operation cause unpredictable results. pins work combination with block locking registers. When active, these pins write protect appropriate blocks regardless associated block locking registers setting.
Hardware Data Protection Hardware data protection protects devices from unintentional erase program operation. performed device automatically following three ways: Detection: below (typical), program erase functions inhibited.
Data Polling (I/O7)
device provides Data Polling feature indicate progress completion program erase operation modes. During program operation, attempt read device will result complement last loaded data I/O7. Once program cycle complete, true data last loaded data valid outputs. During erase operation, attempt read device will result I/O7. After erase cycle complete, attempt read device will result I/O7.
Write Inhibit Mode: holding signal low, high inhibits write cycle (A/A mode only). Noise/Glitch Protection: pulses less than (typical) input will initiate write cycle (A/A mode only).
Reset
read, program, erase operation devices reset INIT pins. INIT pins internally hard-wired have same function devices. INIT only available modes. available modes. required drive INIT pins during system reset ensure proper initialization. During memory read operation, pulls INIT will reset devices back standby mode then FWH[3:0] interface LAD[3:0] interface will high impedance state. During program erase operation, pulls INIT will abort program erase operation reset devices back standby mode. reset latency will occur before devices resume standby mode when such reset performed. When program erase operation reset before completion such operation, memory contents devices become invalid incomplete program erase operation.
Toggle (I/O6)
A49FL004 also provides Toggle feature detect progress completion program erase operation. During program erase operation, attempt read data from devices will result I/O6 toggling between "0". When program erase operation complete, I/O6 will stop toggling valid data will read. Toggle accessed time during program erase operation.
Data Protection
device features software data protection function protect device from unintentional erase program operation. performed JEDEC standard Software Data Protection (SDP) command sequences. Table Command Definition. program operation initiated three memory write cycles unlock command sequence. chip (only available mode), sector block erase operation initiated memory write cycles unlock command sequence. During command sequence, invalid command sequence will abort operation force device back standby mode.
Memory Hardware Write Protection A49FL004 KByte boot block. When working in-system, memory hardware write protection feature
Product Identification
product identification mode used read Manufacturer Device software Product Entry command both in-system hardware interface interface modes. product identification mode activated three-bus-cycle command. Refer Table Manufacturer Device A49FL004 Table Command Definition. mode, product identification also read directly FFBC0000h Manufacturer "99h" FFBC0001h Device GByte system memory map.
activated control pins Block Lock Write Protection both modes. When
pulled (VIL), boot block hardware write protected. sector erase, block erase, byte program command attempts erase program boot block will ignored. When pulled (VIL), Block Block A49FL004 (except boot block) hardware write
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Table Product Identification
Description Address Data
Manufacturer Device A49FL004
00000h 00003h 00001h
Figure System Memory Device Memory A49FL004
FFFFFFFFh
49FL004
07FFFF
070000 06FFFF 060000 05FFFF 050000 04FFFF 040000 03FFFF 030000 02FFFF 020000 01FFFF 010000 00FFFF
FFF80000h
000000
itio
0000h
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Table Sector/Block Address Table Block Size Sector Hardware Block (Kbytes)
Sector Size bytes)
Sector Number
Address Range 7F000h 7FFFFh 7E000h 7EFFFh 7D000h 7DFFFh 7C000h 7CFFFh 7B000h 7BFFFh 7A000h 7AFFFh 79000h 79FFFh 78000h 78FFFh 77000h 77FFFh 76000h 76FFFh 75000h 75FFFh 74000h 74FFFh 73000h 73FFFh 72000h 72FFFh 71000h 71FFFh 70000h 70FFFh 60000h 6FFFFh 50000h 5FFFFh 40000h 4FFFFh 30000h 3FFFFh 20000h 2FFFFh 10000h 1FFFFh 00000h 0FFFFh
Block 7(Boot Block)
Kbytes/Sector
Block Block Block
Kbytes/Sector Kbytes/Sector Kbytes/Sector Kbytes/Sector Kbytes/Sector Kbytes/Sector Kbytes/Sector
Block Block Block Block
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Table Software Data Protection Command Definition
Command Cycle Cycles Addr(2) Data Cycle Addr Data Cycle Addr Data Cycle Addr Data Cycle Addr Data Cycle Addr Data
Block Erase Read Sector Erase Chip Erase
5555H Addr 5555H 5555H 5555H 5555H
XXXXH
2AAAH DOUT 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH
5555H 5555H 5555H 5555H 5555H 5555H
5555H 5555H 5555H Addr
2AAAH 2AAAH 2AAAH
5555H
Byte Program Product Entry Product Exit Product Exit
5555H
Notes: Chip erase available Mode only. Address A[15:0] used command decoding internally must FWH/LPC modes. Don't care where most-significant address A49FL004. Sector address erased. Block address erased. Either Product Exit command used.
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Operating Range Range A49FL004
Operating Temperature Power Supply
+70°C 3.0V -3.6V
Table Operating Characteristics
Symbol Parameter Limits Units Test Conditions
ICC1 ICC2
Active Read Current (FWH/LPC) Program/Erase Current Standby Current (FWH/LPC Mode) Ready Mode Current (FWH/LPC Mode) Input Leakage Current ID[3:0] Pins Input Leakage Current Output Leakage Current Input High Voltage Input Voltage Output Voltage Output High Voltage 0.9VDD 0.7VDD -0.5
FWH4 LFRAME VIL, 33MHz, IOUT 0mA,
FWH4 LFRAME VIH, 33MHz, FWH4 LFRAME VIL, 33MHz, IOUT 0mA, VDD, VDD, VI/O VDD,
VDD+0.5 0.3VDD 0.1VDD
IOL= 2.0mA, -100µA,
Notes: Characterized tested.
Table Impedance (VDD=3.3V, T=25°C, f=1MHz)
Parameter Description Test Condition
CI/O LPIN
Capacitance Input Capacitance Inductance
VI/O
12pF 12pF 20nH
Notes: These parameters characterized tested. Refer specification.
Table FWH/LPC Interface Clock Characteristics
Symbol Parameter Units
tCYC tHIGH tLOW
Cycle Time High Time Time Slew Rate (peak-to-peak)
INIT Slew Rate
V/ns mV/ns
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Table FWH/LPC Memory Read/Write Operations Characteristics
Symbol Parameter Units
tCYC tVAL tOFF
Clock Cycle Time Input Time Input Hold Time Clock Data Clock Active Time (Float Active Delay) Clock Inactive Time (Active Float Delay)
Table FWH/LPC Interface Measurement Condition Parameters
Symbol Value Units
VTH4 VTL1 VTEST VMAX1
Input Signal Edge Rate 1V/ns Notes: input test environment done with overdrive over VIL. Timing parameters must with more overdrive that this. VMAX specifies maximum peak-to-peak waveform allowed measuring input timing. Production testing different voltage values, must correlate results back these parameters.
Figure Input Timing Parameters
VTEST FWH[3:0] LAD[3:0] (Valid Input Data) Valid Inputs VMAX
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Figure Output Timing Parameters
TEST FWH[3:0] LAD[3:0] (Valid Output Data) FWH[3:0] LAD[3:0] (Float Output Data)
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Table FWH/LPC Interface Input/Output Characteristics
Symbol Parameter Test Conditions Units
VOUT 0.3VDD (AC) Switching Current High (Test Point) (AC) Switching Current (Test Point) slewr
-17.1(VDD-VOUT) Equation 16VDD -17.1(VDD VOUT) Equation 38VDD -25+(VIN+1)/0.015 25+(VIN-VDD-1)/0.015
V/ns V/ns
0.3VDD VOUT 0.9VDD 0.7VDD VOUT VOUT 0.7VDD VOUT 0.6VDD 0.6VDD VOUT 0.1VDD 0.18VDD VOUT VOUT=0.18VDD VDD+4 VDD+1 0.2VDD-0.6VDD load 0.6VDD-0.2VDD load
Clamp Current High Clamp Current Output Rise Slew Rate Output Fall Slew Rate
slewf
Notes: specification. specification output load used.
Table Mode Interface Reset Timing Parameters, VDD=3.0-3.6V
Symbol Parameter Units
tPRST tKRST tRSTP tRSTF tRST
Reset Active Time Stable Reset Active Time Clock Stable Reset Pulse Width Reset Active Output Float Delay Reset Inactive Time Input Active
Note: There will reset latency reset procedure performed during programming erase operation. Figure Reset Timing Diagram
TKRST INIT TRSTF FWH[3:0] LAD[3:0] FWH4 TRSTE TRST
Program Erase Operation Aborted
TPRST
TRSTP
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Figure Mode Input/Output Reference Waveforms
VIHT INPUT VILT test inputs driven (0.9VDD) logic HIGH VILT (0.1VDD) logic LOW. Measurement reference points inputs outputs (0.5VDD) (0.5VDD). Input rise fall times (10% 90%) Note: VINPUT Test VOUTPUT Test IHT: VINPUT HIGH Test ILT: VINPUT Test Reference Points OUTPUT
Figure Mode Test Load Condition
TESTER
CL=30pF
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MODE CHARACTERISTICS Table Mode Read Operations Characteristics
Symbol Parameter Units
Read Cycle Time High Address Setup Time Address Set-up Time Address Hold Time Address Output Delay
Output Delay Output High
tRST tVCS
Setup Time Output Hold from Address, whichever occurred first
Table Write (Program/Erase) Operations Characteristics
Symbol tRST Parameter Units
High Address Setup Time Address Setup Time Address Hold Time High Time
High Setup Time High Hold Time
tCWH tOES tOEH tWPH tVCS
Write Pulse Width
Pulse Width High
Data Setup Time Data Hold Time Byte Programming Time Chip, Sector Block Erase Cycle Time Setup Time
Figure Mode Read Cycle Timing Diagram
TRSTP
TRST
Address
Column Address Address Column Address
Address
High-Z TOLZ
Data Valid
TOHZ High-Z
I/O7-I/O0
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Figure Mode Write Cycle Timing Diagram
Address
TRST
ddress olumn ddress
TCWH TOES
TWPH
I/O7 -I/O0 High-Z
Valid
Figure Mode Data# Polling Timing Diagram
Address
Address Column Address Address Column Address Address Column Address Address Column Address
TOEP High-Z
I/O7
Data
Data#
Data#
Data
Final Input Command
Status
Status
Data
Command Input
Write Operation Progress
Write Operation Complete
Figure Mode Toggle Timing Diagram
Address
Address Column Address Address Column Address Address Column Address Address Column Address
High-Z
Data
Data
Final Input Command
Status
Status
Data
Command Input
Write Operation Progress
Write Operation Complete
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Figure Mode Byte Program Timing Diagram
Four-Byte Byte Program Command Sequence 5555 Address 2AAA 5555
TWPH
High-Z
I/O7-I/O0
Byte Program Command Input Byte Program Address Byte Program Data
Byte Program Operation Progress
Figure Mode Block Erase Timing Diagram
Six-Byte Block Erase Command Sequence 5555 Address 2AAA 5555 5555 2AAA
TWPH
High-Z
30/50
I/O7-I/O0
Block Erase Command Input Block Address
Block Erase Operation Progress
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Figure Mode Chip Erase Timing Diagram
Six-Byte Chip Erase Command Sequence 5555 Address 2AAA 5555 5555 2AAA 5555
TWPH
TSCE
High-Z
I/O7-I/O0
Chip Erase Command Input
Chip Erase Operation Progress
Figure Mode Product Entry Read Timing Diagram
Three-Byte Product Entry Command Sequence 5555 Address 2AAA 5555 0000 0001 0003
TWPH
TIDA
High-Z
I/O7-I/O0
Figure Mode Product Exit Reset Timing Diagram
Three-Byte Product Exit Reset Command Sequence 5555 Address 2AAA 5555
TWPH
High-Z
I/O7-I/O0
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Figure Automatic Byte Program Algorithm
Start
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
Write Command Address: 5555H Data:
Write Command Address: Data:
I/O7 Data I/O6 Stop Toggle?
Byte Program Completed
Byte Program Address Byte Program Data
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Figure Automatic Block Erase Algorithm
Start
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
Write Command Address: 5555H Data:
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
I/O7 Data I/O6 Stop Toggle?
Write Command Address: Data:
Block Erase Completed
Block Address
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Figure Automatic Chip Erase Algorithm
Start
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
Write Command Address: 5555H Data:
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
I/O7 Data I/O6 Stop Toggle?
Write Command Address: 5555H Data:
Chip Erase Completed
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Figure Product Command Flowchart
Start
Start
Write Command Address: 5555H Data:
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
Write Command Address: 2AAAH Data:
Write Command Address: 5555H Data:
Write Command Address: 5555H Data:
Write Command Address: XXXXH Data:
Enter Product Mode
Exit Product Mode
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Ordering Information
A49FL004T
Temperature Range
Commercial (0°C +85°C)
Clock Frequency
33MHz
Package Type
PLCC TSOP (8mmX14mm)
Device Number
Mbit Flash Memory
Part
Clock Frequency (MHz)
Boot Block Location
Temperature Range +85°C
Package Type
A49FL004TL-33
32-pin PLCC
A49FL004TL-33F
+85°C +85°C +85°C
32-pin Pb-Free PLCC 32-pin TSOP (8mm 32-pin Pb-Free TSOP (8mm
A49FL004TX-33
A49FL004TX-33F
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Package Information PLCC Outline Dimension
unit: inches/mm
Dimensions inches
Dimensions 0.47 2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91 2.80 0.71 0.46 0.254 13.97 11.43 1.27 12.95 10.41 14.99 12.45 2.29 3.40 2.93 0.81 0.54 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.075
Symbol
0.0185 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075
0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.510 0.410 0.590 0.490 0.090
0.134 0.115 0.032 0.021 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.003
Notes: Dimensions include resin fins. Dimensions Board surface mount pitch design reference only.
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Package Information
TSOP TYPE 14mm) Outline Dimensions unit: inches/mm
Pin1
0.254 Gage Plane Detail
Detail
Dimensions inches Symbol 0.002 0.037 0.0067 0.004 0.311 0.543 0.484 0.020 0.000 0.039 0.0087 0.315 0.0197 0.551 0.488 0.024 0.047 0.006 0.041 0.0106 0.0083 0.319 0.559 0.492 0.028 0.003
Dimensions 0.05 0.95 0.17 0.10 7.90 13.80 12.30 0.50 0.00 1.00 0.22 8.00 0.50 14.00 12.40 0.60 1.20 0.15 1.05 0.27 0.21 8.10 14.20 12.50 0.70 0.076
Notes: Dimension does include mold flash. Dimension does include interlead flash. Dimension does include dambar protrusion.
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Mbit CMOS 3.3Volt-only Firmware Hub/LPC Flash Memory Preliminary

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