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A48P4616

Document Title 16M X 16 Bit DDR DRAM Revision History

A48P4616
Preliminary
Document Title 16M X 16 Bit DDR DRAM Revision History
Rev. No.
16M X 16 Bit DDR DRAM
History
Initial issue
Issue Date
September 5, 2005
Remark
Preliminary
Preliminary (September, 2005, Version 0.0)
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A48P4616
Features
DDR 256M bit, die C, based on 110nm design rules. Double data rate architecture: two data transfers per clock cycle. Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.
General Description
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Pin Configuration
TSOP (II)
Column Address Table
Organization 64Mb x 4 32Mb x 8 16Mb x16 Coiumn Addres A0-A9, A11 A0-A9 A0-A8
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A48P4616
Block Diagram (64Mb x 4)
Note: 1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device it does not represent an actual circuit implementation. 2. DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
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Block Diagram (32Mb x 8)
Note: 1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device it does not represent an actual circuit implementation. 2. DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
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Block Diagram (16Mb x 16)
Note: 1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device it does not represent an actual circuit implementation. 2. DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
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Pin Descriptions
Symbol Type Description Clock: CK and CK are differential clock inputs. All address and control input signals CK, CK Input are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power Down and Self Refresh operation (all banks idle), or Active Power Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during Power Down. Input buffers, excluding CKE, are disabled during self refresh. The standard pinout includes one CKE pin. Optional pinouts might include CKE1 on a different pin, in addition to CKE0, to facilitate independent power down control of stacked devices. Chip Select: All commands are masked when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS is considered part of CS , CS0 , CS1 Input the command code. The standard pinout includes one CS pin. Optional pinouts might include CS1 on a different pin, in addition to CS0 , to allow upper or lower deck selection on stacked devices.
CKE, CKE0, CKE1
Input
Command Inputs: RAS , CAS , WE (along with CS ) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. During a Read, DM can be driven high, low, or floated. Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. BA0 and BA1 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. Address Inputs: Provide the row address for Active commands, and the column address and Auto Precharge bit for Read / Write commands, to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode Register Set command. Data Input / Output: Data bus. Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-DQ7 UDQS corresponds to the data on DQ8-DQ15 No Connect: No internal electrical connection is present.
Input
BS0, BS1
Input
A0-A12
Input
DQ DQS. LDQS, UDQS NC NU VDDQ VSSQ VDD VSS VREF
Input / Output Input / Output
Electrical connection is present. Should not be connected at second level of assembly. Supply Supply Supply Supply Supply
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A48P4616
Functional Description
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456 bits. The 256Mb DDR SDRAM is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The doubledata-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I / O pins. A single read or write access for the 256Mb DDR SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I / O pins. Read and write accesses to the DDR SDRAM are burst oriented accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1 select the bank A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access. Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.
Initialization
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Register Definition
Mode Register Burst Length
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both Read and Write bursts.
Mode Register Operation BA1
0 BA0 0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 BT A2 A1 A0 Address Bus Mode Register
Operating Mode
CAS Latency CAS Latency
Burst Length
Operating Mode
A12-A9 A8 A7 A6-A0 Type A6
A3 Burst Type Type
Burst Length A2 A1 A0 Type
Sequential Interleave
Valid Valid VS
Normal operation Do not reset DLL Normal operation in DLL Reset Vendor-Specific Test Mode Reserved
Reserved Reserved 2 3 (Option) Reserved 1.5 (Option) 2.5 Reserved
Reserved 2 4 8 Reserved Reserved Reserved Reserved
Note: 1. VS Vendor Specific 2. BA0 and BA1 must be 0, 0 to select the Mode Register (vs. the Extended Mode Register).
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Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definition on page 10.
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 2 or 2.5 clocks. If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Burst Definition
Note: 1. For a burst length of two, A1-A i selects the two-data-element block A0 selects the first access within the block. 2. For a burst length of four, A2-A i selects the four-data-element block A0-A1 selects the first access within the block. 3. For a burst length of eight, A3-A i selects the eight-data- element block A0-A2 selects the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
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Operating Mode
The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register Set command issued to reset the DLL should always be followed by a Mode Register Set command to select normal operating mode. All other combinations of values for A7-A12 are reserved for future use and / or test modes. Test modes and reserved states should not be used as unknown operation or incompatibility with future versions may result.
CAS Latencies
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Extended Mode Register
DLL Enable / Disable
QFC Enable / Disable Output Drive Strength
Extended Mode Register Definition
A2 QFC
A0 DLL
Address Bus Extended Mode Register
Operating Mode
Operating Mode A12-A3 A2-A0 Type
Drive Strength A1 Type
Disable Enable (Optional)
Enable Disable
Valid -
Normal Operation All Other States Reserved
Normal Reserved
Note: BA0 and BA1 must be 1, 0 to select the Extended Mode Register (vs. the base Mode Register)
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Commands
Truth Tables 1a and 1b prvide a reference of the commands supported by DDR SDRAM device. A verbal description of each commands follows.
Name (Function)
CS RAS CAS
Address
Deselect (Nop) No Openration (Nop) Active (Select Bank And Activate Row) Read (Select Bank And Activate Column, And Start Read Burst) Write (Select Bank And Activate Column, And Start Write Burst) Burst Terminate Precharge (Deactivate Row In Bank Or Banks) Auto Refresh Or Self Refresh (Enter Self Refresh Mode) Mode Register Set
X X Bank / Row Bank / Col Bank / Col X Code X Op-Code
NOP NOP ACT Read Write BST PRE AR / SR MRS
Write Enable Write Inhibit
Valid X
Note: Used to mask write data provided coincident with the corresponding data.
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Deselect The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected. No Operation (NOP)
The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. If Auto Precharge is selected, the row being accessed is precharged at the end of the Write burst if Auto Precharge is not selected, the row remains open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data is written to memory if the DM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to that byte / column location.
Precharge
Mode Register Set
The mode registers are loaded via inputs A0-A12, BA0 and BA1 while issuing the Mode Register Set Command. See mode register descriptions in the Register Definition section. The Mode Register Set command can only be issued when all banks are idle and no bursts are in progress. A subsequent executable command cannot be issued until tMRD is met.
Active
The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and completed before opening a different row in the same bank.
Auto Precharge
Auto Precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific Read or Write command. A precharge of the bank / row that is addressed with the Read or Write command is automatically performed upon completion of the Read or Write burst. Auto Precharge is non-persistent in that it is either enabled or disabled for each individual Read or Write command. Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This is determined as if an explicit Precharge command was issued at the earliest possible time without violating tRAS(min). The user must not issue another command to the same bank until the precharge (tRP) is completed. The NTC DDR SDRAM devices supports the optional tRAS lockout feature. This feature allows a Read command with Auto Precharge to be issued to a bank that has been activated (opened) but has not yet satisfied the tRAS(min) specification. The tRAS lockout feature essentially delays the onset of the auto precharge operation until two conditions occur. One, the entire burst length of data has been successfully prefetched from the memory array and two, tRAS(min) has been satisfied.
Write
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Self Refresh
Burst Terminate
The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most re-cently registered Read command prior to the Burst Terminate command is truncated, as shown in the Operation section of this data sheet. Write burst cycles are not to be terminated with the Burst Terminate command.
Auto Refresh
Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS (CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be issued each time a refresh is required.
tRAP Definition
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Operations
Bank / Row Activation
Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must be "opened" (activated). This is accomplished via the Active command and addresses A0-A12, BA0 and BA1 (see Activating a Specific Row in a Specific Bank), which decode and select both the bank and the row to be activated. After opening a row (issuing an Active command), a Read or Write command may be issued to that row, subject to the tRCD specification. A subsequent Active command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive Active commands to the same bank is defined by tRC. A subsequent Active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive Active commands to different banks is defined by tRRD.
Reads
Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated with a Read command. The starting column and bank addresses are provided with the Read command and Auto Precharge is either enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge at the completion of the burst, provided tRAS has been satisfied. For the generic Read commands used in the following illustrations, Auto Precharge is disabled.
Activating a Specific Row in a Specific Bank
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tRCD and tRRD Definition
Read Command
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Writes
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Write Command
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Precharge
Precharge Command
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Power Down
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Power Down
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Truth Table 2: Clock Enble(CKE)
Current CKE n-1 CKE n Command n Action n Note
Previous Cycle Previous Cycle
Self Refresh Self Refresh Power Down Power Down All Banks Idle All Banks Idle Bank(s) Active
X Deselect or NOP X Deselect or NOP Deselect or NOP Auto Refresh Deselect or NOP See "Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)" on page 44
Maintain Self-Refresh Exit Self-Refresh Maintain Power Down Exit Power Down Precharge Power Down Entry Self Refresh Entry Active Power Down Entry 1
Note: 1. CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge. 2. Current state is the state of the DDR SDRAM immediately prior to clock edge n. 3. Command n is the command registered at clock edge n, and action n is a result of command n. 4. All states and sequences not shown are illegal or reserved.
5. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
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Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)
Current State
CS RAS CAS WE
Command
Action
NOP. Continue previous operation NOP. Continue previous operation
Deselect No Operation Active Auto Refresh Mode Register Set Read Write Precharge Read Precharge Burst Terminate Read Write Precharge
Select and Activate Row
Row Active Read (Auto Precharge Disabled) Write (Auto Precharge Disabled)
Select column and start Read Burst Select column and start Write Burst
Deactivate row in bank(s)
Select column and start new Read Burst
Burst Terminate
Select column and start Read Burst Select column and start Write Burst
Truncate Write burst, start Precharge
11. Requires appropriate DM masking.
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Truth Table 4: Current State Bank n - Command to Bank m (Different bank)
Current State
CS RAS CAS WE
Command
Action
NOP / Continue previous operation NOP / Continue previous operation
Any Idle Row Activating, Active, or Precharging Read (Auto Precharge Disabled) Write (Auto Precharge Disabled)
Deselect No Operation Any Command Otherwise Allowed to Bank m Active Read Write Precharge Active Read Precharge Active Read Write Precharge
Select and Activate Row Select column and start Read Burst Select column and start Write Burst
Select and Activate Row
Select column and start new Read Burst
Select and Activate Row
Select column and start Read Burst Select column and start new Write Burst
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Truth Table 4: Current State Bank n - Command to Bank m (Different bank) (continued)
Current State
CS RAS CAS WE
Command
Action
Select and Activate Row
Read (With Auto Precharge) Write (With Auto Precharge)
Active Read Write Precharge Active Read Write Precharge
Select column and start new Read Burst Select column and start Write Burst
Select and Activate Row
Select column and start Read Burst Select column and start new Write Burst
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Simplified State Diagram
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Absolute Maximum Ratings
Symbol Parameter Rating Unit
VIN, VOUT VIN VDD VDDQ TA TATG PD IOUT
Voltage on I / O pins relative to VSS Voltage on Inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating Temperature (Ambient) Storage Temperature (Plastic) Power Dissipation Short Circuit Output Current
0.5 to VDDQ+ 0.5
-0.5 to +3.6 -0.5 to +3.6 -0.5 to +3.6 0 to +70 -55 to +150 1.0 5.0
Notes: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DQS / DQ / DM Slew Rate DDR333 Parameter Symbol Min (6K) Max Min DDR400 (5T) Max Unit Note
DCS / DQ / DM Slew Rate
DCSLEW
Notes: 1. Measured between V IH (DC), V IL (DC), and V IL (DC), V IH (DC). 2. DQS, DQ, and DM input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transition through the DC region must be monotonic.
Capacitance
Parameter Symbol Min Max Unit Note
Input Capacitance: CK, CK Delta Input Capacitance: CK, CK Input Capacitance: All Other Input-only pins (except DM) Delta Input Capacitance: All Other Input-only pins (except DM) Input / Output Capacitance: DQ, DQS, DM Delta Input / Output Capacitance: DQ, DQS, DM
CI1 Delta CI1 CI2 Delta CI2 CI / O Delta CI / O
2. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is required to match input propagation times of DQ, DQS and DM in the system.
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Symbol Parameter Min Max Unit Note
VDD VDDQ VSS, VSSQ VREF VTT VIH (DC) VIL (DC) VIN (DC) VID (DC) VIX (DC) VIRatio II IOZ IOH IOL
2.3 2.3 0 0.49 x VDDQ VREF + 0.04 VREF + 0.15 - 0.3 - 0.3 0.30 0.30 0.71 -5 -5 - 16.8
2.7 2.7 0 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 VDDQ + 0.6 1.4 5 5
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DC Electrical Characteristics and Operating Conditions
Symbol Parameter Min Max Unit Note
IOHW IOLW
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Normal Strength Driver Pulldown and Pullup Characteristics
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Normal Strength Driver Pulldown and Pullup Currents
Pulldown Current (mA) Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Typical Low Tycpial High 6.0 12.2 18.1 24.1 29.8 34.6 39.4 43.7 47.5 51.3 54.1 56.2 57.9 59.3 60.1 60.5 61.0 61.5 62.0 62.5 62.9 63.3 63.8 64.1 64.6 64.8 65.0 6.8 13.5 20.1 26.6 33.0 39.1 44.2 49.8 55.2 60.3 65.2 69.9 74.2 78.4 82.3 85.9 89.1 92.2 95.3 97.2 99.1 100.9 101.9 102.8 103.8 104.6 105.4 Min 4.6 9.2 13.8 18.4 23.0 27.7 32.2 36.8 39.6 42.6 44.8 46.2 47.1 47.4 47.7 48.0 48.4 48.9 49.1 49.4 49.6 49.8 49.9 50.0 50.2 50.4 50.5 Max 9.6 18.2 26.0 33.9 41.8 49.4 56.8 63.2 69.9 76.3 82.5 88.3 93.8 99.1 103.8 108.4 112.1 115.9 119.6 123.3 126.5 129.5 132.4 135.0 137.3 139.2 140.8 -6.1 -12.2 -18.1 -24.0 -29.8 -34.3 -38.1 -41.1 -43.8 -46.0 -47.8 -49.2 -50.0 -50.5 -50.7 -51.0 -51.1 -51.3 -51.5 -51.6 -51.8 -52.0 -52.2 -52.3 -52.5 -52.7 -52.8 Pullup Current (mA) Tycpial Low Tycpial High -7.6 -14.5 -21.2 -27.7 -34.1 -40.5 -46.9 -53.1 -59.4 -65.5 -71.6 -77.6 -83.6 -89.7 -95.5 -101.3 -107.1 -112.4 -118.7 -124.0 -129.3 -134.6 -139.9 -145.2 -150.5 -155.3 -160.1 Min -4.6 -9.2 -13.8 -18.4 -23.0 -27.7 -32.2 -36.0 -38.2 -38.7 -39.0 -39.2 -39.4 -39.6 -39.9 -40.1 -40.2 -40.3 -40.4 -40.5 -40.6 -40.7 -40.8 -40.9 -41.0 -41.1 -41.2 Max -10.0 -20.0 -29.8 -38.8 -46.8 -54.4 -61.8 -69.5 -77.3 -85.2 -93.0 -100.6 -108.1 -115.5 -123.0 -130.4 -136.7 -144.2 -150.5 -156.9 -163.2 -169.6 -176.0 -181.3 -187.6 -192.9 -198.2
Normal Strength Driver Evaluation Conditions
typical Temperature (Tambient) VDDQ Process conditions 25 °C 2.5V Typical process
Minimum 70 °C 2.3V Slow-slow process
Maximum 0 °C 2.7V Fast-fast process
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AC Characteristics
AC Output Load Circuit Diagrams
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AC Input Operating Conditions
Symbol Parameter / Condition Min Max Unit Note
VIH (AC) VIL (AC) VID (AC) VIX (AC)
Input High (Logic 1) Voltage, DQ, DQS, and DM Signals Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals Input Differential Voltage, CK and CK Inputs Input Crossing Point Voltage, CK and CK Inputs
VREF + 0.31 VREF - 0.31 0.7 0.5VDDQ - 0.2 VDDQ + 0.6 0.5 VDDQ + 0.2
IDD Specifications and Conditions
Symbol
Parameter / Condition
(min)
Unit Note
IDD1 IDD2P IDD2N IDD3P
Idle Standby Current: CS VIH (min) all banks idle CKE VIH address and control inputs changing once per clock cycle Active Power Down Standby Current: one bank active Power Down mode CKE VIL (max) Active Standby Current: One bank active / precharge CS
IDD3N
IDD4R
IDD4W IDD5 IDD6 IDD7
Notes: 1. IDD specifications are tested after the device is properly initialized. 2. Enables on-chip refresh and address counters.
Preliminary (September, 2005, Version 0.0)
AMIC Technology, Corp.
A48P4616
Electrical Characteristics & AC Timing - Absolute Specifications
Symbol Parameter DDR333 (6K) DDR400 (5T) Min Max Unit Note
ns ns tCK tCK
tDQSCK DQS output access time from CK / CK tCH tCL CK high-level width CK low-level width
ns ns ns ns +0.65 +0.65 +0.40 ns ns ns
tHP tQH tQHS tDQSS tDQSH tDQSL tDSS tDSH tMRD
Minimum half clk period for any given cycle Defined by clk high (tCH) or low (tCL) time. Data output hold time from DQS Data hold Skew Factor TSOP Package
min tCL, tCH tHP, tQHS 0.55 0.75 0.35 0.35 0.2 0.2 12 0 0.40 0.25 0.75 0.75 0.60 1.25
min tCL, tCH tHP, tQHS 0.5 0.72 0.35 0.35 0.2 0.2 12 0 0.40 0.25 0.6 0.6 0.60 1.25
tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK ns ns
Write command to 1st DQS latching transition
DQS input high pulse width (write cycle) DQS input low pulse width (write cycle) DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) Mode register set command cycle time
tWPRES Write preamble setup time tWPST tWPRE tIH tIS Write postamble Write postamble
Address and control input hold time (fast slew rate) Address and control input hold time (fast slew rate)
Preliminary (September, 2005, Version 0.0)
AMIC Technology, Corp.
A48P4616
Electrical Characteristics & AC Timing - Absolute Specifications (continued)
Symbol DDR333 6K DDR400 5T Min Max
Parameter
Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Read preamble Read postamble Active to Precharge Active to Active / Auto-refresh command period Auto-refresh to Active / Auto-refresh command period Active to Read or write dalay Active to read command with Autoprecharge Precharge command period Active bank A to Active bank B command Write vecovery time Auto precharge write recovery + precharge time Intemal write to read command delay Power down exit time Exit self-refresh to non-read command
Exit self-refresh to read command
tIH tIH tRPRE tRPST tRAS tRC tRFC tRCD tRAP tRP tRRD tWR tDAL tWTR tPDEX tXSNR tXSRD tREFI 0.8 0.8 0.9 0.40 40 60 72 18 min (tRCD, tRAS) 18 12 15 1 6 75 200
0.65 0.65 1.1 0.60 70K 0.9 2.0 42 55 70 15 min (tRCD, tRAS) 15 10 15 2 6 75 200 7.8 7.8 1.1 0.6 70K
ns ns tCK tCK ns ns tCK tCK tCK tCK tCK tCK tCK tCK ns tCK tCK s
Average Periodic Refresh Interval
Preliminary (September, 2005, Version 0.0)
AMIC Technology, Corp.
A48P4616
Electrical Characteristics & AC Timing - Absolute Specifications (continued)
Input Slew Rate Delta (tIS) Delta (tIH) Unit Note
1. Input slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising transitions. 2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
15. An input setup and hold time derating table is used to increase tDS and tDH in the case where the I / O slew rate is below 0.5
Input Slew Rate Delta (tDS) Delta (tDH) Unit Note
1. I / O slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising transitions. 2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
16. An I / O Delta Rise, Fall Derating table is used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ.
Input Slew Rate Delta (tDS) Delta (tDH) Unit Note
Preliminary (September, 2005, Version 0.0)
AMIC Technology, Corp.
A48P4616
Preliminary (September, 2005, Version 0.0)
AMIC Technology, Corp.
A48P4616
Initialize and Mode Register Sets
Preliminary (September, 2005, Version 0.0)
AMIC Technology, Corp.
A48P4616
Power Down Mode
Preliminary (September, 2005, Version 0.0)
AMIC Technology, Corp.
A48P4616
Auto Refresh Mode
Preliminary (September, 2005, Version 0.0)
AMIC Technology, Corp.
A48P4616
Self Refresh Mode
Preliminary (September, 2005, Version 0.0)
AMIC Technology, Corp.
A48P4616
Preliminary (September, 2005, Version 0.0)
AMIC Technology, Corp.
A48P4616
Preliminary (September, 2005, Version 0.0)
AMIC Technology, Corp.
A48P4616
Preliminary (September, 2005, Version 0.0)
AMIC Technology, Corp.
A48P4616
Preliminary (September, 2005, Version 0.0)
AMIC Technology, Corp.
A48P4616
Preliminary (September, 2005, Version 0.0)
AMIC Technology, Corp.
A48P4616
Preliminary (September, 2005, Version 0.0)
AMIC Technology, Corp.
A48P4616
Preliminary (September, 2005, Version 0.0)
AMIC Technology, Corp.
A48P4616
Package Dimensions (400mil 66 lead TSOP Package)
Preliminary (September, 2005, Version 0.0)
AMIC Technology, Corp.