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Intel® 440GX AGPset: 82443GX Host Bridge/Controller
Order Number: 290638-001
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. 82443GX chipset contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available upon request. two-wire communications bus/protocol developed Philips. SMBus subset bus/protocol developed Intel. Implementations bus/protocol SMBus bus/protocol require licenses from various entities, including Philips Electronics N.V. North American Philips Corporation. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 1997-1998 *Third-party brands names property their respective owners.
82443GX Host Bridge
Intel 82443GX Features
Processor/System support
Optimized Pentium® Pentium® Xeonprocessors system frequency Supports full symmetric Multiprocessor (SMP) Protocol processors; APIC related buffer management support (WSC# signal) In-order transaction dynamic deferred transaction support Supports GTL+ AGTL+ driver technology (gated GTL+ receivers reduced power) Integrated DRAM controller Supports double-sided DIMMs rows memory) 64-bit data interface with support (SDRAM only) Unbuffered Registered SDRAM (Synchronous) Support (x-1-1-1 access MHz) Enhanced SDRAM Open Page Architecture Support 16-, 64-, 128-, 256-Mbit* DRAM devices with page sizes Rev. 2.1, 3.3V 33MHz interface compliant Parity Generation Support Data streaming support from DRAM Delayed Transaction support PCI-DRAM Reads Supports concurrent CPU, transactions main memory
interface
Supports single compliant device (AGP-66/133 3.3V device) Specification compliant AGP-data/transaction flow optimized arbitration mechanism side-band interface efficient request pipelining without interfering with data streams AGP-specific data buffering Supports concurrent CPU, transactions main memory high-priority transactions ("expedite") support Power management functions Stop Clock Grant Halt special cycle translation (host Bus) "Deep Green" Desktop support system suspend/resume (i.e., DRAM power-on suspend) SDRAM self-refresh power down support suspend mode Independent, internal dynamic clock gating reduces average power dissipation Static STOP CLOCK support Power-on Suspend mode Suspend DRAM ACPI compliant power management Packaging/Voltage 3.3V core mixed 3.3V Supporting Bridge System Management (SMB) with support DIMM Serial Presence Detect (SPD) PCI-ISA Bridge (PIIX4E) Power Management Support 3.3V core mixed 3.3V interface 2.5V signals open-drain output buffers
interface
Intel® 440GX AGPset intended Pentium® processor Pentium® Xeonprocessor platforms. 82443GX Host Bridge provides Host-to-PCI bridge, optimized DRAM controller data path, Accelerated Graphic Port (AGP) interface. high performance, component level interconnect targeted graphics applications based performance enhancements PCI. subsystem portion Intel® 440GX AGPset platform based 82371EB (PIIX4E), highly integrated version Intel's PCI-ISA bridge family.
Proper operation 82443GX AGPset with 256-Mbit SDRAM devices been verified. Intel's current plans validate this feature second half 1998 when 256-Mbit SDRAM devices available. Intel 82443GX contain design defects errors known errata which cause products deviate from published specifications. Current characterized errata available request.
82443GX Host Bridge
Intel 82443GX Simplified Block Diagram
A[31:3]# ADS# BPRI# BNR# CPURST# DBSY# DEFER# HD[63:0]# HIT# HITM# HLOCK# HREQ[4:0]# HTRDY# DRDY# RS[2:0]# CSA[7:0]# CSB[7:0]# DQMA[7:0] DQMB[5,1] GCKE SRAS[B,A]# FENA SCAS[B,A]# MAA[14:0] MAB[14,13,12#,11#,10,9#:0 WEA# WEB# MD[63:0] MECC[7:0] AD[31:0] C/BE[3:0]# FRAME# TRDY# IRDY# DEVSEL# SERR# PLOCK# STOP# PHOLD# PHLDA# WSC# PREQ0# PREQ[4:1]# PGNT0# PGNT[4:1]# GAD[31:0] GC/BE[3:0]# GFRAME# GIRDY# GTRDY# GSTOP# GDEVSEL# GREQ# GGNT# GPAR PIPE# SBA[7:0] RBF# STOP# ST[2:0] ADSTB_A ADSTB_B SBSTB
Host Interface
Interface (PCI
DRAM Interface
Interface
HCLKIN PCLKIN GTLREF[B:A] AGPREF VTT[B:A] REF5V PCIRST# CRESET# BREQ0# TESTIN# GCLKO GCLKIN DCLKO DCLKWR
Clocks, Reset, Test, Misc.
Power Mgnt
CLKRUN# SUSTAT# GXPWROK
GX_BLK.VSD
82443GX Host Bridge
Contents
Architectural Overview .1-1 Signal Description .2-1 Host Interface Signals.2-1 DRAM Interface .2-3 Interface (Primary) .2-4 Primary Sideband Interface .2-6 Interface Signals.2-6 Clocks, Reset, Miscellaneous .2-8 Power-Up/Reset Strap Options.2-9 Mapped Registers .3-2 3.1.1 CONFADD-Configuration Address Register.3-2 3.1.2 CONFDATA-Configuration Data Register .3-3 3.1.3 PM2_CTL-ACPI Power Control Control Register .3-4 Configuration Space Access.3-4 3.2.1 Configuration Space Mechanism Overview .3-5 3.2.2 Routing Configuration Accesses .3-5 3.2.3 Configuration Mechanism Overview .3-6 3.2.3.1 Type Access .3-6 3.2.3.2 Type Access .3-6 3.2.4 Configuration Mechanism Overview .3-6 3.2.5 Mapping Configuration Cycles .3-7 Host-to-PCI Bridge Registers (Device .3-8 3.3.1 VID-Vendor Identification Register (Device 0).3-10 3.3.2 DID-Device Identification Register (Device .3-10 3.3.3 PCICMD-PCI Command Register (Device .3-11 3.3.4 PCISTS-PCI Status Register (Device .3-12 3.3.5 RID-Revision Identification Register (Device .3-13 3.3.6 SUBC-Sub-Class Code Register (Device .3-13 3.3.7 BCC-Base Class Code Register (Device .3-13 3.3.8 MLT-Master Latency Timer Register (Device 0).3-14 3.3.9 HDR-Header Type Register (Device .3-14 3.3.10 APBASE-Aperture Base Configuration Register (Device 0).3-14 3.3.11 SVID-Subsystem Vendor Identification Register (Device 0).3-15 3.3.12 SID-Subsystem Identification Register (Device 0).3-16 3.3.13 CAPPTR-Capabilities Pointer Register (Device .3-16 3.3.14 NBXCFG-NBX Configuration Register (Device .3-16 3.3.15 DRAMC-DRAM Control Register (Device .3-19 3.3.16 PAM[6:0]-Programmable Attribute Registers (Device 0).3-20 3.3.17 DRB[0:7]-DRAM Boundary Registers (Device .3-22 3.3.18 FDHC-Fixed DRAM Hole Control Register (Device .3-24 3.3.19 MBSC-Memory Buffer Strength Control Register (Device 0).3-24 3.3.20 SMRAM-System Management Control Register (Device 0).3-28
Register Description.3-1
82443GX Host Bridge
3.3.21 ESMRAMC-Extended System Management Control Register (Device .3-29 3.3.22 RPS-SDRAM Page Size Register (Device 0).3-30 3.3.23 SDRAMC-SDRAM Control Register (Device .3-30 3.3.24 PGPOL-Paging Policy Register (Device .3-32 3.3.25 PMCR-Power Management Control Register (Device .3-33 3.3.26 SCRR-Suspend Refresh Rate Register (Device .3-34 3.3.27 EAP-Error Address Pointer Register (Device 0).3-34 3.3.28 ERRCMD-Error Command Register (Device .3-35 3.3.29 ERRSTS-Error Status Register (Device 0).3-36 3.3.30 ACAPID-AGP Capability Identifier Register (Device .3-37 3.3.31 AGPSTAT-AGP Status Register (Device .3-37 3.3.32 AGPCMD-AGP Command Register (Device 0).3-38 3.3.33 AGPCTRL-AGP Control Register (Device .3-39 3.3.34 APSIZE-Aperture Size Register (Device .3-40 3.3.35 ATTBASE-Aperture Translation Table Base Register (Device .3-40 3.3.36 MBFS-Memory Buffer Frequency Select Register (Device .3-41 3.3.37 BSPAD-BIOS Scratch Register (Device .3-43 3.3.38 DWTC-DRAM Write Thermal Throttling Control Register (Device .3-43 3.3.39 DRTC-DRAM Read Thermal Throttling Control Register (Device .3-44 3.3.40 BUFFC-Buffer Control Register (Device .3-45 PCI-to-PCI Bridge Registers (Device .3-46 3.4.1 VID1-Vendor Identification Register (Device 1).3-47 3.4.2 DID1-Device Identification Register (Device .3-47 3.4.3 PCICMD1-PCI-to-PCI Command Register (Device .3-48 3.4.4 PCISTS1-PCI-to-PCI Status Register (Device .3-49 3.4.5 RID1-Revision Identification Register (Device .3-49 3.4.6 SUBC1-Sub-Class Code Register (Device .3-50 3.4.7 BCC1-Base Class Code Register (Device .3-50 3.4.8 MLT1-Master Latency Timer Register (Device 1).3-50 3.4.9 HDR1-Header Type Register (Device .3-51 3.4.10 PBUSN-Primary Number Register (Device 1).3-51 3.4.11 SBUSN-Secondary Number Register (Device .3-51 3.4.12 SUBUSN-Subordinate Number Register (Device .3-52 3.4.13 SMLT-Secondary Master Latency Timer Register (Device .3-52 3.4.14 IOBASE-I/O Base Address Register (Device .3-52 3.4.15 IOLIMIT-I/O Limit Address Register (Device .3-52 3.4.16 SSTS-Secondary PCI-to-PCI Status Register (Device .3-53 3.4.17 MBASE-Memory Base Address Register (Device 1).3-54 3.4.18 MLIMIT-Memory Limit Address Register (Device 1).3-54 3.4.19 PMBASE-Prefetchable Memory Base Address Register (Device .3-55 3.4.20 PMLIMIT-Prefetchable Memory Limit Address Register (Device .3-55 3.4.21 BCTRL-PCI-to-PCI Bridge Control Register (Device .3-56
82443GX Host Bridge
Functional Description .4-1 System Address Map.4-1 4.1.1 Memory Address Ranges .4-2 4.1.1.1 Compatibility Area.4-3 4.1.1.2 Extended Memory Area .4-4 4.1.1.3 Memory Address Range.4-6 4.1.1.4 DRAM Graphics Aperture.4-6 4.1.1.5 System Management Mode (SMM) Memory Range.4-6 4.1.2 Memory Shadowing .4-8 4.1.3 Address Space.4-8 4.1.4 Address Mapping.4-8 4.1.5 Decode Rules Cross-Bridge Address Mapping .4-9 4.1.5.1 Interface Decode Rules .4-9 4.1.5.2 Interface Decode Rules .4-9 4.1.5.3 Legacy Ranges .4-10 Host Interface.4-10 4.2.1 Host Device Support.4-10 4.2.2 Symmetric Multiprocessor (SMP) Protocol Support.4-13 4.2.3 In-Order Queue Pipelining .4-13 4.2.4 Frame Buffer Memory Support (USWC) .4-13 DRAM Interface .4-14 4.3.1 DRAM Organization Configuration.4-14 4.3.1.1 Configuration Mechanism DIMMS .4-16 4.3.2 DRAM Address Translation Decoding .4-17 4.3.3 SDRAMC Register Programming .4-19 4.3.4 SDRAM Paging Policy .4-19 Interface .4-19 Interface .4-20 Data Integrity Support .4-20 4.6.1 Data Integrity Mode Selection.4-20 4.6.1.1 Non-ECC (Default Mode Operation) .4-20 4.6.1.2 Mode .4-20 4.6.1.3 Mode .4-21 4.6.1.4 Generation Error Detection/Correction Reporting .4-21 4.6.1.5 Optimum Coverage .4-22 4.6.2 DRAM Error Signaling Mechanism.4-22 4.6.3 Integrity .4-22 4.6.4 Integrity .4-22 System Clocking .4-23 Power Management.4-23 4.8.1 Overview .4-23 4.8.2 82443GX Reset .4-26 4.8.2.1 Reset .4-27 4.8.2.2 Clock Ratio Straps.4-27 4.8.2.3 82443GX Straps .4-28 4.8.3 Suspend Resume .4-28 4.8.3.1 Suspend Resume protocols .4-28 4.8.3.2 Suspend Refresh .4-29 4.8.4 Clock Control Functions .4-29 4.8.5 SMRAM.4-30
82443GX Host Bridge
Pinout Package Information.5-1 82443GX Pinout .5-1 Package Dimensions .5-8
Figures
Intel® 440GX AGPset System Block Diagram .1-2 82443GX Hierarchy .3-5 SDRAM DIMMs Corresponding Registers .3-23 Memory System Address Space .4-2 Four-DIMM Configuration with switches .4-15 Typical Intel® 440GX AGPset System Clocking .4-23 Reset CPURST# Desktop System When PCIRST# Asserted .4-27 External Glue Logic Drives Clock Ratio Straps .4-28 82443GX Pinout (Top View-left side).5-2 82443GX Pinout (Top View-right side) .5-3 82443GX Package Dimensions-Top Side Views.5-8 82443GX Package Dimensions-Bottom Views.5-9
viii
82443GX Host Bridge
Tables
2-10 4-10 4-11 4-12 4-13 4-14 4-15 Host Interface Signals.2-1 Host Signals supported 82443GX .2-3 DRAM Interface Signals.2-3 Primary Interface Signals.2-4 Primary Sideband Interface Signals.2-6 Interface Signals.2-6 Clocks, Reset, Miscellaneous .2-8 Power Management Interface.2-9 Reference Pins .2-9 Strapping Options .2-10 82443GX Register Device 0.3-8 Attribute Assignment.3-20 Registers Associated Memory Segments .3-21 82443GX Configuration Space-Device 1.3-46 Memory Segments their Attributes.4-3 SMRAM Decoding .4-7 SMRAM Range Decode.4-7 SMRAM Decode Control.4-7 Host Transactions Supported 82443GX.4-11 Host Responses supported 82443GX.4-12 Host Special Cycles with 82443GX .4-12 Data Bytes DIMM Used Programming DRAM Registers.4-16 Supported Memory Configurations .4-18 Muxing DRAM Address Split.4-18 Programmable SDRAM Timing Parameters .4-19 Power Mode .4-25 AGPset Reset .4-26 Reset Signals.4-26 Suspend Resume Events Activities .4-28 82443GX Alphabetical List.5-4 82443GX Package Dimensions (492 BGA) .5-9
82443GX Host Bridge
Architectural Overview
Intel® 440GX AGPset includes 82443GX Host Bridge 82371EB PIIX4E subsystem. 82443GX functions capabilities include:
Support single dual Pentium® processor Pentium® Xeonprocessor
configurations
64-bit GTL+ AGTL+ based System (Host) Interface 32-bit Host address Support 64-bit Main Memory Interface with optimized support SDRAM 32-bit Primary Interface (PCI) with integrated arbiter Interface (AGP) with data transfer capability configurable Secondary
Extensive Data Buffering between interfaces high throughput concurrent operations "Deep Green" Desktop power management support
Figure shows block diagram typical platform based Intel® 440GX AGPset. 82443GX host interface supports Pentium processors Pentium Xeonprocessors frequency. physical interface design based GTL+ specification optimized desktop. 82443GX provides optimized 64-bit DRAM interface. This interface implemented 3.3V-only interface that supports only DRAM technology. copies signals drive maximum DIMMs each; providing unbuffered high performance MHz. 82443GX provides interface operating MHz. This interface implementation compliant with Specification. 82443GX interface implementation based Specification. interface supports data transfer rates. 82443GX designed support PIIX4E bridge. PIIX4E highly integrated multifunctional component supporting following functions capabilities:
compliant PCI-ISA Bridge with support both 3.3V
operations
Deep Green Desktop Power Management Support Enhanced controller Interrupt Controller Timer functions Integrated controller with Ultra DMA/33 support host interface with support ports System Management (SMB) with support DIMM Serial Support external APIC component
82443GX Host Bridge
Architectural Overview
Figure 1-1. Intel® 440GX AGPset System Block Diagram
Pentium® Pentium® XeonProcessor Video Camera Pentium® Pentium® XeonProcessor
System Video Capture
Graphics Device
82443GX Host Bridge
Main Memory 3.3V SDRAM Support
Display
Graphics Local Memory Encoder
Slots Primary (PCI
Video BIOS
System MGMT (SM) Ports (Ultra DMA/33) 82371EB (PIIX4E) (PCI-to-ISA Bridge) System BIOS
sys_blk.vsd
APIC
Ports
Slots
Host Interface Pentium® processor Pentium® Xeonprocessor support second level cache cache interface. control cache handled processor. 82443GX provides control signals address paths transfers between processors system (host bus), bus, main memory. 82443GX supports 4-deep in-order queue (i.e., supports pipelining outstanding transaction requests host bus). system concurrency requirements, along with support pipelining address requests from host bus, 82443GX supports request queuing three interfaces (Host, PCI). Host-initiated cycles decoded PCI, configuration space. Host-initiated memory cycles decoded PCI, (prefetchable non-prefetchable memory space) DRAM (including aperture memory). memory cycles (host, initiated) that target aperture space DRAM, 82443GX translates address using address translation table. Other host cycles forwarded defined address map. initiated cycles that target graphics aperture also translated using aperture translation table. AGP-initiated cycles that target graphics aperture mapped main memory require snoop cycle host bus, since coherency data that particular memory range will maintained software.
82443GX Host Bridge
Architectural Overview
DRAM Interface 82443GX integrates DRAM controller that supports 64-bit main memory interface. DRAM controller supports following features:
DRAM type: Synchronous DRAM (SDRAM) controller optimized dual/quad-bank
SDRAM organization basis
Memory Size: with eight memory rows Addressing Type: Asymmetrical addressing Memory Modules supported: Single double-sided 3.3V DIMMs DRAM device technology: Mbit, Mbit, Mbit, Mbit DRAM Speed: synchronous memory (SDRAM).
Intel® 440GX AGPset also provides DIMM plug-and-play support Serial Presence Detect (SPD) mechanism using SMBus interface. 82443GX provides optional data integrity features including memory array. During reads from DRAM, 82443GX provides error checking correction data. 82443GX supports multiple-bit error detection single-bit error correction when mode enabled single/multi-bit error detection when correction disabled. During writes DRAM, 82443GX generates data QWord basis. Partial QWord writes require read-modify-write cycle when enabled. Interface 82443GX implementation compatible with following:
Accelerated Graphics Port Specification, Accelerated Graphics Port Memory Performance Specification, (4/12/96)
82443GX supports only synchronous interface coupling 82443GX core frequency. interface reach theoretical ~500 MByte/sec transfer rate (i.e., using compliant devices). Interface 82443GX interface 3.3V tolerant), Rev. compliant supports five external masters addition bridge (PIIX4/PIIX4E). PCI-to-DRAM interface reach over MByte/sec transfer rate streaming reads over MBytes/sec streaming writes. System Clocking 82443GX operates host interface, SDRAM, core only; MHz; 66/133 MHz. APIC APIC used support dual processors well enhanced interrupt processing single processor environment. 82443GX supports external status output signal that used control synchronization interrupts configurations that PIIX4E with stand-alone APIC component.
Proper operation 82443GX AGPset with 256-Mbit SDRAM devices been verified. Intel's current plans validate this feature second half 1998 when 256-Mbit SDRAM devices available.
82443GX Host Bridge
Signal Description
Signal Description
This chapter provides detailed description 82443GX signals. signals arranged functional groups according their associated interface.
symbol signal name indicates that active, asserted state occurs when signal voltage level. When present after signal name signal asserted when high voltage level. following notations used describe signal type: I/OD Input Output Open Drain Output pin. This requires pullup processor core Input Open Drain Output pin. This requires pullup processor core Bi-directional Input/Output
signal description also includes type buffer used particular signal: GTL+ Open Drain GTL+ interface signal. Refer GTL+ Specification complete details interface signals. These signals compliant with 3.3V 5.0V Signaling Environment Specifications interface signals. These signals compatible with 3.3V Signaling Environment Specifications
CMOS CMOS buffers Voltage compatible signals. These 3.3V only.
Host Interface Signals
Table 2-1. Host Interface Signals (Sheet
Name Type GTL+ GTL+ GTL+ Description Reset. CPURST# output from 82443GX. 82443GX generates this signal based PCIRST# input (from PIIX4E) also SUSTAT# mobile mode. CPURST# allows CPUs begin execution known state. Address Bus: A[31:3]# connect address bus. During cycles, A[31:3]# inputs. Host Data: These signals connected data bus. Note that data signals inverted bus.
CPURST#
A[31:3]# HD[63:0]#
82443GX Host Bridge
Signal Description
Table 2-1. Host Interface Signals (Sheet
Name ADS# BNR# Type GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ Description Address Strobe: owner asserts ADS# indicate first cycles request phase. Block Next Request: Used block current request owner from issuing request. This signal used dynamically control pipeline depth. Priority Agent Request: 82443GX only Priority Agent bus. asserts this signal obtain ownership address bus. This signal priority over symmetric requests will cause current symmetric owner stop issuing transactions unless HLOCK# signal asserted. Symmetric Agent Request: Asserted 82443GX when CPURST# asserted configure symmetric agents. BREQ0# negated host clocks after CPURST# negated. Data Busy: Used data owner hold data transfers requiring more than cycle. Defer: 82443GX generates deferred response defined rules 82443GX's dynamic defer policy. 82443GX also uses DEFER# signal indicate retry response. Data Ready: Asserted each cycle that data transferred. Hit: Indicates that caching agent holds unmodified version requested line. Also driven conjunction with HITM# target extend snoop window. Modified: Indicates that caching agent holds modified version requested line that this agent assumes responsibility providing line. Also driven conjunction with HIT# extend snoop window. Host Lock: cycles sampled with assertion HLOCK# ADS#, until negation HLOCK# must atomic, i.e. snoopable access DRAM allowed when HLOCK# asserted CPU. Request Command: Asserted during both clocks request phase. first clock, signals define transaction type level detail that sufficient begin snoop request. second clock, signals carry additional information define complete transaction type. transactions supported 82443GX Host Bridge defined Host Interface section this document. Host Target Ready: Indicates that target transaction able enter data transfer phase. Response Signals: Indicates type response according following table: RS[2:0] GTL+ Response type Idle state Retry response Deferred response Reserved (not driven 82443GX) Hard Failure (not driven 82443GX) data response Implicit Writeback Normal data response
BPRI#
BREQ0#
DBSY#
DEFER#
DRDY# HIT#
HITM#
HLOCK#
HREQ[4:0]#
GTL+ GTL+
HTRDY#
RS[2:0]#
NOTE: signals host interface described External Specification. preceding table highlights 82443GX specific uses these signals.
82443GX Host Bridge
Signal Description
Table lists interface signals which supported Intel® 440GX AGPset. Table 2-2. Host Signals supported 82443GX
Signal A[35:32]# AERR# AP[1:0]# BINIT# DEP[7:0]# IERR# INIT# BERR# RSP# BP[3:2]# BPM[1:0]# Function Address Address Parity Error Address Parity Initialization Data ECC/Parity Internal Error Soft Reset Error Request Parity Response Parity Signal BreakPoint BreakPoint Monitor Supported 82443GX Extended addressing (over Parity protection address Parity protection address Checking protocol violation protocol recovery mechanism Enhanced data integrity Direct internal error observation IERR# Implemented PIIX4E, BIST supported external logic. Unrecoverable error without protocol violation Parity protection ADS# PREQ[4:0]# Parity protection RS[2:0]# Breakpoint status Breakpoint performance monitor
DRAM Interface
Table 2-3. DRAM Interface Signals (Sheet Name
CSA[7:0]# /CSB[7:0]#
Type
CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Description
Chip Select (SDRAM): These pins perform function selecting particular SDRAM components during active state. Note that there copies physical memory improve loading. Input/Output Data Mask A-side: These pins control half memory array synchronized output enables during read cycles byte enables during write cycles. Input/Output Data Mask B-side (SDRAM): same function corresponding signals side (DQMAx). These signals used reduce loading configuration. Global CKE: Global used DIMM configuration requiring power down mode SDRAM. External logic must used implement this function. SDRAM Address Strobe: SRAS[B,A]# signals multiple copies same logical SRASx signal (for loading purposes) used generate SDRAM command encoded SRASx/SCASx/WE signals. Enable (FENA): FENA used select proper path through switches DIMM configuration. SDRAM Column Address Strobe: SCAS[B,A]# signals multiple copies same logical SCASx signal (for loading purposes) used generate SDRAM command encoded SRASx/SCASx/WE signals.
DQMA[7:0]
DQMB[1,5]
GCKE
SRAS[B,A]#
FENA
SCAS[B,A]#
82443GX Host Bridge
Signal Description
Table 2-3. DRAM Interface Signals (Sheet Name
MAA[14:0] MAB[12:11]# MAB[14,13,10] MAB[9:0]# WEA# WEB# MD[63:0] MECC[7:0] CMOS
Type
Description
Memory Address(SDRAM): MAA[14:0] MAB[14,13,12#,11#,10,9#:0#] used provide multiplexed column address DRAM. There sets signals which drive max. DIMMs each. MAB[12:11,9:0]# inverted copies MAA[12:11,9:0]. MAA[14,13,10] MAB[14,13,10] identical copies. Each MAA/MAB[14:0] line programmable buffer strength optimize different signal loading conditions. Write Enable Signa: asserted during writes DRAM. lines have programmable buffer strength optimize different signal loading conditions. Memory Data: These signals used interface DRAM data bus. Memory Data: These signals carry Memory data during access DRAM.
CMOS CMOS CMOS
Interface (Primary)
Table 2-4. Primary Interface Signals (Sheet
Name Type Description Address/Data: These signals connected address/data bus. Address driven 82443GX with FRAME# assertion, data driven received following clocks. When 82443GX acts target Bus, AD[31:0] signals inputs contain address during first clock FRAME# assertion input data (writes) output data (reads) subsequent clocks. Device Select: Device select, when asserted, indicates that target device decoded address target current access. 82443GX asserts DEVSEL# based DRAM address range address range being accessed initiator. input indicates whether device been selected. Frame: FRAME# output when 82443GX acts initiator Bus. FRAME# asserted 82443GX indicate beginning duration access. 82443GX asserts FRAME# indicate transaction beginning. While FRAME# asserted, data transfers continue. When FRAME# negated, transaction final data phase. FRAME# input when 82443GX acts target. target, 82443GX latches C/BE[3:0]# AD[31:0] signals first clock edge which samples FRAME# active. Initiator Ready: IRDY# output when 82443GX acts initiator input when 82443GX acts target. assertion IRDY# indicates current initiator's ability complete current data phase transaction.
AD[31:0]
DEVSEL#
FRAME#
IRDY#
82443GX Host Bridge
Signal Description
Table 2-4. Primary Interface Signals (Sheet
Name Type Description Command/Byte Enable: Command Byte Enable signals multiplexed same pins. During address phase transaction, C/BE[3:0]# define command. During data phase C/BE[3:0]# used byte enables. byte enables determine which byte lanes carry meaningful data. command encoding types listed below. C/BE[3:0]# 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Command Type Interrupt Acknowledge Special Cycle Read Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Reserved (Dual Address Cycle) Memory Read Line Memory Write Invalidate
C/BE[3:0]#
Parity: driven 82443GX when acts initiator during address data phases write cycle, during address phase read cycle. driven 82443GX when acts target during each data phase memory read cycle. Even parity generated across AD[31:0] C/BE[3:0]#. Lock: PLOCK# indicates exclusive operation require multiple transactions complete. When PLOCK# asserted, non-exclusive transactions proceed. 82443GX supports lock initiated cycles only. initiated locked cycles supported. Target Ready: TRDY# input when 82443GX acts initiator output when 82443GX acts target. assertion TRDY# indicates target agent's ability complete current data phase transaction. System Error: 82443GX asserts this signal indicate error condition. SERR# assertion 82443GX enabled globally SERRE PCICMD register. SERR# asserted under following conditions: configuration, 82443GX asserts SERR#, single (correctable) errors multiple (non-correctable) errors SERR# signaling enabled ERRCMD control register. errors received during initialization should ignored. 82443GX asserts SERR# clock when detects target abort during 82443GX initiated cycle. 82443GX also assert SERR# when parity error occurs during address data phase. 82443GX assert SERR# when detects address data parity error 82443GX assert SERR# upon detection access invalid entry Graphics Aperture Translation Table. 82443GX assert SERR# upon detecting invalid master access outside aperture outside main DRAM range (i.e. 640k range above TOM). 82443GX assert SERR# upon detecting invalid master access outside aperture. 82443GX asserts SERR# clock when detects target abort during 82443GX initiated cycle. Stop: STOP# input when 82443GX acts initiator output when 82443GX acts target. STOP# used disconnect, retry, abort sequences Bus.
PLOCK#
TRDY#
SERR#
STOP#
NOTE: interface signals conform specification.
82443GX Host Bridge
Signal Description
Primary Sideband Interface
Table 2-5. Primary Sideband Interface Signals
Name Type CMOS Description Hold: This signal comes from PIIX4E. PIIX4E request ownership. 82443GX will flush disable CPU-to-PCI write buffers before granting PIIX4E PHLDA#. This prevents deadlock between ISA. Hold Acknowledge: This signal driven 82443GX grant ownership PIIX4E after CPU-PCI post buffers have been flushed disabled. Write Snoop Complete. This signal asserted active indicate that that snoop activity behalf last PCI-DRAM write transaction complete that safe send APIC interrupt message. Request: PREQ[4:0]# request signals used inputs internal arbiter. Grant: PGNT[4:0]# grant output signals generated internal arbiter.
PHOLD#
PHLDA#
WSC#
PREQ[4:0]# PGNT[4:0]#
Interface Signals
There signals added normal group signals that together constitute interface. sections below describe their operation use, organized five groups:
Addressing Signals Flow Control Signals Status Signals Clocking Signals Strobes Signals
Table 2-6. Interface Signals (Sheet
Name Type Description Sideband Addressing Signals1 Pipelined Read: This signal asserted current master indicate full width address queued target. master queues request each rising clock edge while PIPE# asserted. When PIPE# deasserted requests queued across bus. PIPE# sustained tri-state signal from masters (graphics controller) input 82443GX. Note that initial designs PIPE#. Sideband Address: This provides additional pass address command 82443GX from master. Note that, when sideband addressing disabled, these signals isolated external/internal pull-ups required). Flow Control Signals Read Buffer Full. This signal indicates master ready accept previously requested priority read data. When RBF# asserted 82443GX allowed return priority read data master first block. RBF# only sampled beginning cycle. master always ready accept return read data then required implement this signal.
PIPE#
SBA[7:0]
RBF#
82443GX Host Bridge
Signal Description
Table 2-6. Interface Signals (Sheet
Name Type Description Status Signals Status Bus: This provides information from arbiter Master what ST[2:0] only have meaning master when GGNT# asserted. When GGNT# deasserted these signals have meaning must ignored. Indicates that previously requested priority read data being returned master. Indicates that previously requested high priority read data being returned master. Indicates that master provide priority write data previously queued write command. Indicates that master provide high priority write data previously queued write command.
ST[2:0]
Reserved Reserved Reserved Indicates that master been given permission start transaction. master queue requests asserting PIPE# start transaction asserting FRAME#. ST[2:0] always output from 82443GX input master. Clocking Signals Strobes ADSTB_A Strobe This signal provides timing double clocked data bus. agent that providing data drives this signal. This signal requires 8.2K external pull-up resistor. Strobe This signal additional copy AD_STBA signal. This signal requires 8.2K external pull-up resistor. Sideband Strobe: THis signal provides timing side-band bus. This signal requires 8.2K external pull-up resistor. FRAME# Protocol SIgnals (similar PCI)2 GFRAME# Graphics Frame: Same PCI. used AGP. GFRAME# remains deasserted pull resistor. Graphics Initiator Ready: meaning. GIRDY# indicates compliant master ready provide write data current transaction. Once IRDY# asserted write operation, master allowed insert wait states. assertion IRDY# reads indicates that master ready transfer subsequent block bytes) read data. master never allowed insert wait states during initial data transfer bytes) read transaction. However, insert wait states after each byte block transferred.
ADSTB_B SBSTB
GIRDY#
(There GFRAME# GIRDY# relationship transactions.)
Graphics Target Ready: meaning. GTRDY# indicates compliant target ready provide read data entire transaction (when transfer size less than equal bytes) ready transfer initial subsequent block bytes) data when transfer size greater than bytes. target allowed insert wait states after each block bytes) transferred both read write transactions. Graphics Stop: Same PCI. used AGP. Graphics Device Select: Same PCI. used Graphics Request: Same PCI. (Used request access initiate request.)
GTRDY#
GSTOP# GDEVSEL# GREQ#
82443GX Host Bridge
Signal Description
Table 2-6. Interface Signals (Sheet
Name Type Description Graphics Grant: Same meaning additional information provided ST[2:0]. additional information indicates that selected master recipient previously requested read data (high normal priority), provide write data (high normal priority), previously queued write command been given permission start transaction (AGP PCI). Graphics Address/Data: Same PCI. Graphics Command/Byte Enables: Slightly different meaning. Provides command information (different commands than PCI) when requests being queued when using PIPE#. Provide valid byte information during write transactions used during return read data. Graphics Parity: Same PCI. used transactions, used during transactions defined specification.
GGNT#
GAD[31:0]
GC/BE[3:0]#
GPAR
NOTE: Sideband Addressing Signals. above table contains mechanisms queue requests master. Note that master only mechanism. When PIPE# used queue addresses master allowed queue addresses using bus. example, during configuration time, master indicates that either mechanism, configuration software will indicate which mechanism master will use. Once this choice been made, master will continue mechanism selected until master reset (and reprogrammed) other mode. This change modes dynamic mechanism rather static decision when device first being configured after reset. signals redefined when used transactions carried using protocol extension. transactions interface carried using protocol these signals completely preserve semantics. exact role signals during transactions Table 2-6. LOCK# signal supported interface (even operations). signals described Table behave according specifications when used perform transactions Interface.
Clocks, Reset, Miscellaneous
Table 2-7. Clocks, Reset, Miscellaneous (Sheet
Name HCLKIN Type CMOS CMOS CMOS CMOS CMOS CMOS Description Host Clock This receives buffered host clock. This clock used 82443GX logic that Host clock domain. When SUSTAT# active, there internal 100K pull down this signal. Clock This buffered clock reference that synchronously derived external clock synthesizer component from host clock. This clock used 82443GX logic that clock domain. When SUSTAT# active, there internal 100K pull down this signal. DCLKO DCLKWR SDRAM Clock Out: SDRAM clock reference. feeds external buffer clock device that produces multiple copies DIMMs. SDRAM Write Clock: Feedback reference from external SDRAM clock buffer. Reset: When asserted, this signal will reset 82443GX logic. output bi-directional signals will also tri-state compliant specifications. When SUSTAT# active, there internal 100K pull down this signal. GCLKIN Clock GCLKIN input feedback reference from GCLKOUT signal.
PCLKIN
PCIRST#
82443GX Host Bridge
Signal Description
Table 2-7. Clocks, Reset, Miscellaneous (Sheet
Name GCLKO Type CMOS CMOS CMOS Description Clock Out: frequency MHz. GCLKOUT output used feed both reference input 82443GX compliant device. Delayed Reset: CRESET# delayed copy CPURST#. This signal used control multiplexer strap signals. CRESET# delayed from CPURST# host clocks. Note: This requires external pull-up resistor. used, pull required. TESTIN# Test Input: This used manufacturing, board level test purposes. Note: This internal pull-up.
CRESET#
Table 2-8. Power Management Interface
Name Type Description Primary Clock Run: 82443GX requests central resource (PIIX4E) start maintain clock assertion CLKRUN#. 82443GX tristates CLKRUN# upon deassertion PCIRST# (since running upon deassertion reset). connected PIIX4E external 2.7K pull-up required Desktop, Mobile requires (8.2k-10K) pull-up. Otherwise, pull down required. Suspend Status (from PIIX): SUSTAT# signals system suspend state transition from PIIX4E. used isolate suspend voltage well enter/exit DRAM self-refresh mode. During POS/STR SUSTAT# active. Power GXPWROK input must connected PWROK signal that indicates valid power applied 82443GX.
CLKRUN#
I/OD CMOS
SUSTAT#
CMOS CMOS
GXPWROK
Table 2-9. Reference Pins
Name GTLREF[B:A] VTT[B:A] REF5V AGPREF Buffer voltage reference input Threshold voltage early clamps Power 3.3V Ground reference voltage (for tolerant buffers) External Input Reference Description
Power-Up/Reset Strap Options
Table 2-10 list power-up options that loaded into 82443GX during cold reset. 82443GX required float signals connected straps during cold reset keep them floated minimum host clocks after cold reset sequence. Cold reset sequence performed when 82443GX power applied. Note: signals used select power-up strap options connected either internal pull-down pullup resistors minimum ohms (maximum 150K). That selects default mode signal during reset. enable different modes, external pull pull downs (the opposite internal
82443GX Host Bridge
Signal Description
resistor) approximately connected particular signals. These pull pull down resistors should connected 3.3V power supply. During normal operation 82443GX, including while suspend mode, paths from internal strapping resistors disabled effectively disable resistors. these cases, MAB# lines driven 82443GX valid voltage levels. Note: Note that when resuming from suspend, even while PCIRST# active, MAB# lines remain driven 82443GX strapping latches maintain value stored during cold reset. This first column Table 2-10 lists signal that sampled obtain strapping option. second column shows which register strapping option loaded into. third column description what functionality strapping selects. GTL+ signals connected through normal pull-ups. straps controlled 82443GX (e.g. A15#), driven active least clocks prior active-to-inactive edge CPURST# driven inactive four clocks after active-to-inactive edge CPURST#. Table 2-10. Strapping Options
Signal MAB13# MAB12# NBXCFG[13] Register Name[bit] Reserved. MAB12# strapped host frequency MHz. Strapping MAB12# reserved condition. internal pull-down provides default setting In-Order Queue Depth Enable: MAB11# strapped during rising edge PCIRST#, then 82442GX will drive during CPURST# deassertion. This forces configured non-pipelined operation. MAB11# NBXCFG[2] MAB11 strapped (default), then 82443GX does drive during reset, sampled default non-driven state (i.e. pulled-up GTL+ termination concerned) then maximum allowable queue depth protocol selected (i.e., Note that internal pull-up used provide pipelined mode default. MAB10 Reserved. Disable: When strapped interface disabled, signals tri-stated isolated. When strapped (default), interface enabled. MAB9# PMCR[1] When MMCONFIG strapped active, require that AGP_DISABLE also strapped active. When MMCONFIG strapped inactive, AGP_DISABLE strapped active inactive IDSEL_REDIRECT (bit NBXCFG register) must never activated. This signal internal pull-down resistor. MAB[8:6] A[7]# none Reserved. In-order Queue Depth Status: value A[7]# sampled rising edge CPURST# reflects IOQD maximum allowable bus. Description
NOTE: Proper strapping must used define logical values these signals. Default value "0", provided internal pull-up pull-down resistor overridden external pull-up, pull-down resistor.
2-10
82443GX Host Bridge
Register Description
Register Description
82443GX contains sets software accessible registers, accessed Host address space: Control registers that mapped into space. These registers control access configuration space. Internal configuration registers residing within 82443GX, partitioned into logical device register sets ("logical" since they reside within single physical device). first register dedicated Host-to-PCI Bridge functionality. This (device controls interface operations, DRAM configuration, other chip-set operating parameters optional features. second register (device dedicated Host-to-AGP Bridge functions (controls interface configurations operating parameters). following nomenclature used register access attributes. R/WC Read Only. register read only, writes this register have effect. Read/Write. register with this attribute read written Read/Write Clear. register with this attribute read written. However, write clears (sets corresponding write effect. Read/Write Once. register with this attribute written only once after power After first write, becomes read only. Read/Write/Lock. This register includes lock bit. Once lock been register becomes read only.
R/WO R/WL
82443GX supports configuration space access using mechanism denoted Configuration Mechanism specification. 82443GX internal registers (both Mapped Configuration registers) accessible Host CPU. registers accessed Byte, Word (16-bit), DWord (32-bit) quantities, with exception CONFADD which only accessed Dword. multi-byte numeric fields "little-endian" ordering (i.e., lower addresses contain least significant parts field). Some 82443GX registers described this section contain reserved bits. These bits labeled "Reserved". Software must deal correctly with fields that reserved. reads, software must appropriate masks extract defined bits rely reserved bits being particular value. writes, software must ensure that values reserved positions preserved. That values reserved positions must first read, merged with values other positions then written back. Note: Software does need perform read, merge, write operation configuration address register. addition reserved bits within register, 82443GX contains address locations configuration space Host-to-PCI Bridge entity that marked either "Reserved" "Intel Reserved". 82443GX responds accesses "Reserved" address locations completing host cycle. When "Reserved" register location read, zero value returned. ("Reserved" registers 16-, 32-bit size). Writes "Reserved" registers have effect
82443GX Host Bridge
Register Description
82443GX. Registers that marked "Intel Reserved" must modified system software. Writes "Intel Reserved" registers cause system failure. Reads "Intel Reserved" registers return non-zero value. Software should write reserved configuration locations device-specific region (above address offset 3Fh) Upon reset, 82443GX sets internal configuration registers predetermined default states. However, there exceptions this rule. When reset occurs during POS/STR state, several configuration bits reset their default state. These bits noted following register description. Some register values reset determined external strapping options. default state represents minimum functionality feature required successfully bring system. Hence, does represent optimal system configuration. responsibility system initialization software (usually BIOS) properly determine DRAM configurations, operating parameters optional system features that applicable, program 82443GX registers accordingly.
Mapped Registers
82443GX contains three registers that reside address space Configuration Address (CONFADD) Register, Configuration Data (CONFDATA) Register, Power Management Control Register. Configuration Address Register enables/disables configuration space determines what portion configuration space visible through Configuration Data window.
3.1.1
CONFADD-Configuration Address Register
Address: Default Value: Access: Size: 0CF8h Accessed Dword 00000000h Read/Write bits
CONFADD register accessed only when referenced Dword. Byte Word reference will "pass through" Configuration Address Register onto cycle. CONFADD register contains Number, Device Number, Function Number, Register Number which subsequent configuration access intended.
82443GX Host Bridge
Register Description
30:24
Descriptions Configuration Enable (CFGE). When this accesses configuration space enabled. this reset accesses configuration space disabled. Reserved. Number. When Number programmed target Configuration Cycle either 82443GX that directly connected 82443GX, depending Device Number field. type Configuration Cycle generated Number programmed 82443GX target. Number non-zero type configuration cycle generated with Number mapped AD[23:16] during address phase. Device Number. This field selects agent selected Number. During Type Configuration cycle this field mapped AD[15:11]. During Type Configuration Cycle this field decoded among AD[31:11] driven 82443GX always Device Number Host-to-PCI bridge entity Device Number Host- entity. Therefore, 82443GX internally references AD11 AD12 pins corresponding IDSELs respective devices during configuration cycles. NOTE: AD11 AD12 must connected other device IDSEL signals. Function Number. This field mapped AD[10:8] during PCIx configuration cycles. This allows configuration registers particular function multi-function device accessed. 82443GX only responds configuration cycles with function number 000b; other function number values attempting access 82443GX (Device Number Number will generate master abort. Register Number. This field selects register within particular Bus, Device, Function specified other fields Configuration Address Register. This field mapped AD[7:2] during configuration cycles. Reserved.
23:16
15:11
10:8
3.1.2
CONFDATA-Configuration Data Register
Address: Default Value: Access: Size: 0CFCh 00000000h Read/Write bits
CONFDATA read/write window into configuration space. portion configuration space that referenced CONFDATA determined contents CONFADD.
31:0 Descriptions Configuration Data Window (CDW). CONFADD reference that falls CONFDATA space will mapped configuration space using contents CONFADD.
82443GX Host Bridge
Register Description
3.1.3
PM2_CTL-ACPI Power Control Control Register
Address: Default Value: Access: Size: 0022h Read/Write bits
This register used disable both arbiters 82443GX prevent external masters from acquiring bus. currently running cycles will terminate properly. Accesses this register controlled Power Management Control Register (Offset 7Ah). When PMCR `1', ACPI Register location 0022h enabled. When `0', accesses location 0022h forwarded within programmable range).
Reserved Primary Arbiter Request Disable (ARB_DIS). When this 82443GX will respond REQ# signals, requests, PHOLD# from PIIX4E going active until this back Only External requests masked from arbiters. PIIX passive release mode, masking will occur until active release seen PHLDA# assertion. This prevents possible deadlock. ARB_DIS effect side band signals data transfer requests. Description
Configuration Space Access
82443GX implementation manifests devices within single physical component body:
Device Host-to-PCI Bridge interface, Main Memory Controller, Graphics
Aperture controller, 82443GX specific control registers.
Device Host-to-AGP interface "Virtual" PCI-to-PCI Bridge, including address
space mapping, normal interface, associated sideband signal control. Corresponding configuration registers both devices mapped devices residing (bus Configuration register layout functionality Device should inspected carefully, features added 82443GX initiated reasonable level change relative other proliferation's Pentium® processor AGPsets (i.e. 440FX, 440LX). Configuration registers 82443GX Device based normal configuration space template PCI-to-PCI Bridge described Bridge Architecture Specification. Figure shows hierarchy 82443GX. hierarchy, primary highest level hierarchy PCI-to-PCI bridge function provides access AGP/PCI This below primary hierarchy represented
82443GX Host Bridge
Register Description
Figure 3-1. 82443GX Hierarchy
82443GX Host Bridge
Host-to-PCI Bridge
Virtual Host-to-PCI Bridge
Device
3.2.1
Configuration Space Mechanism Overview
82443GX supports interfaces: (referenced Primary PCI) (referenced AGP). interface treated second from configuration point view. following sections describe configuration space mapping mechanism associated with both buses. Note: configuration space device controlled AGP_DIS PMCR register. When AGP_DIS (PMCR[1]) configuration space device enabled, registers device accessible through configuration mechanism defined below. When AGP_DIS (PMCR[1]) configuration space device disabled. configuration cycles (reads writes) device will cause master abort status device set. Configuration read cycles will return data 1's. Configuration write cycles will have effect registers.
3.2.2
Routing Configuration Accesses
Routing configuration accesses controlled PCI-to-PCI bridge normal mechanism using information contained within PRIMARY NUMBER, SECONDARY NUMBER, SUBORDINATE NUMBER registers Host-to-AGP internal "virtual" PCI-to-PCI bridge device. Detailed description mechanism translating cycles configuration cycles buses described below. distinguish between configuration cycles targeting logical device register sets supported 82443GX, this document refers Host-to-PCI bridge interface Host- interface AGP.
82443GX Host Bridge
Register Description
3.2.3
Configuration Mechanism Overview
defines slot based "configuration space" that allows each device contain functions with each function containing 8-bit configuration registers. specification defines cycles access configuration space: Configuration Read Configuration Write. Memory spaces supported directly CPU. Configuration space supported mapping mechanism implemented within chip-set. specification defines mechanisms access configuration space, Mechanism Mechanism 82443GX supports only Mechanism configuration access mechanism makes CONFADD Register CONFDATA Register. reference configuration register Dword write cycle used place value into CONFADD that specifies bus, device that bus, function within device, specific configuration register device function being accessed. CONFADD[31] must enable configuration cycle. CONFDATA then becomes window into four bytes configuration space specified contents CONFADD. read write CONFDATA will result Host Bridge translating CONFADD into configuration cycle.
3.2.3.1
Type Access
Number field CONFADD Type Configuration cycle performed (i.e. #0). CONFADD[10:2] mapped directly AD[10:2]. Device Number field CONFADD decoded onto AD[31:11]. Host-to-PCI Bridge entity within 82443GX accessed Device segment. Host- /AGP Bridge entity within 82443GX accessed Device segment. access Device 82443GX will assert AD13, Device will assert AD14, forth Device which will assert AD31. Only line asserted time. device numbers higher than cause type configuration access with IDSEL asserted, which will result Master Abort.
3.2.3.2
Type Access
Number field CONFADD non-zero, then Type Configuration cycle performed (i.e. #0). CONFADD[23:2] mapped directly AD[23:2]. AD[1:0] driven indicate Type Configuration cycle. other lines driven
3.2.4
Configuration Mechanism Overview
This mechanism compatible with mechanism supported defined above. configuration mechanism same both accessing PCI-only devices attached interface.
82443GX Host Bridge
Register Description
3.2.5
Mapping Configuration Cycles
From AGPset configuration perspective, seen another interface residing Secondary side "virtual" PCI-to-PCI bridge referred 82443GX Host- bridge. Primary side, "virtual" PCI-to-PCI bridge attached referred this document interface. "virtual" PCI-to-PCI bridge entity used Type Configuration cycles onto Type Type configuration cycles interface. Type configuration cycles that have BUS-NUMBER that matches SECONDARYBUS-NUMBER "virtual" bridge will translated into Type configuration cycles interface. Type configuration cycles that have BUS-NUMBER that behind "virtual" bridge will translated into Type configuration cycles interface. Note: supports total devices mapping bits 15:11 CONFADD IDSEL lines AD[31:11]. secondary busses (including bus), only devices supported mapping bits 15:11 CONFADD IDSEL lines (AD[31:16]). prepare mapping configuration cycles initialization software will through following sequence: Scan devices residing (i.e., using Type configuration accesses. every device residing which implements PCI-to-PCI bridge functionality, will configure secondary bridge with appropriate number scan further down hierarchy. This process will include configuration "virtual" PCI-to-PCI Bridge within 82443GX used address space software specific manner.
82443GX Host Bridge
Register Description
Host-to-PCI Bridge Registers (Device
Table shows 82443GX configuration space device
Table 3-1. 82443GX Register Device (Sheet
Address Offset 00-01h 02-03h 04-05h 06-07h 10-13h 14-2Bh 2C-2Dh 2E-2Fh 30-33h 35-4Fh 50-53h 54-56h 59-5Fh 60-67h 69-6Eh 6F-70h 74-75h 76-77h 78-79h 7B-7Ch 7D-7Fh Register Symbol PCICMD PCISTS SUBC APBASE SVID CAPPTR NBXCFG DRAMC PAM[6:0] DRB[7:0] FDHC MBSC SMRAM ESMRAMC SDRAMC PGPOL PMCR SCRR Register Name Vendor Identification Device Identification Command Register Status Register Revision Identification Reserved Sub-Class Code Base Class Code Reserved Master Latency Timer Header Type Aperture Base Address Reserved Subsystem Vendor Identification Subsystem Identification Reserved Capabilities Pointer Reserved 440GX Configuration Reserved DRAM Control Intel Reserved Programmable Attribute registers) DRAM Boundary registers) Fixed DRAM Hole Control Memory Buffer Strength Control Reserved Intel Reserved System Management Control Extended System Management Control. SDRAM Page Size SDRAM Control Register Paging Policy Register Power Management Control Register Suspend Refresh Rate Register Reserved Default Value 8086h 71A0h/71A2h 0006h 0210h/0200h 00000008h A0h/00h [0000h]:[00S0_00 00_000S_0S00b] 00S0_0000b 0000-0000-0000h 0000h 0000h 0000_S0S0b 0038h Access R/WC R/W,RO R/WO R/WO
82443GX Host Bridge
Register Description
Table 3-1. 82443GX Register Device (Sheet
Address Offset 80-83h 84-8Fh 91-92h 94-97h 98-99h 9B-9Fh A0-A3h A4-A7h A8-ABh AC-AFh B0-B3h B5-B7h B8-BBh BE-BFh C0-C3h C4-C7h CA-CCh CD-CFh D0-D7h D8-DFh E0-E7h E8-EFh F0-F1h F2-F7h F8-FBh FC-FFh NOTES: DWTC DRTC BUFFC Register Symbol ERRCMD ERRSTS ACAPID AGPSTAT AGPCMD AGPCTRL APSIZE ATTBASE MBFS BSPAD Register Name Error Address Pointer Register Reserved Error Command Register Error Status Register Reserved Intel Reserved Intel Reserved Intel Reserved Reserved Capability Identifier Status Register Command Register Reserved Control Register) Aperture Size Control Register Reserved Aperture Translation Table Reserved Reserved Reserved Intel Reserved Intel Reserved Intel Reserved Intel Reserved Memory Buffer Frequency Select Reserved BIOS Scratch Intel Reserved DRAM Write Thermal Throttling Control DRAM Read Thermal Throttling Control Buffer Control Register Intel Reserved Intel Reserved Intel Reserved Default Value 00000000h 0000h 00006104h 0500h 00100002h 00000000h 1F000203h 00000000h 00000000h 00000000h 00000000h 00000000h 000000h 00.00h 000.000h 000.000h 000.000h 0000h 0000F800h 00000F20h 00000000h Access R/WC R/WC, R/W/L R/W/L R/W/L
symbol represents strapping option. Write operations must attempted Intel Reserved registers.
82443GX Host Bridge
Register Description
3.3.1
VID-Vendor Identification Register (Device
Address Offset: Default Value: Attribute: Size: 00-01h 8086h Read Only bits
Register contains vendor identification number. This 16-bit register combined with Device Identification Register uniquely identify device. Writes this register have effect.
15:0 Description Vendor Identification Number. This 16-bit value assigned Intel. Intel 8086h.
3.3.2
DID-Device Identification Register (Device
Address Offset: Default Value: Attribute: Size: 02-03h 71A0h/71A2h Read Only bits
This 16-bit register combined with Vendor Identification register uniquely identifies device. Writes this register have effect.
Description Device Identification Number. This value assigned 82443GX Host-to-PCI Bridge Function 15:0 71A0h When AGP_DIS (PMCR[1]) =71A0h. 71A2h When AGP_DIS 71A2h.
3-10
82443GX Host Bridge
Register Description
3.3.3
PCICMD-PCI Command Register (Device
Address Offset: Default: Access: Size 04-05h 0006h Read/Write bits
This 16-bit register provides basic control over 82443GX interface ability respond cycles. PCICMD Register enables disables SERR# signal, 82443GX response special cycles, enables disables master accesses main memory.
15:10 Reserved. Fast Back-to-Back. Fast back-to-back cycles different targets implemented 82443GX. Hardwired SERR# Enable (SERRE). Note that this only controls SERR# bus. Device SERRE control error reporting conditions occurred bus. control bits used logical manner control SERR# driver. this 82443GX's SERR# signal driver enabled SERR# asserted when error condition occurs, corresponding enabled ERRCMD register. error status reported ERRSTS PCISTS registers. Also, this 82443GX's parity error reporting enabled PERRE located this register, then 82443GX will report address data parity errors (when potential target). SERR# never driven 82443GX. Address/Data Stepping. implemented (hardwired Parity Error Enable (PERRE). Note that PERR# signal implemented 82443GX. Enable. Address data parity errors reported SERR# mechanism enabled SERRE bit). Disable. Address data parity errors reported 82443GX SERR# signal. (NOTE: Other types error conditions still signaled SERR# mechanism.) NOTE: 82443GX interface still required generate parity even parity error reporting disabled this bit. Reserved. Memory Write Invalidate Enable. 82443GX never uses this command. Hardwired Special Cycle Enable. 82443GX ignores special cycles generated PCI. Hardwired Master Enable (BME). 82443GX does support disabling master capability Bus. Hardwired permitting 82443GX function master. Memory Access Enable (MAE). This enables/disables master access main memory (DRAM). 82443GX always allows master access main memory. Hardwired Access Enable (IOAE). 82443GX does respond cycles. Hardwired Descriptions
82443GX Host Bridge
3-11
Register Description
3.3.4
PCISTS-PCI Status Register (Device
Address Offset: Default Value: Access: Size: 06-07h 0210h/0200h Read Only, Read/Write Clear bits
PCISTS 16-bit status register that reports occurrence master abort target abort bus. PCISTS also indicates DEVSEL# timing that been 82443GX hardware target responses bus. Bits [15:12] read/write clear bits [10:9] read only.
Descriptions Detected Parity Error (DPE). Note that function this affected PERRE bit. PERR# implemented 82443GX. Indicates 82443GX's detection parity error address data phase transactions. Software sets writing this bit. Signaled System Error (SSE). This when 82443GX asserts SERR# enabled error condition under device Software sets writing this bit. Received Master Abort Status (RMAS). Note that Master abort normal expected termination special cycles. When 82443GX terminates transaction (82443GX master) with unexpected master abort, this Software resets this writing Received Target Abort Status (RTAS). When 82443GX-initiated transaction terminated with target abort, RTAS 82443GX also asserts SERR# enabled ERRCMD register. Software resets RTAS writing Signaled Target Abort Status (STAS). 82443GX does generate target abort. Hardwired DEVSEL# Timing (DEVT). This 2-bit field indicates timing DEVSEL# signal when 82443GX responds target PCI, indicates time when valid DEVSEL# sampled initiator cycle. Medium (hardwired Data Parity Detected (DPD). 82443GX does implement PERR# pin. However, data parity errors still detected reported SERR# enabled SERRE PERRE). Hardwired Fast Back-to-Back (FB2B). 82443GX target does support fast back-to-back transactions bus. Hardwired Reserved. Capability List (CLIST). When (PMCR[1]) this When (PMCR[1]) this Reserved.
10:9
3-12
82443GX Host Bridge
Register Description
3.3.5
RID-Revision Identification Register (Device
Address Offset: Default Value: Access: Size: Read Only bits
This register contains revision number 82443GX Function These bits read only writes this register have effect.
Description Revision Identification Number. This 8-bit value that indicates revision identification number 82443GX Function
3.3.6
SUBC-Sub-Class Code Register (Device
Address Offset: Default Value: Access: Size: Read Only bits
This register contains Sub-Class Code 82443GX Function This code indicating Host Bridge device. register read only.
Description Sub-Class Code (SUBC). This 8-bit value that indicates category Bridge into which 82443GX falls. code indicating Host Bridge.
3.3.7
BCC-Base Class Code Register (Device
Address Offset: Default Value: Access: Size: Read Only bits
This register contains Base Class Code 82443GX Function This code indicating Bridge device. This register read only.
Description Base Class Code (BASEC). This 8-bit value that indicates Base Class Code 82443GX. This code value 06h, indicating Bridge device.
82443GX Host Bridge
3-13
Register Description
3.3.8
MLT-Master Latency Timer Register (Device
Address Offset: Default Value: Access: Size: Read/Write bits
This register controls amount time that 82443GX burst data master. MLT[2:0] bits reserved assumed when determining Count Value.
Description Master Latency Timer Count Value Access. 8-bit register that controls amount time 82443GX, master, burst data Bus. default value disables this function. example, programmed 18h, then value clocks. Reserved.
3.3.9
HDR-Header Type Register (Device
Offset: Default: Access: Size: Read Only bits
This register identifies header layout configuration space.
Descriptions Header Type (HEADT). This read only field always returns when read. Writes have affect this field.
3.3.10
APBASE-Aperture Base Configuration Register (Device
Offset: Default: Access: Size: 10-13h 00000008h Read/Write, Read Only bits
APBASE normal Base Address register that used request base Graphics Aperture. normal Configuration mechanism defines base address configuration register such that only fixed amount space requested (dependent which bits hardwired behave hardwired "0"). allow flexibility aperture) additional register called APSIZE used "back-end" register control which bits APBASE will behave hardwired "0". This register will programmed 82443GX specific BIOS code that will before generic configuration software run. Note: NBXCFG register used prevent accesses aperture range before this register initialized configuration software appropriate translation table structure been established main memory.
3-14
82443GX Host Bridge
Register Description
Description Upper Programmable Base Address bits (R/W). These bits used locate range size selected lower bits 27:4. Default 0000b Lower "Hardwired"/Programmable Base Address bits. These bits behave "hardwired" programmable depending contents APSIZE register defined below: Aperture Size
31:28
27:22
Bits 27:22 controlled bits APSIZE register following manner: APSIZE[5]=0 then APBASE[27]=0 APSIZE[5]=1 then APBASE[27]=r/w (read/write). same applies correspondingly other bits. Default APSIZE[5:0]=000000b forces default APBASE[27:22] =000000b (i.e., bits respond "hardwired" This provides default maximum aperture size 82443GX specific BIOS responsible selecting smaller size required) before configuration software runs establishes system address map. 21:4 Hardwired "0". This forces minimum aperture size selected this register 4MB. Prefetchable (RO). This hardwired identify Graphics Aperture range prefetchable i.e., device returns bytes reads regardless byte enables), 82443GX merge processor writes into this range without causing errors. Type (RO). These bits determine addressing type they hardwired "00" indicate that address range defined upper bits this register located anywhere 32-bit address space. Memory Space Indicator (RO). Hardwired identify aperture range memory range.
3.3.11
SVID-Subsystem Vendor Identification Register (Device
Offset: Default: Access: Size:
15:0
2C-2Dh 0000h Read/Write Once bits
Description Subsystem Vendor (R/WO). This value used identify vendor subsystem. default value 00h. This field should programmed during boot-up. After this field written once, becomes read only.
82443GX Host Bridge
3-15
Register Description
3.3.12
SID-Subsystem Identification Register (Device
Offset: Default: Access: Size:
15:0
2E-2Fh 0000h Read/Write Once bits
Description Subsystem (R/WO). This value used identify particular subsystem. default value 00h. This field should programmed during boot-up. After this field written once, becomes read only.
3.3.13
CAPPTR-Capabilities Pointer Register (Device
Offset: Default: Access: Size: A0h/00h Read Only bits
CAPPTR provides offset that pointer location where normal registers located.
Description Pointer start normal register block. When AGP_DIS (PMCR[1]) value this field A0h. When AGP_DIS (PMCR[1]) this field 00h.
3.3.14
NBXCFG-NBX Configuration Register (Device
Offset: Default: Access: Size:
50-53h bits 31-16: 0000h bits 15-0: 00S0-0000-000S-0S00b Read/Write, Read Only strapping options bits
Description SDRAM Without ECC. Bit[n] this array corresponds row[n] SDRAM array. When reading SDRAM (DIMM) which none-ECC, 82443GX drives data lines during first data transfer burst read.
31:24
components populated this row. 82443GX will drive signals. components populated this row. 82443GX will drive lines first read data transferred when this addressed.
23:19
Reserved. Host Fast Data Ready Enable (HBFDRE). Assertion DRAM data host occurs clock after sampling snoop results. (default) Assertion DRAM data host occurs same clock snoop result being sampled. This mode faster clock cycle.
Intel Reserved
3-16
82443GX Host Bridge
Register Description
Description IDSEL_REDIRECT. This programmable option make 82443GX compatible with 430TX base design. initiated configuration cycles PCI, Device which targeted 82443GX's host bridge: When (default), IDSEL1 AD12) allocated this bridge. external AD12 never activated. initiated configuration cycles BUS0, DEVICE7 targeted device that IDSEL input connected IDSEL7 (AD18). When `1', IDSEL7 AD18) allocated this bridge. Since internal 82443GX, external AD18 never activated. initiated configuration cycles BUS0, DEVICE7 targeted device that IDSEL input connected IDSEL1 (AD12). some 430TX based systems, this connected PIIX4E. Note that initiated configuration cycles other buses other devices normally mapped affected.
WSC# Handshake Disable. Uni-Processor mode, this should `1'. DualProcessor mode where external IOAPIC used, this should (default). Setting this `0', enables WSC# handshake mechanism. Intel Reserved. Host/DRAM Frequency. These bits used determine host DRAM frequency. external strapping option reset.
13:12
Reserved Reserved Reserved Access Enable. When PHLDA# active there outstanding passive release transaction pending: this 82443GX allows traffic, this (default) 82443GX blocks traffic. traffic must target bus. Enable =Disable Agent Aperture Access Disable. This used prevent access aperture from side.
Disable Enable (default). this (default) accesses aperture enabled side. Note: This don't care this register Aperture Access Global Enable. This used prevent access aperture from port (CPU, AGP) before aperture range established configuration software appropriate translation table main DRAM been initialized. Default "0". must after system fully configured aperture accesses. Enable. Note that this globally controls accesses aperture. Once enabled, provides next level control accesses originated from side. Disable DRAM Data Integrity Mode (DDIM) (R/W). These bits select DRAM data integrity modes. Non-ECC (Byte-Wise Writes supported) (Default)
EC-only Error Checking with correction Mode (Error Checking/Correction) Mode with hardware scrubbing enabled Diagnostic Mode Enable (EDME) (R/W). Enable. When this 82443GX will enter Diagnostic test mode 82443GX forces MECC[7:0] lines writes memory. During reads, read MECC[7:0] lines compared against internally generated ECC. Recognized errors indicated ERRSTS register normal operation. Normal operation mode (default).
82443GX Host Bridge
3-17
Register Description
Present (MDAP).
Description
This used indicate presence secondary monochrome adapter bus, while primary graphics controller bus. This works conjunction with VGA_EN (Register device follows: VGA_EN MDAP Description cycles sent PCI. master cycles range claimed 82443GX. cycles sent AGP. master writes range claimed 82443GX forwarded bus. cycles sent AGP, except cycles range aliased ranges defined below). master writes range (outside range) claimed 82443GX forwarded AGP. master read/writes range ignored 82443GX.
ranges subset ranges follows: Memory: 0B0000h-0B7FFFh I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh Reserved. USWC Write Post During Bridge Access Enable (UWPIO) (R/W). Enable. Host USWC writes memory posted. Disable. Posting USWC allowed. In-Order Queue Depth (IOQD) (RO). This reflects value sampled deassertion CPURST#. indicates depth Pentium processor in-order queue (i.e., level Pentium processor pipelining). In-order queue maximum. sampled (i.e,. undriven Pentium processor bus), depth Pentium processor in-order queue configured maximum allowed Pentium processor protocol (i.e., However, actual maximum supported 82443GX controlled 82443GX's Pentium processor interface logic using BNR# signaling mechanism. sampled asserted (i.e., "0"). depth Pentium processor in-order queue (i.e., pipelining support Pentium processor bus). NOTE: During reset, driven either 82443GX external source defined strapping option MAB11# pin. Reserved.
3-18
82443GX Host Bridge
Register Description
3.3.15
DRAMC-DRAM Control Register (Device
Address Offset: Default Value: Access: Size:
Reserved. Intel Reserved DRAM Type (DT). This field indicates DRAM type used populate entire array. When SDRAM timings used cycles memory. When timings memory cycles accommodate Registered SDRAMs. registered SDRAM timings, address control lines SDRAMs assumed registered, while memory data bits registered. SDRAM Registered SDRAM cannot mixed within system. Reserved SDRAM Registered SDRAM Reserved NOTE: When PCIRST# assertion occurs during POS/STR, this reset `0'. DRAM Refresh Rate (DRR). DRAM refresh rate adjusted according frequency selected this field. Disabling refresh cycle (000) results eventual loss DRAM data. Changing value will reset refresh request timer. This field used conjunction with SDRAM frequency bits NBXCFG register determine correct load value refresh timer. Refresh Disabled 15.6 31.2 62.4 124.8 Reserved Reserved NOTE: When PCIRST# assertion occurs during POS/STR, this reset `0'.
0000_0000b Read/Write bits
Description
82443GX Host Bridge
3-19
Register Description
3.3.16
PAM[6:0]-Programmable Attribute Registers (Device
Address Offset: Default Value: Attribute: (PAM0) (PAM6) Read/Write
82443GX allows programmable memory attributes Legacy memory segments various sizes address range. Seven Programmable Attribute (PAM) Registers used support these features. Cacheability these areas controlled MTRR registers Pentium processor. bits used specify memory attributes each memory segment. These bits apply both host accesses initiator accesses areas. These attributes are: Read Enable. When host read accesses corresponding memory segment claimed 82443GX directed main memory. Conversely, when host read accesses directed PCI. Write Enable. When host write accesses corresponding memory segment claimed 82443GX directed main memory. Conversely, when host write accesses directed PCI.
attributes permit memory segment Read Only, Write Only, Read/Write, disabled. example, memory segment segment Read Only. Each Register controls regions, typically size. Each these regions 4-bit field. four bits that control each region have same encoding defined Table 3-2. Table 3-2. Attribute Assignment
Bits Reserved Bits Reserved Bits Bits Description Disabled. DRAM disabled accesses directed PCI. 82443GX does respond target read write access this area. Read Only. Reads forwarded DRAM writes forwarded termination. This write protects corresponding memory segment. 82443GX will respond target read accesses write accesses. Write Only. Writes forwarded DRAM reads forwarded termination. 82443GX will respond target write accesses read accesses. Read/Write. This normal operating mode main memory. Both read write cycles from host claimed 82443GX forwarded DRAM. 82443GX will respond target both read write accesses.
example, consider BIOS that implemented expansion bus. During initialization process, BIOS shadowed main memory increase system performance. When BIOS shadowed main memory, should copied same address location. shadow BIOS, attributes that address range should write only. BIOS shadowed first doing read that address. This read forwarded expansion bus.
3-20
82443GX Host Bridge
Register Description
host then does write same address, which directed main memory. After BIOS shadowed, attributes that memory area read only that writes forwarded expansion bus. Table shows registers associated attribute bits: Table 3-3. Registers Associated Memory Segments
PAM0[3:0] PAM0[7:4] PAM1[3:0] PAM1[7:4] PAM2[3:0] PAM2[7:4] PAM3[3:0] PAM3[7:4] PAM4[3:0] PAM4[7:4] PAM5[3:0] PAM5[7:4] PAM6[3:0] PAM6[7:4] Attribute Bits Reserved 0F0000h 0FFFFFh 0C0000h 0C3FFFh 0C4000h 0C7FFFh 0C8000h 0CBFFFh 0CC000h 0CFFFFh 0D0000h 0D3FFFh 0D4000h 0D7FFFh 0D8000h 0DBFFFh 0DC000h 0DFFFFh 0E0000h 0E3FFFh 0E4000h 0E7FFFh 0E8000h 0EBFFFh 0EC000h 0EFFFFh BIOS Area Add-on Add-on Add-on Add-on Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS BIOS Extension BIOS Extension BIOS Extension BIOS Extension Memory Segment Comments Offset
NOTE: C0000h CFFFFh segment used space enabled SMRAM register
Application Area (00000h-9FFFh) area further divided into parts. area 7FFFFh always mapped main memory controlled 82443GX, while address range from 080000 09FFFFh mapped main DRAM. default this range mapped main memory declared main memory hole (accesses forwarded PCI) 82443GX's FDHC configuration register. Video Buffer Area (A0000h-BFFFFh) This area controlled attribute bits. host-initiated cycles this region always forwarded either unless this range accessed mode. Routing accesses controlled Legacy control mechanism "virtual" PCI-to-PCI bridge device embedded within 82443GX. This area programmed area SMRAM register. When used space this range accessed from AGP. Expansion Area (C0000h-DFFFFh) This area divided into eight segments which assigned with different attributes control register defined Table 3-3. Extended System BIOS Area (E0000h-EFFFFh) This area divided into four segments which assigned with different attributes control register defined Table 3-3. System BIOS Area (F0000h-FFFFFh) This area single segment which assigned with different attributes control register defined Table 3-3.
82443GX Host Bridge
3-21
Register Description
3.3.17
DRB[0:7]-DRAM Boundary Registers (Device
Address Offset: Default Value: Access: Size: (DRB0) (DRB7) Read/Write bits/register
82443GX supports physical rows DRAM. width bits. DRAM Boundary Registers define upper lower addresses each DRAM row. Contents these 8-bit registers represent boundary addresses granularity. example, value indicates DRB0 Total memory row0 DRB1 Total memory row0 row1 DRB2 Total memory row0 row1 row2 DRB3 Total memory row0 row1 row2 row3 DRB4 Total memory row0 row1 row2 row3 row4 DRB5 Total memory row0 row1 row2 row3 row4 row5 DRB6 Total memory row0 row1 row2 row3 row4 row5 row6 DRB7 Total memory row0 row1 row2 row3 row4 row5 row6 row7
DRAM array configured with single double-sided DIMMs using parts listed Table 4-9. array also supports width DRAM components registered DIMMs. Each register defines address range that will cause particular line asserted (e.g., first DRAM minus then accesses within MByte range will cause CSx0#/ RASx0# asserted). DRAM Boundary (DRB) Registers programmed with 8bit upper address limit value. This upper address limit compared bits [30:23] requested address, each row, determine DRAM being targeted. specify memory size DRB7 must 00h. When this value set, 82443GX internally detects this value sets internal system memory size" signal. cleared otherwise. Note: DRBx Decoding. ability detect total system memory possible DRB7 only. possible, however, achieve memory lower DRAM rows when some populated rows each. total memory size DRBx, where x<7, then BIOS must DBRx 0FFh total memory available minus following rows (from 0FFh. DRAM selected only address[31:30] zero.
Description Boundary Address. This 8-bit value compared against address lines A[30:23] determine upper address limit particular (i.e., minus previous size). NOTE: When PCIRST# assertion occurs during POS/STR, these bits reset 01h.
Note:
3-22
82443GX Host Bridge
Register Description
Boundary Address These values represent upper address limits eight rows (i.e., this minus previous size). Unpopulated rows have value equal previous (row size DRB7 reflects maximum amount DRAM system. memory determined value written into DRB7. Note: 82443GX supports maximum DRAM. example general purpose configuration where eight physical rows configured either single-sided double-sided DIMMs, memory array would configured like shown Figure 3-2. this configuration, 82443GX drives eight signals directly DIMM rows. single-sided DIMMs populated, even signals used CS#s connected. double-sided DIMMs used, four signals used DIMM. Figure 3-2. SDRAM DIMMs Corresponding Registers
CSA7#/CSB7# CSA6#/CSB6# CSA5#/CSB5# CSA4#/CSB4# CSA3#/CSB3# CSA2#/CSB2# CSA1#/CSB1# CSA0#/CSB0# DIMM3 Back DIMM3 Front DIMM2 Back DIMM2 Front DIMM1 Back DIMM1 Front DIMM0 Back DIMM0 Front DRB7 DRB6 DRB5 DRB4 DRB3 DRB2 DRB1 DRB0
following examples describe Registers programmed cases singlesided double-sided DIMMs motherboard. Example Single-sided DIMMs Assume total DRAM required using single-sided DIMMs. this configuration, DIMMs required. DRB0 DRB1 DRB2 DRB3 DRB4 DRB5 DRB6 DRB7 populated DIMM, Mbyte this row) empty populated DIMM, Mbyte this row) empty empty empty empty empty
82443GX Host Bridge
3-23
Register Description
Example Mixed Single-/Double-sided DIMMs another example, consider system that initially shipped with memory using DIMM that rest memory array should upgradable maximum supported memory This handled further populating array with single-sided DIMM (one row) double-sided DIMM (two rows), yielding total DRAM. Registers programmed follows: DRB0 DRB1 DRB2 DRB3 DRB4 DRB5 DRB6 DRB7 populated with 8MB, single-sided DIMM empty populated with DIMM populated with other DIMM populated with single-sided DIMM empty empty empty
3.3.18
FDHC-Fixed DRAM Hole Control Register (Device
Address Offset: Default Value: Access: Size: Read/Write bits
This 8-bit register controls fixed DRAM holes:
Description Hole Enable (HEN). This field enables memory hole DRAM space. Host cycles matching enabled hole passed PCI. cycles matching enabled hole will ignored 82443GX DEVSEL#). NOTE: selected hole remapped. None KB-640 (128 bytes) byte) Reserved Reserved.
3.3.19
MBSC-Memory Buffer Strength Control Register (Device
Address Offset: Default Value: Access: Size: 69-6Eh 000000000000h Read/Write bits
This register programs various DRAM interface signal buffer strengths, based non-mixed memory configurations DRAM type (SDRAM Registered SDRAM), DRAM density (x4, x16), DRAM technology (16Mbit, 64Mbit, 128Mbit, 256Mbit1), rows populated. Note that DRAM only supported when used registered DIMMs.
Proper operation 82443GX AGPset with 256-Mbit SDRAM devices been verified. Intel's current plans validate this feature second half 1998 when 256-Mbit SDRAM devices available.
3-24
82443GX Host Bridge
Register Description
47:40 Reserved
Description
39:38
MAA[14:0], WEA#, SRASA#, SCASA# Buffer Strengths. This field sets buffer strength MAA[14:0], WEA#, SRASA#, SCASA# pins. Reserved (Invalid setting) MAB[12:11, 9:0]# MAB[14,13,10], WEB#, SRASB#, SCASB# Buffer Strengths. This field sets buffer strength MAB[12:11, 9:0]# MAB[14,13,10], WEB#, SRASB#, SCASB# pins. Note that address's MAB# inverted copies MAA, with exception MAB[14,13,10]. Reserved (Invalid setting) [63:0] Buffer Strength Control DIMM Configuration: This field sets buffer strength MD[63:0] path that connected DIMM2 DIMM3. buffer strength programmable based SDRAM load detected DIMM slots This path enabled when FENA asserted (High) 82443GX. DIMM non-FET Configuration: This field should programmed same value MD[63:0] Buffer Strength Control This buffer strength programmable based upon SDRAM load detected DIMM connectors. Reserved (Invalid setting) [63:0] Buffer Strength Control DIMM Configuration: This field sets buffer strength MD[63:0] path that connected DIMM0 DIMM1. buffer strength programmable based upon SDRAM load detected DIMM slots This path enabled when FENA asserted (Low) 82443GX. DIMM non-FET Configurations: buffer strength programmable based upon SDRAM load detected DIMM connectors. Reserved (Invalid setting) MECC [7:0] Buffer Strength Control DIMM Configuration: This field sets buffer strength MECC[7:0] path that connected DIMM2 DIMM3 buffer strength programmable based upon SDRAM load detected DIMM slots This path enabled when FENA deasserted (High) 82443GX. DIMM non-FET Configurations: This field should programmed same value MECC[7:0] Buffer Strength Control This buffer strength programmable based upon SDRAM load detected DIMM connectors. Reserved (Invalid setting)
37:36
35:34
33:32
31:30
82443GX Host Bridge
3-25
Register Description
Description MECC [7:0] Buffer Strength Control DIMM Configuration: This field sets buffer strength MECC[7:0] path that connected DIMM0 DIMM1. buffer strength programmable based upon SDRAM load detected DIMM slots This path enabled when FENA deasserted (High) 82443GX. DIMM non-FET Configuration: buffer strength programmable based upon SDRAM load detected DIMM slots. Reserved (Invalid setting) CSB7# Buffer Strength. This field sets buffer strength CSB7# pins. Reserved (Invalid setting) CSA7# Buffer Strength. This field sets buffer strength CSA7# pins. Reserved (Invalid setting) CSB6# Buffer Strength. This field sets buffer strength CSB6# pins. Reserved (Invalid setting) CSA6# Buffer Strength. This field sets buffer strength CSA6#pins. Reserved (Invalid setting) CSA5#/, CSB5# Buffer Strength. This field sets buffer strength CSA5#, CSB5# pins. CSA4#, CSB4# Buffer Strength. This field sets buffer strength CSA4#, CSB4# pins. CSA3#, CSB3# Buffer Strength. This field sets buffer strength CSA3#, CSB3# pins. CSA2#, CSB2# Buffer Strength. This field sets buffer strength CSA2#, CSB2# pins. CSA1#, CSB1# Buffer Strength. This field sets buffer strength CSA1#, CSB1# pins. CSA0#, CSB0# Buffer Strength. This field sets buffer strength CSA0#, CSB0# pins.
29:28
27:26
25:24
23:22
21:20
3-26
82443GX Host Bridge
Register Description
Description DQMA5 Buffer Strength. This field sets buffer strength DQMA5 pins. Reserved (Invalid setting) Reserved (Invalid setting) DQMA1 Buffer Strength. This field sets buffer strength DQMA1 pin. Reserved (Invalid setting) DQMB5 Buffer Strength. This field sets buffer strength DQMB5 pin. Reserved (Invalid setting) Reserved (Invalid setting) DQMB1 Buffer Strength. This field sets buffer strength DQMB1 pin. Reserved (Invalid setting) Reserved (Invalid setting) DQMA[7:6,4:2,0] Buffer Strength. This field sets buffer strength DQMA[7:6,4:2,0] pins. Reserved (Invalid setting) GCKE Buffer Strength. This field sets buffer strength GCKE pin. Reserved (Invalid setting) Reserved (Invalid setting) Reserved (Invalid setting) FENA Buffer Strength. This field sets buffer strength FENA pin. Reserved (Invalid setting) Reserved (Invalid setting)
13:12
11:10
82443GX Host Bridge
3-27
Register Description
3.3.20
SMRAM-System Management Control Register (Device
Address Offset: Default Value: Access: Size: Read/Write bits
SMRAMC register controls accesses Compatible Extended SMRAM spaces treated. Open, Close, Lock bits function only when G_SMRAME Also, OPEN must reset before LOCK set.
Reserved Space Open (D_OPEN). When D_OPEN=1 D_LCK=0, space DRAM made visible even when decode active. This intended help BIOS initialize space. Software should ensure that D_OPEN=1 D_CLS=1 same time. When D_LCK D_OPEN reset becomes read only. Space Closed (D_CLS). When D_CLS space DRAM accessible data references, even decode active. Code references still access space DRAM. This will allow software reference "through" space update display even when mapped over range. Software should ensure that D_OPEN=1 D_CLS=1 same time. Space Locked (D_LCK). When D_LCK then D_OPEN reset D_LCK, D_OPEN, H_SMRAM_EN, TSEG_SZ, TSEG_EN DRB7 become read only. D_LCK normal configuration space write only cleared power-on reset. combination D_LCK D_OPEN provide convenience with security. BIOS D_OPEN function initialize space then D_LCK "lock down" space future that application software BIOS itself) violate integrity space, even program knowledge D_OPEN function. Global SMRAM Enable (G_SMRAME). G_SMRAME H_SMRAM_EN then Compatible SMRAM functions enabled, providing DRAM accessible A0000h address while (ADS# with decode). enable Extended SMRAM function this Refer section more details. Once D_LCK set, this becomes read only. Compatible Space Base Segment (C_BASE_SEG) (RO). This field programs location space. "SMM DRAM" remapped. simply "made visible" conditions right access space, otherwise access forwarded PCI. Hardwired indicate that 82443GX supports space A0000h-BFFFFh. Description
3-28
82443GX Host Bridge
Register Description
3.3.21
ESMRAMC-Extended System Management Control Register (Device
Address Offset: Default Value: Access: Size: Read/Write bits
Extended SMRAM register controls configuration Extended SMRAM space. Extended SMRAM (E_SMRAM) memory provides write-back cacheable SMRAM memory space that above Mbyte. Description
H_SMRAM_EN (H_SMRAME). Controls memory space location (i.e above Mbyte below Mbyte). When G_SMRAME SMRAME High SMRAM memory space enabled, Compatible SMRAM memory disabled, accesses 0A0000h 0FFFFFh range forwarded PCI, while SMRAM accesses from 100A0000h 100FFFFFh remapped DRAM address A0000h FFFFFh When SMRAME SMRAM then Compatible SMRAM space enabled. Once D_LCK set, this becomes read only. E_SMRAM_ERR (E_SMERR). This when accesses defined memory ranges Extended SMRAM (High Memory T-segment) while space with D-OPEN software's responsibility clear this bit. software must write this clear SMRAM_Cache (SM_CACHE). This forced 82443GX. SMRAM_L1_EN (SM_L1). This forced 82443GX. SMRAM_L2_EN (SM_L2). This forced 82443GX. TSEG_SZ[1:0] (T_SZ). Selects size TSEG memory block, enabled. This memory taken from DRAM space (i.e., TSEG_SZ), which longer claimed memory controller (all accesses this space sent TSEG_EN set). physical address extended SMRAM memory appears from (256M TSEG_SZ) (256M TOM). This address remapped DRAM address (TOM TSEG_SZ) TOM. This field decodes follows: (TOM-128KB) (TOM-256KB) (TOM-512KB) (TOM-1MB) Once D_LCK set, this becomes read only. TSEG_EN (T_EN). Enabling SMRAM memory (TSEG, additional SMRAM memory) Extended SMRAM space only. When G_SMRAME TSEG_EN TSEG enabled appear appropriate physical address space. Once D_LCK set, this becomes read only.
82443GX Host Bridge
3-29
Register Description
3.3.22
RPS-SDRAM Page Size Register (Device
Address Offset: Default Value: Access: Size: 74h-75h 0000h Read/Write bits
This register sets page size SDRAM.
Description Page Size (PS). Each pair bits this register indicate page size used DRAM. encoding fields. Bits[1:0] 15:0 bits 11:10 13:12 15:14 Page Size Reserved Corresponding register DRB[0], DRB[1], DRB[2], DRB[3], DRB[4], DRB[5], DRB[6], DRB[7],
3-30
82443GX Host Bridge
Register Description
3.3.23
SDRAMC-SDRAM Control Register (Device
Address Offset: Default Value: Access: Size:
15:8 Reserved SDRAM Mode Select (SMS). These bits allow 82443GX drive various commands SDRAMs. These special modes intended initialization power Mode Normal SDRAM Operation. (default) Command Enable. this mode cycles SDRAM result Command SDRAM interface. Banks Precharge Enable. this mode cycles SDRAM result Banks Precharge Command SDRAM interface. Mode Register Enable. this mode cycles SDRAM result mode register command SDRAM interface. command driven MAx[14:0] lines. MAx[2:0] must always driven burst mode. must driven interleave wrap type. MAx4 needs driven value programmed CAS# Latency bit. MAx[6:5] should always driven MAx[12:7] must driven 000000. BIOS must calculate drive correct host address each memory such that correct command driven MAx[12:0] lines. Enable. this mode cycles SDRAM result cycle SDRAM interface. Reserved. Reserved. Reserved.
76h-77h Read/Write bits
Description
Note: BIOS must take into consideration inversion when programming DIMM slots SDRAMPWR. Reserved SDRAMPWR should `1'. Note: When PCIRST# assertion occurs during POS/STR, these bits reset Leadoff Command Timing (LCT). These bits control when SDRAM command pins (SRASx#, SCASx# WEx#) CSx# considered valid leadoffs cycles. Clock Clock Note: platforms, BIOS should leave default value CAS# Latency (CL). This controls number CLKs between when read command sampled SDRAMs when 82443GX samples read data from SDRAMs. given populated with registered SDRAM DIMM, extra clock inserted between read command when 82443GX samples read data. registered DIMM with CL=2, this should DCLK CAS# latency. DCLK CAS# latency. SDRAM RAS# CAS# Delay (SRCD). This controls number DCLKs from Activate command read write command. clocks will inserted between activate command either read write command. clocks will inserted between activate either read write command. SDRAM RAS# Precharge (SRP). This controls number DCLKs RAS# precharge. clocks RAS# precharge. clocks RAS# precharge.
82443GX Host Bridge
3-31
Register Description
3.3.24
PGPOL-Paging Policy Register (Device
Address Offset: Default Value: Access: Size:
78-79h 0000h Read/Write bits
Description
15:8
Banks (BPR). Each this field corresponds memory array. corresponds while corresponds These bits defined only SDRAM systems define whether corresponding bank implementation four bank implementation. Those with banks (bit=0) have pages open given time. Those with four banks (bit=1) have four pages open time. Note that bits referencing empty rows `don't care'. banks banks
Reserved. Intel Reserved. DRAM Idle Timer (DIT). This field determines number clocks that DRAM controller will remain idle state before precharging pages. 0000 clocks 0001 clocks 0010 clocks
0011 clocks 0100 clocks 0101 clocks 0110 clocks 0111 clocks 1XXX Infinite (pages closed idle condition).
3-32
82443GX Host Bridge
Register Description
3.3.25
PMCR-Power Management Control Register (Device
Address Offset: Default Value: Access Size
Intel Reserved ACPI Control Register Enable (SCRE). Enable. ACPI control register 82443GX enabled, cycles address 0022h handled 82443GX forwarded PCI. Disable (default). cycles address 0022h passed bus. Intel Reserved Normal Refresh Enable (NREF_EN). This used enable normal refresh operation following POS/STR state. After coming reset software must this before doing access memory. Enable Disable Intel Reserved Gated Clock Enable (GCLKEN). GCLKEN enables internal dynamic clock gating 82443GX when AGPset "IDLE" state occurs. This happens when 82443GX detects idle state buses. Enable Disable Disable (AGP_DIS). This register Read Only configuration write ignored. Disable. interface clocks associated logic permanently disabled. This mode entered using strapping option that sampled 82443GX during reset. Enable reset without PCIRST enable (CRst_En). This enables 82443GX assert reset without incoming PCIRST#. This option allows reset processor when system coming state. Defaults upon PCIRST# assertion. Enable Disable NOTE: When PCIRST# assertion occurs during POS/STR, this reset `0'.
0000_S0S0b Read/Write Bits
Description
82443GX Host Bridge
3-33
Register Description
3.3.26
SCRR-Suspend Refresh Rate Register (Device
Address Offset: Default Value: Access Size
15:13 Reserved. Suspend refresh Rate Auto Adjust Enable (SRRAEN). SRRAEN cleared default during cold reset only. affected PCIRST# during resume from suspend. Disable (default). Indicates that suspend refresh rate updated 82443GX hardware track system operating conditions. this case, expected that BIOS will reflect worst case operating conditions that minimum refresh rate will provided. Enable. Indicates that 82443GX hardware adjusts suspend refresh rate according system operating conditions comparing number OSCCLKs given time. This mode allows system dynamically adjust refresh rate thus minimize suspend power consumption while guaranteeing required refresh rate. Suspend Refresh Rate (SRR). rate loaded into counter which counts down OSCCLK rising edges. When expires, suspend refresh request triggered. This field loaded BIOS reflect desirable refresh rate. addition, 82443GX will update automatically, when above SRRAEN either case, register accessible read write operation times. 11:0 This 12-bit field provides dynamic range greater than maximum refresh rate that supported 249.6uSEC. field cleared default during cold reset only. affected PCIRST# during resume from suspend. default value this register 038h, decimal. represents 15.5uS time between refreshes with slowest corner OSCCLK cycle time 270nS.
7Bh-7Ch 0038h Read/Write Bits
Description
3.3.27
EAP-Error Address Pointer Register (Device
Address Offset: Default Value: Access Size
80-83h 00000000h Read Only, Read/Write-Clear Bits
Description
31:12
Error Address Pointer (EAP) (RO). This field used store block main memory which error (single multi-bit error) occurred. Note that this field represents address first error occurrence after bits have been cleared software. Once bits value different than 00b, result error, this field locked doesn't change result error. Reserved. Multiple Error (MBE) (R/WC). This indicates that multi-bit error occurred, address been logged bits 31:12. register locked until clears this writing Software uses bits detect whether logged error address Single Multi error, since both Single Multiple Error bits Error Status register set. Once software completes error processing, value written this field clear value (back unlock error logging mechanism. Note: errors received during initialization should ignored. Single Error (SBE) (R/WC). Indicates that single error occurred, address been logged bits 31:12. register locked until clears this writing Note: errors received during initialization should ignored.
11:2
3-34
82443GX Host Bridge
Register Description
3.3.28
ERRCMD-Error Command Register (Device
Address Offset: Default Value: Access: Size: Read/Write bits
This 8-bit register controls 82443GX responses various system errors. actual assertion SERR# enabled Command register.
Description SERR# Non-Snoopable Access Outside Graphics Aperture. When enabled ERRSTS registers transitions from (during access address outside graphics aperture) then SERR# assertion event will generated. Enable (default). Disable. SERR# Invalid DRAM Access. non-snoopable READ accesses locations outside graphics aperture outside main DRAM range (i.e., range above memory) invalid. When this set, ERRSTS will SERR# will asserted, read accesses directed main memory aperture range. Enable. Disable reporting this condition SERR#. SERR# Access Invalid Graphics Aperture Translation Table Entry. When enabled, 82443GX sets ERRSTS asserts SERR# following read write access invalid entry Graphics Aperture Translation Table residing main memory. Enable. Disable reporting this condition SERR#. SERR# Receiving Target Abort. Enable. 82443GX asserts SERR# receiving target abort either Disable. 82443GX does assert SERR# receipt target abort. SERR# Detected Thermal Throttling Condition. Enable. 82443GX asserts SERR# when thermal throttling condition detected either read write function. 82443GX does assert SERR# thermal throttling. SERR# Assertion Mode. SERR# level mode signal. Systems that connect SERR# EXTSMI# error reporting should this SERR# asserted clock (normal mode). (default) SERR# Receiving Multiple-Bit ECC/Parity Error. When enabled, 82443GX asserts SERR# when detects multiple-bit error reported DRAM controller. systems supporting this must disabled. Enable. Disable. Note: errors received during initialization should ignored. SERR# Receiving Single-bit Error. When enabled, 82443GX asserts SERR# when detects single-bit error. systems supporting ECC, this must disabled. Enable. Disable. Note: errors received during initialization should ignored.
82443GX Host Bridge
3-35
Register Description
3.3.29
ERRSTS-Error Status Register (Device
Address Offset: Default Value: Access: Size: 91-92h 0000h Read Only, Read/Write Clear bits
This 16-bit register used report error conditions SERR# mechanism. SERR# generated zero transition these flags enabled ERRCMD register).
15:13 Reserved. Read thermal Throttling Condition. Read thermal throttling condition occurred. Software writes clear this bit. Default=0 Write Thermal Throttling Condition. Write thermal throttling condition occurred. Software writes clear this bit. Default=0 non-snoopable access outside Graphics Aperture. access occurred address that outside graphics aperture range. Software writes clear this bit. Default=0 Invalid non-snoopable DRAM read access (R/WC). non-snoopable READ access attempted outside graphics aperture outside main memory (i.e,. range above memory). Software must write clear this status bit. Access Invalid Graphics Aperture Translation Table Entry (AIGATT) (R\WC). invalid translation table entry returned response graphics aperture read write access. Software must write clear this bit. Multi-bit First Error (MBFRE) (RO). This field contains encoded value DRAM which first multi-bit error occurred. simple binary encoding used indicate containing multi-bit error. When error detected, this field updated set. This field will then locked further updates) until flag been reset. value this field undefined. Multiple-bit (uncorrectable) Error Flag (MEF) (R/WC). Memory data transfer uncorrectable error(i.e., multiple-bit error). When enabled, multiple error reported DRAM controller propagated SERR# pin, enabled ERRCMD register. BIOS writes clear this unlock MBFRE field. (Default Single-bit First Error (SBFRE) (RO). This field contains encoded value DRAM which first single-bit error occurred. simple binary encoding used indicate containing single-bit error. When error detected, this field updated set. This field then locked further updates) until flag been reset. value this field undefined. Single-bit (correctable) Error Flag (SEF) (R/WC). Memory data transfer single-bit correctable error corrected data sent access. When enabled, single error reported propagated SERR# pin, enabled ERRCMD register. BIOS writes clear this unlock SBFRE field. Description
3-36
82443GX Host Bridge
Register Description
3.3.30
ACAPID-AGP Capability Identifier Register (Device
Address Offset: Default Value: Access: Size: A0-A3h 00100002h/00000000h Read Only bits
This register provides normal identifier capability.
31:24 Reserved Major Revision Number. This field provides major revision number specification which this version 82443GX conforms. When (PMCR[1]) this number value "0001b" (i.e., implying 1.x). When (PMCR[1]) This number "0000b". Minor Revision Number. These bits provide minor revision number specification which this version 82443GX conforms. This number hardwired value "0000" (i.e., implying x.0). Together with major revision number this field identifies 82443GX compliant device. Next Capability Pointer. capability first last capability described capability pointer mechanism. Hardwired indicate capability linked list. Capability This field identifies linked list item containing registers. When (PMCR[1]) this field value 0000_0010b assigned SIG. When (PMCR[1]) this field value 00h. Description
23:20
19:16
15:8
3.3.31
AGPSTAT-AGP Status Register (Device
Address Offset: Default Value: Access: Size: A4-A7h 1F000203h Read Only bits
This register reports compliant device capability/status.
31:24 23:10 Description Maximum Request Queue Depth (RO). This field hardwired indicate maximum outstanding command requests handled 82443GX. Reserved Side Band Addressing Supported. This indicates that 82443GX supports side band addressing. hardwired Reserved Data Transfer Type Supported (R/W). identifies compliant device supports data transfer mode identifies compliant device supports data transfer mode. Configuration software will update this field setting only that corresponds capability master (after that capability been verified accessing same functional register within masters configuration space). allowed data transfer mode supported data transfer mode supported (default) NOTE: selected data transfer mode apply both bus.
82443GX Host Bridge
3-37
Register Description
3.3.32
AGPCMD-AGP Command Register (Device
Address Offset: Default Value: Access: Size: A8-ABh 00000000h Read/Write bits
This register provides control operational parameters.
31:10 Reserved. Side Band Enable. This enables side band addressing mechanism. Enable. Disable. Enable. When disabled, 82443GX ignores operations, including sync cycle. operations received while this serviced even this reset this transitions from clock edge middle command being delivered mode command will issued. When this 82443GX will respond operations delivered PIPE#, operations delivered Side Band Enable also parameters AGPCMD AGPCTRL registers must prior setting this `1'. With exception GTLB_ENABLE (bit AGPCTRL), ATTBASE register (offset B8h), which modified dynamically. Enable. Disable. Reserved. Data Transfer Rate. (and only one) this field must indicate desired data transfer rate (Bit 2X). same must both master target. Configuration software will update this field setting only that corresponds capability master (after that capability been verified accessing same functional register within masters configuration space.) default data transfer rate. data transfer rate. Illegal NOTE: This field applies buses. Description
3-38
82443GX Host Bridge
Register Description
3.3.33
AGPCTRL-AGP Control Register (Device
Address Offset: Default Value: Access: Size: B0-B3h 00000000h Read/Write bits
This register provides additional control interface.
31:16 Reserved. Snoopable Writes Order With Reads Disable (AGPDCD). When (default), 82443GX maintains ordering between snoopable write cycles reads. When 82443GX handles reads snoopable writes independent streams. AGPDCD (Bit Reserved Graphics Aperture Write-AGP Read Synchronization Enable (AGPRSE). When this 82443GX will ensure that writes posted Global Write Buffer Graphics Aperture retired DRAM before 82443GX will initiate CPU-to-AGP cycle. This used ensure synchronization between master. AGPDCD description defines interaction between AGPRSE AGPDCD bit. Enable Disable (Default) 12:8 Reserved GTLB Enable (and GTLB Flush Control). Enable. Normal operations Graphics Translation Lookaside Buffer. Disable (default). GTLB flushed clearing valid bits associated with each entry. Reserved. AGPRSE (Bit Description visible reads. flushes only when address hit. Illegal. Illegal flushes when write occurs Description
82443GX Host Bridge
3-39
Register Description
3.3.34
APSIZE-Aperture Size Register (Device
Address Offset: Default Value: Access: Size: Read/Write bits
This register determines effective size Graphics Aperture used particular 82443GX configuration. This register updated 82443GX-specific BIOS configuration sequence before normal enumeration sequence takes place. register updated, default value selects aperture maximum size (i.e., MB). size table that will correspond aperture practical most applications and, therefore, these bits must programmed smaller practical value that forces adequate address range requested APBASE register from configuration software.
Reserved. Graphics Aperture Size (APSIZE) (R/W). Each APSIZE[5:0] operates similarly ordered bits APBASE[27:22] Aperture Base configuration register. When particular this field "0", forces similarly ordered APBASE[27:22] behave "hardwired" When particular this field "1", allows corresponding APBASE[27:22] read/ write accessible. Only following combinations allowed: 1111 1110 1100 1000 0000 0000 0000 256MB Default APSIZE[5:0]=000000b forces default APBASE[27:22] =000000b (i.e., bits respond "hardwired" This provides maximum aperture size another example, programming APSIZE[5:0]=111000b hardwires APBASE[24:22]=000b while enabling APBASE[27:25] read/write programmable. Description
3.3.35
ATTBASE-Aperture Translation Table Base Register (Device
Address Offset: Default Value: Access: Size: B8-BBh 00000000h Read/Write bits
This register provides starting address Graphics Aperture Translation Table base located main DRAM. ATTBASE register dynamically changed. Note: address provided ATTBASE aligned.
31:12 11:0 Description Aperture Translation Table Base Address. Bits 31:12 correspond address bits 31:12, respectively. This field contains pointer base translation table used memory space addresses aperture range addresses main memory. Reserved.
3-40
82443GX Host Bridge
Register Description
3.3.36
MBFS-Memory Buffer Frequency Select Register (Device
Address Offset: Default Value: Access: Size: CA-CCh 000000h Read/Write bits
settings this register enable buffers each following signal groups.
Reserved MAA[14:0], WEA#, SRASA#, SCASA#. This enables buffers MAA[14:0], WEA#, SRASA#, SCASA#. Reserved MAB[12:11, 9:0]# MAB[14,13,10], WEB#, SRASB#, SCASB#. This enables buffers MAB[12:11, 9:0]# MAB[14,13,10], WEB#, SRASB#, SCASB#. Note that address's MABx# inverted copies MAA, with exception MAB[14,13,10]. Reserved [63:0] [Control 2]). This enables buffers [63:0] [Control (Refer corresponding MBSC register programming details). Reserved [63:0] [Control This enables buffers [63:0] [Control (Refer corresponding MBSC register programming details). MECC [7:0] [Control This enables buffers MECC [7:0] [Control (Refer corresponding MBSC register programming details). MECC [7:0] [Control This enables buffers MECC [7:0] [Control (Refer corresponding MBSC register programming details). Reserved CSB7#. This enables buffers CSB7#. Reserved CSA7#. This enables buffers CSA7#. Reserved CSB6#. This enables buffers CSB6#. Reserved CSA6#. This enables buffers CSA6#.
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