NSBMC096-16 Burst Memory Controller NSBMC096 Burst Memory Control

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NSBMC096-16 Burst Memory Controller NSBMC096 Burst Memory Control

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NSBMC096-16 Burst Memory Controller
NSBMC096-16 Burst Memory Controller
NSBMC096 Burst Memory Controller integrated circuit which implements aspects DRAM control high performance systems using i960 SuperScalar Embedded Processor NSBMC096 functionally equivalent V96BMC extremely high instruction rate achieved these processors place extraordinary demands memory system design maximum throughput sustained costs minimized Static offers simple solution high speed memory systems However high cost density make this expensive space consumptive choice Dynamic RAMs attractive alternative with higher density cost Their drawbacks slower access time more complex control circuitry required operate them access time problem solved DRAMs used page mode this mode access times rival that static control circuit problem resolved NSBMC096 function that NSBMC096 performs optimally translate burst access protocol i960 page mode access protocol supported dynamic RAMs device manages two-way interleaved arrangements DRAMs such that during burst access data read written rate word system clock cycle NSBMC096 been designed allow maximum flexibility application full range processor speeds supported wide range DRAM speeds sizes organizations glue logic required because interface customized i960 System integration further enhanced providing 24-bit heartbeat timer watch timer on-chip NSBMC096 packaged 132-pin PQFP with footprint only square inches reduces design complexity space requirements fully derated loading temperature voltage
Features
Interfaces directly i960 Integrated Page Cache Management Manages Page Mode Dynamic Memory devices On-chip Memory Address Multiplexer Drivers Supports DRAMs trom counter timer Non-interleaved interleaved operation 5-Bit Watch Timer Software-configured operational parameters High-Speed Power CMOS technology
Block Diagram
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This document contains information concerning product that been developed National Semiconductor Corporation Corporation This information intended help evaluating this product National Semiconductor Corporation Corporation reserves right change improve specifications this product without notice
TRI-STATE registered trademark National Semiconductor Corporation NSBMC096and WATCHDOGare trademarks National Semiconductor Corporation i960 registered trademark Intel Corporation V96BMCis trademark Corporation C1995 National Semiconductor Corporation 11805 RRD-B30M115 Printed
Logic Connection Diagrams
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Order Number NSBMC096VF Package Number VF132A
Descriptions
TABLE Signal Name PCLK BERR BLAST BTERM READY REFRESH Signal Name AA10 AA11 CASA0 CASA1 CASA2 CASA3 RASA0 RASA1 RASA2 RASA3 MWEA Signal Name AB10 AB11 CASB0 CASB1 CASB2 CASB3 RASB0 RASB1 RASB2 RASB3 MWEB RESET
Note order switching characteristics this device guaranteed necessary connect power pins (VCC VSS) appropriate power levels impedance wiring power pins required systems using i960 with attendant high switching rates multi-layer printed circuit boards with buried power ground planes required
Descriptions (Continued)
i960 INTERFACE following pins functionally equivalent those i960 from which their names taken Like named pins i960 NSBMC960 wired together 3-State outputs weakly pulled typical situations resistor sufficient
Description Address (Input) This system word address which determines location which access required Address Strobe (Input Active Low) Indicates that access cycle being started Data Code (Input) Signals whether access data instructions
BLAST BTERM READY RESET
Burst Last (Input Active Low) Indicates that last cycle burst progress Data Enable (Input Active Low) This input monitored Watch Timer detect access returning READY Burst Terminate (Output 3-State Active Low) This output used request termination burst progress Used disable burst writes Data Ready (Output 3-State Active Low) READY output used signal that data processor valid Read that data been accepted Write Reset (Input Active Low) Assertion this input sets NSBMC960 initial state Following initialization NSBMC960 must configured before memory access possible Byte Enable (Input Active Low) These inputs used determine which byte(s) within addressed word accessed WRITE READ (Input) This input indicates direction which data transferred from data Supervisor (Input Active Low) Indicates that processor operating supervisor mode Required access configuration registers System Clock (Input) Processor output clock required operate synchronize NSBMC960 internal functions Error (Output Active Low) When enabled this signal generated Watch Circuit prevent processor lock-up access region that responding Interrupt (Output Active Low) This signal assented when 24-bit counter reaches terminal count interrupt enabled programmed pulse handshake operation Chip (Input) These inputs select address offset NSBMC960 configuration registers Each NSBMC960 system must have unique address proper operation
PCLK BERR
Descriptions (Continued)
MEMORY INTERFACE NSBMC960 designed drive memory array organized leaves each bits address control signals memory array output through high current drivers order minimize propagation delay input impedance trace capacitance External array drivers required address control signals however should externally terminated Description Multiplexed Address (Output These buses transfer multiplexed column addresses memory array leaves When non-interleaved operation selected only address should used Address Strobes (Output Active Low) These strobes indicate presence valid address busses B)0-11 These signals connected each leaf memory Four banks interleaved memory attached NSBMC960 Column Address Strobe (Output Active Low) These strobes latch column address from They assigned each byte leaf Memory Write Enable (Output Active Low) These DRAM write strobes supplied each leaf minimize signal loading Refresh progress (Output Active Low) This output gives notice that refresh cycle executed timing leads refresh cycle Multiple operating modes facilitate choice buffer type simple buffers (``245''s) latches (``543''s) registers (``646''s) supported Description Data Transmit (Output Active Low) These outputs multi-function signals signal names they appear logic symbol default signal names (Mode purpose these outputs control buffer output enables during data read transactions effect control multiplexing data from each memory leaf onto i960 data Data Latch Enable (Output Active Low) These outputs mode independent however timing signals change different operational modes They control transparent latches that hold data transmiffed during write transaction modes latch controls follow timing each leaf while modes timing shortened clock
RAS(A B)0-3
CAS(A B)0-3 MWE(A REFRESH
BUFFER CONTROLS Buffer control signals provided simplify control interface between DRAM i960 data busses TX(A
LE(A
Functional Description
PRODUCT OVERVIEW NSBMC960 couples i960 interface DRAM access protocols generates buffer data multiplexor controls incorporates system monitor timing resources These functional elements shown Figure maximum controllers included system each managing banks memory NSBMC960 directly drives array fast page mode DRAMs This array organized leaves bits each Standard memory sizes from kbit Mbit supported 32-bit access allowed interleaved mode selected burst access zero-wait-state memory non-interleaved 1-wait-state burst access results NSBMC960 allows flexibility control data buffers memory array Propagation delay minimized providing these controls directly design flexibility maximized allowing control strategy programmable Buffers diverse 74FCT245 74FCT543 74FCT646 74FCT853 74FCT861 used without additional glue logic
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FIGURE Functional Block Diagram CONFIGURATION CONTROL NSBMC960 contains bits configuration data that controls it's operational mode configuration programmed sending data address Figure shows format configuration access byte select field determines which byte 64-bit field will updated contents byte data field Bits reserved must ``0'' base address fixed 0xff0f0000 while select field must match value programmed pins order protect against accidental programming configuration registers only modified when processor supervisor mode
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FIGURE Address Fields Used Access Configuration Data
Functional Description (Continued)
BLOCK ADDRESS FIELD Once configured NSBMC096 responds access requests within programmed block address range programmed value sets starting address block while size block determined DRAM size control bits block address however constrained start boundary that integer multiple block size example Mbit DRAMs used memory block size Mbytes must start Mbyte boundary
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FIGURE Configuration Register Control Fields CYCLE EXTEND order maximize choice memory device speeds that used various system clock rates Address Strobe (RAS) period basic access programmed either clock cycles When cleared ``0'' configuration indicates that clock cycles wait states) used (2-0-0-0 burst access) when ``1'' required wait states basic access 3-0-1-0 burst) Setting ``1'' also effect increasing pre-charge time clock cycle Calculation number cycles required access type detailed NSBMC096 Application Guide BURST WRITE DISABLE configuration word ``1'' burst write cycles disabled Subsequently when NSBMC096 detects start burst write access asserts BTERM signal request that processor terminate burst progress transfer remaining data using series simple cycles This feature included order facilitate implementation systems without latching buffers Latching buffers required prevent data hold violations during burst writes burst writes disabled latching buffers longer required ADDRESS HOLD configuration register controls time which memory address switches from column address This allows designer control address hold time relative that slowest memory used range clock speeds Setting yields maximum address hold time clearing shortens address hold favor additional column address setup INTERLEAVE DISABLE cost sensitive applications sometimes desirable system operate with single bank memory reduce minimum memory required this case interleave mode programmed ``1'' second bank memory added this programmed ``0'' enable interleave operation peak performance noninterleave mode burst access either 2-1-1-1 with Cycle Extend disabled 3-2-2-2 with Extended Cycle Non-interleave operation uses only leaf signals
Functional Description (Continued)
BUFFER CONTROL MODE FIELD transfer Data from memory sub-system i960 occurs through buffers controlled NSBMC096 signals (LEA LEB) provide transparent latch controls during write cycles have variable timing fixed interpretation other signals change both timing function according programmed mode Table presents these signals using names that based function performed Signals containing transmit controls buffers that have output enables (transmit from memory system) Buffers such '245s '646s which have direction enable pins controlled (chip enable) modes Signals ending with specific other leaves memory controlled NSBMC096 Signals without suffixes apply both leaves signal LeafB required some configurations indicates which memory leaf will selected next clock cycle TABLE Interpretation Buffer Control Signals Various Control Modes Mode Signal Signal LeafB LeafB TABLE Size Code Settings DRAM Density Address Range Size Memory Size Code Memory Block Size Banks Memory Types 256k 256k
Note that banks sequentially addressed within block
Table presents some possible configurations with corresponding mode settings comprehensive discussion selection buffer strategy refer NSBMC096 Application Guide TABLE Possible NSBMC096 Memory Buffer Configurations Buffer Type 74FCT245 74FCT245 74FCT646 74FCT543 Am29C983 None DRAM Type Nibble Nibble Nibble Write Access 2-4-4-4 2-4-4-4 1-0-0-0 1-0-0-0 1-0-0-0 2-4-4-4 Read Access 2-0-0-0 2-0-0-0 2-0-0-0 2-0-0-0 2-0-0-0 2-0-0-0 Buffer Mode Mode Mode Mode Mode Mode Mode
These configurations have burst writes disabled
DRAM SIZE FIELD This three field bits 12-14 selects DRAM device address size consequently memory block size Note that memory both leaves bank required same size organization correct operation Table lists size codes corresponding device sizes
REFRESH RATE FIELD system clock frequency used derive period DRAM refresh cycles refresh rate calculated (PCLK clock frequency) (programmed value example system clock programmed value (0x18) NSBMC096 will execute refresh cycles 256k DRAM algorithm employed NSBMC096 guarantees time complete device refresh however individual refresh delayed pre-empt bursts progress Since maximum burst clock cycles length this delay endangers data integrity Access devices other than NSBMC096 controlled memory delayed refresh access memory while refresh progress completed once refresh cycle complete TIMER CONTROL FIELD 24-bit timer counter which scales PCLK programmable amount automatically reloads when terminal count reached contents timer cannot read directly however counter will generate interrupt when terminal count reached timer disabled following RESET Timer Reload value (Configuration Bytes must programmed before timer enabled terminal count interrupt generated comply with either edge triggered level sense interrupt controllers Edge triggered mode generates pulse that cycles when terminal count reached Level sense mode output asserted when terminal count reached output remains until Acknowledge Timer Interrupt op-code written configuration byte section Operation Control further detail concerning timer interrupt control WATCH TIMER CONTROL FIELD NSBMC096 contains circuitry that monitors access requests regardless target address Access made region configured external ready hang processor some reason READY returned terminate access NSBMC096 detect such condition watch feature enabled will return READY BERR
Functional Description (Continued)
monitor operates monitoring state signal Should asserted longer than programmed Time value configuration register Ready asserted configuration configuration BERR also asserted BERR signal behaves much like timer interrupt that programmed produce pulse level state level state operation selected (configuration BERR will only deasserted when configuration register accessed read cycle configuration cleared zero cycle pulse produced time-out providing both modes operation BERR signal connected directly processor external WATCHDOGcircuit OPERATION CONTROL FIELD Byte configuration register contains three fields first field (from LSB) reserved test purposes must zero proper in-circuit operation second field operation control field which used control state page cache timer interrupts error signal third field bits refresh rate NSBMC096 been designed such that bits operation control field written with ``1'' access other fields disabled previous value retained bits operation control field ``0'' reserved refresh rate fields updated from current input Since control register accessed byte automatic masking non-control field bits simplifies programming control parameters parameters this field modified on-the-fly functions disabled reset operational controls have been encoded such that access register will only modify parameter
Control Function Update Bits with data Instruction Access Page Cache Disable (Default) Instruction Access Page Cache Enable Data Access Page Cache Disable (Default) Data Access Page Cache Enable Acknowledge Timer Interrupt Enable Timer Output Level Sense Interrupt Disable Timer Interrupts Enable Timer Output Edge Sense Interrupt behavior program being executed related ``run-length'' data instruction access processor internal cache utilization locality data instruction references Since throughput lowered cache misses page cache dynamically enabled disabled instruction data access this manner programmer apply mechanism judiciously order maximize throughput systems which Instruction data spaces controlled independent NSBMC096s page cache management used greater effect data instruction ``run length'' ceases factor determining performance this type configuration cache efficiency simply function locality reference control strategy page cache mechanism much simpler derive implement PCache management independently controlled instruction data access recommended starting strategy improving performance mixed instruction data systems rely burst mechanism internal cache instruction fetching enable PCache Data access only This general rule thumb improved once program behavior benchmarked
PAGE CACHE MANAGEMENT Page Cache management implemented NSBMC096 incorporates mechanism whereby advantage taken page access mode DRAMs only burst access also non-sequential data instruction access mechanism relies fact that long asserted access selected gained simply asserting column address strobe resulting access slower than burst only amount time required ensure that desired address same previously selected benefits this type access obvious however there drawbacks required address does reside same page that selected currently selected must released selected before access proceed process de-selecting selecting requires that precharge time allowed expire before selection begin This pre-charge time require additional cycles over standard access startup efficiency this type cache (PCache) related large extent locality reference datum being accessed systems that have mixed Instruction Data memory systems PCache efficiency very dependent
Application Example
System Clock Refresh Rate Memory Size Buffer Mode Cycle Extend (Size Signal Signal (Mode Interleave Enabled Address Hold clock cycle (Row Address Hold Required Configuration startup 0000 0000 1000 Configuration Setup 0xFF0F0000 (0xFF0F0000 0xFF0F0658 (0xFF0F0400 (0x96 0xFF0F0A20 (0xFF0F0800 (0x88 0xFF0F0C00 (0xFF0F0C00 Disabled clock derived from tRSHL NSBMC096 access time DRAM buffer delay 74FCT245 setup time processor's data inputs) Disabled (0b000000000100)
Burst Write Base Address
1000
1001 Config Config Config Config
0110
0000
0000
(0x00889600)
bits bits bits bits inputs processor require only small pull resistor keep them de-asserted when high impedance state multiple processor peripherals connected READY BTERM 3-state drivers should used such manner that signals actively de-asserted prior driver being placed its' high impedance state this rule followed simple ``wire or'' used Alternately sources READY BTERM combined using multiple input gates processor signals driven outputs
ease with which NSBMC096 integrated into system design illustrated diagram Figure system shown supports i960 with between memory depending devices selected managed single NSBMC096 This specific example accommodates devices Connection NSBMC096 i960 processor accomplished simply wiring together pins with same names only exceptions READY BTERM NSBMC096 only device that generates these signals they connected directly appropri-
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FIGURE Possible System Interconnection using V96BMC (Mode where used CEB)
Timing Parameters
INTERFACE TIMING NSBMC096 interface i960 been designed direct interconnect necessary place other Iogic devices between processor NSBMC096 their encouraged introduction intermediate address control signal buffers result skews delays that will require system clock frequency derated operation under worst case conditions timing diagrams presented this section assume that signals between processor NSBMC096 un-buffered REFRESH TIMING Figure details timing only refresh performed memory controller when there competing request from master competing request defined request that occurs between request this range timing exactly shown illustrated diagram represents timing that results when Cycle Extend disabled Cycle Extend enabled additional cycle inserted SIMPLE ACCESS TIMING NSBMC096 return data processor only clock cycles basic access wait states) depending whether Cycle Extend enabled multiple access cycles requested back back then will pause minimum clocks between cycles insure that pre-charge time This will result clocks between successive simple cycles
Figure shows timing relationship between system clock processor control signals NSBMC096 outputs NSBMC096 outputs derived synchronously with exception tARA (processor address address delay) simple access cycles shown diagram first read cycle that assumes that NSBMC096 idle prior start cycle second backed onto first show effect pre-charge imposed NSBMC096 Cycle Extend enabled wait state will inserted after cycles
BURST ACCESS TIMING When burst access requested processor NSBMC096 generates sequence Figure burst words (load double example) processor generates BLAST sequence shortened appropriately first access burst sequence begins same manner simple access Consequently timing parameters from Figure applied Figure
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FIGURE Refresh Timing
Timing Parameters (Continued)
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FIGURE Basic Access Timing
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FIGURE Burst Access Timing
Timing Parameters (Continued)
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FIGURE Burst Access PCache
Figures show sequence events that occur when PCache enabled sequence Figure shows back-to-back bursts same page This type sequence yields highest data transfer rate achievable
with DRAM Figure shows worst case scenario This example shows back-to-back simple access different rows with PCache enabled
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FIGURE Simple Access PCache Miss
Absolute Maximum Ratings
Military Aerospace specified devices required please contact National Semiconductor Sales Office Distributors availability specifications Supply Voltage (VCC) Input Voltage (VIN) Input Current (IIN) Storage Temperature STG) Voltages References Ground
Recommended Operating Conditions
Supply Voltage (VCC) Ambient Temperature Range Plastic Package Ceramic Package
Electrical Characteristics
Symbol IOZL IOZH ICC(Max) COUT Description Level Input Voltage High Level Input Voltage Level Input Current High Level Input Current Level Output Voltage High Level Output Voltage Level TRI-STATE Output Current Level TRI-STATE Output Current Maximum Supply Current Continuous Burst Access Input Capacitance Output Capacitance Conditions Continuous Simple Access
Units
Timing Parameters (Unless otherwise stated
Symbol tADSU tADH tBLSU tBLH tRZH tRHL tRLH tRHZ tARA tRAH tCAV tCAH tDRAH tRSHL tRSLH tCHL tCLH tBHL tBLH tBSV tBSH tWEHL tWELH tBCAH tBCAV tLEHL tLELH tRFA tRFH tRFHL tRFLH Description Address Strobe Setup Time Address Strobe Hold Time Synchronous Input Setup Synchronous Input Hold BLAST Input Setup BLAST Input Hold READY 3-state Valid Delay Relative PCLK READY Synchronous Assertion Delay READY Synchronous De-assertion Delay READY Valid 3-state Delay Relative PCLK Address Input Address Output Delay (Note PCLK PCLK Address Hold PCLK PCLK Column Address Valid (Note PCLK Column Address Hold DRAM Address Hold (Note PCLK Asserted Delay (Note PCLK De-asserted Delay (Note PCLK Asserted Delay (Note PCLK De-asserted Delay (Note PCLK Buffer Control Asserted Delay (Note PCLK Buffer Control De-asserted Delay (Note PCLK Bank Select Valid Time (Note PCLK Bank Select Hold Time (Note PCLK Write Enable Asserted Delay (Note PCLK Write Enable De-asserted Delay (Note PCLK Column Address Hold Time (Burst) (Note PCLK Column Address Valid Delay (Burst) (Note PCLK Latch Enable Assertion PCLK Latch Enable De-assertion PCLK Address Valid (Refresh) PCLK Address Hold (Refresh) REFRESH Synchronous Assertion Delay REFRESH Synchronous De-assertion Delay tM-4
tM-4 tM-3 Units
Signal output delays measured relative PCLK (except indicated) using load Note Derate given delays load excess Note PCLK High duration when configuration PCLK cycle time (PCLK frequency) configuration Timing silicon
Errata NSBMC096
document defines known errata related operation NSBMC096 Memory Controller ERRATUM Pulse mode interrupts from NSBMC096 cycles long current i960CA requires minimum interrupt pulse width three clock cycles RECOMMENDED Program NSBMC096 level mode interrupts ERRATUM When NSBMC096 programmed extended timing mode operation back back memory read cycles will fail RECOMMENDED Program i960CA memory region NSBMC096 insert wait state following each memory access NXDA
Ordering Code Information
National Semiconductor Mode Burst Mode Controller Processor Intel i960 Frequency Packaging 132-Lead PQFP
NSBMC096-16 Burst Memory Controller
Physical Dimensions inches (millimeters)
132-Pin Plastic Quad Flatpak (PQFP) Order Number NSBMC096VF Package Number VF132A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION used herein Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform when properly used accordance with instructions provided labeling reasonably expected result significant injury user
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NSBMC096-16 Burst Memory Controller NSBMC096 Burst Memory Control

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