NM27C020 152-Bit (256K Erasable CMOS EPROM General Description

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NM27C020 152-Bit (256K Erasable CMOS EPROM General Description

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NM27C020 152-Bit (256K Erasable CMOS EPROM
NM27C020 152-Bit (256K Erasable CMOS EPROM
General Description
NM27C020 high performance 152-bit EPROM organized K-words bits each pin-compatibility with byte-wide JEDEC EPROMs enables upgrades through Mbit EPROMs ``Don't Care'' feature during read operations enables memory expansions Mbits with printed circuit board changes NM27C020 provides microprocessor-based systems extensive storage capacity large portions operating system application software access time provides no-wait-state operation with high-performance CPUs NM27C020 offers single chip solution code storage requirements 100% firmware-based equipment Frequently-used software routines quickly executed from EPROM storage greatly enhancing system utility NM27C020 manufactured using National's advanced CMOS AMGEPROM technology NM27C020 member high density National EPROM series which range densities
Features
High performance CMOS access time Simplified upgrade path ``Don't Care'' during normal read operation JEDEC standard configuration Manufacturer's identification code JEDEC standard configuration 32-pin 32-pin PLCC
Block Diagram
Names
Symbol Description Addresses Chip Enable Output Enable Outputs Program Don't Care (During Read)
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TRI-STATE registered trademark National Semiconductor Corporation AMGis trademark Incorporated C1996 National Semiconductor Corporation
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RRD-B30M17 Printed
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Connection Diagrams
Configuration
Mbit Mbit Mbit 27C512 27C256
NM27C020
27C256 27C512 27C010 27C040 27C080
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Note Compatible EPROM configurations shown blocks adjacent NM27C020 pins
Commercial Temp Range Parameter Order Number NM27C020 NM27C020 NM27C020 NM27C020 Access Time (ns)
PLCC Configuration
Extended Temp Range (b40 Parameter Order Number NM27C020 NM27C020 NM27C020 Packages Types NM27C020 Ceramic PLCC Access Time (ns)
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Ordering Information
National Memory EPROM CMOS Access Time Operating Temperature Range Blank Commercial Extended Package Ceramic PLCC Size Mbit
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Absolute Maximum Ratings
Storage Temperature Input Voltages Except with Respect Ground (Note with Respect Ground Supply Voltage with Respect Ground Protection (MIL 883C Method 3015 Output Voltages with Respect Ground (Note
(Note Note Stresses above those listed under ``Absolute Maximum Ratings'' cause permanent damage device This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied Exposure absolute maximum rating conditions extended periods time affect device reliability
2000V
Operating Range
Range Comm'l Military Industrial Temperature
Tolerance
Read Characteristics Over Operating Range with
Symbol ISB1 (Note ISB2 (Note Parameter Input Level Input High Level Output Voltage Output High Voltage Standby Current (CMOS) Standby Current (TTL) Active Current b400 Inputs VOUT
Test Conditions
Units
Commercial Industrial
Supply Current Read Voltage Input Load Current Output Leakage Current
Read Characteristics Over Operating Range with
Symbol tACC (Note (Note Parameter Address Output Delay Output Delay Output Delay Output Disable Output Float Output Hold from Addresses Whichever Occurred First Units
attached Frequency Graphs
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Frequency
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FIGURE
Temperature
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FIGURE
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Capacitance
Symbol COUT Parameter Input Capacitance Output Capacitance
(Note Conditions VOUT Units
Test Conditions
Output Load Input Rise Fall Times Gate (Note Input Pulse Levels Timing Measurement Reference Level (Note Inputs Outputs
Waveforms (Notes
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Note Stresses above those listed under ``Absolute Maximum Ratings'' cause permanent damage device This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied Exposure absolute maximum rating conditions extended periods affect device reliability Note This parameter only sampled 100% tested Note delayed tACC after falling edge without impacting tACC Note compare level determined follows High TRI-STATE measured VOH1 (DC) TRI-STATE measured VOL1 (DC) Note TRI-STATE attained using Note power switching characteristics EPROMs require careful device decoupling recommended that least ceramic capacitor used every device between Note outputs must restricted avoid latch-up device damage Note Gate includes fixture capacitance Note connected except during programming Note Inputs outputs undershoot
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Programming Characteristics (Notes
Symbol tOES tCES tVPS tVCS tOUT Parameter Address Setup Time Setup Time Setup Time Data Setup Time Setup Time Setup Time Address Hold Time Data Hold Time Output Enable Output Float Delay Program Pulse Width Data Valid from Supply Current during Programming Pulse Supply Current Temperature Ambient Power Supply Voltage Programming Supply Voltage Input Rise Fall Time Input Voltage Input High Voltage Input Timing Reference Voltage Output Timing Reference Voltage
Conditions Units
Programming Waveforms (Note
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Note National's standard product warranty applies only devices programmed specifications described herein Note must applied simultaneously before removed simultaneously after EPROM must inserted into removed from board with voltage applied Note maximum absolute allowable voltage which applied during programming Care must taken when switching supply prevent overshoot from exceeding this maximum specification least capacitor required across suppress spurious voltage transients which damage device Note Programming program verify tested with fast Program Algorithm typical power supply voltages timings limit parameters design parameters tested guaranteed Note During power must brought high VIH) either coincident with before power applied
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Fast Programming Algorithm Flow Chart
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FIGURE
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Functional Description
DEVICE OPERATION modes operation device listed Table should noted that inputs modes levels power supplies required power supply must during three programming modes must other three modes power supply must during three programming modes other three modes Read Mode part control functions both which must logically active order obtain data outputs Chip Enable (CE) power control should used device selection Output Enable (OE) output control should used gate data output pins independent device selection Assuming that addresses stable address access time (tACC) equal delay from output (tCE) Data available outputs after falling edge assuming that been addresses have been stable least tACC Standby Mode device standby mode which reduces active power dissipation over from device placed standby mode applying CMOS high signal input When standby mode outputs high impedance state independent input Output OR-Tying Because part usually used larger memory arrays National provided 2-line control function that accommodates this multiple memory connections 2line control function allows lowest possible memory power dissipation complete assurance that output contention will occur most efficiently these control lines recommended that decoded used primary device selecting function while made common connection devices array connected READ line from system control This assures that deselected memory devices their power standby modes that output pins active only when data desired from particular memory device Programming CAUTION Exceeding will damage device Initially after each erasure bits device ``1'' state Data introduced selectively programming ``0''s into desired locations Although only ``0''s will programmed both ``1''s ``0''s present data word only change ``0'' ``1'' ultraviolet light erasure part programming mode when power supply required that least capacitor placed across ground suppress spurious voltage transients which damage device data programmed applied bits parallel data output pins levels required address data inputs When address data stable active program pulse applied input program pulse must applied each address location programmed EPROM programmed with Fast Programming Algorithm shown Figure Each Address programmed with series pulses until verifies good maximum pulses Most memory cells will program with single pulse EPROM must programmed with signal applied input Programming multiple EPROM parallel with same data easily accomplished simplicity programming requirements Like inputs parallel EPROM connected together when they programmed with same data level pulse applied input programs paralleled EPROM Program Inhibit Programming multiple EPROM's parallel with different data also easily accomplished Except like inputs (including PGM) parallel EPROM common level program pulse applied EPROM's input with will program that EPROM high level input inhibits other EPROMs from being programmed Program Verify verify should performed programmed bits determine whether they were correctly programmed verify performed with must except during programming program verify
Mode Selection
modes operation NM27C020 listed Table single power supply required read mode inputs levels except device signature TABLE Modes Selection Mode Read Output Disable Standby Programming Program Verify Program Inhibit
Note
Pins
(Note
Outputs DOUT High-Z High-Z DOUT High-Z
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Functional Description (Continued)
Manufacturer's Identification Code part manufacturer's identification code programming When device inserted EPROM programmer socket programmer reads code then automatically calls specific programming algorithm part This automatic programming control only possible with programmers which have capability reading code Manufacturer's Identification code shown Table specifically identifies manufacturer device type code NM27C020 ``8F07'' where ``8F'' designates that made National Semiconductor ``07'' designates Megabit byte-wide part code accessed applying address address control pins held except Address held manufacturer's code held from device code code read eight data pins O0-O7 Proper code access only guaranteed ERASURE CHARACTERISTICS erasure characteristics device such that erasure begins occur when exposed light with wavelengths shorter than approximately 4000 Angstroms should noted that sunlight certain types fluorescent lamps have wavelengths 3000 -4000 range After programming opaque labels should placed over device window prevent unintentional erasure Covering window will also prevent temporary functional failures generation photo currents recommended erasure procedure device exposure shortwave ultraviolet light which wavelength 2537 integrated dose intensity exposure time) erasure should minimum Wsec device should placed within inch lamp tubes during erasure erasure system should calibrated periodically distance from lamp device should maintained inch erasure time increases square distance distance doubled erasure time increases factor Lamps lose intensity they When lamp changed distance changed lamp aged system should checked make certain full erasure occurring Incomplete erasure will cause symptoms that misleading Programmers components even system designs have been erroneously suspected when incomplete erasure problem SYSTEM CONSIDERATION power switching characteristics EPROMs require careful decoupling devices supply current three segments that interest system designer standby current level active current level transient current peaks that produced voltage transitions input pins magnitude these transient current peaks dependent output capacitance loading device associated transient voltage peaks suppressed properly selected decoupling capacitors recommended that least ceramic capacitor used every device between This should high frequency capacitor inherent inductance addition least bulk electrolytic capacitor should used between each eight devices bulk capacitor should located near where power supply connected array purpose bulk capacitor overcome voltage drop caused inductive effects board traces
TABLE Manufacturer's Identification Code Pins Manufacturer Code Device Code (12) (26) (21) (20) (19) (18) (17) (15) (14) (13) Data
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Physical Dimensions inches (millimeters) unless otherwise noted
32-Lead EPROM Ceramic Dual-In-Line Package Order Number NM27C020Q Package Number J32AQ
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
32-Lead PLCC Package Order Number NM27C020VXXX Package Number VA32A
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NM27C020 152-Bit (256K Erasable CMOS EPROM
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION used herein Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform when properly used accordance with instructions provided labeling reasonably expected result significant injury user
National Semiconductor Corporation Americas 1(800) 272-9959 1(800) 737-7018 Email support
critical component component life support device system whose failure perform reasonably expected cause failure life support device system affect safety effectiveness
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National Semiconductor Europe 180-530 Email europe support Deutsch 180-530 English 180-532 Fran 180-532 Italiano 180-534
National Semiconductor Southeast Asia (852) 2376 3901 Email support
National Semiconductor Japan 81-3-5620-7561 81-3-5620-6179
National does assume responsibility circuitry described circuit patent licenses implied National reserves right time without notice change said circuitry specifications

NM27C020 152-Bit (256K Erasable CMOS EPROM General Description

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