COP688HG COP888HG 8-Bit Microcontroller with UART Three Multi-Function
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COP688HG COP888HG 8-Bit Microcontroller with UART Three Multi-Function Timers
COP688HG COP888HG 8-Bit Microcontroller with UART Three Multi-Function Timers
COP8feature family microcontrollers uses 8-bit single chip core architecture fabricated with National Semiconductor's M2CMOSprocess technology COP888HG member this expandable 8-bit core processor family microcontrollers (Continued)
Schmitt trigger inputs ports Packages with pins PLCC with pins
Instruction Features
Features
Full duplex UART Three 16-bit timers each with 16-bit registers supporting Processor Independent mode External Event counter mode Input Capture mode Quiet design (low radiated emissions) kbytes on-board bytes on-board
Additional Peripheral Features
instruction cycle time Fourteen multi-source vectored interrupts servicing External Interrupt with selectable edge Idle Timer Three Timers (Each with Interrupts) MICROWIRE PLUSMulti-Input Wake-Up Software Trap UART Default (default interrupt) Versatile easy-to-use instruction 8-bit Stack Pointer (SP) stack 8-bit Register Indirect Data Memory Pointers
Idle Timer Multi-Input Wake-Up (MIWU) with optional interrupts analog comparators WATCHDOGand Clock Monitor logic MICROWIRE PLUSserial
Fully Static CMOS
Features
power saving modes HALT IDLE current drain (typically Single supply operation Temperature ranges
Memory mapped Software selectable options (TRI-STATE Output Push-Pull Output Weak Pull-Up Input High Impedance Input)
Development Support
Emulation devices Real time emulation full program debug offered MetaLink's Development System
TRI-STATE registered trademark National Semiconductor Corporation MICROWIRE MICROWIREand WATCHDOGare trademarks National Semiconductor Corporation PC-AT PC-XT registered trademarks International Business Machines Corporation iceMASTERis trademark MetaLink Corporation C1996 National Semiconductor Corporation DD12858 RRD-B30M96 Printed
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Block Diagram
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FIGURE COP888HG Block Diagram
General Description (Continued) fully static part fabricated using double-metal silicon gate microCMOS technology Features include 8-bit memory mapped architecture MICROWIRE PLUS serial three 16-bit timer counters supporting three modes (Processor Independent generation External Event counter Input Capture mode capabilities) full duplex UART comparators power saving modes (HALT IDLE) both with multi-sourced wakeup interrupt capability This multi-sourced interrupt capability
also used independent HALT IDLE modes Each software selectable configurations devices operate over voltage range High throughput achieved with efficient regular instruction operating maximum rate instruction radiated emissions achieved gradual turn-on output drivers internal smoothing filters chip logic crystal oscillator
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Connection Diagrams
Plastic Chip Carrier Dual-In-Line Package
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View Order Number COP688HG-XXX COP888HG-XXX Package Number V44A
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View Order Number COP688HG-XXX COP888HG-XXX Package Number N40A FIGURE Connection Diagrams
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Connection Diagrams (Continued)
Pinouts 44-Pin Packages Port RESET Type MIWU MIWU MIWU MIWU MIWU MIWU MIWU MIWU HALT Restart 40-Pin COMP1INb COMP1IN COMP1OUT COMP2INb COMP2IN COMP2OUT 44-Pin PLCC
WDOUT
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Absolute Maximum Ratings
Supply Voltage (VCC) Voltage Total Current into (Source)
Total Current (Sink) Storage Temperature Range
Note Absolute maximum ratings indicate limits beyond which damage device occur electrical specifications ensured when operating device absolute maximum ratings
Electrical Characteristics
Parameter Operating Voltage Power Supply Ripple (Note Supply Current (Note HALT Current (Note IDLE Current Input Levels (VIH VIL) RESET Logic High Logic Other Inputs Logic High Logic Hi-Z Input Leakage Input Pullup Current Port Input Hysteresis (Note Output Current Levels Outputs Source Sink (Note Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE Leakage Allowable Sink Source Current (Note Outputs (Sink) others Maximum Input Current without Latchup (Notes Retention Voltage Input Capacitance (Note Load Capacitance (Note
COP888HG unless otherwise specified Conditions
Units
Peak-to-Peak
Rise Fall Time (min)
1000
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Electrical Characteristics
Parameter Instruction Cycle Time (tc) Crystal Resonator Oscillator Inputs tSETUP tHOLD Output Propagation Delay tPD1 tPD0 Others MICROWIRE Setup Time (tUWS) (Note MICROWIRE Hold Time (tUWH) (Note MICROWIRE Output Propagation Delay (tUPD) Input Pulse Width Interrupt Input High Time Interrupt Input Time Timer Input High Time Timer Input Time Reset Pulse Width
Instruction Cycle Time
COP888HG unless otherwise specified Conditions Units
Note Maximum rate voltage change must less than Note Supply IDLE currents measured with driven with square wave Oscillator driven phase with inputs connected outputs driven connected load Note HALT mode will stop from oscillating Crystal configurations bringing high Test Conditions inputs tied ports TRI-STATE mode tied ground outputs tied ground clock monitor disabled Note user must guarantee that does source more than during RESET sources more than during reset device will into programming mode Note Pins RESET designed with high voltage input network These pins allow input voltages pins will have sink current when biased voltages (the pins have source current when biased voltage below VCC) effective resistance 750X (typical) These pins will latch voltage pins must limited WARNING Voltages excess will cause damage pins This warning excludes transients Note output propagation delay referenced instruction cycle where output change occurs Note Parameter characterized tested
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Absolute Maximum Ratings
Military Aerospace specified devices required please contact National Semiconductor Sales Office Distributors availability specifications Supply Voltage (VCC) Voltage Total Current into (Source) Total Current (Sink) Storage Temperature Range
Note Absolute maximum ratings indicate limits beyond which damage device occur electrical specifications ensured when operating device absolute maximum ratings
Electrical Characteristics
Parameter Operating Voltage Power Supply Ripple (Note Supply Current (Note HALT Current (Note IDLE Current Input Levels (VIH VIL) RESET Logic High Logic Other Inputs Logic High Logic Hi-Z Input Leakage Input Pullup Current Port Input Hysteresis Output Current Levels Outputs Source Sink Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE Leakage Allowable Sink Source Current Outputs (Sink) others Maximum Input Current without Latchup (Notes Retention Voltage Input Capacitance Load Capacitance
COP688HG unless otherwise specified
Conditions
Units
Peak-to-Peak
(Note
Room Temperature Rise Fall Time (min) (Note (Note
1000
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Electrical Characteristics
Parameter Instruction Cycle Time (tc) Crystal Resonator Inputs tSETUP tHOLD Output Propagation Delay tPD1 tPD0 Others MICROWIRE Setup Time (tUWS) (Note MICROWIRE Hold Time (tUWH) (Note MICROWIRE Output Propagation Delay (tUPD) Input Pulse Width (Note Interrupt Input High Time Interrupt Input Time Timer Input High Time Timer Input Time Reset Pulse Width
COP688HG unless otherwise specified Conditions Units
Note Maximum rate voltage change must less than Note Supply current measured after running 2000 cycles with square wave input open inputs rails outputs open Note HALT mode will stop from oscillating Crystal configurations Measurement HALT done with device neither sourcing sinking current with G0-G5 programmed outputs driving load outputs programmed driving load inputs tied clock monitor comparators disabled Parameter refers HALT mode entered setting Port data register Part will pull during HALT crystal clock mode Note Pins RESET designed with high voltage input network These pins allow input voltages pins will have sink current when biased voltages (the pins have source current when biased voltage below VCC) effective resistance 750X (typical) These pins will latch voltage pins must limited WARNING Voltages excess will cause damage pins This warning excludes transients Note Parameter characterized tested Note Instruction Cycle Time
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Comparators Characteristics
Parameter Input Offset Voltage Input Common Mode Voltage Range Level Output Current High Level Output Current Supply Current Comparator (When Enabled) Response Time Overdrive Load Conditions
Units
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FIGURE MICROWIRE PLUS Timing
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Descriptions
power supply pins pins must connected clock input This come from generated oscillator crystal oscillator conjunction with CKO) Oscillator Description section RESET master reset input Reset Description section device contains three bidirectional 8-bit ports where each individual independently configured input (Schmitt Trigger inputs ports output TRI-STATE under program control Three data memory address locations allocated each these ports Each port associated 8-bit memory mapped registers CONFIGURATION register output DATA register memory mapped address also reserved input pins each port (See memory various addresses associated with ports Figure shows port configurations DATA CONFIGURATION registers allow each port individually configured under software control shown below CONFIGURATION Register DATA Register Port Set-Up Hi-Z Input (TRI-STATE Output) Input with Weak Pull-Up Push-Pull Zero Output Push-Pull Output used UART transmit receive used timer input functions used timer input functions Port following alternate features MIWU MIWU MIWU MIWU MIWU MIWU MIWU MIWU Port 8-bit port with pins input (G6) dedicated output (G7) Pins have Schmitt Triggers their inputs serves dedicated WDOUT WATCHDOG output while either input output depending oscillator mask option selected With crystal oscillator option selected serves dedicated output clock output With single-pin oscillator mask option selected serves general purpose input also used bring device HALT mode with high transition There registers associated with Port data register configuration register Therefore each bits individually configured under software control Since input only dedicated clock output (crystal clock option) general purpose input clock option) associated bits data configuration registers used special purpose functions outlined next page Reading data bits will return zeros
PORT 8-bit port L-pins have Schmitt triggers inputs Port supports Multi-Input Wake eight pins used UART external clock
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FIGURE Port Configurations
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Descriptions (Continued)
Note that chip will placed HALT mode writing ``1'' Port Data Register Similarly chip will placed IDLE mode writing ``1'' Port Data Register Writing ``1'' Port Configuration Register enables MICROWIRE PLUS operate with alternate phase clock configuration high enables clock start delay after HALT when clock configuration used Config CLKDLY Alternate Data HALT IDLE
tecture though based Harvard architecture permits transfer data from REGISTERS 8-bit addition subtraction logical shift operation instruction (tc) cycle time There registers 8-bit Accumulator Register 15-bit Program Counter Register upper bits program counter (PC) lower bits program counter (PC) 8-bit address pointer which optionally post auto incremented decremented 8-bit alternate address pointer which optionally post auto incremented decremented 8-bit stack pointer which points subroutine interrupt stack RAM) initialized address with reset 8-bit Data Segment Address Register used extend lower half address range into data segments bytes each registers memory mapped with exception Accumulator Program Counter (PC) PROGRAM MEMORY program memory consists kbytes These bytes hold program instructions constant data (data tables LAID instruction jump vectors instruction interrupt vectors instruction) program memory addressed 15-bit program counter (PC) interrupts devices vector program memory location DATA MEMORY data memory address space includes on-chip data registers registers (Configuration Data Pin) control registers MICROWIRE PLUS shift register various registers counters associated with timers (with exception IDLE timer) Data memory addressed directly instruction indirectly pointers register data memory consists bytes Sixteen bytes mapped ``registers'' addresses These registers loaded immediately also decremented tested with DRSZ (decrement register skip zero) instruction memory pointer registers memory mapped into this space address locations respectively with other registers being available general usage instruction permits memory reset tested registers (except memory mapped therefore bits register bits directly individually reset tested accumulator bits also directly individually tested
Note contents undefined upon power-up
Port following alternate features INTR (External Interrupt Input) (Timer Capture Input) (Timer (MICROWIRE Serial Data Output) (MICROWIRE Serial Clock) (MICROWIRE Serial Data Input) Port following dedicated functions WDOUT WATCHDOG Clock Monitor dedicated output Oscillator dedicated output general purpose input Port 8-bit port 40-pin device does have full complement Port pins unavailable pins terminated read operation these unterminated pins will return unpredicatable values Port eight-bit Hi-Z input port Port used Comparator Port I4-I6 used Comparator Port following alternate features COMP1bIN (Comparator Negative Input) COMP1 (Comparator Positive Input) COMP1OUT (Comparator Output) COMP2bIN (Comparator Negative Input) COMP2 (Comparator Positive Input) COMP2OUT (Comparator Output) Port 8-bit output port that preset high when RESET goes user more port outputs (except together order higher drive
Functional Description
architecture device modified Harvard architecture With Harvard architecture control store program memory (ROM) separated from data store memory (RAM) Both have their separate addressing space with separate address buses archi-
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Data Memory Segment Extension
Data memory address used memory mapped location Data Segment Address Register data store memory either addressed directly single byte address within instruction indirectly relative reference pointers (each contains single-byte address) This single-byte address allows addressing range locations from upper this single-byte address divides data store memory into separate sections outlined previously With exception register memory from address locations 00F0 00FF memory memory mapped with upper single-byte address being equal zero This allows upper single-byte address determine whether base address range (from 0000 00FF) extended this upper equals (representing address range 0080 00FF) then address extension does take place Alternatively this upper equals zero then data segment extension register used extend base address range (from 0000 007F) from XX00 XX7F where represents bits from register Thus 128-byte data segment extensions located from addresses 0100 017F data segment 0200 027F data segment FF00 FF7F data segment base address range from 0000 007F represents data segment available data segments register must changed under program control move from data segment (128 bytes) another However upper base segment (containing memory registers registers control registers always available regardless contents register since upper base segment (address range 0080 00FF) independent data segment extension instructions that utilize stack pointer (SP) always reference stack part base segment (Segment regardless contents register register changed these instructions Consequently stack (used with subroutine linkage interrupts) always located base segment stack pointer will intitialized point data memory location 006F result reset bytes contained base segment split between lower upper base segments first bytes resident from address 0000 006F lower base segment while remaining bytes represent data memory registers located addresses 00F0 00FF upper base segment located upper sixteen addresses (0070 007F) lower base segment Additional beyond these initial bytes however will always memory mapped groups bytes less) data segment address extensions (XX00 XX7F) lower base segment additional bytes memory mapped address locations 0100 017F
Figure illustrates register data memory extension used extending lower half base address range hex) into data segments bytes each with total addressing range kbytes from XX00 XX7F This organization allows total data segments bytes each with additional upper base segment bytes Furthermore addressing modes
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Reads ones
FIGURE Organization
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Reset
RESET input when pulled initializes microcontroller Initialization will occur whenever RESET input pulled Upon initialization data configuration registers ports cleared resulting these Ports being initialized TRI-STATE mode Port exception noted below) since dedicated WATCHDOG Clock Monitor error output Port high ICNTRL CNTRL T2CNTRL T3CNTRL control registers cleared Comparator Select Register cleared register initialized zero Multi-Input Wakeup registers WKEN WKEDG cleared Wakeup register WKPND unknown stack pointer initialized device comes reset with both WATCHDOG logic Clock Monitor detector armed with WATCHDOG service window bits Clock Monitor WATCHDOG Clock Monitor circuits inhibited during reset WATCHDOG service window bits being initialized high default maximum WATCHDOG service window clock cycles Clock Monitor being initialized high will cause Clock Monitor error following reset clock reached minimum specified frequency termination reset Clock Monitor error will cause active error output This error output will continue until clock cycles following clock frequency reaching minimum specified value which time output will enter TRI-STATE mode external network shown Figure should used ensure that RESET held until power supply chip stabilizes
clock (crystal configuration) input frequency divided down produce instruction cycle clock
Figure shows Crystal oscillator diagrams
CRYSTAL OSCILLATOR connected make closed loop crystal resonator) controlled oscillator Table shows component values required various standard crystal values OSCILLATOR selecting single oscillator input single oscillator circuit connected available general purpose input HALT restart input Table shows variation oscillator frequencies functions component values
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FIGURE Crystal Oscillator Diagrams TABLE Crystal Oscillator Configuration (kX) (MX) (pF) (pF) Freq (MHz) Conditions
TABLE Oscillator Configuration
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(kX)
(pF)
Freq (MHz)
Instr Cycle (ms)
Conditions
Power Supply Rise Time
FIGURE Recommended Reset Circuit
Oscillator Circuits
chip driven clock input input which between output
Note 200k
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Control Registers
CNTRL Register (Address 00EE) Timer1 (T1) MICROWIRE PLUS control register contains following bits Select MICROWIRE PLUS clock divide IEDG External interrupt edge polarity select Rising edge Falling edge) MSEL Selects MICROWIRE PLUS signals respectively T1C0 Timer Start Stop control timer modes Timer Underflow Interrupt Pending Flag timer mode T1C1 Timer mode control T1C2 Timer mode control T1C3 Timer mode control T1C3 T1C2 T1C1 T1C0 MSEL IEDG LPEN Port Interrupt Enable (Multi-Input Wakeup Interrupt) could used flag
Unused LPEN T0PND T0EN mWPND mWEN T1PNDB T1ENB
Register (Address 00EF) register contains following select bits Global interrupt enable (enables interrupts) EXEN Enable external interrupt BUSY MICROWIRE PLUS busy shifting flag EXPND External interrupt pending T1ENA Timer Interrupt Enable Timer Underflow Input capture edge T1PNDA Timer Interrupt Pending Flag (Autoreload mode Underflow Mode capture edge mode Carry Flag Half Carry Flag T1PNDA T1ENA EXPND BUSY EXEN
T2CNTRL Register (Address 00C6) T2CNTRL register contains following bits T2ENB Timer Interrupt Enable Input capture edge T2PNDB Timer Interrupt Pending Flag capture edge T2ENA Timer Interrupt Enable Timer Underflow Input capture edge T2PNDA Timer Interrupt Pending Flag (Autoreload mode Underflow mode capture edge mode T2C0 Timer Start Stop control timer modes Timer Underflow Interrupt Pending Flag timer mode T2C1 Timer mode control T2C2 Timer mode control T2C3 Timer mode control
T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB
Half-Carry also affected instructions that affect Carry flag (Set Carry) (Reset Carry) instructions will respectively clear both carry flags addition instructions SUBC instructions affect carry Half Carry flags ICNTRL Register (Address 00E8) ICNTRL register contains following bits T1ENB Timer Interrupt Enable Input capture edge T1PNDB Timer Interrupt Pending Flag capture edge mWEN Enable MICROWIRE PLUS interrupt mWPND MICROWIRE PLUS interrupt pending T0EN Timer Interrupt Enable (Bit toggle) T0PND Timer Interrupt pending
T3CNTRL Register (Address 00B6) T3CNTRL register contains following bits T3ENB Timer Interrupt Enable Input capture edge T3PNDB Timer Interrupt Pending Flag capture edge T3ENA Timer Interrupt Enable Timer Underflow Input capture edge T3PNDA Timer Interrupt Pending Flag (Autoload mode Underflow mode capture edge mode T3C0 Timer Start Stop control timer modes Timer Underflow Interrupt Pending Flag timer mode T3C1 Timer mode control T3C2 Timer mode control T3C3 Timer mode control
T3C3 T3C2 T3C1 T3C0 T3PNDA T3ENA T3PNDB T3ENB
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Timers
device contains very versatile timers timers associated autoreload capture registers power containing random data TIMER (IDLE TIMER) device supports applications that require maintaining real time power with IDLE mode This IDLE mode support furnished IDLE timer which 16-bit timer Timer runs continuously fixed rate instruction cycle clock user cannot read write IDLE Timer which count down timer Timer supports following functions
register Subsequent underflows cause timer reloaded from registers alternately beginning with register Timer control bits TxC3 TxC2 TxC1 timer mode operation
Exit Idle Mode (See Idle Mode description) WATCHDOG logic (See WATCHDOG description)
Start delay HALT mode IDLE Timer generate interrupt when thirteenth toggles This toggle latched into T0PND pending flag will occur every maximum clock frequency control flag T0EN allows interrupt from thirteenth Timer enabled disabled Setting T0EN will enable interrupt while resetting will disable interrupt
TIMER TIMER TIMER device three powerful timer counter blocks associated features functioning timer block described referring timer block Since three timer blocks identical comments equally applicable three timer blocks Each timer block consists 16-bit timer supporting 16-bit autoreload capture registers Each timer block pins associated with supports required timer block while input timer block powerful flexible timer block allows device easily perform timer functions with minimal software overhead timer block three operating modes Processor Independent mode External Event Counter mode Input Capture mode control bits TxC3 TxC2 TxC1 allow selection different modes operation Mode Processor Independent Mode name suggests this mode allows device generate signal with very minimal user intervention user only define parameters signal time time) Once begun timer block will continuously generate signal completely independent microcontroller user software services timer block only when parameters require updating this mode timer counts down fixed rate Upon every underflow timer alternately reloaded with contents supporting registers very first underflow timer causes timer reload from
Figure shows block diagram timer mode underflows programmed toggle output underflows also programmed generate interrupts Underflows from timer alternately latched into pending flags TxPNDA TxPNDB user must reset these pending flags under software control control enable flags TxENA TxENB allow interrupts from timer underflow enabled disabled Setting timer enable flag TxENA will cause interrupt when timer underflow causes register reloaded into timer Setting timer enable flag TxENB will cause interrupt when timer underflow causes register reloaded into timer Resetting timer enable flags will disable associated interrupts Either both timer underflow interrupts enabled This gives user flexibility interrupting once period either rising falling edge output Alternatively user choose interrupt both edges output
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FIGURE Timer Mode Mode External Event Counter Mode This mode quite similar processor independent mode described above main difference that timer clocked input signal from timer control bits TxC3 TxC2 TxC1 allow timer clocked either positive negative edge from Underflows from timer latched into TxPNDA pending flag Setting TxENA control flag will cause interrupt when timer underflows this mode input used independent positive edge sensitive interrupt input TxENB control flag occurrence positive edge input latched into TxPNDB flag
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Timers (Continued) Figure shows block diagram timer External Event Counter mode
Note output available this mode since being used counter input clock
Underflows from timer also programmed generate interrupts Underflows latched into timer TxC0 pending flag (the TxC0 control serves timer underflow interrupt pending flag Input Capture mode) Consequently TxC0 control should reset when entering Input Capture mode timer underflow interrupt enabled with TxENA control flag When interrupt occurs Input Capture mode user must check both TxPNDA TxC0 pending flags order determine whether input capture timer underflow both) caused interrupt
Figure shows block diagram timer Input Capture mode
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FIGURE Timer External Event Counter Mode Mode Input Capture Mode device precisely measure external frequencies time external events placing timer block input capture mode this mode timer constantly running fixed rate registers capture registers Each register acts conjunction with register acts conjunction with register acts conjunction with timer value gets copied over into register when trigger event occurs corresponding Control bits TxC3 TxC2 TxC1 allow trigger events specified either positive negative edge trigger condition each input specified independently trigger conditions also programmed generate interrupts occurrence specified trigger condition pins will respectively latched into pending flags TxPNDA TxPNDB control flag TxENA allows interrupt either enabled disabled Setting TxENA flag enables interrupts generated when selected trigger condition occurs Similarly flag TxENB controls interrupts from
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FIGURE Timer Input Capture Mode TIMER CONTROL FLAGS timers have indentical control structures control bits their functions summarized below TxC0 Timer Start Stop control Modes (Processor Independent External Event Counter) where Start Stop Timer Underflow Interrupt Pending Flag Mode (Input Capture) TxPNDA Timer Interrupt Pending Flag TxPNDB Timer Interrupt Pending Flag TxENA Timer Interrupt Enable Flag TxENB Timer Interrupt Enable Flag Timer Interrupt Enabled Timer Interrupt Disabled TxC3 Timer mode control TxC2 Timer mode control TxC1 Timer mode control
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Timers (Continued)
timer mode control bits (TxC3 TxC2 TxC1) detailed below TxC3 TxC2 TxC1 Timer Mode MODE (External Event Counter) MODE (External Event Counter) MODE (PWM) Toggle MODE (PWM) Toggle MODE (Capture) Captures Edge Edge MODE (Capture) Captures Edge Edge MODE (Capture) Captures Edge Edge MODE (Capture) Captures Edge Edge Interrupt Source Timer Underflow Timer Underflow Autoreload Autoreload Edge Timer Underflow Edge Timer Underflow Edge Timer Underflow Edge Timer Underflow Interrupt Source Edge Edge Autoreload Autoreload Edge Timer Counts Edge Edge
Edge
Edge
Edge
Power Save Modes
device offers user power save modes operation HALT IDLE HALT mode microcontroller activities stopped IDLE mode on-board oscillator circuitry WATCHDOG logic Clock Monitor timer active other microcontroller activities stopped either mode on-board registers states timers (with exception unaltered HALT MODE device placed HALT mode writing ``1'' HALT flag data bit) microcontroller activities including clock timers stopped WATCHDOG logic disabled during HALT mode However clock monitor circuitry enabled remains active will cause WATCHDOG output (WDOUT) HALT mode used user does want activate WDOUT Clock Monitor should disabled after device comes reset (resetting Clock Monitor control with first write WDSVR register) HALT mode power requirements device minimal applied voltage (VCC) decreased without altering state machine device supports three different ways exiting HALT mode first method exiting HALT mode with Multi-Input Wakeup feature port second method with high transition (G7) This method precludes crystal clock configuration (since becomes dedicated output) used with clock configuration third method exiting HALT mode pulling RESET Since crystal ceramic resonator selected oscillator Wakeup signal allowed start chip running immediately since crystal oscillators ceramic resonators have delayed start time reach full amplitude frequency stability IDLE timer used generate fixed delay ensure that oscillator indeed stabilized before allowing instruction execution this case upon detecting valid Wakeup signal only oscillator circuitry enabled IDLE timer loaded with value clocked with instruction cycle clock clock derived dividing oscillator clock down factor Schmitt trigger following inverter chip ensures that IDLE timer clocked only when oscillator sufficiently large amplitude meet Schmitt trigger specifications This Schmitt trigger part oscillator closed loop startup timeout from IDLE timer enables clock signals routed rest chip clock option being used fixed delay introduced optionally control CLKDLY mapped configuration controls whether delay introduced delay included CLKDLY excluded CLKDLY reset CLKDLY cleared reset
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Power Save Modes (Continued)
device mask options associated with HALT mode first mask option enables HALT mode feature while second mask option disables HALT mode With HALT mode enable mask option device will enter exit HALT mode described above With HALT disable mask option device cannot placed HALT mode (writing ``1'' HALT flag will have effect HALT flag will remain ``0'') IDLE MODE device placed IDLE mode writing ``1'' IDLE flag data bit) this mode activities except associated on-board oscillator circuitry IDLE Timer stopped power supply requirements micro-controller this mode operation typically around normal power requirement microcontroller with HALT mode device returned normal operation with reset with Multi-Input Wakeup from Port Alternately microcontroller resumes normal operation from IDLE mode when thirteenth (representing internal clock frequency IDLE Timer toggles This toggle condition thirteenth IDLE Timer latched into T0PND pending flag user option being interrupted with transition thirteenth IDLE Timer interrupt enabled disabled T0EN control Setting T0EN flag enables interrupt vice versa user enter IDLE mode with Timer interrupt enabled this case when T0PND gets device will first execute Timer interrupt service routine then return instruction following ``Enter Idle Mode'' instruction Alternatively user enter IDLE mode with IDLE Timer interrupt disabled this case device will resume normal operation with instruction immediately following ``Enter IDLE Mode'' instruction
Note necessary program instructions following both HALT mode IDLE mode instructions These instructions necessary allow clock resynchronization following HALT IDLE modes
Multi-Input Wakeup
Multi-Input Wakeup feature return (wakeup) device from either HALT IDLE modes Alternately Multi-Input Wakeup Interrupt feature also used generate edge selectable external interrupts
Figure shows Multi-Input Wakeup logic
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FIGURE Multi-Input Wake Logic
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Multi-Input Wakeup (Continued)
Multi-Input Wakeup feature utilizes Port user selects which particular port combination Port bits) will cause device exit HALT IDLE modes selection done through WKEN WKEN 8-bit read write register which contains control every port Setting particular WKEN enables Wakeup from associated port user select whether trigger condition selected Port going either positive edge (low high transition) negative edge (high transition) This selection made WKEDG which 8bit control register with assigned each Port Setting control will select trigger condition negative edge that particular Port Resetting selects trigger condition positive edge Changing edge select entails several steps order avoid pseudo Wakeup condition result edge change First associated WKEN should reset followed edge select change WKEDG Next associated WKPND should cleared followed associated WKEN being re-enabled example serve clarify this procedure Suppose wish change edge select from positive (low going high) negative (high going low) Port where previously been enabled input interrupt program would follows RBIT WKEN Disable Port Wakeup SBIT WKEDG Select going edge sensitivity RBIT WKPND Clear pending SBIT WKEN Re-enable Wakeup port bits have been used outputs then changed inputs with Multi-Input Wakeup Interrupt safety procedure should also followed avoid inherited pseudo wakeup conditions After selected port bits have been changed from output input before associated WKEN bits enabled associated edge select bits WKEDG should reset desired edge selects followed associated WKPND bits being cleared This same procedure should used following reset since port inputs left floating result reset occurrence selected trigger condition Multi-Input Wakeup latched into pending register called WKPND respective bits WKPND register will occurrence selected trigger edge corresponding Port user responsibility clearing these pending flags Since WKPND pending register occurrence selected wakeup conditions device will enter HALT mode Wakeup both enabled pending Consequently user responsibility clearing pending flags before attempting enter HALT mode WKEN WKPND WKEDG read write registers cleared reset PORT INTERRUPTS Port provides user with additional eight fully selectable edge sensitive interrupts which vectored into same service subroutine interrupt from Port shares logic with wake circuitry register WKEN allows interrupts from Port individually enabled disabled register WKEDG specifies trigger condition either positive negative edge Finally register WKPND latches pending trigger conditions (Global Interrupt Enable) enables interrupt function control flag LPEN functions global interrupt enable Port interrupts Setting LPEN flag will enable interrupts vice versa separate global pending flag needed since register WKPND adequate Since Port also used waking device HALT IDLE modes user elect exit HALT IDLE modes either with without interrupt enabled elects disable interrupt then device will restart execution from instruction immediately following instruction that placed microcontroller HALT IDLE modes other case device will first execute interrupt service routine then revert normal operation (See HALT MODE clock option wakeup information
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UART
device contains full-duplex software programmable UART UART (Figure consists transmit shift register receive shift register seven addressable registers follows transmit buffer register (TBUF) receiver buffer register (RBUF) UART control status register (ENU) UART receive control status register (ENUR) UART interrupt clock source register (ENUI) prescaler select register (PSR) baud (BAUD) register register contains flags transmit receive functions this register also determines length data frame bits) value ninth transmission parity selection bits ENUR register flags framing data overrun parity errors while UART receiving Other functions ENUR register include saving ninth received data frame enabling disabling UART's attention mode operation providing additional receiver transmitter status information RCVG XMTG bits determination internal external clock source done ENUI register well selecting number stop bits enabling disabling transmit receive interrupts control flag this register also select UART mode operation asynchronous synchronous
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FIGURE UART Block Diagram
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UART (Continued)
UART CONTROL STATUS REGISTERS operation UART programmed through three registers ENUR ENUI function individual bits these registers follows ENU-UART Control Status Register (Address 0BA)
PSEL1 XBIT9 CHL1 PSEL0 CHL0 RBFL TBMT
PSEL1 PSEL0 PSEL1 PSEL0
Mark(1) Parity enabled) Space(0) Parity enabled)
This enables disables Parity 8-bit modes only) Parity disabled Parity enabled ENUR UART RECEIVE CONTROL STATUS REGISTER RCVG This high whenever framing error occurs goes when goes high XMTG This indicate that UART transmitting gets reset last frame (end last Stop bit) ATTN ATTENTION Mode enabled while this This cleared automatically receiving character with data nine RBIT9 Contains ninth data received when UART operating with nine data bits frame SPARE Reserved future Flags Parity Error Indicates Parity Error been detected since last time ENUR register read Indicates occurrence Parity Error Flags Framing Error Indicates Framing Error been detected since last time ENUR register read Indicates occurrence Framing Error Flags Data Overrun Error Indicates Data Overrun Error been detected since last time ENUR register read Indicates occurrence Data Overrun Error ENUI UART INTERRUPT CLOCK SOURCE REGISTER This enables disables interrupt from transmitter section Interrupt from transmitter disabled Interrupt from transmitter enabled This enables disables interrupt from receiver section Interrupt from receiver disabled Interrupt from receiver enabled XTCLK This selects clock source transmitter section XTCLK clock source selected through BAUD registers XTCLK Signal (L1) used clock XRCLK This selects clock source receiver section XRCLK clock source selected through BAUD registers XRCLK Signal (L1) used clock SSEL UART mode select SSEL Asynchronous Mode SSEL Synchronous Mode
ENUR-UART Receive Control Status Register (Address 0BB)
SPARE RBIT9 ATTN XMTG RCVG
ENUI-UART Interrupt Clock Source Register (Address 0BC)
STP2 STP78 ETDX
used cleared reset reset read-only cannot written software cleared read when read software cleared automatically Writing does affect state
SSEL XRCLK XTCLK
read write
DESCRIPTION UART REGISTER BITS UART CONTROL STATUS REGISTER TBMT This when UART transfers byte data from TBUF register into TSFT register transmission automatically reset when software writes into TBUF register RBFL This when UART received complete character copied into RBUF register automatically reset when software reads character from RBUF This global UART error flag which gets combination errors (DOE occur CHL1 CHL0 These bits select character frame format Parity included generated verified hardware CHL1 CHL0 frame contains eight data bits CHL1 CHL0 frame contains seven data bits CHL1 CHL0 frame contains nine data bits CHL1 CHL0 Loopback Mode selected Transmitter output internally looped back receiver input Nine framing format used XBIT9 PSEL0 Programs ninth transmission when UART operating with nine data bits frame seven eight data bits frame this conjunction with PSEL1 selects parity PSEL1 PSEL0 Parity select bits PSEL1 PSEL0 Parity Parity enabled) PSEL1 PSEL0 Parity Parity enabled)
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UART (Continued)
ETDX (UART Transmit Pin) alternate function assigned Port selected setting ETDX simulate line break generation software should reset ETDX output logic zero through Port data configuration registers STP78 This program last Stop length STP2 This programs number Stop bits transmitted STP2 Stop transmitted STP2 Stop bits transmitted
when framing error occurs goes once goes high TBMT XMTG RBFL RCVG read only bits SYNCHRONOUS MODE this mode data transferred synchronously with clock Data transmitted rising edge received falling edge synchronous clock This mode selected setting SSEL ENUI register input frequency UART same baud rate When external clock input selected data transmit receive performed synchronously with this clock through pins data transmit receive selected with clock output device generates synchronous clock output internal baud rate generator used produce synchronous clock Data transmit receive performed synchronously with this clock FRAMING FORMATS UART supports several serial framing formats (Figure format selected using control bits ENUR ENUI registers first format data transmission (CHL0 CHL1 consists Start seven Data bits (excluding parity) Stop bits applications using parity parity generated verified hardware second format (CHL0 CHL1 consists Start eight Data bits (excluding parity) Stop bits Parity generated verified hardware third format transmission (CHL0 CHL1 consists Start nine Data bits Stop bits This format also supports UART ``ATTENTION'' feature When operating this format eight bits TBUF RBUF used data ninth data transmitted received using bits ENUR registers called XBIT9 RBIT9 RBIT9 read only Parity generated verified this mode above framing formats last Stop programmed length Stop bits selected (selected) second Stop will length parity enabled disabled located register Parity selected 8-bit modes only parity enabled (PEN parity selection then performed PSEL0 PSEL1 bits located register Note that XBIT9 PSEL0 located register serves mutually exclusive functions This programs ninth transmission when UART operating with nine data bits frame There parity selection this framing format other framing formats XBIT9 needed PSEL0 used conjunction with PSEL1 select parity frame formats receiver differ from transmitter number Stop bits required receiver only requires Stop frame regardless setting Stop selection bits control register Note that implicit assumption made full duplex UART operation that framing formats same transmitter receiver
Associated Pins
Data transmitted received alternate function assigned Port selected setting ETDX ENUI register) inherent function Port requiring setup baud rate clock UART generated onchip taken from external source Port (CKX) external clock either input output determined Port Configuration Data registers (Bit input accepts clock signal which selected drive transmitter receiver output presents internal Baud Rate Generator output
UART Operation
UART modes operation asynchronous mode synchronous mode ASYNCHRONOUS MODE This mode selected resetting SSEL ENUI register) zero input frequency UART times baud rate TSFT TBUF registers double-buffer data transmission While TSFT shifting current character TBUF register loaded software with next byte transmitted When TSFT finishes transmitting current character contents TBUF transferred TSFT register Transmit Buffer Empty Flag (TBMT register) TBMT flag automatically reset UART when software loads character into TBUF register There also XMTG which indicate that UART transmitting This gets reset last frame (end last Stop bit) TBUF read write register RSFT RBUF registers double-buffer data being received UART receiver continually monitors signal level detect beginning Start Upon sensing this level waits half time samples again still receiver considers this valid Start remaining bits character frame each sampled single time mid-bit position Serial data input shifted into RSFT register Upon receiving complete character contents RSFT register copied into RBUF register Received Buffer Full Flag (RBFL) RBFL automatically reset when software reads character from RBUF register RBUF read only register There also RCVG which high
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UART Operation (Continued)
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FIGURE Framing Formats UART INTERRUPTS UART capable generating interrupts Interrupts generated Receive Buffer Full Transmit Buffer Empty Both interrupts have individual interrupt vectors bytes program memory space reserved each interrupt vector vectors located addresses 0xEC 0xEF program memory space interrupts individually enabled disabled using Enable Transmit Interrupt (ETI) Enable Receive Interrupt (ERI) bits ENUI register interrupt from Transmitter pending remains pending long both TBMT bits remove this interrupt software must either clear write TBUF register (thus clearing TBMT bit) interrupt from receiver pending remains pending long both RBFL bits remove this interrupt software must either clear read from RBUF register (thus clearing RBFL bit) source selected BAUD registers Internally basic baud clock created from oscillator frequency through two-stage divider chain consisting (increments prescaler 11-bit binary counter (Figure divide factors specified through read write registers shown Figure Note that 11-bit Baud Rate Divisor spills over into Prescaler Select Register (PSR) cleared upon reset shown Table Prescaler Factor corresponds CLOCK This condition UART power down mode where UART clock turned power saving purpose user must also turn UART clock when different baud rate chosen correspondences between 5-bit Prescaler Select Prescaler factors shown Table There many ways calculate divisor factors particularly effective method would achieve 8432 frequency coming first stage 8432 prescaler output then used drive software programmable baud rate counter create clock following baud rates 1200 1800 2400 3600 4800 7200 9600 19200 38400 (Table III) Other baud rates created using appropriate divisors clock then divided provide rate serial shift registers transmitter receiver
Baud Clock Generation
clock inputs transmitter receiver sections UART individually selected come either from external source (port from
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Baud Clock Generation (Continued)
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FIGURE UART BAUD Clock Generation
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FIGURE UART BAUD Clock Divisor Registers
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Baud Clock Generation (Continued)
TABLE Baud Rate Divisors 8432 Prescaler Output) Baud Rate (110 (134 1200 1800 2400 3600 4800 7200 9600 19200 38400 Baud Rate Divisor (N-1) 1046 TABLE Prescaler Factors Prescaler Select 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Prescaler Factor CLOCK
Note entries Table assume prescaler output 8432 asynchronous mode baud rate could high 625k
example considering Asynchronous Mode clock prescaler factor selected 8432 entry available Table 8432 prescaler output then used with proper Baud Rate Divisor (Table obtain different baud rates baud rate 19200 entry Table value from Table III) Baud Rate Divisor) Baud Rate 8432 19200 divide performed because asynchronous mode input frequency UART times baud rate equation calculate baud rates given below actual Baud Rate found from
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Baud Clock Generation (Continued)
Where Baud Rate frequency Baud Rate Divisor (Table III) Prescaler Divide Factor selected value Prescaler Select Register (Table
Note Synchronous Mode divisor replaced
Note that framing format this mode nine format Start nine data bits Stop bits Parity generated verified this mode
Attention Mode
UART Receiver section supports alternate mode operation referred ATTENTION Mode This mode operation selected ATTN ENUR register data format transmission must also selected having nine Data bits either Stop bits ATTENTION mode operation intended networking device with other processors Typically such environments messages consists device addresses indicating which several destinations should receive them actual data This Mode supports scheme which addresses flagged having ninth data field ninth reset zero byte Data byte While ATTENTION mode UART monitors communication flow ignores characters until address character received Upon receiving address character UART signals that character ready setting RBFL flag which turn interrupts processor UART Receiver interrupts enabled ATTN also cleared automatically this point that data characters well address characters recognized Software examines contents RBUF responds deciding either accept subsequent data stream leaving ATTN reset) wait until next address character seen setting ATTN again) Operation UART Transmitter affected selection this Mode value ninth transmitted programmed setting XBIT9 appropriately value ninth received obtained reading RBIT9 Since this located ENUR register where error flags reside operation will reset error flags
Example Asynchronous Mode Crystal Frequency Desired baud rate 9600 Using above equation calculated first 106) 9600) divided each Prescaler Factor (Table obtain value closest integer This factor happens programmed value (from Table III) should Using above values calculated 106) 9615 error (9615 9600) 9600
Effect HALT IDLE
UART logic reinitialized when either HALT IDLE modes entered This reinitialization sets TBMT flag resets read only bits UART control status registers Read Write bits remain unchanged Transmit Buffer (TBUF) affected Transmit Shift register (TSFT) bits receiver registers RBUF RSFT affected device will exit from HALT IDLE modes when Start character detected (L3) This feature obtained using Multi-Input Wakeup scheme provided device Before entering HALT IDLE modes user program must select Wakeup source This selection done setting WKEN (Wakeup Enable) register Wakeup trigger condition then selected high transition This done WKEDG register (Bit device halted crystal oscillator used Wakeup signal will start chip running immediately because finite start time requirement crystal oscillator idle timer (T0) generates fixed (256 delay ensure that oscillator indeed stabilized before allowing device execute code user consider this delay when data transfer expected immediately after exiting HALT mode
Comparators
device contains differential comparators each with pair inputs (positive negative) output Ports used comparators following Port assignment Comparator1 negative input Comparator1 positive input Comparator1 output Comparator2 negative input Comparator2 positive input Comparator2 output Comparator Select Register (CMPSL) used enable comparators read outputs comparators internally enable outputs comparators pins control bits (enable output enable) result associated with each comparator comparator result bits (CMP1RD CMP2RD) read only bits which will read zero associated comparator enabled Comparator Select Register cleared with reset resulting comparators being disabled comparators should also disabled before entering either HALT IDLE modes order save power configuration CMPSL register follows
Diagnostic
Bits CHARL0 CHARL1 register provide loopback feature diagnostic testing UART When these bits following occur receiver input (RDX) internally connected transmitter output (TDX) output Transmitter Shift Register ``looped back'' into Receive Shift Register input this mode data that transmitted immediately received This feature allows processor verify transmit receive data paths UART
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Comparators (Continued)
CMPSL REGISTER (ADDRESS X'00B7) CMPSL register contains following bits CMP1EN CMP1RD Enable comparator Comparator result (this read only which will read comparator enabled) Selects comparator output provided that CMPIEN enable comparator Enable comparator Comparator result (this read only which will read comparator enabled) Selects comparator output provided that CMP2EN enable comparator
Interrupts
device supports vectored interrupt scheme supports total fourteen interrupt sources following table lists possible interrupt sources their arbitration ranking memory locations reserved interrupt vector each source bytes program memory space reserved each interrupt source interrupt sources except software interrupt maskable Each maskable interrupts have Enable more Pending bits maskable interrupt active associated enable pending bits interrupt active then processor will interrupted soon ready start executing instruction except above conditions happen during Software Trap service routine This exception described Software Trap sub-section interruption process accomplished with INTR instruction (opcode which jammed inside Instruction Register replaces opcode about executed following steps performed every interrupt (Global Interrupt Enable) reset address instruction about executed pushed into stack (Program Counter) branches address 00FF This procedure takes cycles execute Vector Address Hi-Low Byte 0yFE 0yFF 0yFC 0yFD Underflow Underflow BUSY 0yFA 0yFB 0yF8 0yF9 0yF6 0yF7 0yF4 0yF5 0yF2 0yF3 0yF0 0yF1 Receive Transmit Underflow Underflow Port Edge Reserved 0yEE 0yEF 0yEC 0yED 0yEA 0yEB 0yE8 0yE9 0yE6 0yE7 0yE4 0yE5 0yE2 0yE3 0yE0 0yE1
CMP10E CMP2EN CMP2RD
CMP20E
Unused CMP20E CMP2RD CMP2EN CMP10E CMP1RD CMP1EN Unused
Note that unused bits CMPSL used software flags Comparator outputs have same spec Ports except that rise fall times symmetrical
Arbitration Ranking Highest (10) (11) (12) (13) (14) (15) (16) Lowest
Source Software Reserved External Timer Timer Timer MICROWIRE PLUS Reserved UART UART Timer Timer Timer Timer Port Wakeup Default
Description INTR Instruction
variable which represents block vector table must located same 256-byte block except located last address block this case table must next block
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Interrupts (Continued) this time since other maskable interrupts disabled user free whatever context switching required saving context machine stack with PUSH instructions user would then program (Vector Interrupt Select) instruction order branch interrupt service routine highest priority interrupt enabled pending time Note that this necessarily interrupt that caused branch address location 00FF prior context switching Thus interrupt with higher rank than which caused interruption becomes active before decision which interrupt service made then interrupt with higher rank will override lower ones will acknowledged lower priority interrupt(s) still pending however will cause another interrupt immediately following completion interrupt service routine associated with higher priority interrupt just serviced This lower priority interrupt will occur immediately following RETI (Return from Interrupt) instruction interrupt service routine just completed Inside interrupt service routine associated pending cleared software RETI (Return from Interrupt) instruction interrupt service routine will (Global Interrupt Enable) allowing processor interrupted again another interrupt active pending instruction looks active interrupts time executed performs indirect jump beginning service routine with highest rank addresses different interrupt service routines called vectors chosen user stored table starting 01E0 (assuming that located between 00FF 01DF) vectors 15-bit wide therefore occupy locations vector table must located same 256byte block (0y00 0yFF) except located last
address block this case table must next block vector table cannot inserted first 256-byte block vector maskable interrupt with lowest rank located 0yE0 (Hi-Order byte) 0yE1 (Lo-Order byte) forth increasing rank number vector maskable interrupt with highest rank located 0yFA (Hi-Order byte) 0yFB (Lo-Order byte) Software Trap highest rank vector located 0yFE 0yFF accident gets executed interrupt active then (Program Counter) will branch vector located 0yE0 0yE1 WARNING Default interrupt handler routine must present minimum this handler should confirm that cleared (this indicates that interrupt sequence been taken) take care required housekeeping restore context return Some sort Warm Restart procedure should implemented These events occur without error part system designer programmer
Note There always possibility interrupt occurring during instruction which attempting reset other interrupt enable this occurs when single cycle instruction being used reset interrupt enable interrupt enable will reset interrupt still occur This because interrupt processing started same time interrupt being reset avoid this scenario user should always three four cycle instruction reset interrupt enable bits
Figure shows Interrupt block diagram
SOFTWARE TRAP Software Trap (ST) special kind non-maskable interrupt which occurs when INTR instruction (used acknowledge interrupts) fetched from placed inside instruction register This happen when pointing beyond available address space when stack over-popped
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FIGURE Interrupt Block Diagram
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Interrupts (Continued)
When occurs user re-initialize stack pointer recovery procedure (similar reset necessarily containing same initialization procedures) before restarting occurrence latched into pending affected pending (not accessible user) used inhibit other interrupts direct program service routine with instruction RPND instruction used clear software interrupt pending This pending also cleared reset highest rank among interrupts Nothing (except another interrupt being serviced
Clock Monitor
Clock Monitor aboard device selected deselected under program control Clock Monitor guaranteed reject clock instruction cycle clock greater equal This equates clock input rate greater equal
WATCHDOG Operation
WATCHDOG Clock Monitor disabled during reset device comes reset with WATCHDOG armed WATCHDOG Window Select bits (bits WDSVR Register) Clock Monitor (bit WDSVR Register) enabled Thus Clock Monitor error will occur after coming reset instruction cycle clock frequency reached minimum specified value including case where oscillator fails start WDSVR register written only once after reset data (bits through WDSVR Register) must match valid write This write WDSVR register involves irrevocable choices selection WATCHDOG service window (ii) enabling disabling Clock Monitor Hence first write WDSVR Register involves selecting deselecting Clock Monitor select WATCHDOG service window match WATCHDOG data Subsequent writes WDSVR register will compare value being written user WATCHDOG service window value data (bits through WDSVR Register Table shows sequence events that occur user must service WATCHDOG least once before upper limit service window expires WATCHDOG serviced more than once every lower limit service window user service WATCHDOG many times wished time period between lower upper limits service window first write WDSVR Register also counted WATCHDOG service WATCHDOG output associated with This WDOUT port WDOUT active WDOUT high impedance state inactive state Upon triggering WATCHDOG logic will pull WDOUT (G1) additional cycles after signal level WDOUT goes below lower Schmitt trigger threshold After this delay device will stop forcing WDOUT output WATCHDOG service window will restart when WDOUT goes high recommended that user WDOUT back through resistor order pull WDOUT high WATCHDOG service while WDOUT signal active will ignored state WDOUT guaranteed reset powers then WATCHDOG will time WDOUT will enter high impedance state Clock Monitor forces upon detecting clock frequency error Clock Monitor error will continue until clock frequency reached minimum specified value after which output will enter high impedance TRI-STATE mode following clock cycles Clock Monitor generates continual Clock Monitor error oscillator fails start fails reach minimum specified frequency specification Clock Monitor follows clock rejection Guaranteed clock rejection
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WATCHDOG
device contains WATCHDOG clock monitor WATCHDOG designed detect user program getting stuck infinite loops resulting loss program control ``runaway'' programs Clock Monitor used detect absence clock very slow clock below specified rate WATCHDOG consists independent logic blocks UPPER LOWER UPPER establishes upper limit service window LOWER defines lower limit service window Servicing WATCHDOG consists writing specific value WATCHDOG Service Register named WDSVR which memory mapped This value composed three fields consisting 2-bit Window Select 5-bit Data field 1-bit Clock Monitor Select field Table shows WDSVR register TABLE WATCHDOG Service Register (WDSVR) Window Select Data Clock Monitor
lower limit service window fixed 2048 instruction cycles Bits WDSVR register allow user pick upper limit service window Table shows four possible combinations lower upper limits WATCHDOG service window This flexibility choosing WATCHDOG service window prevents undue burden user software Bits WDSVR register represent 5bit Data field data fixed 01100 WDSVR Register Clock Monitor Select TABLE WATCHDOG Service Window Select WDSVR WDSVR Service Window (Lower-Upper Limits) Cycles 2k-16k Cycles 2k-32k Cycles 2k-64k Cycles
WATCHDOG Operation (Continued)
WATCHDOG CLOCK MONITOR SUMMARY following salient points regarding WATCHDOG CLOCK MONITOR should noted Both WATCHDOG CLOCK MONITOR detector circuits inhibited during RESET
With single-pin oscillator mask option selected
CLKDLY reset WATCHDOG service window will resume following HALT mode from where left before entering HALT mode
With crystal oscillator mask option selected with
single-pin oscillator mask option selected CLKDLY WATCHDOG service window will selected value from WDSVR following HALT Consequently WATCHDOG should serviced least 2048 instruction cycles following HALT must serviced within selected window avoid WATCHDOG error
Following RESET WATCHDOG CLOCK MONITOR both enabled with WATCHDOG having maximum service window selected
WATCHDOG service window CLOCK MONITOR enable disable option only changed once during initial WATCHDOG service following RESET
initial WATCHDOG service must match data
value WATCHDOG Service register WDSVR order avoid WATCHDOG error
IDLE timer initialized with RESET user sync IDLE counter cycle with
IDLE counter (T0) interrupt monitoring T0PND flag T0PND flag whenever thirteenth IDLE counter toggles (every 4096 instruction cycles) user responsible resetting T0PND flag
Subsequent WATCHDOG services must match three
data fields WDSVR order avoid WATCHDOG errors
correct data value cannot read from
WATCHDOG Service register WDSVR attempt read this data value 01100 from WDSVR will read data value
hardware WATCHDOG service occurs just device exits IDLE mode Consequently WATCHDOG should serviced least 2048 instruction cycles following IDLE must serviced within selected window avoid WATCHDOG error
WATCHDOG detector circuit inhibited during both
HALT IDLE modes
Following RESET initial WATCHDOG service (where
service window CLOCK MONITOR enable disable must selected) programmed anywhere within maximum service window instruction cycles) initialized RESET Note that this initial WATCHDOG service programmed within initial 2048 instruction cycles without causing WATCHDOG error
CLOCK MONITOR detector circuit active during
both HALT IDLE modes Consequently device inadvertently entering HALT mode will detected CLOCK MONITOR error (provided that CLOCK MONITOR enable option been selected program)
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Detection Illegal Conditions
device detect various illegal conditions resulting from coding errors transient noise power supply voltage drops runaway programs Reading undefined gets zeros opcode software interrupt zero program fetches instructions from undefined this will force software interrupt thus signaling that illegal condition occurred subroutine stack grows down each call (jump subroutine) interrupt PUSH grows each return stack pointer initialized location during reset Consequently there more returns than calls stack pointer will point addresses (which undefined RAM) Undefined from addresses (Segment other segments Segments read which turn will cause program return address 7FFF This undefined location instruction fetched (all 0's) from this location will generate software interrupt signaling illegal condition Thus chip detect following illegal conditions Executing from undefined Over ``POP''ing stack having more returns than calls When software interrupt occurs user re-initialize stack pointer recovery procedure before restarting (this recovery program probably similar that following reset might contain same program initialization procedures) recovery program should reset software interrupt pending using RPND instruction
MICROWIRE PLUS
MICROWIRE PLUS serial synchronous communications interface MICROWIRE PLUS capability enables device interface with National Semiconductor's MICROWIRE peripherals converters display drivers E2PROMs with other microcontrollers which support MICROWIRE interface consists 8-bit serial shift register (SIO) with serial data input (SI) serial data output (SO) serial shift clock (SK) Figure shows block diagram MICROWIRE PLUS logic
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FIGURE MICROWIRE PLUS Block Diagram shift clock selected from either internal source external source Operating MICROWIRE PLUS arrangement with internal clock source called Master mode operation Similarly operating MICROWIRE PLUS arrangement with external shift clock called Slave mode operation CNTRL register used configure control MICROWIRE PLUS mode MICROWIRE PLUS MSEL CNTRL register master mode clock rate selected bits CNTRL register Table VIII details different clock rates that selected
TABLE WATCHDOG Service Actions Data Match Don't Care Mismatch Don't Care Window Data Match Mismatch Don't Care Don't Care Clock Monitor Match Don't Care Don't Care Mismatch Action Valid Service Restart Service Window Error Generate WATCHDOG Output Error Generate WATCHDOG Output Error Generate WATCHDOG Output
TABLE VIII MICROWIRE PLUS Master Mode Clock Select Where instruction cycle clock
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MICROWIRE PLUS (Continued)
MICROWIRE PLUS OPERATION Setting BUSY register causes MICROWIRE PLUS start shifting data gets reset when eight data bits have been shifted user reset BUSY software allow less than bits shift enabled interrupt generated when eight data bits have been shifted device enter MICROWIRE PLUS mode either Master Slave Figure shows microcontroller devices several peripherals interconnected using MICROWIRE PLUS arrangements Warning register should only loaded when clock Loading register while clock high will result undefined data register clock normally when shifting Setting BUSY flag when input clock high MICROWIRE PLUS slave mode cause current clock shift register narrow safety BUSY flag should only when input clock MICROWIRE PLUS Master Mode Operation MICROWIRE PLUS Master mode operation shift clock (SK) generated internally device MICROWIRE Master always initiates data exchanges MSEL CNTRL register must enable functions onto Port pins must also selected outputs setting appropriate bits Port configuration register Table summarizes settings required Master mode operation MICROWIRE PLUS Slave Mode Operation MICROWIRE PLUS Slave mode operation clock generated external source Setting MSEL CNTRL register enables functions onto Port must selected input selected output setting resetting appropriate bits Port configuration register Table summarizes settings required enter Slave mode operation user must BUSY flag immediately upon entering Slave mode This will ensure that data bits sent Master will shifted properly After eight clock pulses BUSY flag will cleared sequence repeated Alternate Phase Operation device allows either normal clock alternate phase clock shift data register both modes normally normal mode data shifted rising edge clock data shifted falling edge clock register shifted each falling edge clock alternate phase operation data shifted falling edge clock shifted rising edge clock control flag SKSEL allows either normal clock alternate clock selected Resetting SKSEL causes MICROWIRE PLUS logic clocked from normal signal Setting SKSEL flag selects alternate clock SKSEL mapped into configuration SKSEL flag will power reset condition selecting normal signal TABLE This table assumes that control flag MSEL (SO) (SK) Config Config Operation
MICROWIRE PLUS Master
TRI- MICROWIRE PLUS STATE Master MICROWIRE PLUS Slave
TRI- MICROWIRE PLUS STATE Slave
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FIGURE MICROWIRE PLUS Application
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Memory
ports registers (except mapped into data memory address space Address 0000 006F 0070 007F xx80 xxAF xxB0 XXB1 xxB2 xxB3 xxB4 xxB5 xxB6 xxB7 xxB8 xxB9 xxBA xxBB xxBC xxBD xxBE xxBF xxC0 xxC1 xxC2 xxC3 xxC4 xxC5 xxC6 xxC7 xxC8 xxC9 xxCA xxCB xxCC xxCD xxCF Contents On-Chip bytes (112 bytes) Unused Address Space (Reads Ones) Unused Address Space (Reads Undefined Data) Timer Lower Byte Timer Upper Byte Timer Autoload Register T3RA Lower Byte Timer Autoload Register T3RA Upper Byte Timer Autoload Register T3RB Lower Byte Timer Autoload Register T3RB Upper Byte Timer Control Register Comparator Select Register (CMPSL) UART Transmit Buffer (TBUF) UART Receive Buffer (RBUF) UART Control Status Register (ENU) UART Receive Control Status Register (ENUR) UART Interrupt Clock Source Register (ENUI) UART Baud Register (BAUD) UART Prescale Select Register (PSR) Reserved UART Timer Lower Byte Timer Upper Byte Timer Autoload Register T2RA Lower Byte Timer Autoload Register T2RA Upper Byte Timer Autoload Register T2RB Lower Byte Timer Autoload Register T2RB Upper Byte Timer Control Register WATCHDOG Service Register (Reg WDSVR) MIWU Edge Select Register (Reg WKEDG) MIWU Enable Register (Reg WKEN) MIWU Pending Register (Reg WKPND) Reserved Reserved Reserved Address xxD0 xxD1 xxD2 xxD3 xxD4 xxD5 xxD6 xxD7 xxD8 xxD9 xxDA xxDB xxDC xxDD xxDF xxE0 xxE5 xxE6 xxE7 xxE8 xxE9 xxEA xxEB xxEC xxED xxEE xxEF xxF0 xxFC xxFD xxFE xxFF 0100 017F 0200 027F 0300 037F Contents Port Data Register Port Configuration Register Port Input Pins (Read Only) Reserved Port Port Data Register Port Configuration Register Port Input Pins (Read Only) Port Input Pins (Read Only) Port Data Register Port Configuration Register Port Input Pins (Read Only) Reserved Port Port Reserved Port Reserved Control Registers Timer Autoload Register T1RB Lower Byte Timer Autoload Register T1RB Upper Byte ICNTRL Register MICROWIRE PLUS Shift Register Timer Lower Byte Timer Upper Byte Timer Autoload Register T1RA Lower Byte Timer Autoload Register T1RA Upper Byte CNTRL Control Register Register On-Chip Mapped Registers Register Register Register Register On-Chip Bytes On-Chip Bytes On-Chip Bytes
Reading memory locations 0070H-007FH (Segment will return ones Reading unused memory locations 0080H-00AFH (Segment will return undefined data Reading memory locations from other Segments Segment Segment will return ones
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Addressing Modes
There addressing modes operand addressing four transfer control OPERAND ADDRESSING MODES Register Indirect This ``normal'' addressing mode operand data memory addressed pointer pointer Register Indirect (with auto post increment decrement pointer) This addressing mode used with instructions operand data memory addressed pointer pointer This register indirect mode that automatically post increments decrements register after executing instruction Direct instruction contains 8-bit address field that directly points data memory operand Immediate instruction contains 8-bit immediate field operand Short Immediate This addressing mode used with Load Immediate instruction instruction contains 4-bit immediate field operand Indirect This addressing mode used with LAID instruction contents accumulator used partial address (lower bits accessing data operand from program memory TRANSFER CONTROL ADDRESSING MODES Relative This mode used instruction with instruction field being added program counter program location range from allow 1-byte relative jump implemented instruction) There ``pages'' when using since bits used Absolute This mode used with instructions with instruction field bits replacing lower bits program counter (PC) This allows jumping location current program memory segment Absolute Long This mode used with JMPL JSRL instructions with instruction field bits replacing entire bits program counter (PC) This allows jumping location program memory space Indirect This mode used with instruction contents accumulator used partial address (lower bits accessing location program memory contents this program memory location serve partial address (lower bits jump next instruction
Note special case Indirect Transfer Control addressing mode where double byte vector associated with interrupt transferred from adjacent addresses program memory into program counter (PC) order jump associated interrupt service routine
Instruction
Register Symbol Definition Registers 8-Bit Accumulator Register 8-Bit Address Register 8-Bit Address Register 8-Bit Segment Register 8-Bit Stack Pointer Register 15-Bit Program Counter Register Upper Bits Lower Bits Register Carry Register Half Carry Register Global Interrupt Enable Interrupt Vector Upper Byte Interrupt Vector Lower Byte
Symbols Meml Memory Indirectly Addressed Register Memory Indirectly Addressed Register Direct Addressed Memory Direct Addressed Memory Direct Addressed Memory Immediate Data 8-Bit Immediate Data Register Memory Addresses (Includes Number Loaded with Exchanged with
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Instruction (Continued)
INSTRUCTION SUBC ANDSZ IFEQ IFEQ IFNE IFGT IFBNE DRSZ SBIT RBIT IFBIT RPND LAID DCOR SWAP IFNC PUSH JMPL JSRL RETSK RETI INTR Meml Meml Meml Meml Meml Meml Meml Meml Meml Meml with Carry Subtract with Carry Logical Logical Immed Skip Zero Logical Logical EXclusive EQual EQual Equal Greater Than Equal Decrement Skip Zero Reset Reset PeNDing Flag EXchange with Memory EXchange with Memory LoaD with Memory LoaD with Memory LoaD with Immed LoaD Memory Immed LoaD Register Memory Immed EXchange with Memory EXchange with Memory LoaD with Memory LoaD with Memory LoaD Memory Immed CLeaR INCrement DECrement Load InDirect from Decimal CORrect Rotate Right thru Rotate Left thru SWAP nibbles Reset stack into PUSH onto stack Vector Interrupt Service Routine Jump absolute Long Jump absolute Jump relative short Jump SubRoutine Long Jump SubRoutine Jump InDirect RETurn from subroutine RETurn SKip RETurn from Interrupt Generate Interrupt OPeration Meml Meml Carry Half Carry MemI Carry Half Carry Meml Skip next Imm) Meml Meml Compare next Compare Meml next Meml Compare Meml next Meml Compare Meml next Meml next lower bits Skip (bit immediate) true next instruction Reset Software Interrupt Pending Flag Meml correction (follows SUBC) true next instruction true next instruction bits 32k) bits) except SPb1 SPb2 SPb1 SPb2 SPb1 SPb1 skip next instruction SPb1 SPb1 SPb2
Addr Addr Disp Addr Addr
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Instruction Execution Time
Most instructions single byte (with immediate addressing mode instructions taking bytes) Most single byte instructions take cycle time execute Skipped instructions require number cycles skipped where equals number bytes skipped instruction opcode BYTES CYCLES INSTRUCTION table details Bytes Cycles Instruction following table shows number bytes cycles each instruction format byte cycle Arithmetic Logic Instructions SUBC IFEQ IFNE IFGT IFBNE DRSZ SBIT RBIT IFBIT RPND Direct Immed Instructions Using CLRA INCA DECA LAID DCOR RRCA RLCA SWAPA IFNC PUSHA POPA ANDSZ Transfer Control Instructions JMPL JSRL RETSK RETI INTR
Memory Transfer Instructions Register Indirect IFEQ Direct Immed Register Indirect Auto Incr Decr
Memory location addressed directly
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Opcode Table
Upper Nibble DRSZ DRSZ DRSZ LAID IFNE JMPL JSRL POPA RETSK RETI DECA SBIT SBIT SBIT SBIT SBIT INCA SBIT IFEQ IFNE IFNC SBIT RBIT RBIT RBIT RBIT RBIT RBIT RBIT RLCA SBIT RBIT IFBIT PUSHA IFBIT DCORA IFBNE IFBNE IFBNE IFBNE IFBNE IFBNE IFBNE IFBNE IFBNE IFBNE IFBIT SWAPA IFBNE IFBIT CLRA IFBNE x400-x4FF x500-x5FF x600-x6FF x700-x7FF x800-x8FF x900-x9FF IFGT IFGT IFBIT IFBNE x300-x3FF IFEQ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ RPND IFEQ IFBIT IFBNE x200-x2FF SUBC IFBIT IFBNE x100-x1FF RRCA IFBIT ANDSZ IFBNE x000-x0FF x000-x0FF x100-x1FF x200-x2FF x300-x3FF x400-x4FF x500-x5FF x600-x6FF x700-x7FF x800-x8FF INTR x900-x9FF xA00-xAFF xA00-xAFF xB00-xBFF xB00-xBFF xC00-xCFF xC00-xCFF xD00-xDFF xD00-xDFF xE00-xEFF xE00-xEFF xF00-xFFF xF00-xFFF Lower Nibble
JPb15 JPb31
JPb14 JPb30
JPb13 JPb29
JPb12 JPb28
JPb11 JPb27
JPb10 JPb26
JPb9
JPb25
JPb8
JPb24
JPb7
JPb23
JPb6
JPb22
JPb5
JPb21
JPb4
JPb20
JPb3
JPb19
JPb2
JPb18
JPb1
JPb17
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JPb0
JPb16
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immediate data directly addressed memory location unused opcode Note opcode also opcode IFBIT
Mask Options
mask programmable options shown below options programmed same time pattern submission OPTION CLOCK CONFIGURATION Crystal Oscillator (CKI (CKO) clock generator output crystal resonator with being clock input Single-pin controlled oscillator (CKI available HALT restart general purpose input OPTION HALT Enable HALT mode Disable HALT mode OPTION BONDING 44-Pin PLCC 40-Pin chip driven clock input input which between output clock clock option been selected) input frequency divided down produce instruction cycle clock
Development Support
Summary
iceMASTER IM-COP8 Full feature in-circuit emulation COP8 products full COP8 Basic Feature Family device package specific probes available
COP8 Debug Module Moderate cost in-circuit emulation
development programming unit
COP8
Evaluation Programming Unit EPUCOP888HG cost In-circuit simulation development programming unit development Assembler Linker Librarian Utility Software Development Tool
Assembler COP8-DEV-IBMA installable cross
Compiler COP8C installable cross development Software Tool
EPROM Programmer Support Covering needs
from engineering prototype pilot production full production environments
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Development Support (Continued)
IceMASTER (IM) IN-CIRCUIT EMULATION iceMASTER IM-COP8 full feature based in-circuit emulation tool developed marketed MetaLink Corporation support whole COP8 family products National resale vendor these products Figure configuration iceMASTER IM-COP8 with device specific COP8 Probe provides rich feature developing testing maintaining product
Watch windows content updated automatically each
execution break
Instruction instruction memory register changes displayed source window when single step operation
Single base unit debugger software reconfigurable
support entire COP8 family only probe personality needs change Debugger software processor customized reconfigured from master model file
Processor specific symbolic display registers
level assignments configured from master model file
Real-time in-circuit emulation full 4V-5 operation
range full DC-10 clock Chip options programmable jumper selectable
Halt Idle mode notification On-line HELP customized specific processor using
master model file
Direct connection application board package compatible socket surface mount assembly
Includes copy COP8-DEV-IBMA assembler linker Order Information Base Unit IM-COP8 400-1 IM-COP8 400-2 iceMASTER Probe MHW-888GG40DWPC MHW-888GG44PWPC PLCC iceMASTER base unit 110V power supply iceMASTER base unit 220V power supply
Full kbytes loadable programming space that overlays (replaces) on-chip EPROM On-chip blocks used directly recreated probe necessary
Full frame synchronous trace memory Address instruction unspecified circuit connectable trace lines Display source source) assembly mixed
full hardware configurable break trace trace control pass count increment events Tool integrated interactive symbolic debugger supports both assembler (COFF) Compiler COD) linked object formats
Real time peformance profiling analysis selectable bucket definition
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FIGURE iceMASTER Environment
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Development Support (Continued)
IceMASTER DEBUG MODULE (DM) iceMASTER Debug Module based combination in-circuit emulation tool COP8 based EPROM programming tool developed marketed MetaLink Corporation support whole COP8 family products National resale vendor these products Figure configuration iceMASTER Debug Module moderate cost development tool capability in-circuit emulation specific COP8 microcontroller addition serves programming tool COP8 EPROM product families Summary features follows
Instruction instruction memory register changes displayed when single step operation
Debugger software processor customized reconfigured from master model file
Processor specific symbolic display registers
level assignments configured from master model file
Halt Idle mode notification Programming menu supports full product line programmable EPROM COP8 products Program data taken directly from overlay
Programming PLCC PLCC parts requires
external programming adapters
Real-time in-circuit emulation full operating voltage
range operation full DC-10 clock
processor pins cabled application
development board with package compatible cable socket surface mount assembly
Includes wall-mount power supply On-board generator from input connection
external supply supported Requires level adjustment family programming specification (correct level provided on-screen pop-down display) Online HELP customized specific processor using master model file
Full kbytes loadable programming space that overlays (replaces) on-chip EPROM On-chip blocks used directly recreated necessary
On-line HELP customized specific processor using
master model file
frames synchronous trace memory display
source source) assembly mixed most recent history prior break available trace memory
Includes copy COP8-DEV-IBMA assembler linker Order Information Debug Module Unit COP8-DM 888GG Cable Adapters DM-COP8 DM-COP8 PLCC
Configured break points uses INTR instruction which
modestly intrusive
Software only supported features selectable Tool integrated interactive symbolic debugger supports both
Assembler (COFF) Compiler COD) linked
object formats
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FIGURE COP8-DM Environment
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Development Support (Continued)
IceMASTER EVALUATION PROGRAMMING UNIT (EPU) iceMASTER EPU-COP888HG based in-circuit simulation tool support feature family COP8 products Figure configuration simulation capability very cost means evaluating general COP8 architecture addition programming capability with added adapters programming whole COP8 product family EPROM products product includes following features
Tool integrated interactive symbolic debugger supports both assembler (COFF) Compiler COD) linked object formats
Instruction instruction memory register changes displayed when single step operation
Processor specific symbolic display registers
level assignments configured from master model file
Halt Idle mode notification Restart requires special handling
Non-real-time in-circuit simulation
Program overlay memory resident instructions downloaded over RS-232 executed Approximate performance ages supported processor pins cabled application development environment
Programming menu supports full product line programmable EPROM COP8 products Only socket available unit Adapters available other part package configurations
Includes 40-pin cable adapter Other target pack-
Integral wall mount power supply provides develops required program parts
Includes copy COP8-DEV-IBMA assembler linker
Order Information Evaluation Programming Unit EPU-COP888GG Evaluation Programming Unit with debugger programmer control software programming socket
Full kbytes loadable programming space that overlays (replaces) on-chip EPROM On-chip blocks used directly recreated necessary
On-chip timer watch-dog execution well synchronized instruction simulation
frames synchronous trace memory display
source source) assembly mixed most recent history prior break available trace memory COP8-PGMA-DS COP8-PGMA-DS44P
General Programming Adapters SOIC adapter
software configured break points uses INTR instruction which modestly intrusive
Common look-feel debugger software across MetaLink products only supported features selectable
SOIC plus PLCC adapter
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FIGURE CPU-COP8 Tool Environment
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Development Support (Continued)
COP8 ASSEMBLER LINKER SOFTWARE DEVELOPMENT TOOL National Semiconductor offers relocateable COP8 macro cross assembler linker librarian utility software development tool Features summarized follows COP8 COMPILER Compiler developed marketed Byte Craft Limited COP8C compiler fully integrated development tool specifically designed support compact embedded configuration COP8 family products Features summarized follows
Basic Feature Family instruction ``device''
type
ANSI with some restrictions extensions that optimize development COP8 embedded application
Integrated utilities generate code file outputs DUMPCOFF utility This product integrated part MetaLink tools development fully supported MetaLink debugger ordered separately bundled with MetaLink products additional cost Order Information Assembler COP8-DEV-IBMA Assembler installable Floppy Disk Drive format Periodic upgrades most recent version available National's Internet
Nested macro capability Extensive assembler directives Supported platform Generates National standard COFF output files Integrated Linker Librarian
BITS data type extension Register declaration
with direct level definitions
pragma
language support interrupt routines Expert system rule based code geration optimization
Performs consistency checks against architectural
definitions target COP8 device
Generates program memory code Supports linking compiled object COP8 assembled
object formats
Global optimization linked code Symbolic debug load format fully source level supported
MetaLink debugger
Approved List Manufacturer Microsystems North America (800) 225-2102 (713) 688-4600 (713) 688-0920 (800) 426-1045 (206) 881-6444 (206) 882-1043 (510) 623-8860 Europe
49-8152-4183 49-8856-932616
Asia
852-234-16611 852-2710-8121
Data
44-0734-440011
Call North America
HI-LO
Call Asia
886-2-764-0215 886-2-756-6403
Technology MetaLink
(800) 624-8949 (919) 430-7915 (800) 638-2423 (602) 926-0797 (602) 693-0681 (408) 263-6667
44-1226-767404 0-1226-370-434 49-80 9156 96-0 49-80 9123 41-1-9450300 852-737-1800
Systems General Needhams
886-2-9173005 886-2-911-1283
(916) 924-8037 (916) 924-8065
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Development Support (Continued)
SINGLE-CHIP EMULATOR SUPPORT COP8 family supported single-chip emulators detailed information refer emulator specific datasheet emulator selection table below Emulator Ordering Information Device Number COP87L88GGV-XE COP87L88GGN-XE Clock Option Crystal HALT Crystal HALT Package PLCC Emulates COP888HG COP888HG DIAL-A-HELPER Standard Modem Modem CANADA EUROPE Baud Set-up (800) NSC-MICRO (800) 672-6427 0-8141-351332 Length Parity Stop 8-Bit None Days
Operation
INDUSTRY WIDE EPROM PROGRAMMING SUPPORT Programming support addition MetaLink development tools provided full range independent approved vendors meet needs from engineering laboratory full production AVAILABLE LITERATURE more information please COP8 Basic Family User's Manual Literature Number 620895 COP8 Feature Family User's Manual Literature Number 620897 National's Family 8-bit Microcontrollers COP8 Selection Guide Literature Number 630009 DIAL-A-HELPER Dial-A-Helper service provided Microcontroller Applications group Dial-A-Helper Electronic Information System that accessed Bulletin Board System (BBS) data modem site Internet standard client application site Internet using standard Internet browser such Netscape Mosaic Dial-A-Helper system provides access automated information storage retrieval system system capabilities include MESSAGE SECTION (electronic mail when accessed BBS) communication from Microcontroller Applications Group FILE SECTION which consists several file areas where valuable application software utilities could found
DIAL-A-HELPER nscmicro user anonymous password username yourhost site domain DIAL-A-HELPER WorldWide Browser nscmicro National Semiconductor WorldWide WorldWide http national CUSTOMER RESPONSE CENTER Complete product information technical support available from National's customer response centers CANADA email EUROPE email Deutsch English Fran Italiano JAPAN ASIA Beijing Shanghai (800) 272-9959 support tevm2
europe support
180-530 180-532 180-532 180-534 81-043-299-2309
10-6856-8601 21-6415-4092
Hong Kong 852) 2737-1600 Korea Malaysia Singapore Taiwan AUSTRALIA INDIA 2-3771-6909 60-4) 644-9061 255-2226
886-2-521-3288
3-9558-9999 80-559-9467
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Physical Dimensions inches (millimeters) unless otherwise noted
Molded Dual-In-Line Package Order Number COP688HG-XXX COP888HG-XXX Package Number N40A
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Plastic Leaded Chip Carrier Order Number COP688HG-XXX COP888HG-XXX Package Number V44A
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COP688HG COP888HG 8-Bit Microcontroller with UART Three Multi-Function Timers
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Plastic Quad Flat Pack (PQFP) (VEJ) Order Number COP888HG Package Number VEJ44A
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION used herein Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform when properly used accordance with instructions provided labeling reasonably expected result significant injury user
National Semiconductor Corporation 1111 West Bardin Road Arlington 76017 1(800) 272-9959 1(800) 737-7018
critical component component life support device system whose failure perform reasonably expected cause failure life support device system affect safety effectiveness
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National Semiconductor Japan 81-043-299-2308 81-043-299-2408
National does assume responsibility circuitry described circuit patent licenses implied National reserves right time without notice change said circuitry specifications
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