AK4114 High Feature 192kHz 24bit Digital Audio Interface Transcei

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AK4114 High Feature 192kHz 24bit Digital Audio Interface Transcei

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[AK4114]
AK4114
High Feature 192kHz 24bit Digital Audio Interface Transceiver
GENERAL DESCRIPTION AK4114 digital audio transceiver supporting 192kHz, 24bits. channel status decoder supports both consumer professional modes. AK4114 automatically detect Non-PCM stream. When combined with multi channel codec (AK4527B AK4529), chips provide system solution AC-3 applications. dedicated pins serial control mode setting. small package, 48pin LQFP saves system space. *AC-3 trademark Dolby Laboratories. FEATURES AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible jitter Analog Lock Range 32kHz 192kHz Clock Source: X'tal 8-channel Receiver input 2-channel Transmission output (Through output DIT) Auxiliary digital input De-emphasis 32kHz, 44.1kHz, 48kHz 96kHz Detection Functions Non-PCM Stream Detection DTS-CD Stream Detection Sampling Frequency Detection (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz) Unlock Parity Error Detection Validity Flag Detection 24bit Audio Data Format Audio I/F: Master Slave Mode 40-bit Channel Status Buffer Burst Preamble Buffer Non-PCM stream Q-subcode Buffer stream Serial Master Clock Outputs: 64fs/128fs/256fs/512fs Operating Voltage: 3.6V with tolerance Small Package: 48pin LQFP 70°C
MS0098-E-01
2001/5
[AK4114]
AVSS AVDD Input Selector
X'tal
Clock Recovery
Oscillator Clock Generator MCKO1 MCKO2
DAIF Decoder
Audio
LRCK BICK SDTO DAUX
DVDD DVSS TVDD AC-3/MPEG Detect Error STATUS Detect Q-subcode buffer CCLK CDTO CDTI
B,C,U,VOUT
INT0
INT1
P/S="L"
Serial Control Mode
AVSS AVDD IPS0 DIF0 DIF1 DIF2 DAUX DAIF Decoder Audio LRCK BICK SDTO Input Selector X'tal Clock Recovery Oscillator Clock Generator MCKO1 MCKO2
OCKS0
DVDD DVSS TVDD
AC-3/MPEG Detect
Error STATUS Detect
OCKS1
B,C,U,VOUT
INT0
INT1
P/S="H" IPS1
Parallel Control Mode
MS0098-E-01
2001/5
[AK4114]
Ordering Guide
AK4114VQ 48pin LQFP (0.5mm pitch)
Layout
TEST1
VCOM
AVSS
AVSS
AVDD
AVSS
INT1
IPS0/RX4 AVSS DIF0/RX5 TEST2 DIF1/RX6 AVSS DIF2/RX7 IPS1/IIC P/SN XTL0 XTL1
View
INT0 OCKS0/CSN/CAD0 OCKS1/CCLK/SCL CM1/CDTI/SDA CM0/CDTO/CAD1 DAUX MCKO2 BICK SDTO
AK4114VQ
MCKO1
DVSS
DVDD
COUT
UOUT
TVDD
BOUT
VOUT
MS0098-E-01
DVSS
LRCK
2001/5
[AK4114]
PIN/FUNCTION
Name IPS0 NC(AVSS) DIF0 TEST2 DIF1 NC(AVSS) DIF2 IPS1 P/SN XTL0 XTL1 TVDD BOUT COUT UOUT VOUT DVDD DVSS MCKO1 LRCK SDTO BICK MCKO2 DAUX Function Input Channel Select Parallel Mode Receiver Channel Serial Mode (Internal biased pin) Connect internal bonding. This should connected AVSS. Audio Data Interface Format Parallel Mode Receiver Channel Serial Mode (Internal biased pin) TEST This should connect AVSS. Audio Data Interface Format Parallel Mode Receiver Channel Serial Mode (Internal biased pin) Connect internal bonding. This should connected AVSS. Audio Data Interface Format Parallel Mode Receiver Channel Serial Mode (Internal biased pin) Input Channel Select Parallel Mode Select Serial Mode. "L": 4-wire Serial, "H": Parallel/Serial Select "L": Serial Mode, "H": Parallel Mode X'tal Frequency Select X'tal Frequency Select V-bit Input Transmitter Output Input Buffer Power Supply Pin, 3.3V Connect internal bonding. This should connected DVSS. Transmit Channel (Through Data) Output When "0", Transmit Channel (Through Data) Output Pin. When "1", Transmit Channel (DAUX Data) Output (Default). Block-Start Output Receiver Input during first flames. C-bit Output Receiver Input U-bit Output Receiver Input V-bit Output Receiver Input Digital Power Supply Pin, 3.3V Digital Ground Master Clock Output Channel Clock Audio Serial Data Output Audio Serial Data Clock Master Clock Output Auxiliary Audio Data Input X'tal Output X'tal Input
MS0098-E-01
2001/5
[AK4114]
PIN/FUNCTION (Continued)
Function Power-Down Mode When "L", AK4114 powered-down reset. Master Clock Operation Mode Parallel Mode CDTO Control Data Output Serial Mode, IIC= "L". CAD1 Chip Address Serial Mode, IIC= "H". Master Clock Operation Mode Parallel Mode CDTI Control Data Input Serial Mode, IIC= "L". Control Data Serial Mode, IIC= "H". OCKS1 Output Clock Select Parallel Mode CCLK Control Data Clock Serial Mode, IIC= Control Data Clock Serial Mode, IIC= OCKS0 Output Clock Select Parallel Mode Chip Select Serial Mode, IIC="L". CAD0 Chip Address Serial Mode, IIC= "H". INT0 Interrupt INT1 Interrupt AVDD Analog Power Supply Pin, 3.3V External Resistor +/-1% resistor should connected AVSS externally. Common Voltage Output VCOM 0.47µF capacitor should connected AVSS externally. AVSS Analog Ground Receiver Channel (Internal biased pin) This channel default serial mode. Connect NC(AVSS) internal bonding. This should connected AVSS. Receiver Channel (Internal biased pin) TEST pin. TEST1 This should connected AVSS. Receiver Channel (Internal biased pin) Connect NC(AVSS) internal bonding. This should connected AVSS. Receiver Channel (Internal biased pin) Note input pins except internal biased pins should left floating. Name
MS0098-E-01
2001/5
[AK4114]
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note Parameter Symbol -0.3 AVDD Power Supplies: Analog -0.3 DVDD Digital -0.3 TVDD Input Buffer |AVSS-DVSS| (Note Input Current (Any pins except supplies) Input Voltage (Except pin) -0.3 TVDD+0.3 Input Voltage (XTI pin) VINX -0.3 DVDD+0.3 Ambient Temperature (Power applied) Storage Temperature Tstg Note voltages with respect ground. Note AVSS DVSS must connected same ground. WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes. Units
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS=0V; Note Parameter Power Supplies: Analog Digital Input Buffer Note voltages with respect ground. Symbol AVDD DVDD TVDD DVDD AVDD Units
S/PDIF RECEIVER CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V) Parameter Symbol Input Resistance Input Voltage Input Hysteresis Input Sample Frequency Units mVpp
CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V; unless otherwise specified) Parameter Symbol Units Power Supply Current Normal operation: (Note Power down: (Note High-Level Input Voltage 70%DVDD TVDD Low-Level Input Voltage DVSS-0.3 30%DVDD DVDD-0.4 High-Level Output Voltage (Iout=-400µA) Low-Level Output Voltage (Except pin: Iout=400µA) pin: Iout= 3mA) Input Leakage Current Note AVDD, DVDD=3.3V, TVDD=5.0V, CL=20pF, fs=192kHz, X'tal=24.576MHz, Clock Operation Mode OCKS1=1, OCKS0=1. AVDD=11mA (typ), DVDD=17mA (typ), TVDD=10µA (typ). DVDD=28mA (typ) when circuit Figure attached both pins. Note inputs open digital input pins held DVDD DVSS.
MS0098-E-01
2001/5
[AK4114]
SWITCHING CHARACTERISTICS
(Ta=25°C; DVDD, AVDD2.7~3.6V, TVDD=2.7~5.5V; CL=20pF) Parameter Symbol Master Clock Timing Crystal Resonator Frequency fXTAL External Clock Frequency fECLK Duty dECLK MCKO1 Output Frequency fMCK1 Duty dMCK1 MCKO2 Output Frequency fMCK2 Duty dMCK2 Clock Recover Frequency (RX0-7) fpll LRCK Frequency Duty Cycle dLCK Audio Interface Timing Slave Mode tBCK BICK Period tBCKL BICK Pulse Width tBCKH Pulse Width High tLRB LRCK Edge BICK (Note tBLR BICK LRCK Edge (Note tLRM LRCK SDTO (MSB) tBSD BICK SDTO tDXH DAUX Hold Time tDXS DAUX Setup Time Master Mode fBCK BICK Frequency dBCK BICK Duty tMBLR BICK LRCK tBSD BICK SDTO tDXH DAUX Hold Time tDXS DAUX Setup Time Control Interface Timing (4-wire serial mode) tCCK CCLK Period tCCKL CCLK Pulse Width tCCKH Pulse Width High tCDS CDTI Setup Time tCDH CDTI Hold Time tCSW Time tCSS CCLK tCSH CCLK tDCD CDTO Delay tCCZ CDTO Hi-Z 11.2896 11.2896 4.096 2.048 24.576 24.576 24.576 24.576 Units
64fs
Note BICK rising edge must occur same time LRCK edge.
MS0098-E-01
2001/5
[AK4114]
SWITCHING CHARACTERISTICS (Continued)
(Ta=25°C; DVDD, AVDD2.7~3.6V, TVDD=2.7~5.5V; CL=20pF) Parameter Symbol Control Interface Timing mode): fSCL Clock Frequency tBUF Free Time Between Transmissions tHD:STA Start Condition Hold Time (prior first clock pulse) tLOW Clock Time tHIGH Clock High Time tSU:STA Setup Time Repeated Start Condition tHD:DAT Hold Time from Falling (Note tSU:DAT Setup Time from Rising Rise Time Both Lines Fall Time Both Lines tSU:STO Setup Time Stop Condition Capacitive load Reset Timing Pulse Width Note Data must held sufficient time bridge transition time SCL. Note registered trademark Philips Semiconductors. 1000 Units
Purchase Asahi Kasei Microsystems Co., components conveys license under Philips patent components system, provided system conform specifications defined Philips.
MS0098-E-01
2001/5
[AK4114]
Timing Diagram
1/fECLK tECLKH tECLKL dECLK tECLKH fECLK tECLKL fECLK
1/fMCK1
MCKO1 tMCKH1 tMCKL1
50%DVDD dMCK1 tMCKH1 fMCK1 tMCKL1 fMCK1
1/fMCK2
MCKO2 tMCKH2 tMCKL2
50%DVDD dMCK2 tMCKH2 fMCK2 tMCKL2 fMCK2
1/fs tLRH tLRL dLCK tLRH tLRL
LRCK
Figure Clock Timing
tBCK tBLR BICK tLRB tBCKL tBCKH tLRM tBSD 50%DVDD
LRCK
SDTO tDXS tDXH
DAUX
Figure Serial Interface Timing (Slave Mode)
MS0098-E-01
2001/5
[AK4114]
LRCK
50%DVDD
tMBLR BICK 50%DVDD
tBSD 50%DVDD
SDTO tDXS tDXH
DAUX
Figure Serial Interface Timing (Master Mode)
tCSS tCCK tCCKL tCCKH CCLK tCDH tCDS
CDTI
CDTO
Hi-Z
Figure WRITE/READ Command Input Timing 4-wire serial mode
MS0098-E-01
2001/5
[AK4114]
tCSW tCSH
CCLK
CDTI
CDTO
Hi-Z
Figure WRITE Data Input Timing 4-wire serial mode
CCLK
CDTI
tDCD
CDTO
Hi-Z
50%DVDD
Figure READ Data Output Timing 4-wire serial mode
tCSW tCSH CCLK
CDTI
tCCZ
CDTO
50%DVDD
Figure READ Data Input Timing 4-wire serial mode
MS0098-E-01
2001/5
[AK4114]
tBUF tLOW tHIGH tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA Start tSU:STO Stop
Figure mode Timing
Figure Power Down Reset Timing
MS0098-E-01
2001/5
[AK4114]
OPERATION OVERVIEW Non-PCM (AC-3, MPEG, etc.) DTS-CD Bitstream Detection
AK4114 Non-PCM steam auto-detection function. When 32bit mode Non-PCM preamble based Dolby "AC-3 Data Stream IEC60958 Interface" detected, AUTO goes "1". 96bit sync code consists 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 0x4E1F. Detection this pattern will AUTO "1". Once AUTO "1", will remain until 4096 frames pass through chip without additional sync pattern being detected. When those preambles detected, burst preambles that follow those sync codes stored registers. AK4114 also DTS-CD bitstream auto-detection function. When AK4114 detects DTS-CD bitstreams, DTSCD goes "1". When next sync code does come within 4096 flames, DTSCD goes until when AK4114 detects stream again.
192kHz Clock Recovery
chip jitter wide lock range with 32kHz 192kHz lock time less than 20ms. AK4114 sampling frequency detect function. either clock comparison against X'tal oscillator using channel status, AK4114 detects sampling frequency (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz 192kHz). loses lock when received sync interval incorrect.
Master Clock
AK4114 clock outputs, MCKO1 MCKO2. These clocks derived from either recovered clock from X'tal oscillator. frequencies master clock outputs (MCKO1 MCKO2) OCKS0 OCKS1 shown Table 512fs clock will output when 96kHz 192kHz. 256fs clock will output when 192kHz. OCKS1 OCKS0 MCKO1 256fs 256fs 512fs 128fs MCKO2 256fs 128fs 256fs 64fs X'tal 256fs 256fs 512fs 128fs (max)
Default
Table Master Clock Frequency Select (Stereo mode)
Clock Operation Mode
CM0/CM1 pins bits) select clock source data source SDTO. Mode clock source switched from X'tal when goes unlock state. Mode3, clock source fixed X'tal, also operating recovered data such bits monitored. Mode2 recommended that frequency X'tal different from recovered frequency from PLL. UNLOCK X'tal Clock source SDTO Default ON(Note) X'tal DAUX X'tal DAUX X'tal DAUX Oscillation (Power-up), OFF: STOP (Power-down) Note When X'tal used clock comparison detection (i.e. XTL1,0= "1,1"), X'tal off. Table Clock Operation Mode select Mode
MS0098-E-01
2001/5
[AK4114]
Clock Source
following circuits available feed clock AK4114. X'tal
AK4114
Figure X'tal mode Note: External capacitance depends crystal oscillator (Typ. 10-40pF)
External clock
External Clock
AK4114
Figure External clock mode Note: Input clock must exceed DVDD.
Fixed Clock Operation Mode
AK4114
Figure mode
MS0098-E-01
2001/5
[AK4114]
Sampling Frequency Pre-emphasis Detection
AK4114 methods detecting sampling frequency follows. Clock comparison between recovered clock X'tal oscillator Sampling frequency information channel status Those could selected XTL1, bits. detected frequency reported FS3-0 bits. XTL1 XTL0 X'tal Frequency 11.2896MHz 12.288MHz 24.576MHz (Use channel status) Table Reference X'tal frequency XTL1,0= "1,1" Consumer Register output mode Professional mode Clock comparison (Note (Note Byte3 Byte0 Byte4 Bit3,2,1,0 Bit7,6 Bit6,5,4,3 44.1kHz 44.1kHz 0000 0000 Reserved Reserved 0001 (Others) 48kHz 48kHz 0010 0000 32kHz 32kHz 0011 0000 88.2kHz 88.2kHz (1000) 1010 96kHz 96kHz (1010) 0010 176.4kHz 176.4kHz (1100) 1011 192kHz 192kHz (1110) 0011 Note1: least range identified value Table case intermediate frequency those two, FS3-0 bits indicate nearer value. When frequency much bigger than 192kHz much smaller than 32kHz, FS3-0 bits indicate "0001". Note2: When consumer mode, Byte3 Bit3-0 copied FS3-0. Table Information Except XTL1,0= "1,1"
Default
pre-emphasis information detected reported bit. These information extracted from channel default. switched channel CS12 control register. Pre-emphasis Byte Bits 0X100 0X100
Table Consumer Mode Pre-emphasis Byte Bits
Table Professional Mode
MS0098-E-01
2001/5
[AK4114]
De-emphasis Filter Control
AK4114 includes digital de-emphasis filter (tc=50/15µs) filter corresponding four sampling frequencies (32kHz, 44.1kHz, 48kHz 96kHz). When DEAU bit="1", de-emphasis filter enabled automatically sampling frequency pre-emphasis information channel status. AK4114 goes this mode default. Therefore, Parallel Mode, AK4114 always placed this mode status bits channel control de-emphasis filter. Serial Mode, DEM0/1 bits control de-emphasis filter when DEAU "0". internal de-emphasis filter bypassed recovered data output without change either pre-emphasis de-emphasis Mode OFF. (Others) Mode 44.1kHz 48kHz 32kHz 96kHz
Table De-emphasis Auto Control DEAU (Default) DEM1 DEM0 Mode 44.1kHz 48kHz 32kHz 96kHz
Default
Table De-emphasis Manual Control DEAU
System Reset Power-Down
AK4114 power-down mode circuits partially powerd-down bit. RSTN initializes register resets internal timing. Parallel Mode, only control enabled. AK4114 should reset once bringing upon power-up. Pin: analog digital circuit placed power-down reset mode bringing PDN= "L". registers initialized, clocks stopped. Reading/Witting register disabled. RSTN (Address 00H; D0): registers except RSTN initialized bringing RSTN "0". internal timings also initialized. Witting register available except RSTN. Reading register disabled. (Address 00H; D1): clock recovery part initialized bringing "0". this case, clocks stopped. registers initialized mode settings kept. Writing Reading registers enabled.
MS0098-E-01
2001/5
[AK4114]
Biphase Input Through Output
Eight receiver inputs (RX0-7) available Serial Control Mode. Each input includes amplifier corresponding unbalance mode accept signal 200mV more. IPS2-0 selects receiver channel. When "1", Block start signal, output from each pins. IPS2 IPS1 IPS0 INPUT Data
Default
Table Recovery Data Select
1/4fs COUT U,V)
C(R191)
C(L0)
C(R0)
C(L1)
C(L31)
C(R31) C(L32)
(Normal mode) SDTO R190 L191 R191
LRCK (except I2S) LRCK (I2S)
R190 (Mono mode) SDTO (except I2S) LRCK (except I2S) LRCK (I2S)
L191
R191
Figure output/input timings
MS0098-E-01
2001/5
[AK4114]
Biphase Output
AK4114 output either through output(from DIR) transmitter output(DIT; data from DAUX transformed IEC60958 format.) from TX1/0 pins. Those could selected bit. source through output from could selected among RX0-8 OPS00,01 bits, TX1, OPS10,11 bits respectively. When output DAUX data, could controlled first bytes could controlled CT39-CT0 bits control registers. When bit0= "0"(consumer mode), bit20-23(Audio channel) could controlled directly controlled CT20 bit. When CT20 "1", AK4114 outputs "1000" C20-23 left channel output "0100" C20-23 right channel automatically. When CT20 "0", AK4114 outputs "0000" "1000" frame "0100" frame bits fixed "0".as C20-23 both channel. could controlled UDIT follows; When UDIT "0", always "L". When UDIT "1", recovered bits used DIT( DIR-DIT loop mode bit). This mode only available when locked master mode. OPS02 OPS01 OPS00 Output Data
Default
Table Output Data Select OPS12 OPS11 OPS10 Output Data DAUX
Default
Table Output Data Select
(Normal mode) LRCK (except I2S) LRCK (I2S) DAUX (Mono mode)
R191
L191/R191
L0/R0
L1/R1
Figure DAUX input timings
MS0098-E-01
2001/5
[AK4114]
Double sampling frequency mode
When MONO "1", AK4114 outputs data with double speed according "Single channel double sampling frequency mode" AES3. example, when 192kHz mono data transmitted received, channels 96kHz biphase data used. this case, frame 96kHz LRCK frequency 192kHz. When MONO "1", AK4114 outputs mono data from SDTO follows.
frame
Biphase (Image)
MONO
LRCK (except IIS) LRCK (IIS) SDTO
LRCK
Figure MONO mode (RX)
AK4114 SDTO (Master)
MCKO MCLK BICK LRCK
(AK4394/5)
SDTI
AK4114 SDTO (Slave)
Figure MONO mode Connection Example (RX)
MS0098-E-01
2001/5
ASAHI KASEI
[AK4114]
When MONO "0", AK4114 outputs data through biphase signal. When MONO "1", then data. LRCK
LRCK (except IIS) LRCK (IIS) Serial Data DAUX
MONO TLR=0 Biphase (Image)
MONO TLR=1 Biphase (Image)
frame
Figure MONO mode (TX)
AK4114 DAUX (Master)
MCKO MCLK BICK LRCK
(AK5394)
SDATA
AK4114 DAUX (Slave)
Figure MONO mode Connection Example (TX) Note: When connection example (Figure multiple AK4114s used, LRCK BICK should input after reset that phase outputs aligned. AK4114s should following sequence (Figure 19).
MS0098-E-01
2001/5
ASAHI KASEI Upon power Mode
LRCK, BICK
Stereo mode Mono mode
[AK4114]
During operation RSTN Mode
LRCK, BICK
Stereo mode Mono mode
Reset AK4114s RSTN "1". AK4114s MONO mode while they still slave mode. AK4114s master mode that LRCK input other AK4114s same time, LRCK should input AK4114s same time. Figure MONO mode setup sequence (TX)
MS0098-E-01
2001/5
[AK4114]
Biphase signal input/output circuit
0.1uF Coax
AK4114
Figure Consumer Input Circuit (Coaxial Input) Note: case coaxial input, coupling level this input from next input line pattern exceeds 50mV, there possibility occur incorrect operation. this case, possible lower coupling level adding this decoupling capacitor.
Optical Receiver Optical Fiber
AK4114
Figure Consumer Input Circuit (Optical Input) case coaxial input, input level line small, Serial Mode, careful crosstalk among input lines. example, inserting shield pattern among them. Parallel Mode, only channel input (RX1) available RX2-4 change other pins audio format control. Those pins must fixed "L". AK4114 includes output buffer. output level meets combination 0.5V+/-20% using external resistor network. Figure transformer 1:1.
DVSS cable
3.3V 3.0V
Figure External Resistor Network Note: When AK4114 power-down mode (PDN= "L"), power supply current suppressed using couple capacitor following figure since output becomes uncertain power-down mode.
0.1uF DVSS cable
3.3V 3.0V
MS0098-E-01
2001/5
[AK4114]
Q-subcode buffers
AK4114 Q-subcode buffer application. AK4114 takes Q-subcode into registers following conditions. sync word (S0,S1) constructed least "0"s. start "1". Those 7bits follows start bit. distance between start bits 8-16 bits. QINT control register goes when Q-subcode differs from one, goes when QINT read.
number min=0; max=8. Figure Configuration U-bit(CD)
TRACK NUMBER INDEX
CTRL
ADRS
MINUTE SECOND FRAME ZERO ABSOLUTE MINUTE ABSOLUTE SECOND ABSOLUTE FRAME G(x)=x^16+x^12+x^5+1
Figure Q-subcode Addr Register Name Q-subcode Address Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode Minute Q-subcode Second Q-subcode Frame
Figure Q-subcode register
MS0098-E-01
2001/5
[AK4114]
Error Handling
There following eight events make INT0/1 "H". INT0/1 shows status following conditions. UNLOCK when loses lock. AK4114 loses lock when distance between preambles correct when those preambles correct. when parity error biphase coding error detected, keeps until this register read. Updated every sub-frame cycle. Reading this register resets itself. AUTO when Non-PCM bitstream detected. Updated every sub-frame cycle. DTSCD when DTS-CD bitstream detected. Updated every sub-frame cycle. AUDION when "AUDIO" recovered channel status indicates "1". Updated every block cycle. when "PEM" recovered channel status indicates "1". Updated every block cycle. QINT when Q-subcode differ from one, keeps until this register read. Updated every sync code cycle Q-subcode. Reading this register resets itself. CINT when received bits differ from one, keeps until this register read. Updated every block cycle. Reading this register resets itself. Both INT0/1 fixed when (CM1,0= "01"). Once INT0 goes "H", this holds 1024/fs cycles(this value changed EFH0/1 bits) after those events removed. INT1 goes same time when those events removed. Each INT0/1 pins mask those eight events individually. Once PAR, QINT CINT goes "1", those registers held until those registers read. While AK4114 loses lock, registers regarding C-bit U-bits initialized keep previous value.
Parallel mode Parallel Mode, INT0 outputs ORed signal between UNLOCK PAR, INT1 outputs ORed signal among AUTO, DTSCD AUDION. Once INT0 goes "H", maintains 1024/fs cycles after error events removed. Table shows state each output pins when INT0/1 "H". Event (State Internal Register) AUTO DTSCD AUDION INT0 INT1 SDTO Previous Data Output Table Error Handling (Parallel Mode) Don't care
UNLOCK
Output Output
Output
MS0098-E-01
2001/5
ASAHI KASEI Serial mode
[AK4114]
Serial Mode, INT0/1 output ORed signal among those eight events. However, each events masked each mask bits. When each masks those events, event does affect INT0/1 operation (those mask affect those resisters (UNLOCK, PAR, etc.) themselves. Once INT0 goes "H", maintains 1024/fs cycles (this value changed EFH0-1 bits) after events removed. Once those PAR, QINT CINT goes "1", holds until reading those registers. While AK4114 loses lock, channel status Q-subcode bits updated holds previous data. initial state, INT0 outputs ORed signal between UNLOCK PAR, INT1 outputs ORed signal among AUTO, DTSCD AUDION. Register DTSCD AUDION QINT CINT Table Error Handling (Serial Mode) SDTO Previous Data Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output
UNLOCK
AUTO
MS0098-E-01
2001/5
[AK4114]
Error (UNLOCK, PAR,.) INT0
(Error)
Hold Time (max: 4096/fs)
INT1 Register (PAR,CINT,QINT) Register (others) Command MCKO,BICK,LRCK (UNLOCK) MCKO,BICK,LRCK (except UNLOCK) SDTO (UNLOCK) SDTO (PAR error) SDTO (others) Vpin (UNLOCK) Vpin (except UNLOCK) Previous Data
Hold Time
Hold
Reset
READ
Free (fs: around 20kHz)
Normal Operation Figure INT0/1 timing
MS0098-E-01
2001/5
[AK4114]
="L" Initialize Read
INT0/1 ="H"
Release Muting
Mute output
Read
(Each Error Handling)
Read (Resets registers)
INT0/1 ="H"
Figure Error Handling Sequence Example
MS0098-E-01
2001/5
[AK4114]
="L" Initialize Read
INT1 ="H"
Read Detect QSUB=
(Read Q-buffer)
QCRC INT1 ="L" data valid
data invalid
Figure Error Handling Sequence Example (for Q/CINT)
MS0098-E-01
2001/5
[AK4114]
Audio Serial Interface Format
DIF0, DIF1 DIF2 pins select eight serial data formats shown Table formats serial data MSB-first, compliment format. SDTO clocked falling edge BICK DAUX latched rising edge BICK. BICK outputs 64fs clock Mode 0-5. Mode Slave Modes, BICK available 128fs fs=48kHz. format equal less than 20bit (Mode0-2), LSBs sub-frame truncated. Mode 3-7, last 4LSBs auxiliary data (see Figure 29). When Parity Error, Biphase Error Frame Length Error occurs sub-frame, AK4114 continues output last normal sub-frame data from SDTO repeatedly until error removed. When Unlock Error occurs, AK4114 output from SDTO. case using DAUX pin, data transformed output from SDTO. DAUX used Clock Operation Mode unlock state Mode input data format DAUX should left justified except Mode5 7(Table 14). Mode5 both input data format DAUX output data format SDTO I2S. Mode6 Slave Mode that corresponding Master Mode Mode4 salve Mode, LRCK BICK should with synchronizing MCKO1/2.
sub-frame IEC958
preamble Aux.
AK4112 Audio Data (MSB First)
Figure configuration
Mode
DIF2
DIF1
DIF0
DAUX 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, 24bit, Left justified 24bit,
SDTO 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, 24bit, Left justified 24bit,
LRCK
BICK 64fs 64fs 64fs 64fs 64fs 64fs 64-128fs 64-128fs
Default
Table Audio data format
MS0098-E-01
2001/5
[AK4114]
LRCK(0)
BICK (0:64fs) SDTO(0)
15:MSB, 0:LSB Data Data
Figure Mode Timing
LRCK(0)
BICK (0:64fs)
SDTO(0)
23:MSB, 0:LSB Data Data
Figure Mode Timing
LRCK
BICK (64fs)
SDTO(0)
23:MSB, 0:LSB Data Data
Figure Mode Timing
Mode4 LRCK, BICK Output Mode6 LRCK, BICK Input
LRCK
BICK (64fs) SDTO(0)
23:MSB, 0:LSB Data Data
Figure Mode Timing
Mode5 LRCK, BICK Output Mode7 LRCK, BICK Input
MS0098-E-01
2001/5
[AK4114]
Serial Control Interface
(1). 4-wire serial control mode (IIC= "L") internal registers either written read 4-wire interface pins: CSN, CCLK, CDTI CDTO. data this interface consists Chip address (2bits, C1-0 fixed "00"), Read/Write (1bit), Register address (MSB first, 5bits) Control data (MSB first, 8bits). Address data clocked rising edge CCLK data clocked falling edge. write operations, data latched after 16th rising edge CCLK, after high-to-low transition CSN. read operations, CDTO output goes high impedance after low-to-high transition CSN. maximum speed CCLK 5MHz. PDN= resets registers their default values. When state changed, AK4114 should reset PDN= "L".
CCLK
CDTI WRITE CDTO CDTI READ CDTO
Hi-Z
Hi-Z
Hi-Z
C1-C0: Chip Address (Fixed "00") R/W: READ/WRITE (0:READ, 1:WRITE) A4-A0: Register Address D7-D0: Control Data Figure 4-wire Serial Control Timing
MS0098-E-01
2001/5
ASAHI KASEI (2). control mode (IIC= "H")
[AK4114]
AK4114 supports standard-mode I2C-bus (max 100kHz). Then AK4114 incorporated fast-mode I2Cbus system (max 400kHz). (2)-1. Data transfer commands preceded START condition. After START condition, slave address sent. After AK4114 recognizes START condition, device interfaced waits slave address transmitted over line. transmitted slave address matches address devices, designated slave device pulls line (ACKNOWLEDGE). data transfer always terminated STOP condition generated master device. (2)-1-1. Data validity data line must stable during HIGH period clock. HIGH state data line only change when clock signal line except START STOP condition.
DATA LINE STABLE DATA VALID
CHANGE DATA ALLOWED
Figure Data transfer (2)-1-2. START STOP condition HIGH transition line while HIGH indicates START condition. sequences start from START condition. HIGH transition line while HIGH defines STOP condition. sequences STOP condition.
START CONDITION
STOP CONDITION
Figure START STOP conditions
MS0098-E-01
2001/5
ASAHI KASEI (2)-1-3. ACKNOWLEDGE
[AK4114]
ACKNOWLEDGE software convention used indicate successful data transfers. transmitting device will release line (HIGH) after transmitting eight bits. receiver must pull down line during acknowledge clock pulse that that remains stable during period this clock pulse. AK4114 will generates acknowledge after each byte been received. read mode, slave, AK4114 will transmit eight bits data, release line monitor line acknowledge. acknowledge detected STOP condition generated master, slave will continue transmit data. acknowledge detected, slave will terminate further data transmissions await STOP condition.
Clock pulse acknowledge
FROM MASTER
DATA OUTPUT TRANSMITTER acknowledge DATA OUTPUT RECEIVER START CONDITION acknowledge
Figure Acknowledge I2C-bus (2)-1-4. FIRST BYTE first byte, which includes seven bits slave address bit, sent after START condition. transmitted slave address matches address device, receiver been addressed pulls down line. most significant five bits slave address fixed "00100". next bits CAD1 CAD0 (device address bits). These bits identify specific device bus. hard-wired input pins (CAD1 CAD0 pin) them. eighth (LSB) first byte (R/W bit) defines whether write read condition requested master. indicates that read operation executed. indicates that write operation executed.
CAD1
CAD0
(Those CAD1/0 should match with CAD1/0 pins.) Figure First Byte
MS0098-E-01
2001/5
ASAHI KASEI (2)-2. WRITE Operations
[AK4114]
WRITE operation AK4114. After receipt start condition first byte, AK4114 generates acknowledge, awaits second byte (register address). second byte consists address control registers AK4114. format first, those most significant 3-bits "Don't care".
Don't care) Figure Second Byte After receipt second byte, AK4114 generates acknowledge, awaits third byte. Those data after second byte contain control data. format first, 8bits.
Figure Byte structure after second byte AK4114 capable more than byte write operation sequence. After receipt third byte, AK4114 generates acknowledge, awaits next data again. master transmit more than words instead terminating write cycle after first data word transferred. After receipt each data, internal 5bits address counter incremented one, next data taken into next address automatically. address exceed prior generating stop condition, address counter will "roll over" previous data will overwritten.
Data(n+x)
Slave Address
Register Address(n)
Data(n)
Data(n+1)
Figure WRITE Operation
MS0098-E-01
2001/5
ASAHI KASEI (2)-3. READ Operations
[AK4114]
READ operation AK4114. After transmission data, master read next address's data generating acknowledge instead terminating write cycle after receipt first data word. After receipt each data, internal 5bits address counter incremented one, next data taken into next address automatically. address exceed prior generating stop condition, address counter will "roll over" previous data will overwritten. AK4114 supports basic read operations: CURRENT ADDRESS READ RANDOM READ. (2)-3-1. CURRENT ADDRESS READ AK4114 contains internal address counter that maintains address last word accessed, incremented one. Therefore, last access (either read write) address next CURRENT READ operation would access data from address n+1. After receipt slave address with "1", AK4114 generates acknowledge, transmits 1byte data which address internal address counter increments internal address counter master does generate acknowledge data generate stop condition, AK4114 discontinues transmission
Data(n+x)
Slave Address
Data(n)
Data(n+1)
Data(n+2)
Figure CURRENT ADDRESS READ (2)-3-2. RANDOM READ Random read operation allows master access memory location random. Prior issuing slave address with "1", master must first perform "dummy" write operation. master issues start condition, slave address(R/W="0") then register address read. After register address's acknowledge, master immediately reissues start condition slave address with "1". Then AK4114 generates acknowledge, 1byte data increments internal address counter master does generate acknowledge data generate stop condition, AK4114 discontinues transmission.
Slave Address
Word Address(n)
Slave Address
Data(n)
Data(n+1)
Data(n+x)
Figure RANDOM READ
MS0098-E-01
2001/5
[AK4114]
Register
Addr
Register Name Power Down Control Format De-em Control Input/ Output Control Input/ Output Control INT0 MASK INT1 MASK Receiver status Receiver status Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte
Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte
CS12 MONO TX1E EFH1
DIF2 OPS12 EFH0
DIF1 OPS11 UDIT MCIT0 MCIT1 CINT CR13 CR21 CR29 CR37
CT13 CT21 CT29 CT39
DIF0 OPS10
OCKS1 DEAU TX0E
OCKS0 DEM1 OPS02 IPS2 MPE0 MPE1 CR10 CR18 CR26 CR34
CT10 CT18 CT26 CT39
DEM0 OPS01 IPS1
RSTN OPS00 IPS0
MQIT0 MAUT0 MQIT1 MAUT1 QINT CR15 CR23 CR31 CR39
CT15 CT23 CT31 CT39
MULK0 MDTS0 MULK1 MDTS1 UNLCK DTSCD CR12 CR20 CR28 CR36
CT12 CT20 CT28 CT39
MAUD0 MPAR0 MAUD1 MPAR1 AUDION QCRC CR17 CR25 CR33
CT17 CT25 CT39
AUTO CR14 CR22 CR30 CR38
CT14 CT22 CT30 CT39
CCRC CR16 CR24 CR32
CT16 CT24 CT32
CR11 CR19 CR27 CR35
CT11 CT19 CT27 CT39
Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Q-subcode Address Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode Minute Q-subcode Second
PC15 PD15
PC14 PD14
PC13 PD13
PC12 PD12
PC11 PD11
PC10 PD10
Q-subcode Frame When goes "L", registers initialized their default values. When RSTN goes "0", internal timing reset registers initialized their default values. data written register even "0".
MS0098-E-01
2001/5
[AK4114]
Register Definitions Reset Initialize
Addr Register Name Power Down Control Default CS12 OCKS1 OCKS0 RSTN
RSTN: Timing Reset Register Initialize Reset Initialize Normal Operation PWN: Power Down Power Down Normal Operation OCKS1-0: Master Clock Frequency Select CM1-0: Master Clock Operation Mode Select BCU: Block start Output Mode When BCU=1, three Output Pins(BOUT, COUT, UOUT) become enabled. block signal goes high start frame remains high until frame CS12: Channel Status Select Channel Channel Selects which channel status used derive C-bit buffers, AUDION, PEM, FS3, FS2, FS1, FS0, de-emphasis filter controlled channel Parallel Mode.
Format De-emphasis Control
Addr Register Name Format De-em Control Default MONO DIF2 DIF1 DIF0 DEAU DEM1 DEM0
DFS: 96kHz De-emphasis Control DEM1-0: 44.1, 48kHz De-emphasis Control (see Table DEAU: De-emphasis Auto Detect Enable Disable Enable DIF2-0: Audio Data Format Control (see Table 14.) MONO: Double sampling frequency mode enable Stereo mode Mono mode
MS0098-E-01
2001/5
[AK4114]
Input/Output Control
Addr Register Name Input/ Output Control Default TX1E OPS12 OPS11 OPS10 TX0E OPS02 OPS01 OPS00
OPS02-00: Output Through Data Select OPS12-10: Output Through Data Select TX0E: Output Enable Disable. outputs "L". Enable TX1E: Output Enable Disable. outputs "L". Enable Addr Register Name Input/ Output Control Default EFH1 EFH0 UDIT IPS2 IPS1 IPS0
IPS2-0: Input Recovery Data Select DIT: Through data/Transmit data select Through data data). Transmit data (DAUX data). TLR: Double sampling frequency mode channel select DIT(stereo) channel channel UDIT: control fixed Recovered used (loop mode bit) EFH1-0: Interrupt Hold Count Select LRCK 1024 LRCK 2048 LRCK 4096 LRCK
MS0098-E-01
2001/5
[AK4114]
Mask Control INT0
Addr Register Name INT0 MASK Default MQI0 MAT0 MCI0 MUL0 MDTS0 MPE0 MAN0 MPR0
MPR0: Mask Enable MAN0: Mask Enable AUDN MPE0: Mask Enable MDTS0: Mask Enable DTSCD MUL0: Mask Enable UNLOCK MCI0: Mask Enable CINT MAT0: Mask Enable AUTO MQI0: Mask Enable QINT Mask disable Mask enable
Mask Control INT1
Addr Register Name INT1 MASK Default MQI1 MAT1 MCI1 MUL1 MDTS1 MPE1 MAN1 MPR1
MPR1: Mask Enable MAN1: Mask Enable AUDN MPE1: Mask Enable MDTS1: Mask Enable DTSCD MUL1: Mask Enable UNLOCK0 MCI1: Mask Enable CINT MAT1: Mask Enable AUTO MQI1: Mask Enable QINT Mask disable Mask enable
MS0098-E-01
2001/5
[AK4114]
Receiver Status
Addr Register Name Receiver status Default QINT AUTO CINT UNLCK DTSCD AUDION
PAR: Parity Error Biphase Error Status 0:No Error 1:Error Parity Error Biphase Error detected sub-frame. AUDION: Audio Output Audio Audio This made encoding channel status bits. PEM: Pre-emphasis Detect. This made encoding channel status bits. DTSCD: DTS-CD Auto Detect detect Detect UNLCK: Lock Status Locked Lock CINT: Channel Status Buffer Interrupt change Changed AUTO: Non-PCM Auto Detect detect Detect QINT: Q-subcode Buffer Interrupt change Changed QINT, CINT bits initialized when read.
Receiver Status
Addr Register Name Receiver status Default QCRC CCRC
CCRC: Cyclic Redundancy Check Channel Status 0:No Error 1:Error QCRC: Cyclic Redundancy Check Q-subcode 0:No Error 1:Error Validity channel status 0:Valid 1:Invalid FS3-0: Sampling Frequency detection (see Table
MS0098-E-01
2001/5
[AK4114]
Receiver Channel Status
Addr Register Name Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Default CR15 CR23 CR31 CR39 CR14 CR22 CR30 CR38 CR13 CR21 CR29 CR37 CR12 CR20 CR28 CR36 CR11 CR19 CR27 CR35 CR10 CR18 CR26 CR34 CR17 CR25 CR33 CR16 CR24 CR32
initialized
CR39-0: Receiver Channel Status Byte
Transmitter Channel Status
Addr Register Name Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Default CT15 CT23 CT31 CT39 CT14 CT22 CT30 CT38 CT13 CT21 CT29 CT37 CT12 CT11 CT20 CT19 CT28 CT27 CT36 CT35 CT10 CT18 CT26 CT34 CT17 CT25 CT335 CT16 CT24 CT32
CT39-0: Transmitter Channel Status Byte
Burst Preamble Pc/Pd non-PCM encoded Audio Bitstreams
Addr Register Name Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Default PC15 PD15 PC14 PD14 PC13 PD13 PC12 PD12 PC11 PD11 PC10 PD10
initialized
PC15-0: Burst Preamble Byte PD15-0: Burst Preamble Byte
MS0098-E-01
2001/5
[AK4114]
Q-subcode Buffer
Addr Register Name Q-subcode Address Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode Minute Q-subcode Second Q-subcode Frame Default
initialized
MS0098-E-01
2001/5
[AK4114]
Burst Preambles non-PCM Bitstreams
sub-frame IEC958
preamble Aux.
bits bitstream
Burst_payload
stuffing
repetition time burst
Figure Data structure IEC60958 Preamble word Length field Contents bits sync word bits sync word bits Burst info bits Length code Table Burst preamble words Value 0xF872 0x4E1F Table numbers bits
MS0098-E-01
2001/5
ASAHI KASEI Bits Value 16-26 29-31 Contents data type NULL data Dolby AC-3 data reserved PAUSE MPEG-1 Layer1 data MPEG-1 Layer2 data MPEG-2 without extension MPEG-2 data with extension reserved MPEG-2, Layer1 sample rate MPEG-2, Layer2 sample rate reserved type type type ATRAC ATRAC2/3 reserved (reserved MPEG-4 data) MPEG-2 data reserved reserved, shall error-flag indicating valid burst_payload error-flag indicating that burst_payload contain errors data type dependent info stream number, shall Table Fields burst info Repetition time burst IEC60958 frames 4096 1536
[AK4114]
1152 1152 1152 1024 2048 1024 1024
8-12 13-15
MS0098-E-01
2001/5
[AK4114]
Non-PCM Bitstream timing
When Non-PCM preamble coming within 4096 frames,
stream
Repetition time
>4096 frames
AUTO
Register
Register
Figure Timing example
When Non-PCM bitstream stops (when MULK0=0),
INT0 <20mS (Lock time) stream Stop Syncs (B,M AUTO <Repetition time INT0 hold time
Register
Register
Figure Timing example
MS0098-E-01
2001/5
[AK4114]
SYSTEM DESIGN
Figure shows example system connection diagram Serial Mode.
Analog Ground Digital Ground
+3.3V Analog Supply 10µF 0.1µF
(Shield)
(SPDIF Sources)
AVSS AVSS AVSS AVSS VCOM AVDD INT1
Microcontroller
INT0
(SPDIF Sources)
AVSS AVSS AVSS P/SN
CCLK CDTI
AK4114
CDTO DAUX MCKO2 BICK MCKO1 SDTO LRCK DVDD DVSS
X'tal=11.2896MHz SDTO MCLK BICK SDTI1 SDTI2 LRCK SDTI3
CODEC (AK4527)
(Micro controller)
XTL0 XTL1 TVDD
10µF
10µF
+3.3V Digital Supply 0.1µF
0.1µF
+3.3V Digital Supply
(SPDIF out) (Microcontroller)
Figure Typical Connection Diagram (Serial Mode) Notes: setting XTL0 XTL1, refer Table depends crystal. AVSS DVSS must connected same ground plane. Digital signals, especially clocks, should kept away from order avoid effect clock jitter performance.
MS0098-E-01
2001/5
[AK4114]
PACKAGE
48pin LQFP(Unit:mm)
1.70Max 0.13 0.13 1.40 0.05
0.22 0.08
0.145 0.05 0.10
0.10
Material Lead finish
Package molding compound: Epoxy Lead frame material: Lead frame surface treatment: Solder plate
MS0098-E-01
2001/5
[AK4114]
MARKING
AK4114VQ XXXXXXX
XXXXXXXX: Date code identifier
IMPORTANT NOTICE These products their specifications subject change without notice. Before considering application, consult Asahi Kasei Microsystems Co., Ltd. (AKM) sales office authorized distributor concerning their current status. assumes liability infringement patent, intellectual property, other right application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. products neither intended authorized critical components safety, life support, other hazard related device system, assumes responsibility relating such use, except with express written consent Representative Director AKM. used here: hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonably expected result loss life significant injury damage person property. critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. responsibility buyer distributor product distributes, disposes otherwise places product with third party notify that party advance above content conditions, buyer distributor agrees assume responsibility liability hold harmless from claims arising from said product absence such notification.
MS0098-E-01
2001/5

AK4114 High Feature 192kHz 24bit Digital Audio Interface Transcei

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