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FS612510-01 / -02

1:10 Zero-Delay Clock Buffer IC

FS612510-01 / -02
AMERICAN MICROSYSTEMS, INC.
1:10 Zero-Delay Clock Buffer IC
November 2000
Features
Description
Generates one bank of ten clock outputs (1Y0 to 1Y9) from one reference clock input (CLK) Designed to meet the PLL Component Specifications as noted in the PC133 SDRAM Registered DIMM Design Specification External feedback input (FBIN) to synchronize all clock outputs to the reference input Operating frequency 25MHz to 140MHz Tight tracking skew (spread-spectrum tolerant) On-chip 25 series damping resistors for driving point-to-point loads Output enable (G) enables or disables low all clock outputs Available with an auto power-down option that turns off the PLL and forces all outputs low when the reference clock stops (FS612510-02) Packaged in a 24-pin TSSOP
The FS612510 is a low skew, low jitter CMOS zero-delay phase-lock loop (PLL) clock buffer IC designed for highspeed motherboard applications, such as those using 133MHz SDRAM. Ten buffered clock outputs are derived from an onboard open-loop PLL. The PLL aligns the frequency and phase of all output clocks to the reference input clock CLK, including an FBOUT clock that feeds back to FBIN to close the loop. Multiple power and ground supplies help reduce the effects of noise on device performance. All ten outputs 1Y0 to 1Y9 are enabled and disabled low by the active-high G signal. The PLL can be bypassed for test purposes by pulling AVDD to ground.
Figure 2: Pin Configuration
AGND VDD 1Y0 1Y1 1Y2
CLK AVDD VDD 1Y9 1Y8 GND GND 1Y7 1Y6 1Y5 VDD FBIN
Figure 1: Block Diagram
FS612510
GND GND 1Y3 1Y4 VDD G FBOUT
1Y0 1Y1
1Y2 1Y3
1Y4 1Y5 1Y6 1Y7
Zero-Delay
Table 1: Function Table
1Y8 1Y9
FS612510
FBOUT
This document contains information on a new product. Specifications and information herein are subject to change without notice.
ISO9001 QS9000
PLL Bypass
FS612510-01 / -02
1:10 Zero-Delay Clock Buffer IC
AMERICAN MICROSYSTEMS, INC.
November 2000
Table 2: Pin Descriptions
NAME 1Y0 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 1Y9 AVDD AGND CLK FBIN FBOUT G GND VDD Clock output Clock output Clock output Clock output Clock output Clock output Clock output Clock output Clock output Clock output
DESCRIPTION
Enabled by G
Power Supply / Test mode enable. This pin provides the power supply to the internal PLL. When the pin is pulled low, the PLL is bypassed and the output clocks directly follow the input clock PLL supply ground Reference clock input (Note: -02 version has a pull-down on this pin) Feedback clock input must be connected to FBOUT to complete the loop Feedback output clock Output enable stops all clocks (1Y0 - 1Y9) in a low state when this pin is low Ground for all clock outputs Power supply for all clock outputs
ISO9001 QS9000
FS612510-01 / -02
AMERICAN MICROSYSTEMS, INC.
1:10 Zero-Delay Clock Buffer IC
November 2000
Power-Down
Device Operation
The FS612510-02 version provides an auto power-down feature that shuts off the PLL, drives all outputs low, and places the device into a low current state if the reference clock stops. The power-down circuit is level sensitive, and detects either a DC high or low on the CLK input.
Tracking Skew
PLL-based buffer ICs may be required to follow a spreadspectrum modulated reference clock for frequencies greater than 66MHz. Spread spectrum modulation limits peak EMI emissions by intentionally introducing jitter onto a clock signal, effectively spreading the peak energy over a range of frequencies. A downstream PLL, contained in a clock buffer IC such as this one, must carefully track the modulated input reference clock. A measure of how closely the downstream PLL follows the modulated clock is called the tracking skew. To ensure a tight tracking skew, the loop bandwidth of a downstream PLL is increased and the loop phase angle is reduced over that of typical PLL-based clock generators. The type of modulation profile used impacts tracking skew. The maximum frequency change occurs at the profile limits where the modulation changes the slew rate polarity. To track the sudden reversal in clock frequency, the downstream PLL must have a large loop bandwidth. The ability of the downstream PLL to catch up to the modulating clock is determined by the loop transfer function phase angle. The spread-spectrum reference clock should be either a triangle-wave or a non-linear (Lexmark) modulation profile, with a modulation frequency of 50kHz or less.
PLL Bypass
When the AVDD pin is pulled low, the reference clock signal bypasses the PLL and is muxed directly through to the outputs. The PLL is powered down, and device acts a fanout buffer. Note that if AVDD is re-established, the PLL requires a power-up and stabilization time to lock to the input clock.
Output Enable / Disable
All ten outputs are enabled or disabled as a group by the G enable signal. A logic-high on G input enables all the clock outputs to swing in phase with the reference clock. A logic-low on G forces all of the clock outputs to a logic-low state. The function table Table 1 shows the effect of the G enable signal on the clock outputs.
ISO9001 QS9000
FS612510-01 / -02
1:10 Zero-Delay Clock Buffer IC
AMERICAN MICROSYSTEMS, INC.
November 2000
Electrical Specifications
Table 3: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability.
SYMBOL AVDD VDD VI VO IIK IOK TS TA TJ
MIN. VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 -50 -50 -65 -55
MAX. 7 7 VDD+0.5 VDD+0.5 50 50 150 125 125 260 2
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge.
Table 4: Operating Conditions
ISO9001 QS9000
FS612510-01 / -02
AMERICAN MICROSYSTEMS, INC.
1:10 Zero-Delay Clock Buffer IC
November 2000
Table 5: DC Electrical Specifications
PARAMETER Overall Supply Current, Dynamic Supply Current, Static Output Enable Input (G) High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Clock Inputs (CLK, FBIN) High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Loading Capacitance Clock Outputs (1Y0:9, FBOUT) High-Level Output Source Current Low-Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Source Current Short Circuit Sink Current
SYMBOL
CONDITIONS / DESCRIPTION
UNITS
VDD+0.3 0.8 5
2.0 VSS-0.3 -5 28 4
VDD+0.3 0.8 5
IOH IOL zO IOZ IOSH IOSL
Table 6: Clock Output Drive (1Y0:4, 2Y0:3, FBOUT)
Voltage 0.1 V 0.2 V 0.4 V 0.6 V 0.8 V 1.0 V 1.2 V 1.4 V 1.6 V 1.8 V 2.0 V 2.2 V 2.4 V 2.6 V 2.8 V 3.0 V 3.3 V 3.6 V Low Drive Current (mA) -47 -45 -43 -40 -38 -35 -32 -29 -26 -22 -18 -15 -10 -6 -2 0 -59 -58 -56 -55 -52 -50 -47 -45 -41 -38 -35 -31 -28 -24 -20 -15 -9 -2 High Drive Current (mA) 2 4 8 12 16 20 24 27 31 34 38 41 43 45 48 49 2 4 9 13 17 21 25 29 33 36 40 43 46 49 51 53 56 59
Output Current (mA)
30 Output Voltage (V) 50 90
ISO9001 QS9000
FS612510-01 / -02
1:10 Zero-Delay Clock Buffer IC
AMERICAN MICROSYSTEMS, INC.
November 2000
Table 7: AC Timing Specifications
PARAMETER Overall Skew, Output to Output Skew, Tracking Static Phase Error Clock Stabilization Time Loop Bandwidth Phase Angle Clock Outputs (1Y0:9, FBOUT) Duty Cycle Jitter, Cycle-Cycle Jitter, Period (peak-peak) Rise Time Fall Time Enable Delay Disable Delay
SYMBOL
CONDITIONS / DESCRIPTION
UNITS
tsk(o)
dt tj(CC) tj(P) tr tf tDLH tDHL
Figure 3: Clock Skew Measurement
Figure 4: Phase Error Measurement
Figure 5: Timing Measurement Points
3.3V 2.4V
Figure 6: Output Enable Measurement
ISO9001 QS9000
FS612510-01 / -02
AMERICAN MICROSYSTEMS, INC.
1:10 Zero-Delay Clock Buffer IC
November 2000
Package Information
Table 8: 24-pin TSSOP Package Dimensions
DIMENSIONS INCHES MIN. A A1 A2 b C D E1 E e L S 1 2 3 0.002 0.0315 0.0075 0.0035 0.303 0.169 MAX. 0.047 0.006 0.0413 0.0118 0.0079 0.311 0.177 MILLIMETERS MIN. 0.05 0.80 0.19 0.09 7.70 4.30 MAX. 1.20 0.15 1.05 0.30 0.20 7.90 4.50
AMERICAN MICROSYSTEMS, INC.
0.252 0.0256 0.0177 0.0079 0° 12 REF 12 REF 0.0295 8°
6.40 BSC 0.65 BSC 0.45 0.20 0° 12 REF 12 REF 0.75 8°
SEATING PLANE
BASE PLANE
Table 9: 24-pin TSSOP Package Characteristics
TYP. 84 1.7 0.6 0.24 0.3 0.1 0.007
UNITS °C / W nH nH pF pF
ISO9001 QS9000
FS612510-01 / -02
1:10 Zero-Delay Clock Buffer IC
AMERICAN MICROSYSTEMS, INC.
November 2000
Ordering Information
Table 10: Device Ordering Codes
DEVICE NUMBER FS612510-01 FS612510-02 ORDERING CODE PACKAGE TYPE 24-pin TSSOP (Thin Shrink Small Outline Package) 24-pin TSSOP (Thin Shrink Small Outline Package) OPERATING TEMPERATURE RANGE 0°C to 70°C (Commercial) 0°C to 70°C (Commercial) SHIPPING CONFIGURATION Tape and Reel Tape and Reel
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: tgp@amis.com
ISO9001 QS9000