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DS07-16502-3E

32-Bit Proprietary Microcontroller

FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16502-3E
32-Bit Proprietary Microcontroller
FR60 MB91301 Series MB91302A / V301A
DESCRIPTION
The MB91301 series are a line of microcontrollers based on a 32-bit RISC CPU core (FR family) , incorporating a variety of I / O resources and a bus control mechanism for embedded control that requires the processing of a high-performance, fast CPU as well as an SDRAM interface that can connect SDRAM directly to the chip. The large address space supported by the 32-bit CPU addressing means that operation is primarily based on external bus access although instruction cache memory of 4 Kbytes and RAM of 4 Kbytes( for data) are included for high-speed execution of CPU instructions. The MB91302A and MB91V301A are FR60 products based on the FR30 / 40 CPU with enhanced bus access for higher speed operation. The device specifications include a D / A converter to facilitate motor control and are ideal for use in DVD players that support fly-by transfer.
FEATURES
The MB91301 series is a line of ICs with various programs embedded in internal ROM.
ROM variation Product name
Built-in the real Built-in IPL time OS version (Internal Program Loader) version
User ROM version
Without ROM version
MB91302A (Continued)
PACKAGES
144-pin, Plastic LQFP 179-pin, Ceramic PGA
(FPT-144P-M12)
(PGA-179C-A03)
MB91301 Series
1. FR CPU
2. Bus interface
3. Built-in memory
· 4 Kbytes DATA RAM · 4 Kbytes RAM (MB91302A) (Continued)
MB91301 Series
4. Instruction cache
· · · · · · · · · · · · Size : 4 Kbytes 2-way set associative 128 blocks / way, 4 entries / block Lock function enables program code to be made cache-resident Areas not used for instruction cache can be used as instruction RAM 5-channel (2-channel external-to-external) 3 transfer triggers : External pin, internal peripheral, software Capable of selecting an internal peripheral as a transfer source freely for each channel Addressing using 32-bit full addressing mode (increment, decrement, fixed) Transfer modes : Demand transfer, burst transfer, step transfer, or block transfer Supports fly-by transfer (between external I / O and memory) Selectable transfer data size : 8, 16, or 32-bit
5. DMAC (DMA Controller)
6. Bit search module
· Searches words from MSB for position of first 1 / 0 bit value change
7. Reload Timers
· 16-bit timer : 3 channels · Internal clock : 2 clock cycle resolution, divide by 2 / 8 / 32 selective
8. UART
Full duplex, double buffer UART Independent 3 channels Data length : 7 bits to 9 bits (without parity) , 6 bits to 8 bits (with parity) Asynchronous (start-stop synchronized) or CLK-synchronous communications selectable Multi-processor mode · Built-in 16-bit timer (U-TIMER) as a baud rate generator to generate arbitrary baud rates · External clock can be used as transfer clock · Variety of error detection functions (parity, frame, overrun) · · · ·
9. Interrupt controller
· External interrupt input : 1 non-maskable interrupt pin and 8 normal interrupt pins (INT0 to INT7) · Internal internal resources : UART, DMAC, A / D, U-TIMER, Delay interrupt, I2C, Free-run timer, Input capture · Programmable priorities (16 levels) for all interrupts except the non-maskable interrupt
10. A / D converter
· · · · · 10-bit resolution, 4 channels Successive approximation type, conversion time : 4.1 µs at 34 MHz Built-in sample and hold circuit Conversion modes : Single conversion mode, scan conversion mode and repeat conversion mode selectable Conversion triggers : Software, external trigger and built-in timer selectable
11. I2C interface
· Internal 2-channels master / slave transmit / receive · Internal arbitration function, clock synch function
12. Free-run timer
· 16 bit : 1channel (Continued)
MB91301 Series
(Continued)
13. Input capture
· 4 channels
14. Other interval timers
· 16-bit timer : 3 channels (U-TIMER) · PPG timer : 4 channels · Watchdog timer : 1 channel
15. Other features
PRODUCT LINEUP
MB91302A Type Mask ROM product (for volume production) 4 Kbytes (only for data) 4 Kbytes ROM has non-ROM model, the optimal real time OS internal model1, and the IPL (Internal Program Loader) internal model2 by adding the user ROM model. LQFP-144 (0.4 mm pitch) MB91V301A Evaluation version (For evaluation and development) 16 Kbytes (data 8 KB+8 KB)
8 Kbytes (RAM)
DSU Package
DSU4 PGA-179
1 : The Fujitsu product of real time OS REALOS / FR by conforming to the µITRON 3.0 is stored and optimized with the MB91302A. 2 : The ROM stores the IPL (Internal Program Loader) . Loading various programs can be executed from the external system by the internal UART / SIO. Using this function, for example, writing on board to the Flash memory connected to the external can be executed.
MB91301 Series
PIN ASSIGNMENTS
· MB91302A
(TOP VIEW)
P91 / MCLKE P92 / MCLK P93 P94 / SRAS / LBA / AS P95 / SCAS / BAA P96 / SWE / WR VSS VCC A00 A01 A02 A03 A04 A05 A06 A07 VSS VCC A08 A09 A10 A11 A12 A13 A14 A15 VSS P60 / A16 P61 / A17 P62 / A18 P63 / A19 P64 / A20 / SDA0 P65 / A21 / SCL0 P66 / A22 / SDA1 P67 / A23 / SCL1 VCC
P13 / D11 P14 / D12 P15 / D13 P16 / D14 P17 / D15 VSS VCC P20 / D16 P21 / D17 P22 / D18 P23 / D19 P24 / D20 P25 / D21 P26 / D22 P27 / D23 VSS VCC D24 D25 D26 D27 D28 D29 D30 D31 VSS VCC P80 / RDY P81 / BGRNT P82 / BRQ RD DQMUU / WR0(UUB) P85 / DQMUL / WR1(ULB) P86 / DQMLU / WR2(LUB) P87 / DQMLL / WR3(LLB) P90 / SYSCLK
D10 / P12 D09 / P11 D08 / P10 VCC VSS D07 / P07 D06 / P06 D05 / P05 D04 / P04 D03 / P03 D02 / P02 D01 / P01 D00 / P00 VCC VSS CS7 / PA7 CS6 / PA6 CS5 / PPG2 / PA5 CS4 / TRG2 / PA4 CS3 / PA3 CS2 / PA2 CS1 / PA1 CS0 / PA0 VCC NMI INIT MD2 MD1 MD0 VCC VSS X1 X0 VCC IORD / PB7 IOWR / PB6 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
DEOP1 / PPG1 / PB5 DACK1 / TRG1 / PB4 DREQ1 / PB3 DEOP0 / PB2 DACK0 / PB1 DREQ0 / PB0 C VSS TIN2 / TRG3 / PH2 TIN1 / PPG3 / PH1 TIN0 / PH0 TRG0 / PJ7 PPG0 / PJ6 SCK1 / PJ5 SOT1 / PJ4 SIN1 / PJ3 SCK0 / PJ2 SOT0 / PJ1 SIN0 / PJ0 VCC INT7 / SCK2 / PG7 INT6 / SOT2 / PG6 INT5 / SIN2 / PG5 INT4 / ATG / PG4 / FRCK INT3 / PG3 / ICU3 INT2 / PG2 / ICU2 INT1 / PG1 / ICU1 INT0 / PG0 / ICU0 AVSS / AVRL AN0 AN1 AN2 AN3 AVR AVRH AVCC
(FPT-144P-M12)
MB91301 Series
· MB91V301A (TOP VIEW)
INDEX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 5 7 10 15 16 20 21 25 26 30 33 37 39 43 50 178 179 4 9 13 14 19 22 27 31 34 38 42 44 52 174 177 2 3 8 12 18 24 28 32 36 41 47 49 55 172 173 176 180 6 11 17 23 29 35 40 45 48 54 60 46 51 53 58 61 56 57 59 65 62 63 64 66 68 69 67 70 74 73 72 71 80 77 76 75 91 85 81 79 78 168 169 171 175 1 165 166 167 170 161 162 163 164 160 157 159 158 156 154 153 152 155 149 147 146 151 148 143 141 136 150 144 138 135 130 125 119 113 107 101 96 90 86 83 82 145 139 137 131 126 122 118 114 108 102 98 93 92 87 84 142 134 132 128 124 121 117 112 109 104 103 99 94 89 88 140 133 129 127 123 120 116 115 111 110 106 105 100 97 95
(PGA-179C-A03)
MB91301 Series
· MB91V301A Pin No. Table No. PIN Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 E5 C3 C4 B3 A1 D5 A2 C5 B4 A3 D6 C6 B5 B6 A4 A5 D7 C7 B7 A6 A7 B8 D8 C8 A8 A9 B9 C9 D9 A10 N.C. P13 / D11 VSS VCC P14 / D12 P15 / D13 P16 / D14 P17 / D15 VSS VCC P20 / D16 P21 / D17 P22 / D18 P23 / D19 P24 / D20 P25 / D21 P26 / D22 P27 / D23 VSS VCC D24 D25 D26 D27 VSS VCC D28 D29 D30 D31
No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
PIN B10 C10 A11 B11 D10 C11 A12 B12 A13 D11 C12 B13 A14 B14 D12 E11 C13 D13 C14 A15 E12 B15 E13 D14 C15 F12 F13 E14 F14 D15
Pin Name VSS VCC P80 / RDY P81 / BGRNT P82 / BRQ RD DQMUU / WR0 (UUB) P85 / DQMUL / WR1 (ULB) P86 / DQMLU / WR2 (LUB) P87 / DQMLL / WR3 (LLB) VSS VCC P90 / SYSCLK P91 / MCLKE P92 / MCLK P93 VSS VCC P94 / SRAS / LBA / AS P95 / SCAS / BAA P96 / SWE / WR VSS VCC A00 A01 A02 A03 A04 A05 A06
No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
PIN E15 G12 G13 G14 F15 G15 H14 H12 H13 H15 J15 J14 J13 J12 K15 K14 K13 L15 L14 K12 L13 M15 M14 N15 L12 M13 N14 P15 P14 M12
Pin Name A07 VSS VCC A08 A09 A10 A11 A12 A13 A14 A15 VSS VCC P60 / A16 P61 / A17 P62 / A18 P63 / A19 SDA0 / P64 / A20 SCL0 / P65 / A21 SDA1 / P66 / A22 SCL1 / P67 / A23 VCC VCC EWR3 EWR2 EWR1 EWR0 ECS EMRAM ICD3 (Continued)
MB91301 Series
(Continued) No. PIN 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 L11 N13 N12 P13 R15 M11 R14 N11 P12 R13 M10 N10 P11 P10 R12 R11 M9 N9 P9 R10 R9 P8 M8 N8 R8 R7 P7 N7 M7 R6
Pin Name ICD2 ICD1 ICD0 VSS VCC BREAK ICLK ICS2 ICS1 ICS0 TRST C AVCC AVRH AVR AN3 AN2 AN1 AN0 AVSS / AVRL INT0 / PG0 / ICU0 INT1 / PG1 / ICU1 INT2 / PG2 / ICU2 INT3 / PG3 / ICU3 INT4 / ATG / PG4 / FRCK INT5 / SIN2 / PG5 INT6 / SOT2 / PG6 INT7 / SCK2 / PG7 VCC SIN0 / PJ0
No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
PIN P6 N6 R5 P5 M6 N5 R4 P4 R3 M5 N4 P3 R2 P2 M4 L5 N3 M3 N2 R1 L4 P1 L3 M2 N1 K4 K3 L2 K2 M1
Pin Name SOT0 / PJ1 SCK0 / PJ2 SIN1 / PJ3 SOT1 / PJ4 SCK1 / PJ5 PPG0 / PJ6 TRG0 / PJ7 TIN0 / PH0 TIN1 / PPG3 / PH1 TIN2 / TRG3 / PH2 VSS C DREQ0 / PB0 DACK0 / PB1 DEOP0 / PB2 DREQ1 / PB3
No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166
PIN L1 J4 J3 J2 K1 J1 H2 H4 H3 H1 G1 G2 G3 G4 F1 F2 F3 E1 E2 F4 E3 D1 D2 C1 E4 D3 C2 B1 B2 D4
Pin Name VCC INIT NMI VSS VCC CS0 / PA0 CS1 / PA1 CS2 / PA2 CS3 / PA3 CS4 / TRG2 / PA4 CS5 / PPG2 / PA5 CS6 / PA6 CS7 / PA7 VSS VCC D00 / P00 D01 / P01 D02 / P02 D03 / P03 VSS VCC D04 / P04 D05 / P05 D06 / P06 D07 / P07 VSS VCC D08 / P10 D09 / P11 D10 / P12
DACK1 / TRG1 / PB4 167 DEOP1 / PPG1 / PB5 168 IOWR / PB6 IORD / PB7 VCC VSS X0 X1 VSS VCC MD0 MD1 MD2 VCC 169 170 171 172 173 174 175 176 177 178 179 180
MB91301 Series
PIN DESCRIPTIONS
· Except for Power supply, GND, and Tool pins
Pin no. MB91302A MB91V301A 166 to 169, 172 to 175
Pin name D00 to D07
I / O circuit type
Function External data bus bits 0 to 7. It is available in the external bus mode. Can be used as ports in 8-bit or 16-bit external bus mode. External data bus bits 8 to 15. It is available in the external bus mode. Can be used as ports in 8-bit or 16-bit external bus mode. External data bus bits 16 to 23. It is available in the external bus mode. Can be used as ports in 8-bit external bus mode. External data bus bits 24 to 31. It is available in the external bus mode. External ready input. The pin has this function when external ready input is enabled. General purpose input / output port. The pin has this function when external ready input is disabled. Acknowledge output for external bus release. Outputs "L" when the external bus is released. The pin has this function when output is enabled. General purpose input / output port. The pin has this function when output is disabled for external bus release acknowledge. External bus release request input. Input "1" to request release of the external bus. The pin has this function when input is enabled. General purpose input / output port. The pin has this function when the external bus release request input is disabled. External bus read strobe output. External bus write strobe output. When WR is used as the write strobe, this becomes the byte-enable pin (UUB). Select signal (DQMUU) of D31 to D24 at using of SDRAM. (Continued)
132 to 139
J P00 to P07 D08 to D15 J P10 to P17 D16 to D23 P20 to P27
142 to 144, 1 to 5
178 to 180, 2, 5 to 8
11 to 18 21 to 24, 27 to 30
D24 to D31 RDY
33 P80
BGRNT 29 34 P81 J
WR0 / (UUB) / DQMUU
MB91301 Series
Pin no. MB91302A MB91V301A
Pin name
I / O circuit type
Function External bus write strobe output. The pin has this function when WR1 output is enabled. When WR is used as the write strobe, this becomes the byteenable pin (ULB). Select signal (DQMUL) of D23 to D16 at using of SDRAM. General purpose input / output port. The pin has this function when the external bus write-enable output is disabled. External bus write strobe output. The pin has this function when WR2 output is enabled. When WR is used as the write strobe, this becomes the byteenable pin (LUB). Select signal (DQMLU) of D08 to D05 at using of SDRAM. General purpose input / output port. The pin has this function when the external bus write-enable output is disabled. External bus write strobe output. The pin has this function when WR3 output is enabled. When WR is used as the write strobe, this becomes the byteenable pin (LLB). Select signal (DQMLL) of D07 to D00 at using of SDRAM. General purpose input / output port. The pin has this functions when the external bus write-enable output is disabled. System clock output. The pin has this function when system clock output is enabled. This outputs the same clock as the external bus operating frequency. (Output halts in stop mode.) General purpose input / output port. The pin has this function when system clock output is disabled. Clock enable signal for memory.
WR1 / (ULB) / DQMUL 33 38 P85 J
WR2 / (LUB) / DQMLU 34 39 P86 J
WR3 / (LLB) / DQMLL 35 40 P87 J
SYSCLK 36 43 P90 MCLKE 37 40 P91 J C
General purpose input / output port. The pin has this function when clock enable output is disabled. Memory clock output. The pin has this function when memory clock output is enabled. This outputs the same clock as the external bus operating frequency. (Output halts in sleep mode.) General purpose input / output port. The pin has this function when memory clock output is disabled.
MCLK 38 45 P92 39 46 P93 C C
General purpose input / output port. (Continued)
MB91301 Series
Pin no. MB91302A MB91V301A
Pin name
I / O circuit type
Function Address strobe output. The pin has this function when ASE bit of port function register 9 is enabled "1". Address strobe output for burst flash ROM. The pin has this function when ASE bit of port function register 9 is enabled "1". RAS single for SDRAM. This pin has this function when ASE bit of port function register 9 is enabled "1". General purpose input / output port. The pin has this function when ASE bit of port function register 9 is "0" general purpose port. Address advance output for burst Flash ROM. The pin has this function when BAAE bit of port function register (PFR9) is enabled.
LBA 40 49 SRAS J
CAS signal for SDRAM. This pin has this function when BAAE bit of port function register (PFR9) is enabled. General purpose input / output port. The pin has this function when BAAE bit of port function register is general purpose port. Memory write strobe output. This pin has this function when WRXE bit of port function register is enabled.
Write output for SDRAM. This pin has this function when WRXE bit of port function register is enabled. General purpose input / output port. This pin has this function when WRXE bit of port function register is general purpose port.
P96 45 to 52 55 to 62 54 to 61 64 to 71 A00 to A07 A08 to A15 A16 to A19 64 to 67 74 to 77 P60 to P63 J C C
External address bits 0 to 7. External address bits 8 to 15. External address bits 16 to 19. It is available in external bus mode. Can be used as ports when external address bus is not used. (Continued)
MB91301 Series
Pin no. MB91302A MB91V301A
Pin name
I / O circuit type
Function Data input pin for I2C bus function. This function is enable when typical operation of I2C is enable. The port output must remains off unless intentionally turned on. (Open drain output) (This function is only for MB91302A, MB91V301A.)
78 A20
External address bus bit 20. This function is enable during prohibited I2C operation and using external bus. General-purpose I / O port. This function is enable during prohibited I2C and nonused external address bus. CLK input pin for I2C bus function. This function is enable when typical operation of I2C is enable. The port output must remains off unless intentionally turned on. (open drain output) (This function is only for MB91302A, MB91V301A.)
79 A21
External address bus bit 21. This function is enable during prohibited I2C operation and using external bus. General-purpose I / O port. This function is enable during prohibited I2C and nonused external address bus. DATA input pin for I2C bus function. This function is enable when typical operation of I2C is enable. The output must remains off unless intentionally turned on. (open drain output) (This function is only for MB91302A, MB91V301A.)
80 A22
External address bus bit 20. This function is enable during prohibited I2C operation and using external bus. General-purpose I / O port. This function is enable during prohibited I2C and nonused external address bus. (Continued)
MB91301 Series
Pin no. MB91302A MB91V301A
Pin name
I / O circuit type
Function CLK input pin for I2C bus function. This function is enable when typical operation of I2C is enable. The port output must remains off unless intentionally turned on. (open drain output) (This function is only for MB91302A, MB91V301A.) External address bus bit 21. This function is enable during prohibited I2C operation and using external bus. General-purpose I / O port. This function is enable during prohibited I2C operation and nonused external address bus. Analog input pin. External interrupt inputs. These inputs are used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. General purpose input / output ports. Input capture input pins. These inputs are used continuously when selected as input capture inputs. In this case, do not output to these ports unless doing so intentionally. External interrupt input. These inputs are used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. External trigger input for A / D converter. This input is used continuously when selected as the A / D converter start trigger. In this case, do not output to this port unless doing so intentionally. General purpose input / output ports. External clock input pin for free-run timer. This input is used continuously when selected as the external clock input pin for the free-run timer. In this case, do not output to this port unless doing so intentionally. External interrupt input. These inputs are used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. UART2 data input pin. This input is used continuously when UART2 is performing input. In this case, do not output to this port unless doing so intentionally. General purpose input / output port. (Continued)
81 A23
P67 76 to 79 106 to 109 AN3 to AN0 INT0 to INT3 81 to 84 111 to 114 PG0 to PG3 ICU0 to ICU3 V D
ATG PG4 FRCK
INT5 86 116 SIN2 PG5 V
MB91301 Series
Pin no. MB91302A MB91V301A
Pin name
I / O circuit type
Function External interrupt input. This input is used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. UART2 data output pin. The pin has this function when UART2 data output is enabled. General purpose input / output port. External interrupt input. This input is used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. UART2 clock input / output pin. The pin has this function when UART2 clock output is enabled. General purpose input / output port. UART0 data input pin. This input is used continuously when UART0 is performing input. In this case, do not output to this port unless doing so intentionally. General purpose input / output port. UART0 data output pin. The pin has this function when UART0 data output is enabled. General purpose input / output port. UART0 clock input / output pin. The pin has this function when UART0 clock output is enabled. General purpose input / output port. UART1 data input pin. This input is used continuously when UART1 is performing input. In this case, do not output to this port unless doing so intentionally. General purpose input / output port. UART1 data output pin. The pin has this function when UART1 data output is enabled. General purpose input / output port. UART1 clock input / output pin. The pin has this function when UART1 clock output is enabled. General purpose input / output port. PPG timer output. This pin has this function when PPG0 output is enabled. General purpose input / output port. (Continued)
INT6 87 117 SOT2 PG6 V
INT7 88 118 SCK2 PG7 SIN0 PJ0 91 121 SOT0 PJ1 92 122 SCK0 PJ2 SIN1 PJ3 94 124 SOT1 PJ4 95 125 SCK1 PJ5 96 126 PPG0 PJ6 U U U U U V
MB91301 Series
Pin no. MB91302A MB91V301A
Pin name
I / O circuit type
Function External trigger input for PPG timer. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. General purpose input / output port. Reload timer input. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. General purpose input / output port. Reload timer input. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. PPG timer output. The pin has this function when PPG3 output is enabled. General purpose input / output port. Reload timer input. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally.
TRG0 PJ7 TIN0 PH0 TIN1
129 PPG3 PH1 TIN2
130 TRG3 PH2 DREQ0 PB0 DACK0 PB1 DEOP0 PB2
External trigger input for PPG timer. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. General purpose input / output port. External input for DMA transfer requests. This input is used continuously when selected as a DMA activation trigger. In this case, do not output to this port unless doing so intentionally. General purpose input / output port. External acknowledge output for DMA transfer requests. The pin has this function when outputting DMA transfer request acknowledgement is enabled. General purpose input / output port. Completion output for DMA external transfer. The pin has this function when outputting DMA transfer completion is enabled. General purpose input / output port. (Continued)
MB91301 Series
Pin no. MB91302A MB91V301A
Pin name
I / O circuit type
Function DMA External input for DMA transfer requests. This input is used continuously when selected as a DMA activation trigger. In this case, do not output to this port unless doing so intentionally. General purpose input / output port. The pin has this function when completion output and stop input are disabled for DMA transfer. External acknowledge output for DMA transfer requests. The pin has this function when outputting DMA transfer request acknowledgement is enabled.
DREQ1 106 136 PB3 J
DACK1 107 137 TRG1 PB4 DEOP1 108 138 PPG1 PB5 IOWR 109 139 PB6 J J J
External trigger input for PPG timer. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. General purpose input / output port. Completion output for DMA external transfer. The pin has this function when outputting DMA transfer completion is enabled. PPG timer output. The pin has this function when PPG1 bit is enabled. General purpose input / output port. Write strobe output for DMA fly-by transfer. The pin has this function when outputting a write strobe for DMA fly-by transfer is enabled. General purpose input / output port. The pin has this function when outputting a write strobe for DMA fly-by transfer is disabled. Read strobe output for DMA fly-by transfer. The pin has this function when outputting a read strobe for DMA fly-by transfer is disabled. General purpose input / output port. The pin has this function when outputting a write strobe for DMA fly-by transfer is disabled. Clock (oscillation) input. Clock (oscillation) output. Mode pins 0 to 2. The levels applied to these pins set the basic operating mode. Connect VCC or VSS. External reset input (Reset to initialize settings) ("L" active) NMI (Non Maskable Interrupt) input ("L" active) (Continued)
IORD 110 140 PB7 112 113 116 to 118 119 120 143 144 147 to 149 152 053 X0 X1 MD0 to MD2 INIT NMI A A G B M J
MB91301 Series
(Continued) Pin no. MB91302A MB91V301A
Pin name CS0
I / O circuit type
Function Chip select 0 output. The pin has this function when chip select 0 output is enabled. General purpose input / output port. The pin has this function when chip select 0 output is disabled. Chip select 1 output. The pin has this function when chip select 1 output is enabled. General purpose input / output port. The pin has this function when chip select 1 output is disabled. Chip select 2 output. The pin has this function when chip select 2 output are enabled. General purpose input / output port. The pin has this function when chip select 2 output is disabled. Chip select 3 output. The pin has this function when chip select 3 output are enabled. General purpose input / output port. The pin has this function when chip select 3 output is disabled. Chip select 4 output. The pin has this function when chip select 4 output is enabled.
156 PA0 CS1
157 PA1 CS2
158 PA2 CS3
159 PA3 CS4
External trigger input for PPG timer. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. General purpose input / output port. The pin has this function when chip select 4 output is disabled. Chip select 5 output. The pin has this function when chip select 5 output are enabled.
PA4 CS5 127 161 PPG2 PA5 CS6 128 162 PA6 CS7 129 163 PA7 J J J
PPG timer output. The pin has this function when PPG2 bit is enabled. General purpose input / output port. The pin has this function when chip select 5 output and PPG timer output are disabled. Chip select 6 output. The pin has this function when chip select 6 output is enabled. General purpose input / output port. The pin has this function when chip select 6 output are disabled. Chip select 7 output. The pin has this function when chip select 7 output are enabled. General purpose input / output port. The pin has this function when chip select 7 output is disabled.
MB91301 Series
I / O CIRCUIT TYPE
Circuit
Remarks · Oscillation feedback resistance approx. 1 M Clock input
Standby control · CMOS hysteresis input with pull-up resistor
P-ch P-ch
Digital input Standby control ·Analog input With switch
Analog input Control (Continued)
MB91301 Series
Circuit
Remarks ·CMOS level output No standby control
Digital input Pull-up control
P-ch P-ch
Digital output Digital output
Digital input Standby control Pull-up control
P-ch P-ch
Digital output
Digital input Standby control Pull-up control
P-ch P-ch
Digital output L
Digital output
Digital input · CMOS level hysteresis input no standby control
Digital input (Continued) 19
MB91301 Series
Circuit
Digital output Digital output
Digital input
· Input buffer with Pull-up
Digital input
Digital output R
N-ch N-ch
Digital output
Digital output Digital output
Digital input (Continued)
MB91301 Series
(Continued) Type
Circuit Pull-up control Digital output with open-drain control Digital output
Digital input
Digital output
Digital output Digital input
Digital output V
Digital output Digital input
MB91301 Series
HANDLING DEVICES
MB91301 series · Operation at start-up Always apply a settings initialization (INIT) to the INIT pin immediately after turning on the power. Also, in order to provide a delay while the oscillator circuits stabilize immediately after start-up, maintain the "L" level input to the INIT pin for the required stabilization delay time. (The initialization processing (INIT) triggered by the INIT pin initializes the oscillation stabilization delay time to the minimum setting.) · External clock input at start-up At power-on start-up, always input a clock signal until the oscillation stabilization delay time is ended. · Output indeterminate at power-on time When the power is turned on, the output pin may remain indeterminate until the internal power supply becomes stable. · Built-in DC / DC regulator This device has a built-in regulator, requiring 3.3 V input to the Vcc pin and a bypass capacitor of approximately 4.7 µF connected to the C pin for the regulator.
3.3 V VCC AVCC AVRH 0.05 µF AVR AVSS / AVRL VSS MB91301 series VSS 4.7 µF
Note of built-in DC / DC regulator
· Note on use of the A / D converter As the MB91301 series contains an A / D converter, be sure to supply power to AVcc at 3.3 V and insert a capacitor of at least 0.05 µF between the AVR pin and the AVss / AVRL pin.
AVCC AVRH AVR
0.05 µF
AVSS / AVRL
MB91301 series
Note on Use of A / D Converter
MB91301 Series
MB91301 series
Note: Stop mode (oscillation stop mode) can not be used. Using an external clock (normal)
MB91301 series
Using an external clock (12.5 MHz Max)
· Notes on during operation of PLL clock mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. · Clock control block For L-level input to the INIT pin, allow for the regulator settling time or oscillation settling time. · Bit search module The 0-detection, 1-detection, and transition-detection data registers (BSD0, BSD1, and BSDC) are only wordaccessible. · I / O port access Byte access only for access to port · Shared port function switching To switch a pin that also serves as a port, use the port function register (PFR). Note, however, that bus pins are switched depending on external bus settings. · D-bus memory Do not set a code area in D-bus memory. No instruction fetch is performed to the D-bus. Instruction fetches to the D-bus area result in incorrect data interpreted as code, which can cause the microcontroller to lose control. Do not set a data area in I-bus memory. 24
MB91301 Series
Unique to the evaluation chip MB91V301A · Tool reset On an evaluation board, use the chip with INIT and TRST connected together. · Simultaneous occurrences of a software break and a user interrupt / NMI When a software break and a user interrupt / NMI take place at the same time, the emulator debugger can cause the following phenomena: · The debugger stops pointing to a location other than the programmed breakpoints. · The halted program is not re-executed correctly. If these phenomena occur, use a hardware break instead of the software break. If the monitor debugger has been used, avoid setting any break at the relevant location. · Single-stepping the RETI instruction If an interrupt occurs frequently during single stepping, execute only the relevant processing routine repeatedly after single-stepping RETI. This will prevent the main routine and low-interrupt-level programs from being executed. Do not single-step the RETI instruction for avoidance purposes. When the debugging of the relevant interrupt routine becomes unnecessary, perform debugging with that interrupt disabled. · Operand break A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data event break to access to the area containing the address of a system stack pointer. · ICE startup sequence When using the ICE, when you start debugging, ensure that the bus configuration is set correctly for the area being used before downloading. After turning on the power to the target, the states of the RD and WR0 to WR3 pins are undefined until you perform the above setting. Accordingly, include enabling pull-up as part of the startup sequence. If using these pins as general-purpose ports, set as output ports to prevent conflict with the output signals during the time the pin states are undefined. External bus width Pin name RD WR0 WR1 (P85) WR2 (P86) WR3 (P87) : Use as output ports.
32 bit Pull-up Pull-up Pull-up Pull-up Pull-up
16 bit Pull-up Pull-up Pull-up
8 bit Pull-up Pull-up
MB91301 Series
BLOCK DIAGRAM
· MB91302A, MB91V301A
FR CPU Core
Instruction Cache 4 KB
DREQ0, DREQ1 DACK0, DACK1 DEOP0, DEOP1 IOWR IORD
Bit search module
MB91302A : RAM 4 KB MB91V301A : RAM 8 KB (stack)
DMAC 5 channels
MB91302A : ROM 4 KB MB91V301A : RAM 8 KB
Bus Converter
X0, X1 MD0 to MD2 INIT
16 32 Adapter
Clock control
External memory I / F
A23 to A00 D31 to D16 D15 to D00 RD, WR WR0 to WR3 CS0 to CS7 RDY BRQ BGRNT SYSCLK MCLK AS MCLKE SRAS SCAS SWE DQMUU, L DQMLU, L LBA BAA PPG0 to PPG3 TRG0 to TRG3
Interrupt controller
INT0 to INT7 NMI SIN0 to SIN2 SOT0 to SOT2 SCK0 to SCK2
8 channels External interrupts
3 channels UART
4 channels PPG timer
3 channels U-TIMER
AN0 to AN3 ATG AVRH, AVCC AVSS / AVRL TIN0 to TIN2 PORT
4 channels A / D converter
3 channels Reload timer
2 channels I2C I / F
SDA0, SDA1 SCL0, SCL1
Free Run Timer
4 channels Input Capture
ICU0 to ICU3
: ROM has non-ROM model, the optimal real time OS internal model, and the IPL (Internal Program Loader) internal model by adding the user ROM model. 29
MB91301 Series
1. Memory Space
The FR family has 4 Gbytes (232 addresses) of logical address space with linear access from the CPU. · Direct Addressing Areas The following areas of address space are used for I / O operations. These areas are called direct addressing areas, in which the address of an operand can be specified directly during an instruction. The direct areas differ according to the size of the data accessed, as follows. byte data access : 000H to 0FFH half word data access : 000H to 1FFH word data access : 000H to 3FFH
MB91301 Series
· Memory map
0000 0000H
Direct addre ssing area see "I / O MAP" I / O
0000 0400H
I / O 0001 0000H 0002 0000H
I-RAM
0003 E000H
Access prohibited
Internal RAM 4 Kbytes
Access prohibited
Internal RAM 4 Kbytes
Access prohibited
Internal RAM 4 Kbytes
Access prohibited
0003 F000H
Internal RAM 8 Kbytes Internal RAM 8 Kbytes Access prohibited
Internal RAM 8 Kbytes
0004 0000H
0004 2000H
External area
0006 0000H 000E 0000H
Access prohibited Access prohibited
External area
000F E000H
000F F000H
Internal ROM 4 Kbytes2
0010 0000H
Internal ROM 4 Kbytes2
Internal RAM 8 Kbytes emulation
Access prohibited
FFFF FFFFH
External area
MB91302A has non-ROM model, the optimal real time OS internal model, and the IPL (Internal program Loader) internal model by adding the user ROM model. 1 : On specific area between 10000H and 2000H, 4 Kbytes RAM can be used. Refer to "INSTRUCTION CACHE". 2 : The real time OS internal model stores the real time OS kernel. The program loader internal model stores the program loader. Note : Internal ROM emulation : only MB91V301A Note : Each mode is set depending on the mode vector fetch after INIT is negated. (For mode setting, see "MODE SETTINGS".) 31
MB91301 Series
2. Registers
The FR series has two types of registers: application-specific registers in the CPU and general purpose registers in memory. · Dedicated registers Program counter (PC) Program status (PS) Table base register (TBR) Return pointer (RP) System stack pointer (SSP) User stack pointer (USP) Multiplication and division result register (MDH / MDL)
: 32-bit register. Stores the current instruction address. : 32-bit register. Contains the register pointer and condition code. : Stores the top address of the vector table used by the EIT (exception / interrupt / trap) function. : Stores the subroutine return address. : Points to the system stack area. : Points to the user stack area. : 32-bit registers used for multiplication and division.
32 bit PC
Initial value Program counter Program status Table base register Return pointer System stack pointer User stack pointer Multiplication and division result register
000F FC00H XXXX XXXXH 0000 0000H XXXX XXXXH XXXX XXXXH XXXX XXXXH XXXX XXXXH
MDH MDL
· PC (Program Counter) The PC is the program counter and stores the address of the currently executing instruction.
· Table base register (TBR) The TBR is the table base register and stores the top address of the vector table used by the EIT function.
TBR 32
MB91301 Series
· Return pointer (RP) The RP is the return pointer and stores the subroutine return address.
· System stack pointer (SSP) The SSP is the system stack pointer and functions as R15 when the S flag is "0".
· User stack pointer (USP) The USP is the user stack pointer and functions as R15 when the S flag is "1".
· Multiplication and division result register (MDH / MDL) MDH / MDL : 32-bit registers used for multiplication and division. MDH MDL : Remainder : Quotient
31 MDH MDL 0
Multiplication and division result register
MB91301 Series
· Program status (PS) This register holds the program status and is divided into the ILM, SCR, and CCR. Bit position 31
PS · Condition code register (CCR) S flag : Specifies which stack pointer to use as R15. I flag : Enables or disables user interrupt requests. N flag : Indicates the sign when an operation result is represented as a "2" complement integer. Z flag : Indicates whether an operation result is "0". V flag : Indicates whether an overflow occurred for an operation result when the operation operand is represented as a "2" complement integer. C flag : Indicates whether an operation resulted in a borrow or a carry from the most significant bit.
Initial Value
- - 00XXXXB
CCR · System condition code register (SCR) D1, D0 flags : Stores intermediate data for stepwise multiplication operations. T flags : A flag specifying whether the step trace trap function is enabled or not.
Initial Value XX0B
SCR · Interrupt level mask register(ILM) ILM4 to ILM0 : This register stores the interrupt level mask value. The value in the ILM register is used as the level mask. Only interrupt requests to the CPU that have an interrupt level that is higher than the level specified in ILM are accepted. 20 ILM4 0 0 1 19 ILM3 0 1 1 18 ILM2 0 ··· 0 ··· 1 1 ILM 34 1 0 0 17 ILM1 0 16 ILM0 0 Interrupt Level 0 ··· 15 ··· 31 High (Medium) Low Initial Value 01111B
MB91301 Series
GENERAL PURPOSE REGISTERS
General purpose registers R0 to R15 are used by the CPU. The registers are used as the accumulator and memory access pointers for CPU operations. 32-bit
Initial Value
XXXX XXXXH
R12 R13 R14 R15
AC (Accumulator) FP (Frame Pointer) SP (Stack Pointer)
XXXX XXXXH 0000 0000H
The following three registers are treated as having special meanings to enhance the operation of some instructions. R13 : Virtual accumulator (AC) R14 : Frame pointer (FP) R15 : Stack pointer (SP) The values of R0 to R14 after a reset are undefined. R15 is initialized to 0000 0000H (SSP value) .
MB91301 Series
MODE SETTINGS
In the FR series, the mode is set by the mode pins (MD2, MD1, and MD0) and mode register (MODR).
1. Mode Pins
The MD2, MD1, and MD0 pins specify how the mode vector fetch is performed. Mode Pins Reset vector access Mode name area MD2 MD1 MD0 0 0 0 0 0 1 Internal ROM vector mode External ROM vector mode Internal External
Remarks
Single-chip mode The bus width is specified by the mode register.
Values other than those listed in the table are prohibited. : Single chip mode is able to set only MB91302A.
2. Mode Register (MODR)
· Details of mode register (MODR) The data written to the mode register by the mode vector fetch operation (see "3.11.3 reset sequences") is called the mode data. After the data is set to the mode register (MODR), the device operates with the operating mode specified by this data. The mode register is set by all types of reset. The register cannot be written to by user programs.
Operation mode setting bits
Initial Value bit Address
23 22 21 20 19 18 ROMA W 17 WTH1 W 16 WTH0 W
XXXXXXXXB
Operation mode setting bits
Initial Value bit Address
31 30 29 28 27 26 ROMA W 25 WTH1 W 24 WTH0 W
XXXXXXXXB
Bit31 to bit24 are all reserved bits. Be sure to set this bit to "00000." Operation is not guaranteed when any value other than "00000." is set.
MB91301 Series
· Operating mode Bus mode Single chip Internal ROM external bus External ROM external bus
Access mode 32-bit bus width 16-bit bus width 8-bit bus width
· Bus mode The bus mode controls the operations of internal ROM and the external access function. It is specified with the mode setting pins (MD2, MD1, and MD0) and the ROMA bit in mode data. · Access mode The access mode controls the external data bus width. It is specified with the WTH1 and WTH0 bits in the mode register and the DBW1 and DBW0 bits in area configuration registers 0 to 7 (ACR0 to ACR7). · Bus Modes The FR family has three bus modes: bus mode 0 (single-chip mode), bus mode 1 (internal-ROM, external-bus mode), and bus mode 2 (external-ROM, external-bus mode). The MB91V301A supports only bus mode 2 (external-ROM, external-bus mode). See "1. Memory Space" in CPU for details. · Bus mode0 (single chip mode) (only MB91302A) The internal I / O, 4 Kbytes D-bus RAM, 32 Kbytes F-bus RAM (FRAM) and 96 Kbytes F-bus ROM are valid, while access to any other areas is invalid under this mode. The function of external pin is peripheral or generalpurpose port. The pin can not be used as the bus pin. · Bus mode 1 (internal ROM external bus mode) The internal I / O, D-bus RAM, F-bus RAM (FRAM) and F-bus ROM are valid, and access to areas where external access is enabled will access external space under this mode. A part of an external terminal functions as a bus terminal. · Bus mode 2 (External-ROM, external-bus mode) This mode enables internal I / O and D-bus RAM, in which any access is access to external space. Some external pins serve as bus pins.
MB91301 Series
This shows the location of the various peripheral resource registers in the memory space. How to read the table Address 000000H Register +0 +1 +2 +3 PDR0 R / W B PDR1 R / W B PDR2 R / W B PDR3 R / W B XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Block T-unit Port Data Register
Read / write attribute, Access type (B : Byte, H : Half-word, W : Word) Initial value after a reset Register name (Address of column 1 register is 4n, address of column 2 register is 4n+2, etc.) Location of left-most register (When using word access, the register in column 1 is in the MSB side of the data.)
Note : Initial values of register bits are represented as follows : "1" : Initial value"1" "0" : Initial value"0" "X" : Initial value"X" "-" : No physical register at this location
MB91301 Series
Address 000000H 000004H 000008H 00000CH 000010H 000014H to 00003CH 000040H 000044H 000048H 00004CH 000050H 000054H 000058H 00005CH
Register +0 PDR0 R / W B XXXXXXXX PDR8 R / W B XXXXXXXX +1 PDR1 R / W B XXXXXXXX PDR9 R / W B - XXXXXXX PDRG R / W B XXXXXXXX PDRH R / W B - - - - - XXX EIRR R / W B, H, W ENIR R / W B, H, W 00000000 00000000 DICR R / W B, H, W HRCL R / W B, H, W ----0 0 - - 11111 TMRLR0 W H, W XXXXXXXX XXXXXXXX TMRLR1 W H, W XXXXXXXX XXXXXXXX TMRLR2 W H, W XXXXXXXX XXXXXXXX ELVR R / W B, H, W 00000000 TMR0 R H, W XXXXXXXX XXXXXXXX TMCSR0 R / W B, H, W - - XX0000 00000000 TMR1 R H, W XXXXXXXX XXXXXXXX TMCSR1 R / W B, H, W - - XX0000 00000000 TMR2 R H, W XXXXXXXX XXXXXXXX TMCSR2 R / W B, H, W - - XX0000 00000000 PDRJ R / W B XXXXXXXX +2 PDR2 R / W B XXXXXXXX PDR6 R / W B XXXXXXXX PDRA R / W B XXXXXXXX +3 PDRB R / W B XXXXXXXX
Block
T-unit Port Data Register
R-bus Port Data Register Reserved
Ext int DLYI / I-unit
Reload Timer 0
Reload Timer 1
Reload Timer 2
000060H
SIDR0 R SSR0 R / W B, H, W SCR0 R / W B, H, W SMR0 R / W B, H, W SODR0 W B, H, W 00001000 00000100 00 - - 0 - 0 XXXXXXXX UTIM0 R H, W (UTIMR0 W H, W) 00000000 00000000 DRCL0 W B ----UTIMC0 R / W B 0 - - 00001
UART0
000064H
U-TIMER 0
000068H
SIDR1 R SSR1 R / W B, H, W SCR1 R / W B, H, W SMR1 R / W B, H, W SODR1 W B, H, W 00001000 00000100 00 - - 0 - 0 XXXXXXXX UTIM1 R H, W (UTIMR1 W H, W ) 00000000 00000000 DRCL1 W B ----UTIMC1 R / W B 0 - - 00001
UART1
00006CH
U-TIMER 1 (Continued)
MB91301 Series
Address
Register +0 +1 +2 +3 SIDR2 R SSR2 R / W B, H, W SCR2 R / W B, H, W SMR2 R / W B, H, W SODR2 W B, H, W 00001000 00000100 00 - - 0 - 0 XXXXXXXX UTIM2 R H, W (UTIMR2 W H, W ) 00000000 00000000 ADCR R B, H, W 000000XX XXXXXXXX ADCR0 R B, H, W XXXXXXXX ADCR1 R B, H, W XXXXXXXX IBCR0 R / W B, H, W 00000000 IBSR0 R B, H, W 00000000 ITBA0 R, R / W B, H, W 00000000 00000000 ISMK0 R / W B, H, W 01111111 ICCR0 R, W, R / W B, H, W 00011111 IBCR1 R / W B, H, W 00000000 IBSR1 R B, H, W 00000000 ITBA1 R, R / W B, H, W 00000000 00000000 ISMK1 R / W B, H, W 01111111 ICCR1 R, W, R / W B, H, W 00011111 ISBA1 R, R / W B, H, W 00000000 IDBL1 R, R / W B, H, W 00000000 ISBA0 R, R / W B, H, W 00000000 IDBL0 R, R / W B, H, W 00000000 DRCL2 W B ----UTIMC2 R / W B 0 - - 00001
Block
000070H
UART2
000074H 000078H 00007CH 000080H to 000090H 000094H
U-TIMER 2
ADCS R / W B, H, W 00000000 00000000 ADCR2 R B, H, W XXXXXXXX
A / D Converter ADCR3 R B, H, W Sequential Comparator XXXXXXXX Reserved
000098H
ITMK0 R, R / W B, H, W 00111111 11111111 IDAR0 R / W B, H, W 00000000
I2C interface0
00009CH 0000A0H 0000A4H 0000A8H to 0000B0H 0000B4H
Reserved
0000B8H
ITMK1 R, R / W B, H, W 00111111 11111111 IDAR1 R / W B, H, W 00000000
I2C interface1
0000BCH 0000C0H 0000C4H 0000C8H to 0000D0H 0000D4H 0000D8H
Reserved TCCS R / W B, H, W 16 bit Free 00000000 Run Timer 16 bit Input Capture (Continued)
MB91301 Series
Address 0000DCH 0000E0H 0000E4H to 000114H 000118H 000011CH 000120H 000124H 000128H 00012CH 000130H 000134H 000138H 00013CH 000140H to 0001FCH 000200H 000204H 000208H 00020CH 000210H
Block 16 bit Input capture
Reserved
PPG timer Reserved
PCSR1 W H, W XXXXXXXX XXXXXXXX PCNH1 R / W B 00000000 PCNL1 R / W B 000000X0
PCSR2 W H, W XXXXXXXX XXXXXXXX PCNH2 R / W B 00000000 PCNL2 R / W B 000000X0
PCSR3 W H, W XXXXXXXX XXXXXXXX PCNH3 R / W B 00000000 PCNL3 R / W B 000000X0
Reserved
(Continued)
MB91301 Series
Address 000214H 000218H 00021CH 000220H 000224H 000228H to 00023CH 000240H 000244H to 000300H 000304H 000308H to 0003E0H 0003E4H 0003E8H to 0003EFH 0003F0H 0003F4H 0003F8H 0003FCH
Register +0 +1 +2 +3 DMACB2 R / W B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA3 R / W B, H, W1 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB3 R / W B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA4 R / W B, H, W1 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 R / W B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMACR R / W B 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX BSD0 W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 R / W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR R W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDRG R / W B 00000000 DDRH R / W B - - - - - 000 DDRJ R / W B 00000000 ICHCR R / W B, H, W 0 - 000000 ISIZE R / W B, H, W - - - - - - 10
Block
Reserved
I-Cache
Reserved
I-Cache
Reserved
Bit Search Module
000400H
R-bus Data Direction Register (Continued)
MB91301 Series
Address 000404H to 00040CH 000410H 000414H to 00041CH
Block
Reserved R-bus Port Function Register Reserved R-bus Pull-up Resistance Control Register Reserved
000420H
000424H to 00043CH 000440H 000444H 000448H 00044CH 000450H 000454H 000458H 00045CH 000460H 000464H 000468H
Interrupt Controller
(Continued)
MB91301 Series
Address 00046CH 000470H to 00047CH
Register +0 +1 +2 +3 ICR44 R / W B, H, W ICR45 R / W B, H, W ICR46 R / W B, H, W ICR47 R / W B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 RSRR R, R / W B, H, W 10000000 (INIT) - 0 - XX - 00 (INIT) XXX - - X00 (RST) CLKR R / W B, H, W - 000 - 000 (INIT) - XXX - XXX (RST) STCR R / W B, H, W TBCR R / W B, H, W 001100 - 1 (INIT) 00XXX - 00 (INIT) 0011XX - 1 (INIT) 00XXX - XX (RST) 00X1XX - X (RST) WPR W B, H, W XXXXXXXX (INIT) XXXXXXXX (RST)
Block
Interrupt Controller
000480H
CTBR W B, H, W XXXXXXXX (INIT) XXXXXXXX (RST)
000484H 000488H to 0005FCH 000600H 000604H 000608H 00060CH 000610H 000614H 000618H 00061CH 000620H 000624H 000628H 00062CH
DIVR0 R / W B, H, W DIVR1 R / W B, H, W 00000011 (INIT) 0000 - - - - (INIT) XXXX - - - - (RST) XXXXXXXX (RST)
Clock Control unit
Reserved DDR2 R / W B 00000000 DDR6 R / W B 00000000 DDRB R / W B 00000000 T-unit Data Direction Register
DDR0 R / W B 00000000 DDR8 R / W B 00000000
DDR1 R / W B 00000000
DDRA R / W B 00000000
PFR9 R / W B - 0000111 PCR1 R / W B 00000000
PFR6 R / W B 11111111 PFRA1 R / W B 11111111 PFRA2 R / W B -0--PCR2 R / W B 00000000 PCR6 R / W B 00000000
PFR61 R / W B - - - - 0000 PFRB1 R / W B 00000000 PCRB R / W B 00000000
T-unit Port Function Register
PCRA R / W B 00000000
T-unit Pull-up Resistance Control Register (Continued)
MB91301 Series
Address 000630H to 00063CH 000640H 000644H 000648H 00064CH 000650H 000654H 000658H 00065CH 000660H 000664H 000668H 00066CH 000670H 000674H 000678H 00067CH 000680H
Register +0 +1 ASR0 R / W H, W 00000000 00000000 ASR1 R / W H, W XXXXXXXX XXXXXXXX ASR2 R / W H, W XXXXXXXX XXXXXXXX ASR3 R / W H, W XXXXXXXX XXXXXXXX ASR4 R / W H, W XXXXXXXX XXXXXXXX ASR5 R / W H, W XXXXXXXX XXXXXXXX ASR6 R / W H, W XXXXXXXX XXXXXXXX ASR7 R / W H, W XXXXXXXX XXXXXXXX AWR0 R / W B, H, W 01111111 11111011 AWR2 R / W B, H, W XXXXXXXX XXXXXXXX AWR4 R / W B, H, W XXXXXXXX XXXXXXXX AWR6 R / W B, H, W XXXXXXXX XXXXXXXX MCRA R / W B, H, W MCRB R / W B, H, W XXXXXXXX XXXXXXXX IOWR0 R / W B, H, W IOWR1 R / W B, H, W IOWR2 R / W B, H, W XXXXXXXX XXXXXXXX XXXXXXXX CSER R / W B, H, W CHER R / W B, H, W 00000001 11111111 RCR R / W B, H, W 00XXXXXX XXXX0XXX TCR R / W B, H, W 00000000 (INIT) 0000XXXX (RST) ACR0 R / W H, W 1111XX00 00000000 ACR1 R / W B, H, W XXXXXXXX XXXXXXXX ACR2 R / W B, H, W XXXXXXXX XXXXXXXX ACR3 R / W B, H, W XXXXXXXX XXXXXXXX ACR4 R / W B, H, W XXXXXXXX XXXXXXXX ACR5 R / W B, H, W XXXXXXXX XXXXXXXX ACR6 R / W B, H, W XXXXXXXX XXXXXXXX ACR7 R / W B, H, W XXXXXXXX XXXXXXXX AWR1 R / W B, H, W XXXXXXXX XXXXXXXX AWR3 R / W B, H, W XXXXXXXX XXXXXXXX AWR5 R / W B, H, W XXXXXXXX XXXXXXXX AWR7 R / W B, H, W XXXXXXXX XXXXXXXX +2 +3
Block
Reserved
T-unit
000684H
(Continued)
MB91301 Series
Address 00068CH to 0007F8H 0007FCH 000800H to 000AFCH 000B00H 000B04H 000B08H 000B0CH 000B10H 000B14H to 000B1CH 000B20H 000B24H 000B28H 000B2CH 000B30H 000B34H 000B38H 000B3CH 000B40H 000B44H
Register +0 +1 MODR W 2 XXXXXXXX ESTS0 R / W B X0000000 ECTL0 R / W B 0X000000 ECNT0 W B XXXXXXXX ESTS1 R / W B XXXXXXXX ECTL1 R / W B 00000000 ECNT1 W B XXXXXXXX ESTS2 R B 1XXXXXXX ECTL2 W B 000X0000 EUSA W B XXX00000 ECTL3 R / W B 00X00X11 EDTC W B 0000XXXX +2 +3
Block
Reserved
T-unit
Reserved
EWPT R H 00000000 00000000 EDTR0 W H XXXXXXXX XXXXXXXX
ECTL4 R (R / W) B ECTL5 R (R / W) B - 0X00000 - - - - 000X EDTR1 W H XXXXXXXX XXXXXXXX
EIA0 W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA1 W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA2 W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA3 W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA4 W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA5 W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA6 W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA7 W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDTA R / W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ED R / W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX (Continued) DSU (Evaluation chip only)
MB91301 Series
Address 000B48H 000B4CH 000B50H 000B54H 000B58H 000B5CH 000B60H 000B64H 000B68H 000B6CH 000B70H to 000FFCH 001000H 001004H 001008H 00100CH 001010H 001014H 001018H 00101CH 001020H
Register +0 +1 +2 +3 EOA0 W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOA1 W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EPCR R / W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EPSR R / W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM0 W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM1 W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOAM0 / EODM0 W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOAM1 / EODM1 W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOD0 W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOD1 W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA0 R / W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA0 R / W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA1 R / W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA1 R / W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA2 R / W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA2 R / W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA3 R / W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA3 R / W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA4 R / W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Block
(Evaluation chip only)
Reserved
(Continued) 47
MB91301 Series
(Continued) Address 001024H 001028H to 001FFCH Register +0 +1 +2 +3 DMADA4 R / W W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Block DMAC
Reserved
1 : Byte access is not permitted for the lower 16 bits of DMAC0 to DMAC4 (DTC15 to DTC0) . 2 : This register is accessed through mode vector fetch it cannot be accessed in normal mode.
MB91301 Series
INTERRUPT VECTORS
Interrupt Reset Mode vector System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction Instruction break exception Operand break trap Step trace trap NMI request (tool) Undefined instruction exception NMI request External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 Reload timer 0 Reload timer 1 Reload timer 2 UART0 (RX completed) UART1 (RX completed) UART2 (RX completed) UART0 (TX completed) UART1 (TX completed) UART2 (TX completed) Interrupt No. 10 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 Interrupt level1 15 (FH) fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H 37CH TBR default address2 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H 000FFF7CH RN 6 7 11 12 8 9 10 0 1 2 3 4 5
(Continued) 49
MB91301 Series
Interrupt DMAC0 (end, error) DMAC1 (end, error) DMAC2 (end, error) DMAC3 (end, error) DMAC4 (end, error) A / D PPG0 PPG1 PPG2 PPG3 System reserved U-TIMER0 U-TIMER1 U-TIMER2 Time base timer overflow I C I / F0 I2C I / F1 System reserved System reserved 16 bit Free Run Timer ICU0 (load) ICU1 (load) ICU2 (load) ICU3 (load) System reserved System reserved System reserved System reserved System reserved System reserved Delay interrupt bit System reserved (Used by REALOS) System reserved (Used by REALOS) System reserved
Interrupt No. 10 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 16 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42
Interrupt level1 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
Offset 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H 2F4H
TBR default address2 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3FH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H 000FFEF4H
(Continued) 50
MB91301 Series
(Continued) Interrupt System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Used by INT instruction Interrupt No. 10 67 68 69 70 71 72 73 74 75 76 77 78 79 80 to 255 16 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 to FF Interrupt level1 Offset 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH to 000H TBR default address2 000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH to 000FFC00H RN
MB91301 Series
INSTRUCTION CACHE
4 bytes
4 bytes I3
4 bytes I2
4 bytes I1
4 bytes I0
Way 1 Cash tag 128 block Cash tag Way 2 Cash tag
128 block
Sub block 3
Sub block 2
Sub block 1
Sub block 0
block 0
Sub block 3
Sub block 2
Sub block 1
Sub block 0
block 127
Sub block 3
Sub block 2
Sub block 1
Sub block 0
block 0
Cash tag
Sub block 3
Sub block 2
Sub block 1
Sub block 0
block 127
MB91301 Series
· Instruction Cache Tags Way 1
Vacancy
Address tag
07 SBV3 06 SBV2 05 SBV1 04 SBV0 09
03 TAGV 08
Vacancy
01 LRU
00 ETLK
Address tag
07 SBV3 06 SBV2 05 SBV1 04 SBV0
03 TAGV
00 ETLK
Vacancy
bit 7 to bit4 SBV3 to SBV0 : Sub-block validation When SBVn contains "1", the corresponding sub-block holds the current instruction data at the address located by the tag. Each sub-block usually holds two instructions (excluding immediate-value transfer instructions). bit 3 TAGV : Tag validation bit This bit indicates whether the address tag value is valid. When the bit contains "0", the corresponding block is invalid regardless of the settings of the sub-block validation bits. (The bit is set to "0" when the cache is flushed.) bit 1 LRU (only in way 1) This bit exists only in the instruction cache tag in way 1. The bit indicates way 1 or 2 as the way containing the last entry accessed in the selected set. When set to "1", the LRU bit indicates that the entry of the set in way 1 is the last entry accessed. When set to "0", it indicates that the one in way 2 is the last entry accessed. bit 0 ETLK : Entry lock This bit is used to lock all the entries in the block corresponding to the tag in the cache. When the ETLK bit is set to "1", the entries are locked and are not updated when a cache miss occurs. Note, however, that invalid sub-blocks are updated. If a cache miss occurs with both of ways 1 and 2 in the entry lock states, access to external memory takes place after losing one cycle used for evaluating the cache miss. 53
MB91301 Series
Control Registers · Cache Size Register (ISIZE) bit Address : 00000307H
Initial value - - - - - - 10B
· Instruction Cache Control Register (ICHCR) The instruction cache (I-cache) control register (ICHCR) controls the operations of the instruction cache. Writing a value to the ICHCR has no effect on the caching of any instruction fetched within three cycles that follow.
bit Address : 000003E7H
Initial value 0 - 000000B
Address 00010000 H 00010200 H 00010400 H 00010600 H 00010800 H 00010FFFH 00014000 H 00014200 H 00014400 H 00014600 H 00014800 H 00014FFFH 00018000 H 00018200 H 00018400 H 00018600 H 00018800 H 00018FFFH 0001C000H 0001C200H 0001C400H 0001C600H 0001C800H 0001CFFFH
Cache off RAM off
Cache off RAM on TAG1
Cache 4 K RAM off
Cache 4 K Cache 2 K RAM on RAM off TAG1
TAG RAM 00010000 H 00010004 H 00010008 H 0001000CH 00010010 H 00010014 H
00018008 H 0001800C H 00018010 H 00018014 H
IRAM1 I-bus RAM (way1) IRAM1 I-bus RAM (way2)
Instruction at address 000 (SBV0) Instruction at address 004 (SBV1) Instruction at address 008 (SBV2) Instruction at address 00C (SBV3) Instruction at address 010 (SBV0) Instruction at address 014 (SBV1)
MB91301 Series
Address 000H 200H 400H 600H 000H 200H 400H 600H
Cache 4 K
Cache off
IRAM1
IRAM2
Direct area
00010000 H 00020000 H 00030000 H 00040000 H 00100000 H FFFFFFFFH IRAM
Direct area
(Even the D-bus RAM area is cashed, when it is transferred to the IA-Bus.) Internal ROM / RAM area should be cached. Each chip-select area can be set as a non-cache area.
Cache area
Internal memory
Cache area
MB91301 Series
PERIPHERAL RESOURCES
1. External Bus Interface Controller
MB91301 Series
· Block Diagram Internal address bus Internal data bus
External data bus
write buffer
switch
read buffer
switch
DATA BLOCK ADDRESS BLOCK
External address bus
address buffer
ASR ASZ comparator
CS0 to CS7
SDRAM control
SRAS, SCAS, SWE, MCLKE, DQMUU, DQMUL, DQMLU, DQMLL under flow
RCR refresh counter
External pin controller All block control
registers & control
RD WR0, WR1, WR2, WR3, AS, BAA
BRQ BGRNT RDY
MB91301 Series
· Register List
31 24 23 ASR0 ASR1 ASR2 ASR3 ASR4 ASR5 ASR6 ASR7 AWR0 AWR2 AWR4 AWR6 MCRA Reserved IOWR0 Reserved CSER RCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved (MODR) MCRB Reserved IOWR1 Reserved CHER 16 15 08 07 ACR0 ACR1 ACR2 ACR3 ACR4 ACR5 ACR6 ACR7 AWR1 AWR3 AWR5 AWR7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TCR Reserved Reserved Reserved Reserved Reserved Reserved 00
Area select registers 0 to 7 (ASR0 to ASR7) Area configuration registers 0 to 7 (ACR0 to ACR7)
Area weight register (AWR0 to AWR7)
Memory setting register (For SDRAM / FCRAM auto-precharge OFF mode) (MCRA) Memory setting register (For FCRAM auto-precharge ON mode) (MCRB) DMAC I / O wait registers (IOWR0 and IOWR1) Chip-select area enable register (CSER) Cache fetch enable register (CHER) Terminal and timing control register (TCR) Refresh control register (RCR)
Notes : · Reserved indicates a reserved register. When writing, always set to "0". · The MODR register cannot be accessed by the user program.
MB91301 Series
MB91301 series pins can be used as I / O ports when not set for use by the external bus interface or the various peripheral I / O functions. · I / O port (with pull-up resistor) block diagram
Port Bus
PDR read
Peripheral input
Pull-up resistor (approx. 25 k)
Peripheral output
PDR : Port Data Register DDR : Data Direction Register PFR : Port Function Register PCR : Pull-up Control Register
MB91301 Series
· Port Data Register (PDR) PDR0 Address : 00000000H PDR1 Address : 00000001H PDR2 Address : 00000002H PDR6 Address : 00000006H PDR8 Address : 00000008H PDR9 Address : 00000009H PDRA Address : 0000000AH PDRB Address : 0000000BH PDRG Address : 00000010H PDRH Address : 00000011H PDRJ Address : 00000013H
Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value - XXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value - - - - - XXXB Initial value XXXXXXXXB
· PDR0 to PDR2, PDR6, PDR8 to PDRB, PDRG, PDRH and PDRJ are the I / O data registers for the I / O pots. · The corresponding PDR0 to DDRJ and PFR6 to PFRJ registers control input / output. · P00 to P07, P10 to P17 and P20 to P27 do not have a PFR (port function register). 62
MB91301 Series
· Data Direction Register (DDR) DDR0 Address : 00000600H DDR1 Address : 00000601H DDR2 Address : 00000602H DDR6 Address : 00000606H DDR8 Address : 00000608H DDR9 Address : 00000609H DDRA Address : 0000060AH DDRB Address : 0000060BH DDRG Address : 00000400H DDRH Address : 00000401H DDRJ Address : 00000403H
Initial value 00000000B Initial value 00000000B Initial value 00000000B Initial value 00000000B Initial value 00000000B Initial value - 0000000B Initial value 00000000B Initial value 00000000B Initial value 00000000B Initial value - - - - - 000B Initial value 00000000B
MB91301 Series
· Pull-up Resistor Control Register (PCR) PCR0 bit 00000620H
Address :
Initial value 00000000B
Address :
PCR1 bit 00000621H
Initial value 00000000B
Address :
PCR2 bit 00000622H
Initial value 00000000B
Address :
PCR6 bit 00000626H
Initial value 00000000B
Address :
PCR8 bit 00000628H
Initial value 00000000B
Address :
PCR9 bit 00000629H
Initial value - 000 - - 0 -B
Address :
PCRA bit 0000062AH
Initial value 00000000B
Address :
PCRB bit 0000062BH
Initial value 00000000B
Address :
PCRH bit 00000421H
Initial value - - - - - 000B
MB91301 Series
· Port Function Register (PFR)
Address :
PFR6 bit 00000616H
Initial value 11111111B
Address :
PFR8 bit 7 6 5 00000618H WR3XE WR2XE WR1XE
Initial value 111 - - 0 - -B
Address :
PFR9 bit 00000619H
Initial value - 0000111B
Address :
PFRA1 bit 7 6 5 4 3 2 1 0 0000061AH CS7XE CS6XE CS5XE CS4XE CS3XE CS2XE CS1XE CS0XE
Initial value 11111111B
Address :
PFRB1 bit 0000061BH
Initial value 00000000B
Address :
PFRB2 bit 0000061CH
Initial value 000 - - - 00B
Address :
PFRA2 bit 0000061EH
Initial value - - 0 - - - - -B
Address :
PFRG bit 00000410H
Initial value 00 - - - - - -B
Address :
PFRH bit 00000411H
Initial value - - - - - - 0 -B
Address :
PFRJ bit 00000413H
Initial value - 000 - 00 -B
Address :
PFR61 bit 00000617H
Initial value - - - - 0000 B
PFR6, PFR8 to PFRB, PFRA2, PFRG, PFRH and PFRJ control the output for the corresponding external bus interface or peripheral output bit. Always write "0" to unused bits in the PFR.
MB91301 Series
3. Interrupt Controller
The interrupt controller receives and processes interrupts. · Hardware Configuration The interrupt controller consists of the following : · ICR register · Interrupt priority determination circuit · Interrupt level and interrupt number (vector) generator · Hold request removal request generator · Principal Functions The main functions of the interrupt controller are as follows : · Detect NMI and interrupt requests · Prioritize interrupts (according to level and number) · Notify interrupt level of selected interrupt request (to CPU) · Notify interrupt number of selected interrupt request (to CPU) If an NMI or interrupt request with an interrupt level other than "11111B" occurs, notify recovery from stop mode (to CPU) · Generate hold request removal requests to the bus master · Block Diagram ("1" when LEVEL 11111B) ("1" when LEVEL 11111B)
WAKEUP
Determine order priority Determine order ofof priority NMI NMI processing processing
5 LEVEL4 to LEVEL40
LEVEL LEVEL determination determination
RI00 ICR00
VECTOR VECTOR 6 determination determination
LEVEL, LEVEL, VECTOR VECTOR generageneration tion
HLDREQ HLDREQ removal removal request request
MHALTI
VCT5 to VCT50
ICR47 RI47 (DLYIRQ)
R-bus
MB91301 Series
· Register List
bit 7 6 5 4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0
Address : 00000440H Address : 00000441H Address : 00000442H Address : 00000443H Address : 00000444H Address : 00000445H Address : 00000446H Address : 00000447H Address : 00000448H Address : 00000449H Address : 0000044AH Address : 0000044BH Address : 0000044CH Address : 0000044DH Address : 0000044EH Address : 0000044FH Address : 00000450H Address : 00000451H Address : 00000452H Address : 00000453H Address : 00000454H Address : 00000455H Address : 00000456H Address : 00000457H Address : 00000458H Address : 00000459H Address : 0000045AH Address : 0000045BH Address : 0000045CH Address : 0000045DH Address : 0000045EH Address : 0000045FH
ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31
(Continued) 67
MB91301 Series
(Continued)
bit 7 6 5 4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0
Address : 00000460H Address : 00000461H Address : 00000462H Address : 00000463H Address : 00000464H Address : 00000465H Address : 00000466H Address : 00000467H Address : 00000468H Address : 00000469H Address : 0000046AH Address : 0000046BH Address : 0000046CH Address : 0000046DH Address : 0000046EH Address : 0000046FH
ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
Address :
0000045H
MHALTI
MB91301 Series
4. External Interrupt / NMI Control Block
The external interrupt control block controls external interrupt requests input to the NMI and INT0 to INT7 pins. The interrupt trigger level can be selected from "H", "L", "rising edge", or "falling edge" (except for NMI). · Block Diagram
R-bus 8
Interrupt enable register
9 INT0 to INT7 NMI
Interrupt request
Request F / F
Edge detection circuit
Interrupt request register
Interrupt level setting register
· Register List External interrupt enable register (ENIR) bit 7 6 5
EN7 EN6 EN5
External interrupt request register (EIRR) bit 15 14 13
ER7 ER6 ER5
12 ER4
11 ER3
10 ER2
Request level setting register (ELVR) bit 15 14
LB7 LA7 6 LA3
13 LB6 5 LB2
12 LA6 4 LA2
11 LB5 3 LB1
10 LA5 2 LA1
MB91301 Series
5. Delay Interrupt Module
The delay interrupt module is used to generate interrupts for task switching. This module can be used to generate and cancel interrupts to the CPU via software. · Block Diagram
R-bus
Interrupt request
· Register List Delay interrupt control register (DICR) bit
MB91301 Series
6. PPG Timer
The PPG timer can output highly precise PWM waveforms efficiently. The MB91301 series contains four channels of PPG timer. · Features of the PPG Timer · Each channel consists of a 16-bit down counter, a 16-bit data register with cycle setting buffer, a 16-bit compare register with duty setting buffer, and pin control section. · The count clocks for the 16-bit down counter can be selected from the following four types : Internal clock , / 4, / 16, / 64 · The counter is initialized to "FFFFH" at a reset or counter borrow. · Each channel has a PPG output. · Register outline Cycle setting register: Reload data register with buffer Duty setting register: Compare register with buffer Transfer from the buffer takes place upon a counter borrow. · Pin control overview A duty match sets the pin control section to 1. (Preferential) A counter borrow resets it to 0. The output value fix mode is available, which can each output all "L" (or "H"). A polarity can also be specified. · An interrupt request can be generated at a combination of the following events : Activation of the PPG timer Counter borrow (cycle match) Duty match Counter borrow (cycle match) or duty match DMA transfer can be initiated by the above interrupt request. · It is possible to set the simultaneous activation of two or more channels by means of software or another interval timer. Restarting during operation can also be set. · The request level to be detected can be selected from among "rising edge", "falling edge", and "both edges".
MB91301 Series
· Block diagram
16-bit reload timer ch0 16-bit reload timer
TRG input PPG timer ch0
General control register 2
General control register 1 (resource select)
TRG input PPG timer ch1
TRG input PPG timer ch2 TRG input PPG timer ch3
External TRG0 to TRG3
· Block diagram for 1 channel
Prescaler
16-bit down counter Start Borrow
PPG mask
PPG output
Peripheral clock
Conversion bit
Enable TRG input Edge detection Soft trigger
Interrupt selection
MB91301 Series
· Register List
bit 15 7 GCN10 0
General control register 10
GCN20
General control register 20
PTMR0 PCSR0 PDUT0 PCNH0 PCNL0
ch0 timer register ch0 cycle setting register ch0 duty setting register ch0 control status register
PTMR1 PCSR1 PDUT1 PCNH1 PCNL1
ch1 timer register ch1 cycle setting register ch1 duty setting register ch1 control status register
PTMR2 PCSR2 PDUT2 PCNH2 PCNL2
ch2 timer register ch2 cycle setting register ch2 duty setting register ch2 control status register
PTMR3 PCSR3 PDUT3 PCNH3 PCNL3
ch3 timer register ch3 cycle setting register
ch3 duty setting register
ch3 control status register
MB91301 Series
7. 16-Bit Reload Timer
The 16-bit timer consists of a 16-bit down-counter, 16-bit reload register, prescaler for generating the internal count clock, and a control register. The clock source can be selected from three internal clock signals (machine clock divided by 2, 8, or 32) or the external event. The interrupt can be used to initiate DMA transfer. The MB91301 series has three 16-bit reload timer channels. · Block Diagram
16-bit reload register (TMRLR)
Reload
16-bit down counter (TMR) UF
Count enable
OUT CTL.
INTE UF CNTE IRQ
Re-trigger
R-bus
Clock selector
CSL1 TRG CSL0
IN CTL.
Prescaler clear
MOD0 MOD1
External trigger selection
External trigger input (TI)
CLKP input
MB91301 Series
· Register List Control status register (TMCSR) bit 15 14
6 13 5 OUTL 12 4 RELD 11 CSL1 3 INTE 10 CSL0 2 UF 9 MOD2 1 CNTE 8 MOD1 0 TRG
7 MOD0
16-bit timer register (TMR) bit 15
16-bit reload register (TMRLR) bit 15
MB91301 Series
8. U-TIMER (16 bit timer for UART baud rate generation)
15 UTIMR (reload register) load 15 UTIM (timer)
clock underflow control
(CLKP) (Peripheral clock)
MUX ch0 only
to UART
under flow U-TIMER 1
MB91301 Series
· Register List
15 8 7 UTIM UTIMR UTIMC 0
· U-TIMER (UTIM)
Address bit 000064H (ch 0) 00006CH (ch 1) 000074H (ch 2)
Initial value 00000000 00000000B
UTIM contains the timer value. Use a 16-bit transfer instruction to access the register. Reload register (UTIMR) Address bit 15 000064H (ch 0) b15 00006CH (ch 1) W 000074H (ch 2)
Initial value 00000000 00000000B
UTIMR is the register that contains the value to be reloaded to UTIM when UTIM causes an underflow. Use a 16-bit transfer instruction to access the register.
MB91301 Series
9. UART
The UART is a serial I / O port for asynchronous (start-stop synchronized) or CLK synchronized transmission. The MB91301 series has three UART channels. · UART Features · Full duplex double buffer · Asynchronous (start-stop synchronized) or CLK synchronized transmission · Supports multi-processor mode · Fully programmable baud rate The internal timer can be set to any desired baud rate (see "8. U-TIMER" description) · Variable baud rate can be input from an external clock. · Error detection functions (parity, framing, overrun) · Transmission signal format is NRZ · The interrupt can be used to initiate DMA transfer. · The DMAC interrupt can be cleared by writing to the DRCL register.
MB91301 Series
· Block Diagram Control signal RX interrupt (to CPU) SCK (clock) From U-TIMER Clock selection circuit TX clock RX clock TX interrupt (to CPU)
External clock SCK RX control circuit SI (Receive data) Start bit detect circuit Receive bit counter Receive parity counter TX control circuit TX start circuit Send bit counter Send parity counter SO (Send data)
Receive status decision circuit
RX shifter
RX complete
TX shifter
TX start
Receive error signal for DMA (to DMAC)
MD1 MD0
SMR register
CS0 SCKE
SCR register
PEN P SBL CL A / D REC RXE TXE
SSR register
PE ORE FRE RDRF TDRE BDS RIE TIE
Control signal
MB91301 Series
· Register List
15 SCR SSR 8 7 SMR SIDR (R) / SODR (W) 0 (R / W) (R / W)
DRCL 8 bit 8 bit
Serial input data register Serial output data register (SIDR / SODR) bit
Serial status register (SSR) 7 bit
4 RDRF
3 TDRE
Serial mode register (SMR) bit
Serial control register (SCR) 7 bit
DRCL register (DRCL) bit