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COM/SEG DRIVER SPLC562A 240-output segment/common driver suitable


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SPLC562A
COM/SEG DRIVER
SPLC562A 240-output segment/common driver suitable driving large/medium scale matrix panels, used personal computers/work-stations. Through (Super Slim TCP) technology, ideal substantially decreasing size frame section module. SPLC562A good both segment driver common driver, create power consuming, high-resolution LCD.
FEATURES
Both Segment Mode Common Mode Number drive outputs: Supply voltage drive: +15V +30V Supply voltage logic system: +2.5V +5.5V power consumption output impedance CMOS silicon gate process (P-type silicon substrate) Package: 278-pin (Tape Carrier Package) bump chip
BLOCK DIAGRAM
V12R V43R Y239 Y240
DISPOFF
Segment Mode Shift clock frequency: 20MHz (Max.) (VDD +5V±10%) 15MHz (Max.) (VDD +4.5V) 12MHz (Max.) (VDD +2.5V +3V) Adopts data system 4-bit 8-bit parallel input modes selectable with mode
LEVEL SHIFTER
4-LEVEL DRIVER
V43L V12L
EIO1 EIO2
ACTIVE CONTROL
LEVEL SHIFTER
LINE LATCH/SHIFTER REGISTER
CONTROL LOGIC
8BITS*2 DATA LATCH
(MD) Automatic transfer function enable signal Automatic counting function which, chip select mode, causes internal clock stopped automatically counting input data
DATA CONTROL
CONVERSION DATA CONTROL TEST CIRCUIT
TEST1
TEST1
Line latch circuits reset when DISPOFF active Common Mode Built-in bits bi-directional shift register (divisible into 120-bits Shift clock frequency: 4.0MHz (Max.) (VDD +2.5V +5.5V) Available single mode(240 bits shift register) dual mode (120 bits shift register Y240 Y240 Y120, Y121 Y240 Y240 Y121, Y120 Signal mode Signal mode Dual mode Dual mode
above shift directions pin-selectable Shift register circuit reset function when DISPOFF active
Remark: TCP's external shape customized. order your TCP's external shape, please contact SUNPLUS salesperson. SUNPLUS TECHNOLOGY reserves right change this documentation without prior notice. believed accurate reliable. Information provided SUNPLUS TECHNOLOGY responsibility assumed addition, SUNPLUS products
However, SUNPLUS TECHNOLOGY makes warranty errors which appear this document.
Contact SUNPLUS TECHNOLOGY obtain latest version device specifications before placing your order. SUNPLUS TECHNOLOGY infringement patent other rights third parties which result from use. reasonably expected result significant injury user, without express written approval Sunplus.
authorized critical components life support devices/ systems aviation devices/systems, where malfunction failure product
PAGE
SPLC562A
CONNECTION
Y238 Y239 Y240
CHIP SURFACE
Note: Doesn't prescribe outline.
DESCRIPTION
Mnemonic Y240 V12L, V12R V43L, V43R V5L, EIO1 EIO2
DISPOFF
#32, #31, #30, #29,
TEST1
Sunplus Technology Co., Ltd.
V12R V43R TEST1 EIO1 DISPOFF EIO2 V43L V12L
Type driver output Power supply driver Power supply driver Power supply driver Power supply driver Input selecting reading direction display data segment mode/Input selecting shift direction shift register common mode Power supply logic system (+2.5V +5.5V) Segment mode/common mode selection Input/output chip selection segment mode/Shift clock input/output shift register common mode Display data input segment mode Display data input segment mode/Dual mode data input common mode Clock input taking display data segment mode Control input output non-select level Latch pulse input display data segment mode/Shift clock input shift register common mode AC-converting signal input driver waveform Mode selection input Test mode selection input Ground (0V) Description PAGE
JAN. 2001 Version:
SPLC562A
BLOCK FUNCTION
ACTIVE CONTROL
case segment mode, controls selection non-selection chip. Following signal, after chip select signal input, select signal generated internally until bits data have been read Once data input been completed, select signal cascade connection output, chip nonselected. case common mode, controls input/output data bidirectional pins.
DATA LATCH
case segment mode, latches data data bus. latched state each driver output controlled control logic data latch control, bits data read sets bits.
TEST CIRCUIT
circuit test. During normal operation, doesn't act.
CONVERSION DATA CONTROL
case segment mode, keep input data which clocks 4-bit parallel mode into latch circuit, keep input data which clock 8-bits parallel mode into latch circuit, after that they internal data bits time.
LINE LATCH/SHIFT REGISTER
case segment mode, bits which have been read into data latch simultaneously latched falling edge signal, output level shifter block. edge signal. case common mode, shifts data from data input falling
DATA LATCH CONTROL
case segment mode, selects state data latch which reads data signals. shift direction controlled control logic, every bits data read selection signal shifts based state control circuit.
LEVEL SHIFTER
logic voltage signal level-shifted driver voltage level, output driver block.
4-LEVEL DRIVER CONTROL LOGIC
Controls operation each block. case segment mode, when signal been input, blocks reset control logic waits selection signal output from active control block. Once selection signal been output, operation data latch data transmission controlled, bits data read chip non-selected. case common mode, controls direction data shift. Drives driver output pins from line latch/shift register data, selecting levels (V0, V12, V43, based S/C, DISPOFF signals.
Sunplus Technology Co., Ltd.
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JAN. 2001 Version:
SPLC562A
INPUT/OUTPUT CIRCUITS
Internal Circuit Applicable pins L/R, S/C, DI6-0, DISPOFF,
Fig. Input Circuit
Control Signal
Internal Circuit
Applicable pins DI7,
Fig. Input Circuit
Internal Circuit
Applicable pins TEST1, TEST2 Fig. Input Circuit
Sunplus Technology Co., Ltd.
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SPLC562A
Internal Circuit
Control Signal
VSS(0
Output Signal
Control Signal
Applicable pins EIO1, EIO2
Fig. Input/Output Circuit
Control Signal
Control Signal
Control Signal
Internal Circuit
Control Signal
Applicable pins
Y240 VSS(0
Fig. Drive Output Circuit
Sunplus Technology Co., Ltd.
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SPLC562A
FUNCTION DESCRIPTION
FUNCTIONS
(Segment Mode) Mnemonic V0R, V0L, V12R, V12L, V43R, V43L, V5L, Description Logic system power supply connects +2.5V +5.5V Ground connects Bias Power supply driver voltage Normally, bias voltage used resistor divider. Ensure that voltage such that <V43<V12<V0. must connect external power supply, supply regular voltage which assigned specification each power pin. applications, even though have same voltage level, layout should shorted directly panel. connect-pin. Input pins display data 4-bit parallel input mode, input data into pins, DI0. 8-bit parallel input mode, input data into pins, DI7-DI0. Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional Operations. Clock input taking display data Data read falling edge clock pulse. Latch pulse input display data Data latched falling edge clock pulse. Input selecting reading direction display data When level "L", data read sequentially from Y240 When level "H", data read sequentially from Y240. Refer "REALATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional Operations.
DISPOFF
That should have individual path
Connect VDD.
Control input output non-select level input signal level-shifted from logic voltage level drive voltage level, controls drive circuit. When level "L", drive output pins (Y240 level While "L", contents line latch reset, display data read data latch regardless condition DISPOFF When DISPOFF function canceled, driver outputs non-select level (V12 V43), then outputs contents data latch next falling edge that time, DISPOFF removal time does correspond what shown characteristics, output reading data correctly. Table truth values shown "TRUTH TABLE" Function Operations.
Segment mode/common mode selection When level "H", segment mode set. signal input driving waveform input signal level-shifted from logic voltage level drive voltage level, controls drive circuit. Normally, inputs frame inversion signal.
Sunplus Technology Co., Ltd.
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Mnemonic Description driver output pin's output voltage level using line latch output signal signal. Table truth values shown "TRUTH TABLE" Function Operations. Mode selection When level "L", 8-bit parallel input mode set. When level "H", 4-bit parallel input mode set. Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional Operations. EIO1, EIO2 Input/output pins chip selection When input Level "L", EIO1 output EIO2 input. When input Level "H", EIO1 input EIO2 output. During output, while after bits data have been read, cycle (from falling edge falling edge XCK), after which returns "H". During input, chip selected while after signal input. chip non-selected after bits data have been read. TEST1 TEST2 Y240 Test mode selection pins During normal operation, level "L". driver output pins Corresponding directly each shift register, level (V0, V12, V43, selected output. Table truth values shown "TRUTH TABLE" Function Operations.
(Common Mode) Mnemonic V0R, V0L, V12R, V12L, V43R, V43L, V5L, Description Logic system power supply connects +2.5V +5.5V. Ground connects Bias Power supply driver voltage Normally, bias voltage used resistor divider. Ensure that voltage such that <V43<V12<V0. (I=0, must connect external power supply, supply regular voltage which assigned specification each power pin. EIO1 Shift clock pulse input bi-directional shift register Data shifted falling edge clock pulse. Shift data input/output bi-directional shift register Output when level "L", input when level "H". When EIO1 used input pin, will pull-down. When EIO1 used output pin, won't pull-down. Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional Operations. Input selecting shift direction bi-directional shift register Data shifted from Y240 when level "L", data shifted from Y240 when level "H". Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional Operations.
Sunplus Technology Co., Ltd.
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Mnemonic EIO2 Description Shift data input/output bi-directional shift register Input when level "L", output when level "H". When EIO2 used input pin, will pull-down. When EIO2 used output pin, won't pull-down. Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional Operations. signal input driving waveform input signal level-shifted from logic voltage level drive voltage level, controls drive circuit. Normally, input frame inversion signal. driver output pin's output voltage level using shift register output signal signal. Table truth values shown "TRUTH TABLE" Functional Operations. Segment mode common mode selection When level "L", common mode set.
DISPOFF
Control input output non-select level input signal level-shifted from logic voltage level drive voltage level, controls drive circuit. When level "L", drive output pins (Y240 level While "L", contents shift register reset reading data. When DISPOFF function canceled, driver outputs non-select level (V12 V43), shift data reading falling edge that time, DISPOFF removal time does correspond what shown characteristics, shift data reading correctly. Table truth values shown "TRUTH TABLE" Functional Operations.
Mode selection When level "L", single mode operation selected, when level "H", dual mode operation selected. Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional Operations.
TEST1 TEST2
used Connect VDD, avoiding floating. used pull-down common mode, connect open. Test mode selection pins During normal operation, level "L". Dual mode data input According data shift direction data shift register, data input starting from 121st bit. When chip used dual mode, will pull-down. When chip used single mode, won't pull-down. Refer "RELATIONSHIP BETWEEN DISPLAY DATA DRIVE OUTPUT PINS" Functional Operations.
Y240
driver output pins Corresponding directly each shift register, level (V0, V12, V43, selected output. Table truth values shown "TRUTH TABLE" Functional Operations.
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FUNCTION OPERATIONS
TRUTH TABLE
(Segment Mode) Latch data
DISPOFF
Note1: (0V), (+2.5V +5.5V),
Driver output voltage level (Y240
Don't care Note2: "Don't care" should fixed "L", avoiding floating. There kinds power supply (logic level voltage drive voltage) driver. Supply regular voltage which assigned specification each power pin.
(Common Mode) Latch data
DISPOFF
Driver output voltage level (Y240
RELATIONSHIP BETWEEN DISPLAY DATA DRIVER OUTPUT PINS
SEGMENT MODE 4-bit Parallel Mode
EIO1 EIO2 Data Input Output Input Input Output CLCOK Y240 Y239 Y238 Y237 Figure clock CLCOK CLCOK Y236 Y235 Y234 Y233 Y232 Y231 Y230 Y229 CLCOK CLCOK CLCOK Y229 Y230 Y231 Y232 Y233 Y234 Y235 Y236 Y237 Y238 Y239 Y240
Sunplus Technology Co., Ltd.
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8bit Parallel Mode
EIO1 EIO2 Data Input Output Input Input Output CLCOK Y240 Y239 Y238 Y237 Y236 Y235 Y234 Y233 Figure clock CLCOK CLCOK Y232 Y231 Y230 Y229 Y228 Y227 Y226 Y225 Y224 Y223 Y222 Y221 Y220 Y219 Y218 Y217 CLCOK CLCOK CLCOK Y217 Y218 Y219 Y220 Y221 Y222 Y223 Y224 Y225 Y226 Y227 Y228 Y229 Y230 Y231 Y232 Y233 Y234 Y235 Y236 Y237 Y238 Y239 Y240
COMMON MODE
(Single) L(shift left) H(shift right) L(shift left) Data transfer direction Y240 Y240 Y240 Y121 Y120 Y120 Y121 Y240 EIO1 Output Input Output EIO2 Input Output Input Input
(Dual)
H(shift right)
Input
Output
Input
Note1: (0V), (+2.5V +5.5V), Don't care Note2: "Don't care" should fixed "L", avoiding floating.
Sunplus Technology Co., Ltd.
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SPLC562A
CONNECTION EXAMPLES PLURAL SEGMENT DRIVERS
CASE data Data flow Y240 EIO2 EIO1 Y240 EIO2 EIO1 Y240 EIO2 EIO1 Last data
CASE
Data flow data EIO2 Y240
EIO1 EIO2 Y240
EIO1 EIO2 Y240 Last data
Sunplus Technology Co., Ltd.
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TIMING CHART 4-DEVICE CASECADE CONNECTION SEGMENT DRIVERS
DATA LAST DATA
device
device
device
device
(device (device
(device
(device
n=60 4-bit parallel input mode. n=30 8-bit parallel input mode.
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SPLC562A
CONNECTION EXAMPLES PLURAL COMMON DRIVERS
Single MODE (L/R "L") First Last
Y240
Y240
Y240
DISPOFF
DISPOFF
DISPOFF
EIO2
EIO1
EIO2
EIO1
EIO2
EIO1 Y240 Last
VSS(VDD)
DISPOFF
Single Mode (L/R "H") DISPOFF
VSS(VDD)
DISPOFF DISPOFF DISPOFF
Y240
Y120 Y121 Y240
EIO1
First
Sunplus Technology Co., Ltd.
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SPLC562A
Dual MODE (L/R "L") First Last First Last
Y240
Y240 Y121 Y120
Y240
DISPOFF
DISPOFF
DISPOFF
EIO2
EIO1
EIO2
EIO1
EIO2
EIO1 Y240
VSS(VDD)
DISPOFF
Dual MODE (L/R "H") DISPOFF
VSS(VDD)
DISPOFF DISPOFF DISPOFF
Y240
Y120 Y121 Y240
EIO1
First
Last First
Last
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SPLC562A
PRECAUTIONS
PRECAUTION WHEN CONNECTING DISCONNECTING POWER
This high-voltage driver, permanently damaged high current which flow voltage supplied driver power supply while logic system power supply floating. when connecting logic power supply, logic condition this inside insecurity. Therefore connect driver power supply after resetting logic condition this inside
DISPOFF function.
After that, cancel DISPOFF function
after driver power supply become stable. detail follows.
When connecting power supply, connect drive
Furthermore, when disconnecting power, drive output pins level DISPOFF function. drive power. After that,
power after connecting logic system power. Furthermore, when disconnecting power, disconnect logic system power after disconnecting driver power.
recommend connecting serial resistor (50~100)
disconnect logic system power after disconnecting
When connecting power supply, follow recommended sequence shown here.
fuse drive power system current limited. suitable value resistor consideration display grade.
DISPOFF
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SPLC562A
ABSOLUTE MAXIMUM RATINGS
Parameter Supply voltage Symbol Supply voltage Input voltage Storage temperature
Note1: Note2: maximum applicable voltage with respect (0V).
Conditions
Applicable Pins V0L,
Ratings -0.3 +6.5 -0.3 -0.3 V0+0.3 -0.3 V0+0.3 -0.3 V0+0.3 -0.3 VDD+0.3 +125
Unit
Referenced VSS(0V)
V12L, V12R V43L, V43R V5L, XCK, L/R, S/C, EIO1, EIO2, DISPOFF TEST1
TSTG
RECOMMENDED OPERATING CONDITIONS
Parameter Supply voltage Supply voltage Operating temperature Symbol Referenced (0V) TOPR V0L, Conditions Applicable Pins Min. +2.5 Typ. Max. +5.5 Unit
Note1: applicable voltage with respect (0V). Note2: Ensure that voltage such that VSSV5V43V12V0.
Sunplus Technology Co., Ltd.
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SPLC562A
ELECTRICAL CHARACTERISTICS
CHARACTERISTICS
(Segment Mode) (VSS +2.5V +5.5V, +15V +30V, +25) Parameter Input voltage Symbol ILIH ILIL ISTB IDD1 IDD2 Conditions -0.4mA +0.4mA |VON| 0.5V +30V +20V Applicable Pins XCK, L/R, S/C, EIO1, EIO2, DISPOFF EIO1, EIO2 XCK, L/R, S/C, EIO1, EIO2, DISPOFF Y240 V0L, Min. 0.8VDD VDD-0.4 Typ. Max. 0.2VDD +0.4 75.0 12.0 Unit
Output voltage
Input leakage current
Output resistance Stand-by current Supply current (Non-selection) Supply current (Selection) Supply current
Note1: +5V, +30V, Note2: +5V, +30V, fXCK 20MHz, No-load, input data turned over data taking clock (4-bit parallel input mode) Note3: +5V, +30V, fXCK 20MHz, No-load, input data turned over data taking clock (4-bit parallel input mode) Note4: +5V, +30V, fXCK 20MHz, 41.6KHz, 80Hz, No-load input data turned over data taking clock (4-bit parallel input mode)
(Common Mode) (VSS +2.5V +5.5V, +15V +30V, +25) Parameter Input voltage Symbol ILIH ILIL ISTB Conditions -0.4mA +0.4mA |VON| 0.5V +30V +20V Applicable Pins XCK, L/R, S/C, EIO1, EIO2, DISPOFF EIO1, EIO2 XCK, L/R, S/C, EIO1, EIO2, DISPOFF Y240 XCK, EIO1, EIO2, ,V0R Min. 0.8VDD VDD-0.4 Typ. Max. 0.2VDD +0.4 Unit
Output voltage
Input leakage current
Output resistance Input pull-down current Stand-by current Supply current Supply current
Note1: +5V, +30V, Note2: +5V, +30V, 41.6KHz, 80Hz case 1/480 duty operation, no-load.
Sunplus Technology Co., Ltd.
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CHARACTERISTICS
(Segment Mode (VSS +4.5V +5.5V, +15V +30V, +25) Parameter Shift clock period Shift clock pulse width Shift clock pulse width Data setup time Data hold time Latch pulse pulse width Shift clock rise latch pulse rise time Shift clock fall latch pulse fall time Latch pulse rise shift clock rise time Latch pulse fall shift clock fall time Input signal rise time Input signal fall time Enable setup time
DISPOFF removal time DISPOFF pulse width
Symbol TWCK TWCKH TWCKL TWLPH TWDL TPD1, TPD2 TPD3
Conditions TF10ns 15pF 15pF 15pF
Min.
Typ.
Max.
Unit
Output delay time Output delay time Output delay time
Note1: Take cascade connection into consideration.
Note2: (TWCK TWCKH TWCKL) maximum case high speed operation.
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(Segment Mode (VSS +3.0V +4.5V, +15V +30V, +25) Parameter Shift clock period Shift clock pulse width Shift clock pulse width Data setup time Data hold time Latch pulse pulse width Shift clock rise latch pulse rise time Shift clock fall latch pulse fall time Latch pulse rise shift clock rise time Latch pulse fall shift clock fall time Input signal rise time Input signal fall time Enable setup time
DISPOFF removal time DISPOFF pulse width
Symbol TWCK TWCKH TWCKL TWLPH TWDL TPD1, TPD2 TPD3
Conditions TF10ns 15pF 15pF 15pF
Min.
Typ.
Max.
Unit
Output delay time Output delay time Output delay time
Note1: Take cascade connection into consideration.
Note2: (TWCK TWCKH TWCKL) maximum case high speed operation.
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SPLC562A
(Segment Mode (VSS +2.5V +3.0V, +15V +30V, +25) Parameter Shift clock period Shift clock pulse width Shift clock pulse width Data setup time Data hold time Latch pulse pulse width Shift clock rise latch pulse rise time Shift clock fall latch pulse fall time Latch pulse rise shift clock rise time Latch pulse fall shift clock fall time Input signal rise time Input signal fall time Enable setup time
DISPOFF removal time DISPOFF pulse width
Symbol TWCK TWCKH TWCKL TWLPH TWDL TPD1, TPD2 TPD3
Conditions TF10ns 15pF 15pF 15pF
Min.
Typ.
Max.
Unit
Output delay time Output delay time Output delay time
Note1: Take cascade connection into consideration.
Note2: (TWCK TWCKH TWCKL) maximum case high speed operation.
TIMING CHARACTERISTICS SEGMENT MODE
TWLPH
TWCKH TWCKL
TWCK
LAST DATA
DATA
TWDL
DISPOFF
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SPLC562A
4-bit parallel input mode. 8-bit parallel input mode.
TPD1 TPD2
DISPOFF
TPD3 Y240
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SPLC562A
(Common Mode) (VSS +2.5V +5.5V, +15V +30V, +25) Parameter Shift clock period Shift pulse width Symbol TWLP TWLPH TWDL TPD1, TPD2 TPD3 Conditions TF20ns +5.0V±10% +2.5V~+4.5V Data setup time Data hold time Input signal rise time Input signal fall time
DISPOFF removal time DISPOFF pulse width
Min.
Typ.
Max.
Unit
15pF 15pF 15pF
Output delay time Output delay time Output delay time
TIMING CHART COMMON MODE
TWLP
TWLPH
EIO2 (DI7) EIO1 TWDL
DISPOFF
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JAN. 2001 Version:
SPLC562A
TPD1 TPD2
DISPOFF
TPD3 Y240 [L/R "L"]
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SPLC562A
SYSTEM CONFIGURATION EXAMPLE
(Case bias)
Controller
DISPOFF
EIO2 DI7-0 EIO1 EIO2 DI7-0
DISP
SEG1 SEG2
EIO1 EIO2 DI7-0 EIO1 EIO2 DI7-0 EIO1
DISP
DISP
DISP
SEG1919 SEG1920
Sunplus Technology Co., Ltd.
PAGE
XD7-0
50-100
SPLC562 EIO2 COM479 COM480 Y240-1 DI7DI0 EIO1 EIO2 DI7DI0 EIO1 DISP DISP COM1 COM2
SPLC562
Y240-1 Y240-1 Y240-1
1920 MATRIX PANEL
JAN. 2001 Version:
SPLC562A
CONFIGURATION
DISPOFF DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY Y240 (0,0) Y239 Y238 Y237 Y236 Y235 Y234 Y233 Y232 Y231 Y230 Y229
TEST2
TEST1
EIO1
EIO2
Chip size pitch
Bumped size
Bumped height
ALIGN COORDINATE
189.25 95um 72.25 190.75 95um
Sunplus Technology Co., Ltd.
Y225
Y226
Y227
Y228
Item
248, 309, 248, 309,
Size 15460 18(Typ.) 1900
Unit
133.2
100um
100um 134.75
Note: 10um 15um 10um
SUNPLUS
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CENTER COORDINATES
Name -7557 -7557 -7557 -7557 -7557 -7557 -7557 -7557 -7557 -7557 -7557 -7557 -7526 -7456 -7386 -7316 -7246 -7176 -7106 -7036 -6966 -6896 -6826 -6756 -6686 -6616 -6546 -6476 -6406 -6336 -6266 -6196 -6126 -6056 -5986 -5916 -5846 -5776 -5706 -5636 -5566 -163 -233 -303 -373 -443 -513 -583 -653 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 PAGE Name -5496 -5426 -5356 -5286 -5216 -5146 -5076 -5006 -4936 -4866 -4796 -4726 -4656 -4586 -4516 -4446 -4376 -4306 -4236 -4166 -4096 -4026 -3956 -3886 -3816 -3746 -3676 -3606 -3536 -3466 -3396 -3326 -3256 -3186 -3116 -3046 -2976 -2906 -2836 -2766 -2696 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 JAN. 2001 Version:
Sunplus Technology Co., Ltd.
SPLC562A
Name Y100 Y101 Y102 Y103 Y104 Y105 Y106 Y107 Y108 Y109 Y110 Y111 Y112 Y113 Y114 Y115 Y116 Y117 Y118 Y119 Y120 Y121 Y122 Y123 Y124 -2626 -2556 -2486 -2416 -2346 -2276 -2206 -2136 -2066 -1996 -1926 -1856 -1786 -1716 -1646 -1576 -1506 -1436 -1366 -1296 -1226 -1156 -1086 -1016 -946 -876 -806 -736 -666 -596 -526 -456 -386 -316 -246 -176 -106 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 Name Y125 Y126 Y127 Y128 Y129 Y130 Y131 Y132 Y133 Y134 Y135 Y136 Y137 Y138 Y139 Y140 Y141 Y142 Y143 Y144 Y145 Y146 Y147 Y148 Y149 Y150 Y151 Y152 Y153 Y154 Y155 Y156 Y157 Y158 Y159 Y160 Y161 Y162 Y163 Y164 Y165 Y166 1014 1084 1154 1224 1294 1364 1434 1504 1574 1644 1714 1784 1854 1924 1994 2064 2134 2204 2274 2344 2414 2484 2554 2624 2694 2764 2834 2904 2974 3044 3114 3184 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841
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JAN. 2001 Version:
SPLC562A
Name Y167 Y168 Y169 Y170 Y171 Y172 Y173 Y174 Y175 Y176 Y177 Y178 Y179 Y180 Y181 Y182 Y183 Y184 Y185 Y186 Y187 Y188 Y189 Y190 Y191 Y192 Y193 Y194 Y195 Y196 Y197 Y198 Y199 Y200 Y201 Y202 Y203 Y204 Y205 Y206 Y207 Y208 3254 3324 3394 3464 3534 3604 3674 3744 3814 3884 3954 4024 4094 4164 4234 4304 4374 4444 4514 4584 4654 4724 4794 4864 4934 5004 5074 5144 5214 5284 5354 5424 5494 5564 5634 5704 5774 5844 5914 5984 6054 6124 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 Name Y209 Y210 Y211 Y212 Y213 Y214 Y215 Y216 Y217 Y218 Y219 Y220 Y221 Y222 Y223 Y224 Y225 Y226 Y227 Y228 Y229 Y230 Y231 Y232 Y233 Y234 Y235 Y236 Y237 Y238 Y239 Y240 DUMMY 6194 6264 6334 6404 6474 6544 6614 6684 6754 6824 6894 6964 7034 7104 7174 7244 7314 7384 7454 7524 7555 7555 7555 7555 7555 7555 7555 7555 7555 7555 7555 7555 7555 7555 7555 7555 7555 7555 7555 7555 7499 7249 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -841 -653 -583 -513 -443 -373 -303 -233 -163
Sunplus Technology Co., Ltd.
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JAN. 2001 Version:
SPLC562A
Name DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY EIO2 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY 6999 6749 6499 6249 5999 5749 5499 5249 4999 4749 4499 4249 3999 3749 3499 3249 2999 2749 2499 2249 1999 1749 1499 1249 -251 -501 -751 -1001 -1251 Name DUMMY DUMMY DISPOFF DUMMY DUMMY DUMMY DUMMY DUMMY EIO1 DUMMY DUMMY DUMMY TEST1 DUMMY TEST2 DUMMY DUMMY DUMMY -1501 -1751 -2001 -2251 -2501 -2751 -3001 -3251 -3501 -3751 -4001 -4251 -4501 -4751 -5001 -5251 -5501 -5751 -6001 -6251 -6501 -6751 -7001 -7251 -7501 -7557 -7557 -7557 -7557 -7557 -7557 -7557 -7557
Sunplus Technology Co., Ltd.
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JAN. 2001 Version:
SPLC562A
DISCLAIMER
information appearing this publication believed accurate. Integrated circuits sold Sunplus Technology covered warranty patent indemnification provisions stipulated terms sale only. SUNPLUS makes warranty, express, statutory implied description regarding information this publication regarding freedom described chip(s) from patent infringement. FURTHERMORE, SUNPLUS MAKES WARRANTY MERCHANTABILITY FITNESS PURPOSE. SUNPLUS reserves right halt production alter specifications prices time without notice. Accordingly, reader cautioned verify that data sheets other information this publication current before placing orders. Products described herein intended normal commercial applications. Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing SUNPLUS such applications. Please note that application circuits illustrated this document reference purposes only.
Sunplus Technology Co., Ltd.
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JAN. 2001 Version:
SPLC562A
Revision History
Date AUG. 2000 NOV. 2000 Revision Description Original Add, CONFIGURATIONS Add, CENTER CORRDINATES JAN. 2001 Delete "Preliminary" Add, Revision History Renew document format 25-28 Page
Sunplus Technology Co., Ltd.
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JAN. 2001 Version:

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