80-CHANNEL SEG/COM DRIVER SPLC206A, 80-channel driver, normally u
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SPLC206A
80-CHANNEL SEG/COM DRIVER
SPLC206A, 80-channel driver, normally used
BLOCK DIAGRAM
Since this product used segment common driver, panel configured only with this product. When
driver circuit 80-bit latch register 80-bit bi-direction shift register
SPLC206A segment mode with 4-bit parallel data filled, chip-enabled-signal automatically generated enabling next SPLC206A.
Data conversion Operation mode
FEATURES
Logic power supply voltage: 5.5V Display duty: 1/16(1/5 bias) 1/240 80-channel driver driver voltage: 6.0V 28.0V Data transfer speed 4.5MHz (VDD 5.0V) 2.5MHz (VDD 3.0V) Automatic generating chip-enabled-signal next SPLC206A segment mode)
CARB
related product. capable driving various types LCD.
Counter
Seletor
SUNPLUS TECHNOLOGY reserves right change this documentation without prior notice. believed accurate reliable.
Information provided SUNPLUS TECHNOLOGY responsibility assumed addition, SUNPLUS products
However, SUNPLUS TECHNOLOGY makes warranty errors which appear this document.
Contact SUNPLUS TECHNOLOGY obtain latest version device specifications before placing your order. SUNPLUS TECHNOLOGY infringement patent other rights third parties which result from use. reasonably expected result significant injury user, without express written approval Sunplus.
authorized critical components life support devices/ systems aviation devices/systems, where malfunction failure product
PAGE
SPLC206A
FUNCTION DESCRIPTION
DATA CONVERTING OPERATING MODE
Since SPLC206A capable performing either segment driver common driver, distinguish signal necessary this determination. signal `FCS' signal selecting these modes. When `FCS' `High', SPLC206A performs When `FCS' `LOW', SPLC206A works segment mode, signal `SHL' will determine Table1: Common signal scan direction =High Shift Register shift direction -SR80DL0 Common signal scan direction Y80-Y1 segment driver. common driver.
COMMON DRIVER OPERATION
When High, shift direction Shift Register scan direction common signal shown follows:
method data transformation.
SEGMENT DRIVER OPERATION
When High High, input data transferred from Channel 80th 1st.
SR79- SR1-
Table2: Common signal scan direction =Low Shift Register Common signal scan direction
description diagram follows:
shift direction -SR1- SR2-
-SR80-
80-BIT BI-DIRECTIONAL SHIFT REGISTER
Lsat
This block works differently segment common modes. When `FCS' `LOW', common mode. this mode, register works 80-bit Shift Register. Thus, Data I/O. other hand, when `HIGH', Register functions 20*4-bit Unit Latch Register (Total twenty 4-bit Unit Latch Registers). Thus, data will enter into 4-bit Latch Registers through parallel.
Figure data transfer form segment mode =High
When High Low, input data transferred from Channel 80th.
description diagram follows:
COUNTER SELECTOR
Basically, this block works when Segment mode. enabled. When SPLC206A such mode when SPLC206A Counter will start counting from through Each count will cooperate with signal enable corresponding 4-Latch Register from 80-bit Bi-directional Shift Register Block.
Lsat
When Counter counts till `20', means data been fully filled those twenty 4-bit Latch Register. CARB equal `0'. moment, signal CARB connected another
Figure data transfer form segment mode
SPLC206A's `EB', that chip (segment mode) will enabled current chip will disable. Therefore, data will transferred after anther until last SPLC206A reached.
Sunplus Technology Co., Ltd.
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APR. 2001 Version:
SPLC206A
80-BIT LATCH REGISTER
When signal falling edge, data 80-bit Bidirectional Shift Register will latched transferred driver circuit.
DRIVER CIRCUIT
combination data 80-bit latch circuit signal generate four levels, output drive LCD.
DESCRIPTION
Mnemonic Type segment mode, driver data latched falling edge. signal should high avoid floating. segment mode, used display data latch signal. common mode, used data shift signal. both modes, valid falling edge. converting signal driver output frame signal) control signal data transferring method. Please refer Figure Figure segment mode. common mode, when low, data input output from pin. should either high avoid floating. When high, conditions reverse. Please refer Table1 Table2. When high, chip works segment mode. signal chip enable, segment data latch starts Setting low. When low, connected VDD. CARB When high 80-bit segment data latched completely, signal CARB changes from high enable next DISSPOFF state above, CARB should connected next When low, leave CARB opened. When signal low, output level turned off. time, data influenced. When signal high, driver returns normal state. TEST Sunplus Technology Co., Ltd. control signal selecting segment common mode. When high, segment mode enabled when low, common mode selected. TEST test pin. TEST should opened normal mode. pull resister built-in internally. driver output. four levels, output according combination signal display data. Table3. PAGE APR. 2001 Version: segment mode, DL0, DL1, input pins data. common mode, when low, input output pin. opposite when high. time, should avoid being float. result common mode, Power supply voltage driving level. VDD>V1>V3>V4>V2>VEE VDD, VSS: logic power supply VEE: power supply driving Description
SPLC206A
Table3: driver output level Common/Segment Data Common Segment
Note:
Display level
ABSOLUTE MAXIMUM RATINGS
Characteristics Operating Voltage Driver Supply Voltage Input Voltage Range Operating Temperature Storage Temperature
conditions AC/DC Electrical Characteristics.
Symbol VLCD TSTO
Ratings -0.3V +7.0V VDD-12V VDD+0.3V -0.3V 0.3V +125
normal operational
Note: Stresses beyond those given Absolute Maximum Rating table cause operational errors damage device.
ELECTRICAL CHARACTERISTICS
Characteristics Input high level Input level Output high Output Resistance Standby current Symbol IST1 IST2 Applicable CL1, CL2, SHL, FCS, TEST, DISPOFF CARB, DL0, CARB, DL0, Y80, VCC-0.4 28.0V 28.0V 10.0V 0.3*VCC Limit Min. 0.7*VCC Typ. Max. Unit Conditions
Note*: Input keep constant voltage
Sunplus Technology Co., Ltd.
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APR. 2001 Version:
SPLC206A
CHARACTERISTICS
Segment mode, 5.0V±10%, 6.0V 28.0V) Characteristics Clock cycle time Clock high level width Clock level width Clock setup time Clock hold time Data setup time Data hold time Enable setup time Cary output delay time phase difference cycle time Symbol tCYC tCWH tCWL tSCL tHCL tESU tCARB tCL1 Applicable CL2, CL1, CL1, CARB, Min. 50*Tcyc Max. Unit CLOAD Test Condition
CHARACTERISTICS
Segment mode, 2.7V 4.5V, 0V,VDD 6.0V 28.0V) Characteristics Clock cycle time Clock high level width Clock level width Clock setup time Clock hold time Data setup time Data hold time Enable setup time Carry output delay time phase difference cycle time Symbol tCYC tCWH tCWL tSCL tHCL tESU tCARB tCL1 Applicable Pins CL1, CL1, CL1, CARB, Min. Tcyc*50 Max. Unit CLOAD Test Conditions
CHARACTERISTICS
Common mode, 2.7V 5.5V,GND 0V,VDD 6.0V 28.0V) Characteristics Clock cycle time Clock high level width Clock level width Clock rise time Clock fall time Data setup time Data hold time Sunplus Technology Co., Ltd. Symbol tCYC tCWH tCWL Applicable Pins PAGE Min. Max. Unit APR. 2001 Version: Condition
SPLC206A
SEGMENT DRIVER OPERATION TIMING
tCWH
tCWL
tCYC
tCWH
tCL1
tSCL
tHCL
tCARB CARB
Last data tCARB
tESU
COMMON DRIVER OPERATION TIMING
tCWL tCWH tCYC
Data (DL0, DL1) Data (DL0, DL1)
Sunplus Technology Co., Ltd.
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APR. 2001 Version:
SPLC206A
COM1 COM2 COM3
DISPOFF TEST CARB
OPEN
DISPOFF TEST CONTROLLER CARB DISPOFF DL0, DL1, DL2,
PANEL 1/240 duty
OPEN
COM238 COM239 COM240
DL0~DL3 DSPOFF
CARB
DL0~DL3 DSPOFF
CARB
DL0~DL3
TEST
TEST
TEST
DSPOFF
SEG238 SEG239 SEG240
SEG1 SEG2 SEG3
OPEN
CARB
Sunplus Technology Co., Ltd.
APPLICATION NOTES
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APR. 2001 Version:
SPLC206A
SEG4
SEG8
SEG12
SEG16
SEG76
SEG80
SEG84
SEG88
SEG92
SEG232
SEG236
SEG240
SEG4
SEG8
SEG3
SEG7
SEG11
SEG15
SEG75
SEG79
SEG83
SEG87
SEG91
SEG231
SEG235
SEG239
SEG3
SEG7
SEG2
SEG6
SEG10
SEG14
SEG74
SEG78
SEG82
SEG86
SEG90
SEG230
SEG234
SEG238
SEG2
SEG6
SEG1
SEG5
SEG9
SEG13
SEG73
SEG77
SEG81
SEG85
SEG89
SEG229
SEG233
SEG237
SEG1
SEG5
CARB (the first
(the next enabled)
Timing charts application example segment driver operation
Timing charts application example common driver operation
Sunplus Technology Co., Ltd.
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APR. 2001 Version:
SPLC206A
ASSIGNMENT LOCATIONS
ASSIGNMENT
Chip Size: 5130 This IC's substrate should connected
Note1: ensure function properly, please bond VDD, AVDD AVSS pins. Note2: 0.1µF capacitor between should placed close passible.
ORDERING INFORMATION
Product Number Package Type
SPLC206A-nnnnV-C
Note1: Code number (nnnnV) assigned customer. Note2: Code number (nnnn 0000 9999) version
Chip form
Sunplus Technology Co., Ltd.
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APR. 2001 Version:
SPLC206A
LOCATIONS
Name Name
TEST
2015 1835 1678 1521 1364 1207 1050 -206 -363 -520 -677 -834 -991 -1148 -1305 -1462 -1619 -1776 -1936 -2111 -2286 -2286 -2286 -2286 -2286 -2286 -2286 -2348 -2348 -2348 -2348 -2348 -2348 -2348
1957 1957 1957 1957 1957 1957 1957 1957 1957 1957 1957 1957 1957 1957 1957 1957 1957 1957 1957 1957 1957 1957 1957 1957 1957 1957 1957 1957 1678 1481 1296 1124 -255 -420 PAGE
DISPOFF CARB
-2348 -2348 -2348 -2348 -2348 -2348 -2348 -2295 -2105 -1915 -1755 -1598 -1441 -1284 -1127 -970 -813 -656 -499 -342 -185 1071 1228 1385 1542 1699 1856 2036 2216 2410 2410 2410 2410 2410
-585 -750 -915 -1084 -1256 -1441 -1626 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1957 -1779 -1600 -1421 -1253 -1086 APR. 2001 Version:
Sunplus Technology Co., Ltd.
SPLC206A
Name Name
2410 2410 2410 2410 2410 2410 2410 2410 2410
-919 -752 -585 -418 -251
2410 2410 2410 2410 2410 2410 2410 2410 2195
1085 1252 1420 1592 1764 1957
Sunplus Technology Co., Ltd.
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APR. 2001 Version:
SPLC206A
PACKAGE CONFIGURATION
LQFP View
TEST DISPOFF
CARB
SPLC206A
Sunplus Technology Co., Ltd.
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APR. 2001 Version:
SPLC206A
PACKAGE INFORMATION
LQFP 100L Outline Dimensions Unit: mm/inches
Sunplus Technology Co., Ltd.
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APR. 2001 Version:
SPLC206A
DISCLAIMER
information appearing this publication believed accurate. Integrated circuits sold Sunplus Technology covered warranty patent indemnification provisions stipulated terms sale only. SUNPLUS makes warranty, express, statutory implied description regarding information this publication regarding freedom described chip(s) from patent infringement. FURTHER, SUNPLUS MAKES WARRANTY MERCHANTABILITY FITNESS PURPOSE. SUNPLUS reserves right halt production alter specifications prices time without notice. Accordingly, reader cautioned verify that data sheets other information this publication current before placing orders. Products described herein intended normal commercial applications. Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing SUNPLUS such applications. Please note that application circuits illustrated this document reference purposes only.
Sunplus Technology Co., Ltd.
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APR. 2001 Version:
SPLC206A
REVISION HISTORY
Date Revision Description Page
OCT. 1998 AUG. 1999
Original "PACKAGE INFORMATION" "DISCLAIMER" Modify format
OCT. 1999
Delete "PRELIMINARY" "PACKAGE CONFIGURATION"
APR. 2001
"Note: 0.1µF capacitor between Revise SPLC206 SPLC206A "PACKAGE CONFIGURATION" drawing rotate degree indicator "REVISION HISTORY" Renew document format
Sunplus Technology Co., Ltd.
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APR. 2001 Version:
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