Document Title 256K CMOS MASK Revision History 256K CMOS MASK

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Document Title 256K CMOS MASK Revision History 256K CMOS MASK

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A238308H
Document Title 256K CMOS MASK Revision History
256K CMOS MASK
History
Initial issue
Issue Date
November 1998
Remark
PRELIMINARY
(November, 1998, Version 0.0)
AMIC Technology, Inc.
A238308H
Features
262,144 organization Access time: 70/120 (max.) Current: Operating: 30mA (max.) 5MHz Standby: 100µA (max.) inputs outputs directly TTL-compatible
256K CMOS MASK
General Description
A238308H chip high-performance 2,097,152 read only memory organized 256K bits. A238308H requires only power supply normal read mode operation input signals levels.
Configurations
(32) (31) (30) (29)
(28) (27) (26)
(25)
(24)
(16) I/O3 (17) I/O4 (18) I/O5 (19) I/IO6 (20)
(12) I/O0 (13) I/O1 (14) I/O2 (15)
I/O7 (21) (22) (23)
(10)
(11)
PRELIMINARY
(November, 1998, Version 0.0)
AMIC Technology, Inc.
A238308H
Configurations
Name A0-A17 I/O7-I/O0
Function Address Inputs Data Outputs Chip Enable Output Enable Power Supply Ground
Operating Modes Truth Table
Mode Read Output Disable Standby Notes Either VIL.
I/O7-I/O0 Data Hi-Z Hi-Z
PRELIMINARY
(November, 1998, Version 0.0)
AMIC Technology, Inc.
A238308H
Functional Description
Read Mode Standby Mode A238308H control functions, both which must logically active order obtain data outputs. power control should used device selection. output control should used data output pins, which independent device selection. Assuming that addresses stable, address access time (tACC) equal delay from output (tCE). Data available output after delay (tOE) from falling edge long been addresses have been stable least tACC tOE. A238308H standby mode which reduces active current from 30mA 100µA. A238308H placed standby mode applying CMOS high signal When standby mode, output high impedance state, independent
Absolute Maximum Ratings*
Ambient Operating Temperature (TA) -10° +85° Storage Temperature Plastic Package (TSTG) -55° 125° Applied Input Voltage (VI): Pins Except -0.6V 0.6V -0.6V 7.0V Output Voltage (VO) -0.6V 7.0V (Note Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability.
*Comments
Notes: During voltage transitions, input undershoot -2.0V periods less than Maximum voltage input overshoot 2.0V periods less than
PRELIMINARY
(November, 1998, Version 0.0)
AMIC Technology, Inc.
A238308H
Read Mode Electrical Characteristics 10%)
Symbol Parameter Output High Voltage Output Voltage Input High Voltage Input Voltage Input Leakage Current -0.5 Min. Max. Unit max. max. Vout max. VIL, Iout 0mA, 5MHz max. max. 0.2V Conditions -400µA 2.1mA
Output Leakage Current
Read Operating Current
Standby Current (TTL)
ISB1
Standby Current (CMOS)
Capacitance 1.0MHz)
Symbol COut Parameter Input Capacitance Output Capacitance Min. Max. Unit Conditions VOut
These parameters sampled 100% tested.
PRELIMINARY
(November, 1998, Version 0.0)
AMIC Technology, Inc.
A238308H
Read Mode Characteristics 10%, VCC)
Symbol Parameter Min. tCYC Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold after Address, whichever Occurred First Output High Delay 70ns Max. Min. 120ns Max. Unit
Read Mode Switching Waveforms
tCYC ADDRESS Address Valid
OUTPUT Valid Output High-Z
PRELIMINARY
(November, 1998, Version 0.0)
AMIC Technology, Inc.
A238308H
Measurement Conditions
70/120 Input Rise Fall Times Input Pulse Voltage: 0.4V 2.4Volt Input Output Timing Ref. Voltage: 0.8V 2.0Volt
2.4V 2.0V 0.8V 0.4V INPUT
Testing Load Circuit
TEST POINTS
2.0V 0.8V OUTPUT
1.3V 1N914
3.3K DEVICE UNDER TEST 100pF
100pF 70/120 includes capacitance
Ordering Information
Part A238308H-70 A238308H-12 Access Time (ns) Operating Current Max. (mA) 5MHz Standby Current Max. (µA)
PRELIMINARY
(November, 1998, Version 0.0)
AMIC Technology, Inc.
A238308H
Location
Coordinate (um) Name (10) (11) (12) (13) (14) (15) (16) I/O0 I/O1 I/O2 -122.2 -317.9 -458.1 -617.9 -758.1 -917.9 -1058.1 -1217.9 -1216.2 -1056 -896.2 -736 -575.8 -416.3 -255.7 -85.4 2222.3 2222.3 2222.3 2222.3 2222.3 2222.3 2222.3 2222.3 -2196.8 -2199.4 -2199.4 -2199.4 -2199.4 -2199.4 -2199.4 -2199.4 (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) I/O3 I/O4 I/O5 I/O6 I/O7 Name 84.7 245.3 404.8 565.4 724.9 886.8 1046.5 1206.8 1223.7 1054.2 754.2 454.2 110.4 -2199.4 -2199.4 -2199.4 -2199.4 -2199.4 -2199.4 -2199.4 -2199.4 2152.3 2222.3 2222.3 2222.3 2222.3 2222.3 2222.3 2208 Coordinate (um)
PRELIMINARY
(November, 1998, Version 0.0)
AMIC Technology, Inc.

Document Title 256K CMOS MASK Revision History 256K CMOS MASK

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