ADVANCED CONTROL UNIT MULTI-CHIP MODULE ACU51 Block Four 8-B

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ADVANCED CONTROL UNIT MULTI-CHIP MODULE ACU51 Block Four 8-B

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SPACE PRODUCTS
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
ACU51 Block
Four 8-Bit Parallel Ports Synch. Serial Ports Four Asynch. Serial Ports Power Control EEPROM 128Kx8
128Kx8
Digital Interface Control
Analog Analog Module
12-Bit Block
Memory
Eight 10-bit DACs
SPECIFICATIONS:
Size Weight: 1.0" 1.4" 0.12" grams Central Processor: 8051-based, works with standard tools, extended function registers Memory: 128k SRAM, 129K EEPROM Digital I/O: BiDirectional, output only Serial Ports: total, four asynchronous (CMOS levels), synchronous Analog Inputs: channels 12-bit resolution Clocking: Internal MHz, Osc. Power: plus 3.3V dissipation) Operating Temperature: -130
FEATURES:
power Power reset Internal external clock Seven sources interrupt operation modes (normal power) power consumption normal, power) digital pins 16-bit timer/event counters serial ports (four RS-232, CMOS, half duplex synchronous) Eight channels conversion (10-bit resolution) Graphical user interface (GUI) available
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©1999 Space Electronics Inc. rights reserved.
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
INTRODUCTION
Objective
This Document details requirements functional, electrical, physical, performance characteristics Advanced Control Unit (ACU) MultiChip Module (MCM) being developed Millennium Program missions.
Scope
requirements document directed towards meeting microcontroller requirements second Millennium deep space probe Martian surface, consequence will automatically meet needs other space-based power applications. This document primarily describes characteristics ACU51 microcontroller Analog ASIC. characteristics SRAM, EEPROM, P-FET pieceparts described specification sheets Appendices respectively. ACU/MCM designed Mission Research Corporation. schematics assembly drawings included Attachments
ASIC ACU51 BIST
Definitions
Analog Digital Converter Application Specific Integrated Circuit Advanced Control Unit Internal Customer specific 8051 Microcontroller Built Self Test Digital Analog Converter Least Significant Least Significant Word Multi-Chip Module Most Significant Most Significant Word Special Function Register
Memory
APPLICABLE DOCUMENTS
Government Specifications
following documents exact issue shown form part this specification extent specified herein. event conflict between documents referenced herein contents specification, contents this specification considered superseding requirement. Specifications: None Standards: None
Non-Government Specifications
following documents exact issue shown form part this specification extent specified herein. event conflict between documents referenced herein contents specification, contents this specification considered superseding requirement. Specifications: None Standards: None Other Publications: Intel 8-bit embedded controllers
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3.1.1
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
REQUIREMENTS
System Requirements Functional Requirements
power, densely integrated, self contained multi-chip module (MCM) requiring only external power operate. designed meet microcontroller requirements second Millennium deep space probe Martian surface, consequence will automatically meet needs other space-based power applications.
3.1.1.1 Control
controlled customized 8051 microcontroller here after referred ACU51. program code used drive internal ACU51 microcontroller consists standard 8051 assembly instructions supporting development with shelf commercial assemblers. Appendix description assembly instructions. internal structure external interface ACU51 microcontroller customized accommodate required interfaces such ADC, DAC, Serial, Memory, Power control interfaces. FIGURE provides block diagram showing internal blocks ACU. functionality interfaces these blocks discussed further detail following sections.
FIGURE BLOCK DIAGRAM
P0(7:0) P1(7:0) P2(7:0) P3(7:0) LCLK PWRENB(3:0)
Memory
PWEn PADDR(15:0) PDATA(7:0) RESn POENn PCEn PBLOCK
A(15:0)
HITACHI HN58C1001 RESn EEPROM 128Kx8
D(7:0) A(16) RDY/BUSY
HCLK HCLKENB HXTAL
AIC51PENB PROMPENB
3.3V
SDIN0 SDOUT0 SCLK0 SDIN SDOUT SCLK
POWER CONTROL
AIC51 BLOCK
STRANS(1:0) STRANS (3:2) SRCV(1:0) SRCV (3:2)
PROG RSTn
CSRAMn CSRAM RBLOCK ADDR(15:0) DATA(11:0)
128Kx8
A(16) A(15:0) D(7:0)
ALOGIN(31:0) RESISTOR BLOCK
A(3:0) D(11:0)
ANALOG BLOCK
ALOGOUT(7:0)
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3.1.1.2 Modes Operation
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
capable operating modes, Power mode High Power mode. High Power mode always entered after initiation hardware reset. Power mode initiated through software control.
3.1.1.2.1 High Power Mode
Within High Power mode fully functional, operates clock rate stated Section 3.1.4.1, temperature stated Section 3.1.6.2.1 with total power dissipation that does exceed that stated Section 3.1.5.1. functional over broader range clock rate (see Section 3.1.4.2) temperature range, exceed maximum power dissipation requirement. During High Power mode, total power dissipation further reduced through power management circuitry which individual blocks powered down demand requires through software control.
3.1.1.2.2 Power Mode
Power mode entered through software control. Within this mode circuitry except wake-up Power Control circuitry powered down. Power dissipation does exceed that stated Section 3.1.5.2 same temperature requirement High Power mode. Prior entering Power mode, information required after exit must stored either non-volatile storage contained within wake-up circuitry. During Power mode, power shut circuitry except wake-up circuit, required perform additional functions while this mode other than that performed wake-up circuit. Power mode exited conclusion time delay programmed software into wake-up circuit prior initiating Power mode. programmed time delay ranges from 4000 seconds second intervals. wake-up circuit operates from frequency clock, described Section 3.1.4.3, reduce circuitry power required divide down circuitry. exit Power mode, ACU51 held reset state until System clock stabilized, which time reset removed. Prior during Power mode flag set, that accessible through software control, indicate that reset exit from Power mode.
Memory
3.1.2
Input/Output Interface
FIGURE shows Multi-Chip Module (ACU/MCM) external interface. description interface pins follow counterclockwise order they shown Figure starting with upper left. description ACU/MCM signals, Appendix
3.1.2.1 Power Interfaces
volt supply analog portion Analog ASIC. referenced analog ground (AGND). should heavily filtered, every effort should made isolate from digital switching noise sources. should bypassed with least 0.01 capacitors near possible ACU/MCM. D3.3V volt supply digital portion ACU/MCM. referenced digital ground (DGND). should bypassed with least capacitor near possible ACU/MCM DGND ground reference digital power ACU/MCM. AGND ground reference analog power ACU/MCM.
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(5V) (5V) Vdd1 (Dig. GND) (AGND) Power
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
FIGURE EXTERNAL INTERFACE
Digital Analog ALOGOUT(7:0)
SDIN0 SDOUT0 SCLK0 Discrete Serial Synch. SDIN SDOUT SCLK
P0(7:0) P1(7:0 P2(7:0) P3(7:0)
LCLK HCLK HCLKENB Control Serial Asynch. STRANS(3:0) SRCV(3:0
ALOGIN(31:0
Analog Digital
Memory
PROG
Programming Control
Power Control
PWENB(3:0)
RSTn
3.1.2.2 ACU/MCM Signal Interfaces
Port (P0.0 P0.7): Port bi-directional port. assertion hardware reset pins port configured inputs. Through software control, each configured either input output writing port control register within ACU51 microprocessor. pins this port accessed driven either word basis. input output characteristics CMOS levels. Port (P1.0 P1.7): Port bi-directional port. assertion hardware reset pins port configured inputs. Through software control, each configured either input output writing port control register within ACU51 microprocessor. pins this port accessed driven either word basis. input output characteristics CMOS levels. addition, Port pins have alternate functions shown TABLE
TABLE PORT ALTERNATE FUNCTIONS
PORT P1.0 P1.1 P1.2 P1.3 P1.4 ALTERNATE NAME ALTERNATE FUNCTION T2EX CEX0 CEX1 External clock input timer/Clock Timer/Counter Capture/Reload trigger direction control External count input External capture/compare Module External capture/compare Module
Port (P2.0 P2.7): Port bi-directional port. assertion hardware reset pins port configured inputs. Through software control, each configured either input output writing port control register within ACU51 microprocessor. pins this port accessed driven either word basis. input output characteristics CMOS levels.
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ADVANCED CONTROL UNIT MULTI-CHIP MODULE
Port (P3.0 P3.1 P3.6 P3.7): Four Port bi-directional pins. assertion hardware reset, pins (P3.0 P3.1 P3.6 P3.7 configured outputs driving level. Through software control, each (P3.0 P3.1 P3.6 P3.7) configured either input output writing port control register within ACU51 microprocessor. These pins accessed driven either word basis. input output characteristics CMOS levels. Port (P3.2 P3.5): Four Port bi-directional pins. assertion hardware reset, pins (P3.2 P3.5) port configured inputs. Through software control, each (P3.2 P3.5) configured either input output writing port control register within ACU51 microprocessor. These pins accessed driven either word basis. input output characteristics CMOS levels. addition, Port pins have alternate functions shown TABLE
TABLE PORT ALTERNATE FUNCTIONS
PORT P3.2 P3.3 P3.4 P3.5 ALTERNATE NAME ALTERNATE FUNCTION INT0n INT1n External Interrupt External interrupt External clock input Timer External clock input Timer
XTAL1: CMOS level input. XTAL1 input terminal Pierce oscillator which used clock source connecting appropriate external crystal passive circuitry across XTAL1 XTAL2 terminals. XTAL1 also used input external clock. XTAL2: XTAL2 output terminal Pierce oscillator which used clock source connecting appropriate external crystal passive circuitry across XTAL1 XTAL2 terminals. RCEN: CMOS level input. RCEN frequency oscillator enable signal. logical high enables frequency oscillator. logical inhibits frequency oscillator. terminal pulled logical high through Kohm resistor D3.3V internal MCM. LCKENB: CMOS level input. high level LCLKENB enables LCLK frequency clock source ACU51 microcontroller. level will enable ACU51 generate frequency clock source from divide down high frequency clock source selected HCKENB. terminal pulled logical high through Kohm resister D3.3V internal MCM. LCLKOUT: LCLKOUT output frequency oscillator. This terminal should connected LCLK terminal on-board frequency oscillator used source frequency clock. LCLK: CMOS level input. This provides alternate clock source Frequency Clock. this clock source ACU51 internally generated clock shall controlled LCKENB. HCLK: CMOS level input. This provides alternate clock source High Frequency Clock. this clock source high frequency crystal controlled HCKENB. output on-board high frequency oscillator connected this terminal. available external clock sources. HCKENB: CMOS level input. high level this enables HCLK high frequency clock source ACU51 microcontroller, turns Pierce oscillator circuit. level enables source connected XTAL1 high frequency clock. terminal pulled logical high through Kohm resistor D3.3V internal MCM. HCLKOUT: HCLKOUT general purpose clock source same frequency external high frequency clock ACU51. HCLKOUT enabled setting ACU51 special function register, PENB, high level. reset, HCLKOUT disabled level. ALOGIN(32-0): Analog level inputs. analog input pins that provide analog channels analog that front ADC. Each input range 0-4.096V with 4.096V being full-scale. ALOGRST: CMOS level input. ALOGRST external reset Analog ASIC. logical high forces reset Analog ASIC. terminal pulled logical through Kohm resistor DGND internal MCM.
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ADVANCED CONTROL UNIT MULTI-CHIP MODULE
PROG: CMOS level input. PROG held high level when exiting hardware reset, taken high during ACU51 operation, ACU51 microcontroller executes instructions from internal ROM. This causes ACU51 receive serial information from serial UART channel program information into program storage space EEPROM. space, ACU51 space available down loading through same UART channel. Once entered, this mode must exited hardware reset. RSTn: CMOS level input. This provides hardware reset module. RSTn active signal must held minimum allow crystal startup correct sequencing state machine controlling EEPROM download SRAM. terminal pulled logical high through Kohm resistor D3.3V internal MCM. ALOGOUT(7:0): Analog level outputs. analog output channels from Analog Module DAC. Each channel delivers current internal scaling resistor steps, providing external voltage steps. full scale output through internal scaling resistor ohms provides full-scale output 4.096V. PWRENB(3:0): CMOS level outputs. These pins powered during Power mode. They provided control power external devices while operating High Power modes. They also used other functions, when output desired during Power mode. SRCV(3:0): CMOS level inputs. These signals comprise four single ended CMOS receiver channels asynchronous serial channels ACU/ MCM. They interface directly with ACU51 microcontroller multiplexed there into single UART. TRAN(3:0): CMOS level outputs. These signals comprise four single ended CMOS transmitter channels asynchronous serial channels module. These four single ended transmitter channels from ACU51 microcontroller driven from single UART, de-multiplexed drive appropriate four asynchronous serial transmitter output channels ACU. SCLK1: CMOS level output. Synchronous serial clock channel clock that provides time base synchronously transmit receive serial data pins SDOUT1 SDIN1 over channel Both channels multiplexed single synchronous serial receiver/transmitter. SDOUT1: CMOS level output. Synchronous Serial data output channel Used transmit serial data synchronously with respect channel serial clock SCLK1. Both channels multiplexed single synchronous serial transmitter. SDIN1: CMOS level input. Synchronous Serial data input channel Used receive serial data synchronously with respect channel serial clock SCLK1. Both channels multiplexed single synchronous serial receiver. SCLK(0): CMOS level output. Synchronous Serial clock channel clock that provides time base synchronously transmit receive serial data pins SDOUT0 SDIN0 over channel Both channels multiplexed single synchronous serial receiver/transmitter. SDOUT0: CMOS level output. Synchronous Serial data output channel Used transmit serial data synchronously with respect channel serial clock SCLK0. Both synchronous serial channels multiplexed single synchronous serial transmitter. SDIN0: CMOS level input. Synchronous Serial data input channel Used receive serial data synchronously with respect channel serial clock SCLK0. Both synchronous serial channels multiplexed single synchronous serial receiver. ALOGOUT (7:0): Analog level outputs. analog output channels from Analog ASIC DAC. Each channel delivers current internal Kohm scaling resistor steps, providing external voltage steps. full scales output through internal scaling resistor Kohms provides full-scale output 4.096V.
Memory
3.1.3
Physical Requirements
3.1.3.1 Size
multi-chip module footprint more than 20.32 dimension 32.26 other. Height does exceed 2.54
3.1.3.2 Packaging
ACU/MCM fabricated with Plastic High Density Interconnect (HDI-P) developed General Electric/Corporate Research Division (GE/CRD). Lower cost, multilayer, co-fired ceramic packages also available.
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3.1.4 Clock Source
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
employs clock sources high frequency frequency clocks. Provisions made allow operation from external oscillators.
3.1.4.1 High Frequency Clock Power
meets power requirements specified Section 3.1.5.1 when operating following clock rate temperature range specified Section 3.1.6.2.1. Note that high frequency oscillator produces approximately oscillations. frequency oscillation function temperature power supply voltage. Maximum frequency:10
3.1.4.2 High Frequency Clock Operational
operates following maximum clock rate. rate excess maximum frequency stated Section 3.1.4.1 rate stated below exceed maximum power requirement stated Section 3.1.5.1. Note that Analog ASIC functions only specified MHz. high frequency clock greater than used, should operated divide mode lower) during operations using Analog ASIC. high frequency oscillator produces approximately oscillations. frequency oscillation function temperature power supply voltage. Maximum Operational Frequency:11.
3.1.4.3 Frequency Clock
Memory
frequency clock used wake-up circuitry initiate exit from Power mode. frequency clock required reduce circuitry power divide circuit provide known time base obtain consistent wake-up time. frequency oscillator produces approximately oscillations. frequency oscillation function temperature power supply voltage. user should take variations oscillation frequency into consideration when programming "wake-up" times from power mode. Operating Frequency:
3.1.5
Power
3.1.5.1 High Power Mode
dissipates more than average power clock frequency stated Section 3.1.4.1 with load output pins.
3.1.5.2 Power Mode
dissipates more than average power. During Power mode, internal blocks powered down except wakeup power control circuitry.
3.1.5.3 Power Supplies 3.1.5.3.1 Analog Supply
5V+/-5% supply provide minimum 5V@8.0mA during maximum clock speed. This supply available during modes operation.
3.1.5.3.2 3.3V Digital Supply
3.3V +/-5% supply provide minimum 3.3V@8.0mA during maximum clock speed. This supply available during modes operation.
3.1.6
Environment
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3.1.6.1 General Lifetime
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
life testing been performed ACU/MCM constituent parts time this document preparation. However, technologies used fabrication consistent with expected operational life years greater.
3.1.6.2 Temperature 3.1.6.2.1 Operating Temperature
Operate specified power: meets specifications after temperature cycling from minimum -120 maximum temperature times rate minute.
3.1.6.2.2 Storage Temperature
Storage temperature does exceed:
3.1.6.3 Mechanical Shock
operates during after maximum shock 15,000
3.1.6.4 Radiation 3.1.6.4.1 Total Dose
total ionizing dose tests have been performed ACU/MCM constituent parts time this document preparation. However, technologies used fabrication consistent with expected hardness level Krad (Si) space dose rates.
Memory
3.1.6.4.2 Single Event Upset (SEU)
Single Event Upset (SEU) testing been performed ACU/MCM constituent parts time this document preparation.
3.1.6.4.3 Single Event Latchup (SEL)
Single Event Latchup (SEL) testing been performed ACU/MCM constituent parts time this document preparation. However, technologies used fabrication consistent with expectation that latchup will encountered particles with MeV/mg/cm2. This means that ACU/MCM likely quite hard SEL.
3.2.1
Internal Requirements Memory
3.2.1.1
provides minimum Kbytes Data with upper bytes aside Memory Mapping Analog Module functions. ability access total Kbytes data memory. Data memory only accessible through MOVX commands. Special Function Register PGADDR described Section 3.2.6.4.2.9, provides page address used MOVX paging commands. lower Kbytes used program execution. program execution from lower space with capability provided execute from ACU. After hardware reset, program nonvolatile data storage contained EEPROM automatically downloaded space. Program execution then automatically starts from address program space RAM. After program execution starts, EEPROM shutdown. FIGURE shows organization including area aside program storage.
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1FFFF 1FFF0
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
FIGURE MEMORY SPACE
Analog Memory Space bytes
Data Space 128K bytes
10000
Program Space bytes 00000
FIGURE shows different methods extent access RAM. used both program execution data storage.
FIGURE ACCESS
128K
Memory
Upper Data Bank
EEPROM transfer
Program execution
MOVC Access
Lower Program Bank
FIGURE PROGRAM EXECUTION TIMING FROM
CLOCK
Inst. Addr. Inst. Addr. Inst. Addr. Inst. Addr.
ADDR
DBUS
Data Sampled
Data Sampled
Data Sampled
CSRAMn
ALOGCSn
MOVX Access
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ADVANCED CONTROL UNIT MULTI-CHIP MODULE
FIGURE MOVX READ: PROGRAM EXECUTION FROM
ADDRESS
RBLOCK DBUS
MOVX Read Address
SRAM ANALOG SRAM !CSRAMn
Data sampled SRAM
CSRAMn ALOGCSn
Memory
FIGURE MOVX WRITE: PROGRAM EXECUTION FROM
ADDRESS
RBLOCK DBUS
MOVX Write Address
SRAM !CSRAMn 8051 SRAM
CSRAMn ALOGCSn
3.2.1.1.1 Interface
Hitachi HC628128A 128Kx8 CMOS SRAM. description interface pins provided below, with functional truth table shown Table
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ADVANCED CONTROL UNIT MULTI-CHIP MODULE
(16:0):RAM Address Bus. 17-bit address access banks Kbytes memory space. Address A(16) defaults level during Program Memory access D(7:0) [I/O(7:0)]: Data Bus. 8-bit data connected lower eight bits ACU51 Data Bus. This used read write data RAM. [WE]: Write Enable. Active level this initiates write cycle disables output. [OE]: Output Enable. Active level this enables output drivers selected. E[CS2]: Chip Select. Active high chip select allows chip operation long state. level this places into standby mode tri-state data outputs. order dissipate minimum amount standby power, must high when low. Sn[CS1]: Chip Select. Active chip select allows chip operation long high state. high level this places into standby mode tri-state data outputs. order dissipate minimum amount standby power, must when high.
TABLE OPERATION TRUTH TABLE
MODE WRITE READ OUTPUT DISABLE STANDBY STANDBY E[CS2] HIGH HIGH HIGH SN[CS1] HIGH WN[WE] HIGH HIGH GN[OE] HIGH D[I/O] DATA-IN DATA-OUT HIGH-Z HIGH-Z HIGH-Z POWER ACTIVE ACTIVE ACTIVE STANDBY STANDBY
Memory
3.2.1.2 EEPROM
ability write Kbytes EEPROM. EEPROM used program memory storage nonvolatile data storage. software controlled read access EEPROM possible, program execution performed EEPROM space. EEPROM programmable while installed ACU, software controlled nonvolatile write command available writing nonvolatile data storage EEPROM space. memory Kbytes EEPROM space shown below Figure
FIGURE EEPROM MEMORY SPACE
128K
Capable being programmed
Lower Program Bank
different methods access their extent shown FIGURE conclusion hardware reset power mode, automatically downloads contents EEPROM space space, after which, program execution commences from space. this time, EEPROM powered down clearing PROM ACU51 Special Function Register PENB.
EEPROM transfer
Upper Data Bank
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128K
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
FIGURE EEPROM ACCESS
Capable being programmed
Lower Program Bank
3.2.1.2.1 EEPROM Interface
program nonvolatile data storage Hitachi HCN58V1001C30 (equivalent Hitachi HN58V1001TP-25 package part) 128Kx8 CMOS EEPROM. description EEPROM interface pins provided below, with functional truth table Table A(16:0): Address CMOS input. Seventeen bits access 128K bytes memory. D(7:0)[I/O(7:0)]2: Data Bi-directional CMOS. 8-bit used access data from EEPROM RESn[RES]: Reset erase/program inhibit CMOS input. When RESn low, EEPROM cannot read programmed. EEPROM reset must held during system reset other periods non-access inhibit unintentional erasure/programming. [CE]: Chip Enable CMOS input. Active signal allows chip operation. During write cycle, addresses latched falling edge data latched rising edge CEn. High level places EEPROM into standby mode. OENn [OE]: Output Enable CMOS input. Active signal enables EEPROM drive D(7:0). High level places EEPROM outputs into high-z state. [WE]: Write Enable CMOS input. Active signal allows EEPROM write cycle begin.
EEPROM transfer
Upper Data Bank
Memory
TABLE EEPROM OPERATION TRUTH TABLE
MODE Read Standby Write Program [CE] HIGH [OE] HIGH [WE] HIGH RESn [RES] HIGH HIGH DATA-OUT HIGH-Z DATA-IN HIGH-Z
3.2.1.2.2 EEPROM Programming
EEPROM programmable through external connections ACU. exits hardware reset with PROG held high level, enters EEPROM programming mode. this mode ACU51 microcontroller controlled from internal ROM. internal causes ACU51 access data through asynchronous serial port Data received blocks ranging from program data words. addition programming data into EEPROM, programming mode provides ability write back data contained RAM, ACU51 data RAM, ACU51 space providing verification programming internal monitoring system debug software development. more details EEPROM programming mode Section 3.2.6.4.1.4.
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3.2.1.2.3 Programming Non-volatile Data
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
ability store data EEPROM non-volatile data storage during normal operation. ACU51 reserves Opcode command store bytes data contained identical addresses EEPROM each execution command. Section 3.2.6.4.1.3 more details non-volatile data storage.
3.2.2
Analog Module
Analog section ACU/MCM consists Analog ASIC Resistor ASIC shown Figure Analog ASIC includes 31:1 analog multiplexer (MUX), 12-bit analog-to-digital converter (ADC), eight 10-bit digital-to-analog converters (DAC), proportional absolute temperature (PTAT) circuit, internal voltage references. Resistor ASIC includes load resistors DACs, variety feedback trim resistors required Analog ASIC reference calibration circuits.
FIGURE ANALOG MODULE BLOCK DIAGRAM
Analog Module AIN(31:0) CLKF(1:0) POCn PRENn D(11:0) A(3:0) Block Digital Interface Control DACMSC(7:0)
Block DACLSC(7:0)
Memory
Resistor Block
ALOGOUT(7:0)
3.2.2.1 Analog Module Digital Interface 3.2.2.1.1 Data Transfers
Analog Module memory mapped ACU51 using common address data used Memory access (see FIGURE Analog Module provided common Write (Wn) line with RAM, Analog Module Chip Select (ALOGCSn). Analog Module uses least significant address lines Address decoding between internal register locations contained within Analog Module. FIGURE shows overall memory with TABLE providing specific address allocations Analog Memory Space. Each register location shown TABLE capable read write access accommodate testability. only accessed using ACU51 MOVX instructions. data expanded bits accommodate single instruction MOVX transfers from Analog Module. upper four bits, D(11:8), data bus, written read from AUXACC register ACU51. Analog Module ignores address changes, transitions pins, does drive data bus, unless selected analog chip select CSn.
TABLE ANALOG ADDRESS ALLOCATIONS
ADDRESS BASE 0FFFXH
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REGISTER NAME CALIB2 CALIB1
FUNCTION 3rd, CAL,
NUMBER BITS
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ADDRESS BASE 0FFFXH REGISTER NAME DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 ADCOUT(3) ADCOUT(2) ADCOUT(1) ADCOUT(0)
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
TABLE ANALOG ADDRESS ALLOCATIONS
FUNCTION Register Register Register Register Register Register Register Register Converter Register Converter Register Converter Register Converter Register Address Command Register NUMBER BITS
Memory
3.2.2.1.2 Clock Rate
Analog ASIC provided single variable external clock that operate four predetermined frequencies internal processing. Analog Module informed which four clock frequencies being used inputs FREQ(1:0) shown TABLE FREQ(1:0) used Analog ASIC optimize internal bias conditions four possible operating frequencies match power throughput. values FREQ(1:0) CLKCON Register. CLKCON sets FREQ(0) CLKCON sets FREQ(1).
TABLE ANALOG MODULE CLOCK FREQUENCIES
FREQ(1) FREQ(0) CLOCK FREQUENCY INPUT 0.625 1.25
clock frequency Analog Module must changed during conversion process. continuous conversion process, Halt command Address Control Register (MAD) must initiated completed prior modifying clock frequency.
3.2.2.1.3 Reset
methods provided resetting Analog ASIC. external reset issued A_RST (INIT) resets internal registers including calibration. A_RST pulled down logical internal ACU/MCM Kohm resistor connected DGND. second method resetting Analog ASIC assert logical high Enable Prime (ENP) terminal. This terminal available externally. Internally, connected ALOGPENBn terminal ACU51. Thus, Analog ASIC reset under program control. During high, Analog ASIC bias currents switched zero. Upon exiting this reset mode, calibration registers must reloaded.
3.2.2.1.4 Power Reduction
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Tri-state Data Bus. Drive digital outputs level. Gate digital inputs; possibility them floating. Clear internal registers. Zero outputs. Calibration registers must reset after leaving power reduction mode.
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
Analog ASIC includes power reduction mode that immediately activated taking high level. While power reduction mode, Analog Module required perform processing. initiation power reduction, Analog Module performs following:
3.2.2.2 Analog Digital Converter (ADC)
Analog Digital Converter (ADC) Analog provide capability monitor external analog channels analog signals internal ACU/MCM.
3.2.2.2.1 Number input
There channels which accessed from terminals ACU/MCM. addition, there channels monitor health status Analog ASIC. channel addresses channel functions listed Table
3.2.2.2.2 Converter Resolution
provides 12-bit resolution
Memory
3.2.2.2.3 Analog Input Levels
input range 4.096V corresponding converted output full-scale increments.
3.2.2.2.4 Bandwidth
capable processing single channel continuously 333K samples second clock rate MHz. Each port input multiplexer, when selected, will input capacitance auto-zeroed switched capacitor amplifier during sampling interval, e.g. four clock periods. Initially, capacitor will zero volts. signal source must capable driving capacitor required settling precision during sampling interval. 12-bit resolution, approximately time constants required. minimum sampling interval clock. worst case time constant must less than maximum source resistance signal source must able drive interconnect other stray capacitances. maximum source impedance proportional clock period, e.g., clock supply, source resistance Extremely high resistance sources sampled with high resolution source capacitance sufficiently high. source capacitance must more than 4096 times switched capacitor value prevent more than resolution from being lost from charge sharing source resistance infinite (e.g., 4096 0.0082 0.01 µF). example, source must paralleled with approximately 0.01 avoid appreciable charge sharing loss. This means that source time constant input signal characteristics arbitrary values source resistance capacitance readily calculated modeling multiplexer input capacitor with initial condition zero volts, which switched onto signal source sampling interval, e.g., clock periods. aperture uncertainty determined digital edge jitter sampling period very small compared nanosecond.
3.2.2.2.5 Functionality
Analog Digital Converter controlled commands sent Address Control Register (MAD). register 8-bit register than contains 6-bit address field 2-bit Command field shown Table address defined bits accommodate maximum external analog input channels internal test status channels. definition address field shown Table command field decoded configure operate four specific modes shown Table
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CMD1 Reset Value 0000 0000 CMD0 SEL5 SEL4
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
TABLE ADDRESS COMMAND REGISTER (MAD)
Address FFF0 SEL3 SEL2 SEL1 SEL0
TABLE ADDRESS FIELD
SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 CHANNEL SELECTED ALOGIN(0) ALOGIN(1) ALOGIN(2) ALOGIN(3) ALOGIN(4) ALOGIN(5) ALOGIN(6) ALOGIN(7) ALOGIN(8) ALOGIN(9) ALOGIN(10) ALOGIN(11) ALOGIN(12) ALOGIN(13) ALOGIN(14) ALOGIN(15) ALOGIN(16) ALOGIN(17) ALOGIN(18) ALOGIN(19) ALOGIN(20) ALOGIN(21) ALOGIN(22) ALOGIN(23) ALOGIN(24) ALOGIN(25) ALOGIN(26) ALOGIN(27) ALOGIN(28) EXTERNAL/INTERNAL External External External External External External External External External External External External External External External External External External External External External External External External External External External External External CHANNEL NUMBER
Memory
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SEL5 SEL4 SEL3 SEL2 SEL1 SEL0
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TABLE ADDRESS FIELD
CHANNEL SELECTED ALOGIN(29) ALOGIN(30) ALOGIN(31) DAC0 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7 PREF NREF PTAT SPARE0 SPARE1 SPARE2 EXTERNAL/INTERNAL External External External Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal CHANNEL NUMBER
Memory
TABLE COMMAND FIELD
MODE DESCRIPTION Random Channel Access Single Channel Continuous (this mode available Analog ASIC, used implementation) Sequential Channel Halt CMD1 (BIT CMD0 (BIT MODE
begins operation MOVX instruction that writes register. description each possible modes operation follows: Mode Random Channel Access. this mode, single analog-to-digital conversions initiated writing address multiplexer address register with extension bits M06, respectively. conversion performed voltage which sampled addressed multiplexer port, data stored ADCOUT(0) register analog-to-digital converter, then chip halts awaiting another command. During this mode, ADCOUT(3:1) retain their previous values. Mode Single Channel Continuous. this mode, analog-to-digital conversion operation initiated writing address multiplexer address register with extension bits M06, respectively. converter performs conversion voltage which sampled addressed multiplexer port, data stored ADCOUT(0) register converter, operation repeats until "halt" command received. conver0916.99Rev0
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sion progress completed regardless when "halt" command received. During this mode, ADCOUT(3:1) retain their previous values. This operating mode available Analog ASIC recommended mode ACU/MCM typical application this mode would END-OFCONVERT (EOC) signal from clock data register into external device. ACU/MCM, connected ALOGEOC terminal ACU-51 microcontroller, pulse short reliably detected ACU-51. Mode Sequential Channel. this mode, analog-to-digital conversion operation initiated writing base address multiplexer address register with extension bits M06, respectively. converter performs conversion voltage which sampled base address port, then next three higher addresses. data stored ADCOUT(3:0) data registers converter shown Table converter then halts. ability access total analog channels, external plus internal. base address corresponds analog input ports sampled sequence "wraps" analog channel etc. example, base address analog channel ports that sampled Analog input channels higher than available. this description, address numbers refer analog input port number. binary addresses these ports range from 000000 first port 101111 forty eighth port. multiplexer address register bits designated through first. through correspond Analog Input Port. Bits define converter mode operation. Mode Halt: "halt" command used terminate continuous conversion (Mode analog-to-digital operation halted writing address multiplexer address register with extension bits M06, respectively. Operation terminates after next full conversion.
TABLE SEQUENTIAL STORAGE
Memory
CONVERTED CHANNELS Addressed Channel Addressed Channel Addressed Channel Addressed Channel
DATA STORAGE LOCATION ADCOUT(0) ADCOUT(1) ADCOUT(2) ADCOUT(3)
Halt mode command required before changing between modes command address change received MOVX instruction register, completes current conversion sequence conversions before executing command. End-of-Convert (EOC) normally logical output. case Modes high completion each conversion (mode only having conversion) remains high clock cycle. receipt Mode command, takes Busy (BSY) output high level signaling that conversion progress. case Mode conversion, returns level each conversion. case Mode conversion, remains high until completion conversion sequence. transition occurs falling edge EOC. signal connected ALOGBN terminal ACU51 microcontroller.
3.2.2.3 Digital Analog Converter (DAC)
Digital Analog Converter (DAC) sub-block Analog ASIC shares digital interface with Analog Digital Converter (ADC).
3.2.2.3.1 Number output channels
There DACs contained Analog ASIC.
3.2.2.3.2 Converter Resolution
Each provides resolution.
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3.2.2.3.3 Analog output levels
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Each provides monatonic output rent 0.25 steps. This current drives effective Kohm scaling resistor resident ACU/MCM. output from internal Kohm scaling resistor provides voltage output range 4.096V steps.
3.2.2.3.4 Functionality
Analog ASIC includes eight independent channels. Each channel controlled ACU51 MOVX write operation corresponding Analog Module register DAC0 DAC7 shown TABLE registers DAC0 DAC7 registers, shown TABLE each which written read from testability. Each register edge triggered eliminate transitional data during MOVX operation from driving channel. digital word clocked into register next rising edge clock after write signal (Wn) asserted.
TABLE DACX REGISTER DEFINITIONS
DACx 7-0) Reset Value 0000 0000 (Address FFFC FFF5)
3.2.2.4 Analog Subsystem Resistor Block
Analog Subsystem Resistor block monolithic resistor ASIC that separate from Analog Module ASIC. provides Analog Module with necessary resistors trimming, references, output scaling. Only load resistors DACs interface directly ACU/MCM terminals. Several trim resistor chains tied pads surface ACU/MCM that appropriate jumpers installed.
Memory
3.2.3
Serial Interfaces
ACU/MCM includes both asynchronous synchronous serial interfaces.
3.2.3.1 Asynchronous Serial
Asynchronous Serial Interface consists four transmit four receive channels that directly interfaces ACU51 microcontroller. FIGURE level block diagram. four receive channels multiplexed into single UART while four transmit channels de-multiplexed from same single UART drive appropriate transmit channel. Selection receive transmit channel under software control through ACU51 SSCON SFR. Only receive transmit channel combination active time, with combination allowable. serial interfaces support only CMOS levels.
FIGURE ASYNCHRONOUS SERIAL LEVEL
SRCV(0)
DEMUX
Asynchronous Serial Control
STRANS(0)
SRCV(1)
STRANS(1)
Data SRCV
Data
STRANS
SRCV
STRANS
ACU51
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Four channels follow modified RS-232 standard; being single-ended (unbalanced), non-terminated line that voltage swing between CMOS logic levels. Each asynchronous serial interface transmit receive data software programmable formats; 8-bit data transfers shown FIGURE 9-bit data transfers shown FIGURE time, active transmit receive channels same format, i.e. 9-bit. more information asynchronous serial interface Section 3.2.6.4.4.2.
FIGURE ASYNCHRONOUS SERIAL 8-BIT TRANSFER
Asychronous Serial Transmit Data
Transmit Clock S6P2 Write Asychronous serial buffer
STRANS
Start
Stop
Interrupt
Asychronous Serial Receive Data
Receive Clock SRCV Start Samples Times Interrupt Stop
Memory
FIGURE ASYNCHRONOUS SERIAL 9-BIT TRANSFERS
Asychronous Serial Transmit Data
Transmit Clock S6P2 Write Asychronous serial buffer
STRANS
Start
Stop
Interrupt
Asychronous Serial Receive Data
Receive Clock SRCV Start Samples Times Interrupt Stop
3.2.3.2 Synchronous Serial
Synchronous Serial Interface consists channels that provide transmit/receive capability. Both channels interface single synchronous serial controller, with selection active channel controlled through ACU51. Only channel active time. Each channel capability transmission reception.
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Each channel consists clock, data-out, data-in pin. Transmission reception under control ACU51 with ACU51 always providing clock. level block diagram interface shown FIGURE
FIGURE SYNCHRONOUS SERIAL LEVEL
DEMUX
Synchronou
Data SDIN0 Data SDOUT0
Serial Control
SDOUT1
DEMUX
SDIN Clock SCLK0
SCLK
AIC51
Channel zero default reset. Both channels consist clock, data-out, data-in pins that single-ended (unbalanced) non-terminated. voltage swing pins CMOS levels. FIGURE shows transfer formats Synchronous Serial interface. more information synchronous serial interface Section 3.2.6.4.4.1.
Memory
FIGURE SYNCHRONOUS SERIAL TRANSFERS
Sychronous Serial Transmit
S1P1 S6P2 Write Sychronous Serial Buffer
SDOUT
SCLK S3P1 Interrupt S6P1
Sychronous Serial Receive
S1P1 S6P2 Write clear sychronous serial receive interrupt (SRI) SDIN
SCLK S3P1 Interrupt
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3.2.4 Power Management Control
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Control circuitry power management contained ACU51. ACU51 provides types power control: internal control blocks external control. Internal control consists signals ACU51PENBn, PROMPENBn, ALOGPENBn. ALOGPENBn interfaces directly Analog Module's internal power control circuitry. ACU51PENBn PROMPENBn interface Power Control block control MOSFETs that supply power individual blocks ACU. ACU51 circuitry guarantees that power ACU51 shut down only initiation Power mode, power appropriately Power mode exit reset. External control available through four signals PWRENB(3:0). provides these control bits outside control signals power control external circuitry. These signals also used general purpose that continues powered during Power mode. During Power mode Power Management Control Bits only ACU51 output lines that continue powered. Power Management control signals controllable software during Power mode. Power mode, Power Management control signals then modified re-power both external circuitry. Below description each signal. PWRENB(3:0): CMOS level outputs. These pins powered during Power mode. They provided control power external devices while operating High Power modes. They also used other uses, when output desired during Power mode. ACU51PENBn: Internal signal from ACU51 Power Control Block. PMOS gate signal that controls power ACU51 RAM. level this enables power. This taken high level only during Power mode, controlled power control circuitry remove reestablish power ACU51 RAM. PROMPENBn: Internal signal from ACU51 Power Control Block. PMOS gate signal that controls power internal EEPROM. level this enables power EEPROM. ALOGPENBn: Internal signal from ACU51 Analog Module's internal power control circuitry. high level signals Analog Module enter power reduction state. (Designated terminal Analog ASIC design.)
Memory
3.2.5
Test
ACU51 microcontroller Built Self Test (BIST) check internal circuitry. external pins ACU51 microcontroller reset during BIST routine, internal registers modified. completion BIST routine internal pass/fail flag that cleared internally generated reset BIST completion. rest tested test program loaded into Program that exercises individual blocks Discrete ACU.
3.2.6
Microcontroller
controlled customized 8051FC microcontroller. program code used drive internal ACU51 microcontroller consists standard 8051 assembly instructions supporting development with shelf commercial assemblers. Appendix description assembly instructions. internal structure external interface ACU51 microcontroller customized accommodate required interfaces such Analog Module, Serial, Memory, Power control interfaces. FIGURE provides block diagram showing interfaces ACU51 microcontroller. functionality interfaces these blocks discussed further detail following sections.
3.2.6.1 Modes Operation 3.2.6.1.1 High Power Mode
Within High Power mode ACU51 microcontroller fully functional. High Power mode entered from reset ACU51.
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P0(7:0) P1(7:0) P2(7:0) P3(7:0)
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FIGURE ACU51 BLOCK DIAGRAM
(3.3V) VSdd (Switched 3.3V)
Discrete
Power
LCLK HCLK HCLKENB HXTAL Clock Control
EEPROM
PWEn PADDR(15:0) PDATA(7:0) RESn POENn PCEn PBLOCK
SDIN0 SDOUT0 SCLK0 SDIN SDOUT SCLK Serial Synch.
Power Control
PWRENB(3:0) ALOGPENB AIC51PENB PROMPENB
STRANS(3:0) SRCV(3:0) Serial Asynch. Programming Control Analog Module
CSRAMn CSRAM RBLOCK ADDR(15:0) DATA(11:0) ALOGCLK ALOGCLKF(1:0) ALOGCSn ALOGBn ALOGEOC
Memory
PROG RSTn
ACU51
3.2.6.1.2 Power Mode
Power mode only entered through software control. Within this mode, circuitry except wake-up Power Control circuitry powered down. Prior entering Power mode, information required after exit must stored either EEPROM storage contained within wake-up circuitry. Power mode initiated upon writing logic high ACU51 Power mode LPENB Power Status Register (LPS1), this time power shut circuitry except wake-up Power Control circuits. While Power mode required perform additional functions other than that performed wake-up circuit. Upon exit from Power mode, ACU51 held reset state until System clock stabilized, which time reset removed. Prior entering Power mode, software Power Flag Power Status Register. This flag reset wake-up initiated reset, evaluated determine reset exit from Power mode. Power mode exited conclusion time delay programmed software into LPS1 LPS0, wake-up circuits, prior initiating Power mode. programmed time delay range from 4095 seconds second intervals. wake-up circuit operates from frequency clock, described Section 3.1.4.3, reduce circuitry power required divide down circuitry.
3.2.6.2 Minimum Functionality Requirement
ACU51 microcontroller provides following capabilities:
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Program Kbytes EEPROM (see Figures Access Kbytes Data (See Figure Timer/Counter Timer/Counter Timer/Counter Single full duplex serial UART tied four separate receive/transmit channels Single synchronous serial controller tied separate receive/transmit channels dual module Programmable Counter Array (PCA), with module containing Watchdog Reset discrete control pins, divided into ports Analog Module interface Power management interface control
3.2.6.3 ACU51 Interface
VDD: +3.3V VSDD1: Switched +3.3V VSS: Ground Port (P0.0 P0.7): Port 8-bit bi-directional port. assertion hardware reset, pins port configured inputs. Through software control, each configured either input output writing port control register within ACU51 microprocessor. pins this port accessed driven either word basis. input output characteristics CMOS levels. Port (P1.0 P1.7): Port 8-bit bi-directional port. assertion hardware reset pins port configured inputs. Through software control, each configured either input output writing port control register within ACU51 microprocessor. pins this port accessed driven either word basis. input output characteristics CMOS levels. addition, Port pins have alternate functions shown TABLE
Memory
TABLE PORT ALTERNATE FUNCTIONS
ALTERNATE FUNCTIONS External clock input Timer/Clock Timer/Counter Capture/Reload trigger direction control External count input External capture/compare Module External capture/compare Module PORT P1.0 P1.1 P1.2 P1.3 P1.4 ALTERNATE NAME T2EX CEX0 CEX1
Port (P2.0 P2.7): Port -bit bi-directional port. assertion hardware reset, pins port configured inputs. Through software control, each configured either input output writing port control register within ACU51 microprocessor. pins this port accessed driven either word basis. input output characteristics CMOS levels. Port (P3.0 P3.1 P3.6 P3.7) Four Port bi-directional pins. assertion hardware reset, these pins configured outputs driving high level. Through software control, each pins configured either input output writing port control register within ACU51 microprocessor. These pins accessed driven either word basis. input output characteristics CMOS levels. Port (P3.2 P3.5): Four Port bi-directional pins. assertion hardware reset, pins (P3.2 P3.5) port configured inputs. Through software control, each (P3.2 P3.5) configured either input output writing port control register within ACU51 microprocessor. These pins accessed driven either word basis. input output characteristics CMOS levels. addition, Port pins have alternate functions shown TABLE
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ALTERNATE FUNCTION External interrupt External interrupt External clock input Timer External clock input Timer
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TABLE PORT ALTERNATE FUNCTIONS
PORT P3.2 P3.3 P3.4 P3.5 ALTERNATE NAME INT0n INT1n
PWRENB(3:0): CMOS level outputs. These pins powered during Power mode. They provided control power external devices while operating High Power modes. pins drive used control power external circuitry also used when output desired during Power mode. These pins function ACU51 Power Enable Register SFR. pins will reset high level. ACU51PENBn: CMOS level output. This used control power ACU51 itself RAM. During Power mode, this line driven logic High level remove power ACU51 module. This function power control circuitry. PROMPENBn: CMOS level output. This used control power EEPROM. During operation this line driven logic High level remove power EEPROM module. This function ACU51 Power Enable Register SFR. ALOGPENB: CMOS level output. This used control power Analog Module. During operation this line driven logic High level place Analog Module stand This function ACU51 Power Enable Register SFR. RSTn: CMOS level input. This provides hardware reset ACU51 microcontroller. RSTn active signal held minimum clock cycles while clock operating. HXTAL1: High frequency crystal input inverting crystal amplifier. HXTAL2: Output from inverting crystal amplifier high frequency crystal. LCLK: CMOS level input. This provides clock source Frequency Clock. this clock source ACU51 internally generated clock controlled LCKENB. This clock drives wake-up circuitry during Power mode. LCKENB: CMOS level input. high level this enables LCLK frequency clock source ACU51 microcontroller. level will enable ACU51 internally generated clock source from divide down high frequency clock source. RCLCLK: Buffered frequency clock output from frequency external oscillator network. This internal accessible from ACU51 outer ring. When frequency oscillator configured, this output connected LCLK provide frequency clock source when LCKENB high level. RCLIN: Input frequency clock oscillator bugger circuit from external resistor capacitor elements. This internal accessible from ACU51 output ring. RCLMID: Driver resistor frequency external oscillator network. This internal accessible from ACU51 output ring. RCLOUT: Driver capacitor frequency external oscillator network. This internal accessible from ACU51 output ring. HCLK: CMOS level input. This provides alternate clock source High Frequency Clock. this clock source high frequency xtal controlled HCKENB. This main clock ACU51 microcontroller. This also used conjunction with RCMID RCOUT develop oscillator. RCMID: Driver resistor external oscillator network. Should left disconnected HCLK driven external clock source. RCOUT: Driver capacitor external oscillator network. Should left disconnected HCLK driven external clock source.
Memory
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HCLKOUT: General purpose clock source same frequency high frequency clock ACU51. HCLKOUT enabled setting ACU51 special function register PENB high level. reset, HCLKOUT disabled level. HCKENB: CMOS level input. high level this enables HCLK high frequency clock source ACU51 microcontroller. level enables high frequency xtal. SDOUT0: CMOS level output. Synchronous Serial data output channel Used transmit serial data synchronously with respect channel serial clock SCLK0. Both synchronous serial channels multiplexed single synchronous serial transmitter ACU51. SDIN0: CMOS level input. Synchronous Serial data input channel Used receive serial data synchronously with respect channel serial clock SCLK0. Both synchronous serial channels multiplexed single synchronous serial receiver ACU51. SCLK(0): CMOS level output. Synchronous Serial clock channel Provides time base synchronously transmit receive serial data pins SDOUT0 SDIN0 over channel Both channels multiplexed single synchronous serial receiver/transmitter ACU51. SDOUT1: Synchronous Serial data output channel Used transmit serial data synchronously with respect channel serial clock SCLK1. Both channels multiplexed single synchronous serial transmitter. SDIN1: Synchronous Serial data input channel Used receive serial data synchronously with respect channel serial clock SCLK1. Both channels multiplexed single synchronous serial receiver. SCLK1: clock that provides time base synchronously transmit receive serial data pins SDOUT1 SDIN1 over channel Both channels multiplexed single synchronous serial receiver/transmitter. SRCV(3:0): CMOS level inputs. These signals comprise four single ended CMOS receiver channels asynchronous serial channels module. They interface directly with ACU51 microcontroller multiplexed there into single UART. STRNS(3:0): CMOS level outputs. These signals comprise four single ended CMOS transmitter channels asynchronous serial UART module. These four single ended transmitter channels from ACU51 microcontroller driven from single UART, de-multiplexed drive appropriate four asynchronous serial transmitter output channels ACU. PROG: CMOS level input. PROG held high level when exiting hardware reset taken high during normal operation, ACU51 microcontroller executes instructions from internal ROM. This causes ACU51 receive serial information from serial UART channel program information into program storage space EEPROM. space, ACU51 space available down loading through same UART channel. Once entered, this mode must exited hardware reset. PROG taken high during normal operation, must remain high until hardware reset initiated. ADDR(15:0): CMOS level outputs. These signals comprise address addressing each blocks RAM. Each blocks selected RBLOCK pin. RBLOCK: CMOS level output. This signal selects high block space. ADDR(15:0) used select word within block. RBLOCK only outputs high level during writing nonvolatile data EEPROM MOVX operations. During program memory accesses, RBLOCK emits level, restricting access lower bytes program memory. logic high selects upper address space. Control this originates from CLKCON SFR. DATA(11:0): Bi-directional CMOS level I/O. These signals comprise data reading/writing external data memory (RAM Analog Module). External data memory only accessible using standard MOVX operations. DATA(11:8) interface AUXACC Special Function Register during MOVX operations. CSRAM: CMOS level output. Chip Select signal, active high level enables RAM. CSRAMn: CMOS level output. Chip Select signal, active level enables RAM. CMOS level output. Read enable signal. Normally high disable memory mapped devices from driving data bus. Logic allows addressed data drive DATA(11:0) long device selected chip select.
Memory
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CMOS level output. Write enable signal. Normally high disable writing memory mapped devices. Logic allows writing data DATA(11:0) addressed memory mapped location long device selected chip select. PADDR(15:0): CMOS level outputs. These signals comprise address addressing each blocks program EEPROM. Each blocks selected PBLOCK pin. PBLOCK: CMOS level output. This signal selects high block program storage nonvolatile data space EEPROM. PADDR(15:0) used select word within block. logic high this selects upper address space. Control this originates from CLKCON SFR. PDATA(7:0): Bi-directional CMOS level I/O. These signals comprise data reading/writing EEPROM. Reading only performed during EEPROM transfers. POENn: CMOS level output. Active control EEPROM output enable. PCEn: CMOS level output. Active EEPROM chip select. PWEn: CMOS level output. Active EEPROM write enable. RESn: CMOS level output. Active EEPROM reset pin. Must held during power reset inhibit accidental data corruption during power ALOGCLK: CMOS level output. Analog Module clock source control Analog Module digital interface circuitry conversion. ALOGCLKF(1:0): CMOS level outputs. Clock Frequency select lines provided inform Analog Module what clock frequency being provided. Internal bias conditions optimized four possible frequencies. clock frequency controlled ACON. ALOGCSn: CMOS level output. Active Chip Select allows read write access Analog module. When high level, transitions ADDR(3:0), ignored Analog Module D(11:0) tri-state. ALOGEOC: CMOS level input. Active High level Convert, signals that current Analog Module conversion complete, that data valid appropriate output registers ADCOUT(3:0). ALOGB: CMOS level input. Active high level Busy, signals that conversion progress. receipt conversion command, remains high until Analog Module completed processing.
Memory
3.2.6.4 Hardware/Software 3.2.6.4.1 Memory
ACU51 capability interface 128K bytes EEPROM 128K bytes RAM. Program execution only possible lower Kbytes space. facilitate program execution from RAM, ACU51 ability quickly copy program space from EEPROM described Section 3.2.6.4.1.5. ACU51 read write access Kbytes data space using MOVX commands. ACU51 also unique instruction called MOVN that ability write data EEPROM providing nonvolatile data storage. Read access EEPROM space available software control. However, EEPROM space down loaded each reset. Internally ACU51 contains bytes Data Memory that available user through software control. user accessible program memory resides ACU51. 3.2.6.4.1.1 Program Memory internal program memory available programmer resides ACU51. small internal preprogrammed implemented controlling special functions such EEPROM programming. Externally ACU51 capability accessing bytes program memory from RAM. Program execution always from lower bytes shown FIGURE RBLOCK only outputs high level during nonvolatile write MOVX operations. During program memory accesses, RBLOCK emits level, restricting access lower bytes program memory.
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3.2.6.4.1.2 Data memory ACU51 processor accesses 128K bytes data memory memory configuration shown FIGURE Data Memory divided into byte blocks that addressable through RBLOCK signal from ACU51. RBLOCK signal changed under program control writing CLKCON. Analog Module occupies sixteen upper address locations 1FFFFH 1FFF0H, when addressed activates chip select ALOGCSn. remainder 128K words used desired accesses activating chip select CSRAM CSRAMn. ACU51 MOVX instructions used access data memory. 8-bit MOVX operation used, external paging address register PGADDR used drive external data address lines ADDR(15:8) facilitate paging. Table shows addressing sources each MOVX operation. MOVX instruction's timing shown Figure Figure MOVX instruction designed accommodate 12-bit external data bus. During write operation, ACU51 will drive DATA(7:0) with value ACC, DATA(11:8) with value AUXACC(3:0). performing read operation from addresses 00000 through IFFEF, ACU51 will drive DATA(11:8) with value AUXACC(3:0); otherwise addresses IFFF0 through IFFFF DATA(11:8) expected driven external source. During read operations, DATA(7:0) will written ACC(7:0); AUXACC(3:0) will receive DATA(7:4), AUXACC(7:4) will receive DATA(11:8). Figure below provides graphical description data flow during MOVX read write operations.
FIGURE EXTERNAL DATA MEMORY ORGANIZATION
1FFFF 1FFF0 Analog Memory Space bytes
Memory
Data Space 128K bytes
10000
Program Space bytes 00000
NOTE: Care should taken unintentionally overwrite program space; possibility program corruption.
TABLE MOVX ADDRESS SOURCES
COMMAND MOVX MOVX DPTR MOVX MOVX DPTR, RBLOCK CLKCON CLKCON CLKCON CLKCON ADDR (15:8) PGADDR PGADDR ADDR (7:0) Internal Internal
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FIGURE MOVX READ WRITE OPERATION INSTRUCTIONS
3.2.6.4.1.3 MOVN Write External Nonvolatile Data Memory ACU51 ability store data Kbytes EEPROM during normal ACU51 operation, providing with nonvolatile data storage. Writing nonvolatile data storage (EEPROM) accomplished executing reserved 8051 opcode designated MOVN MOVe Nonvolatile. Execution this opcode causes ACU51 begin nonvolatile write routine. write routine ability write from words data from EEPROM performed single instruction call. data transferred must reside within same byte page boundary RAM. Prior call MOVN command, user must store count number words write from EEPROM Register. user must also store beginning address DPTR register block select CLKCON select correct bank EEPROM RAM. transfer commences writing word addressed DPTR from same location EEPROM. address source MOVN instruction shown TABLE DPTR register, comprised DPL, provides base address EEPROM nonvolatile write driving address buses ADDR(15:0) PADDR(15:0). CLKCON drives ACU51 outputs RBLOCK PBLOCK. These outputs provide block address select choose either upper lower blocks EEPROM. RBLOCK only outputs high level during nonvolatile write MOVX operations. During program memory accesses, RBLOCK emits level, restricting access lower bytes program memory.
Memory
TABLE NONVOLATILE DATA WRITE ADDRESSES
DEVICE DRIVEN EEPROM CLKCON (MSB) RBLOCK PBLOCK ADDR(15:8) PADDR(15:8) (LSB) ADDR(7:0) PADDR(7:0)
Prior writing nonvolatile data memory, software control must guarantee that EEPROM powered checking that PROM PENB high level. MOVN instruction requires DPTR Register perform nonvolatile write operation. data contained these locations should saved prior executing MOVN command. Reading nonvolatile memory through software control possible. Access only available after reset exit from power mode which time EEPROM automatically transferred space. After this transfer, data accessed using MOVX MOVC commands. MOVC limited access program space. 3.2.6.4.1.4 EEPROM Programming Mode EEPROM programmable through external connections ACU. exits hardware reset with PROG held high level PROG taken high (PROG must thereafter remain high during operation), enters EEPROM programming mode. this mode ACU51 microcontroller controlled from internal ROM. internal causes ACU51 access data through asynchronous UART channel programming source responsible furnishing external clock permitting communication established standard baud rate.
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Typically, programming source provides clock 11.059 permit communication 14.4 Kbaud. Data received blocks ranging from program data words. Each block consists header section data section sent external programmer. ACU51 will configure asynchronous (UART) interface 14,400 baud when external high frequency clock 11.059 MHz. test purposes; baud rate will 345,593.75 baud with external high frequency clock 11.059 MHz. After baud rate set, ACU51 shall transmit request command word external programmer over asynchronous UART channel This instructs programmer that ACU51 ready receive header section. header section consists four following words: Command word: This first word received. command word provides control ACU, directing which block EEPROM data stored, whether data stored read back space, ACU51 data space performed. command word format defined TABLE Address: (Sent only command word This second word received. most significant word 16-bit address where first data word sent stored. Address: (Sent only command word This third word received. least significant word 16-bit address where first data word sent stored. Data Count Word: (Sent only command word This fourth last word header section received. This word specifies word count from words transferred data section. word count specified least significant bits. signifies word, signifying words value signifies words. (bit command word provides 17th address define which block EEPROM that data stored logic high this bit, addresses upper 64K, logic lower 64K. (bit command word defines command executed ACU51. this logic low, ACU51 expects receive full header section data transfer from external programming circuitry stored EEPROM. logic high, evaluates command word follows: logic low, ACU51 writes entire contents Data space asynchronous UART channel transfer will begin with address continue address 1FFFFh space. read back, ACU51 will transmit request command word then await command. logic high, ACU51 will write contents ACU51 special function registers (SFRs), then internal data space asynchronous UART channel transfer will begin with address write used SFRs address FBh, order incrementing address. Next, shall transfer internal space starting with address continue until address ACU51 space transferred. ACU51 read back, ACU51 shall transmit request command word then await command.
Memory
TABLE PROGRAMMING COMMAND WORD
Command Word Symbol Function Block address bit: lower 64K; upper Command Bit: Data transfer program; Data read back Source bit: Read back contents RAM, Read back contents ACU51 SFRs Signifies used
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data section consists minimum word maximum words specified fourth word header. first data word received saved address specified header. second word received saved address first word plus This continues maximum data words. After data words received, ACU51 will automatically write them EEPROM, then transmit request command word 55h. ACU51 will then await command word from programmer. TABLE shows programming word sequence.
TABLE PROGRAMMING WORD SEQUENCE
WORD RECEIVED 132nd WORD FUNCTION Command Word Address Word Address Word Data Count Word First Data Word Second through 128th data word. Optional, dependent upon Data Count Word
Data read back requires that hardware reset performed between programming data EEPROM executing command read data back. exit hardware reset with PROG allows down load EEPROM RAM. Reading back data from checks both programming operation EEPROM transfer operation. PROG taken high level during reset instruct enter Programming mode immediately after EEPROM transfer without executing user programs from RAM. Additionally, PROG taken high level during normal operation that data SFRs monitored during system software debug. Once Programming mode entered, hardware reset required exit 3.2.6.4.1.6 EEPROM Shadow Transfer ACU51 provides ability transfer contents EEPROM RAM. This transfer performed exit from reset exit from power mode. transfers contents EEPROM RAM. transfer under hardware control with ability cancel initiate through software control. transfer provides ability mission critical data stored EEPROM restored event system power outage powered down during Power mode. 3.2.6.4.1.6 Internal Data Memory ACU51 implements bytes internal data RAM. upper bytes this occupy parallel address space Special Function Registers (SFRs). determines internal access address above upper bytes space addressing mode instruction. direct addressing used, access space. indirect addressing used, access internal RAM. Stack operations indirectly addressed upper portion used stack space. FIGURE shows organization internal Data Memory. first bytes reserved four register banks bytes each. processor uses four banks working registers depending bits Special Function Register. reset, bank selected. four register banks required, unused banks used general purpose scratch memory. next bytes (128-bits) individually addressable. remaining bytes byte addressable used general purpose scratch memory. addresses either direct indirect addressing used. addresses larger than 7FH, only indirect addressing used. Direct addressing used access addresses higher than 7FH, accesses ACU51 Special Function Register (SFR) space.
Memory
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Bytes Indirect Access Only Direct Indirect Access
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
FIGURE INTERNAL DATA MEMORY ORGANIZATION
ADDRESSABLE SEGMENT SCRATCH AREA
Memory
REGISTER BANKS
3.2.6.4.2 Special Function Registers
TABLE contains Special Function Register (SFR) memory map. Unoccupied addresses implemented chip. Read accesses these addresses returns unknown values write access effect.
TABLE MEMORY RESET VALUES
00000000 CLKCON 00000000 00000000 CCON 00XXXX00 00000000 T2CON 00000000 PENB 0X111111 T2MOD XXXXXX00 LPS0 00000000 RCAP2L 00000000 LPS1 00000000 RCAP2H 00000000 00000000 00000000 00000000 AUXACC 00000000 CMOD 00XXX000 CCAPM0 X0000000 CCAPM1 X0000000 CCAPM2 CCAPM3 CCAPM4 CCAP0L XXXXXXXX CCAP1L XXXXXXXX CCAP2L CCAP3L CCAP4L 00000000 CCAP0H XXXXXXXX CCAP1H XXXXXXXX CCAP2H CCAP3H CCAP4H
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X0000000 11000000 00000000 0000000 SCON 00000000 00000000 TCON 00000000 00000000 SADDR 00000000 PGADDR 00000000 SBUF XXXXXXXX P0CON 00000000 TMOD 00000000 00000111 SSCON 00000000 P1CON 00000000 00000000 00000000 SSBUF XXXXXXXX P2CON 00000000 00000000 00000000 SADEN 00000000
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
TABLE MEMORY RESET VALUES
X0000000 P3CON 11000011 00000000 MCLK0 00000000 00000000 MCLK1 XXX00000 SELFTEST 00000000 PCON 00XX0000 Removed Modified
Memory
Note: Values shown reset values registers. undefined. Each register groups described individually following sections.
3.2.6.4.2.1 Accumulator Address addressable, Reset value 00000000 accumulator register. instructions with accumulator specific mnemonics refer accumulator 3.2.6.4.2.2 Auxiliary Accumulator AUXACC Address addressable, Reset value 00000000 AUXACC extended accumulator register. MOVX read write operations Analog Module address space uses AUXACC data storage four most significant bits word. 3.2.6.4.2.3 Register Address addressable, Reset value 00000000 register used during multiply divide operations. other instructions, used another scratch register. 3.2.6.4.2.4 Stack Pointer Address 81H, addressable, Reset value 00000111 stack pointer (SP) 8-bit register. incremented before data stored during PUSH CALL instructions. reset, initialized 07H, causing default stack begin location 08H.
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3.2.6.4.2.5 Data Pointer Address 82H, addressable, Reset value 00000000 Address addressable, Reset value 00000000
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
Data Pointer (DPTR) consists 8-bit registers, DPH. intended hold 16-bit address used single 16-bit register independent 8-bit registers. value found DPTR register output 16-bit address external Data Memory Accesses during MOVX @DPTR instructions, MOVN instructions, EEPROM programming. drives order address pins ADDR(7:0) PADDR(7:0) drives high order address pins ADDR(15:8) PADDR(15:8). 3.2.6.4.2.6 Program Status Word Address D0H, addressable, reset value 00000000 Program Status Word (PSW) register contains program status information shown TABLE
TABLE PROGRAM STATUS WORD DEFINITION
Addressable Symbol Function Carry flag Auxiliary Carry flag (for operation) Flag (General purpose flag) Register bank select Register bank select Overflow flag User definable flag Parity flag. Set/cleared hardware each instruction cycle indicate odd/even number 1-bits accumulator (set even parity) Working Register Bank Select Bank (00-07) Bank (08-0F) Bank (10-17) Bank (18-1F) Address Reset Value 0000 0000
Memory
3.2.6.4.2.7 Ports Registers Address 80H, addressable, Reset value 00000000 Address 90H, addressable, Reset value 00000000 Address A0H, addressable, Reset value 00000000 Address B0H, addressable, Reset value 11000000 latches Port Port Port Port respectively.
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ADVANCED CONTROL UNIT MULTI-CHIP MODULE
four ports ACU51 bi-directional. Each consists latch (SFR through P3), output driver, input buffer. Directionality port controlled port control found SFRs P0CON, P1CON, P2CON, P3CON. ports initiation hardware reset configured inputs except P3(7:6) P3(1:0) which configured outputs driving logic low. ports remain this configuration until otherwise configured software through their port control register P0CON, P1CON, P2CON, P3CON. Some Port Port pins multi-functional. They only port pins also serve functions various special features listed TABLE alternate functions these pins only activated corresponding port contains logic Otherwise, port stuck when port configured output.
TABLE ALTERNATE PORT FUNCTIONS
PORT P1.0 P1.1 P1.2 P1.3 P3.2 P3.3 P3.4 P3.5 ALTERNATE NAME T2EX CEX0 INT0n INT1n ALTERNATE FUNCTION External clock input timer/clock Timer/Counter Capture/Reload trigger direction control External count input External count input External interrupt External interrupt
Memory
External clock input Timer External clock input Timer
3.2.6.4.2.8 Ports Control Registers P0CON Address 91H, addressable, Reset value 00000000 P1CON Address 92H, addressable, Reset value 00000000 P2CON- Address 93H, addressable, Reset value 00000000 P3CON Address 94H, addressable, Reset value 11000011 P0CON, P1CON, P2CON, P3CON port directionality control registers Port Port Port Port respectively. control register configures respective port input pin, output. pins except P3(7:6) P3(1:0) configured inputs initiation hardware reset, must configured outputs through software control. 3.2.6.4.2.9 External Paging Address Register PGADDR Address A1H, addressable, Reset value 00000000 PGADDR drives external address lines ADDR(15:8) when executing 8-bit MOVX operation (MOVX@Ri). this manner PGADDR used page external data memory byte blocks. 3.2.6.4.2.10 Timer Registers Address 8CH, addressable, Reset value 00000000 Address 8AH, addressable, Reset value 00000000 Address 8DH, addressable, Reset value 00000000 Address 8BH, addressable, Reset value 00000000 Address CDH, addressable, Reset value 00000000 Address CCH, addressable, Reset value 00000000 TCON Address 88H, addressable, Reset value 00000000 TMOD Address 89H, addressable, Reset value 00000000 T2CON Address C8H, addressable, Reset value 00000000
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T2MOD Address C9H, addressable, Reset value XXXXXX00 RCAP2H Address CBH, addressable, Reset value 00000000 RCAP2L Address CAH, addressable, Reset value 00000000
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
There twelve timer/counter SFRs. Register pairs (TH0, TL0), (TH1, TL1), (TH2, TL2) 16-bit count registers Timer/Counter respectively. Timer control status bits contained TCON TMOD. Timer control status contained T2CON T2MOD. register pair (RCAP2H, RCAP2L) capture/reload registers Timer 16-bit capture 16-bit auto-reload modes. ACU51 contains three 16-bit timer/counters. Each these made 8-bit registers (THx, where Each these three operate either timer counter mode. timer mode, register incremented once every machine cycle oscillator periods). count rate 1/12th oscillator frequency. counter mode, register incremented when transition detected alternate function input corresponding that timer where maximum rate count counter mode that ACU51 detect 1/24th oscillator frequency. 3.2.6.4.2.10.1 Timer Timer While operating either timer counter, timers both have four modes operation (Modes Modes same both timer/counters. mode operation different timer/counters. mode selected bits each timer TMOD register. Timers always configured counters. either Timer/Counter selected operation mode timer register configured 13-bit timer/counter. 13-bits contained 8bits with lower 5-bits prescaler. upper 3-bits indeterminate should ignored. mode selected, timer/counter configured 16-bit timer/counter. cascaded. mode selected, timer configured 8-bit timer/counter with 8-bit auto-reload value. contains timer contains reload value that used each time rolls over from changed when value loaded. mode selected Timer configured separate 8-bit counters. uses timer control bits: C/T, GATE, TR0, TF0, external inputs INT0. required timer mode uses Timer control bits TF1. mode selected Timer hold their present count. TMOD TCON SFRs provide control status Timer Timer TABLE shows definition TMOD SFR. TABLE shows definition TCON register.
Memory
TABLE TMOD REGISTER DEFINITION
TMOD Address Addressable Timer GATE Symbol GATE C/Tn Function Gating Control when set. Timer/Counter enabled only when INT0n INT1n input high control set. When cleared, Timer/Counter enabled whenever control set. Timer Counter selector. Clear timer operation (input from internal system clock). counter operation (input from pin). Mode select C/Tn GATE C/Tn Timer Reset Value 0000 0000
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Mode select Operating Mode
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
TABLE TMOD REGISTER DEFINITION
13-bit timer/counter. with 5-bit prescaler. 16-bit timer/counter. cascaded. 8-bit auto-reload timer/counter. contains value loaded into when overflows. Timer -TL0 8-bit timer/counter controlled Timer control bits. 8-bit timer only controlled Timer control bits. Timer Timer/counter halted.
TABLE 22.TCON REGISTER DEFINITION
TCON Address Addressable Symbol Function Reset Value 0000 0000
Memory
Timer overflow flag. hardware timer/counter overflow. Cleared hardware when processor vectors interrupt service routine. Timer control bit. Set/cleared software turn timer/counter off. Timer overflow flag. hardware timer/counter overflow. Cleared hardware when processor vectors interrupt service routine. Timer control bit. Set/cleared software turn timer/counter off. Interrupt flag. hardware when external interrupt edge detected (transition level activated). Cleared hardware only transition activated. Interrupt type control bit. Set/cleared software specify falling edge/level triggered external interrupt. Interrupt flag. hardware when external interrupt detected (transition level activated). Cleared hardware only transition activated Interrupt type control bit. Set/cleared software specify falling edge/level triggered external interrupt
3.2.6.4.2.10.2 Timer Timer operate either timer event counter. Timer four modes operation (Capture, Auto-Reload, Baud Rate Generator, Clock-out). TABLE shows operating modes Timer selected using bits T2CON T2MOD register.
TABLE TIMER OPERATING MODES
RCLK TCLK CP/RL2n T2OE MODE 16-bit Auto-reload 16-bit Capture Baud Rate Generator Clock-out P1.0 Timer
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ADVANCED CONTROL UNIT MULTI-CHIP MODULE
capture mode, timer 16-bit timer counter which causes T2CON overflow. EXEN2 T2CON register set, values registers transferred RCAP2H RCAP2L registers when transition detected T2EX alternate function input (P1.1). transition also causes EXF2 T2CON register set. auto-reload mode, Timer down counter. direction count controlled DCEN T2MOD. DCEN timer counts Timer count down depending state T2EX alternate function input (P1.1). counter configured counter (DCEN DCEN T2EX counts then sets T2CON reloads value found RCAP2H RCAP2L registers. EXEN2 TCON then transition T2EX input also causes timer reload EXF2 TCON. DCEN T2EX timer counts down. timer underflows when equal values found RCAP2H RCAP2L respectively. underflow sets causes timer reloaded baud rate generator mode discussed serial port Section 3.2.6.4.4.2.4. selected setting RCLK and/or TCLK bits T2CON. clock-out mode, Timer used generate duty cycle clock alternate output port (P1.0). frequency this clock output programmed from with oscillator following equation: Clock-out Frequency Oscillator Frequency (65536 RCAP2H, RCAP2L) clock-out mode Timer rollovers T2CON.
Memory
T2MOD T2CON SFRs provide control status Timer TABLE shows definition T2MOD register. TABLE shows definition T2CON register.
TABLE T2MOD REGISTER DEFINITION
T2MOD Addressable Symbol T2OE DCEN Function implemented. Timer Output Enable bit. Set/cleared software enable/disable Timer clock output. Down Count Enable. When set, Timer configured up/down counter depending value T2EX input. When cleared, timer counter only. T2OE DCEN Address Reset Value XXXX XX00
TABLE T2CON REGISTER DEFINITION
T2CON Addressable Symbol EXF2 Function Timer overflow flag Timer overflow must cleared software. when either RCLK TCLK Timer external flag when either capture reload caused negative transition T2EX EXEN2 Must cleared software. Does cause interrupt DCEN
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Address EXF2 RCLK TCLK EXEN2
Reset Value 0000 0000 C/T2n CP/RL2n
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RCLK TCLK EXEN2 C/T2n CP/RL2n
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
TABLE T2CON REGISTER DEFINITION
Receive clock control. Set/cleared software enable/disable timer overflow receive clock serial port modes Transmit clock control. Set/cleared software enable/diable timer overflow transmit clock serial port modes Timer external enable control. Set/cleared software enable/disable external input T2EX. When site, allows capture compare occur falling transition T2EX. Timer control bit. Set/cleared software turn timer/counter off. Timer counter selector. Clear timer operation (input from internal system clock). timer operation (input from T2EX pin). Capture/Reload flag. When set, captures occur falling transitions T2EX EXEN2 When cleared, auto-reloads occur either with Timer overflows falling transitions T2EX EXEN2 When either RCLK TCLK this ignored timer forced auto-reload Timer overflow.
3.2.6.4.2.11 Programmable Counter Array Registers Address F9H, addressable, Reset value 00000000 Address E9H, addressable, Reset value 00000000 CCON Address D8H, addressable, Reset value 00XXXX00 CMOD Address D9H, addressable, Reset value 00XXX000 CCAPM0 Address DAH, addressable, Reset value X0000000 CCAPM1 Address DBH, addressable, Reset value X0000000 CCAP0H Address FAH, addressable, Reset value XXXXXXXX CCAP0L Address EAH, addressable, Reset value XXXXXXXX CCAP1H Address FBH, addressable, Reset value XXXXXXXX CCAP1L Address EBH, addressable, Reset value XXXXXXXX Programmable Counter Array (PCA) timer/counter consists registers Registers CCON CMOD contain control status bits PCA. CCAPMx registers control mode each five modules. register pairs (CCAPxH, CCAPxL) compare/capture registers each PCA.
Memory
3.2.6.4.3 Timer/Counter
contains single 16-bit counter/timer made SFRs. This timer used both capture/compare modules. clock input programmed from four sources. These oscillator frequency divided oscillator frequency divided Timer overflow, external clock input, ECI, alternate function port P1.2. selection clock controlled CPS0 CPS1 bits CMOD Special Function Register. TABLE shows definitions CMOD register.
TABLE CMOD REGISTER DEFINITIONS
CMOD Address Addressable CIDL Symbol CIDL WDTE CPS1
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Reset Value 00XX X000 WDTE CPS1 CPS0
Function Counter Idle Control. When cleared counter continues count during Idle mode operation. When counter halts while processor Idle mode. Watchdog timer enable. Set/cleared software enable/disable watchdog timer mode Module implemented. Count Pulse Select
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CPS0 Count Pulse Select CPS1 CPS0 Selected Input Internal clock, 1/12 oscillator frequency. Internal clock, oscillator frequency. Timer overflow
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
TABLE CMOD REGISTER DEFINITIONS
External clock (P1.2) input. (max rate oscillator frequency)
Enable counter overflow flag. Set/cleared software enable/disable counter overflow interrupt (CF).
CCON register used halt start Timer Counter. CCON register also contains interrupt flags PCA. Table shows definitions CCON register.
TABLE CCON REGISTER DEFINITIONS
CCON Addressable Symbol CCF1 CCF0 Function counter over flag. hardware when counter rolls over. Must cleared software. Generates interrupt set. counter control bit. Set/cleared software start/halt counter. implemented. module interrupt flag. hardware when match capture occurs. Must cleared software. Generates interrupt ECCF1 CCAPM1. module interrupt flag. hardware when match capture occurs. Must cleared software. Generates interrupt ECCF0 CCAPM0. CCF1 CCF0 Address Reset Value 00XX XX00
Memory
3.2.6.4.4 Capture Compare Modules
contains 16-bit capture compare modules made CCAPxL CCAPxH SFRs. Each modules functions perform: 16-bit capture rising edge CEXx alternate function input. 16-bit capture falling edge CEXx alternate function input. 16-bit capture rising falling edge CEXx alternate function input. 16-bit software timer. 16-bit high speed output CEXx alternate function output. 8-bit pulse width modulator CEXx alternate function output. addition, module used watchdog timer provide chip reset terminal count reached. modules programmed combination modes. Each module mode register called CCAPMx select operating mode that module. TABLE shows definitions CCAPMx SFRs. TABLE shows combinations bits mode register each operating modes. Combinations other than ones shown TABLE produce undefined results.
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CCAPMx Address Addressable Symbol ECOMx CAPPx CAPNx MATx TOGx. PWMx ECCFx Function implemented. ECOMx CAPPx CCAPM0 CCAPM1
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
TABLE CCAPMX DEFINITIONS
Reset Value X000 0000
CAPNx
MATx
TOGx
PWMx
ECCF
Enable comparator. Software sets/clears this enable/disable comparator function. Capture positive. Software sets this enable capture positive edge CEXx input. Capture negative. Software sets this enable capture negative edge CEXx input. Match. When software sets this bit, match counter with Module capture/compare register sets CCFx CCON, flagging interrupt. Toggle. When software sets this bit, match counter with Module capture/compare register causes CEXx toggle opposite state. Pulse width modulation mode. When this set, CEXx 8-bit pulse width modulated output. Enable interrupt. Enables CCFx CCON generate interrupt.
Memory
TABLE MODULE MODES
don't care. ECOM CAPP CAPN EECF MODULE FUNCTION operation 16-bit capture positive edge CEXx 16-bit capture negative edge CEXx 16-bit capture either edge CEXx 16-bit software timer 16-bit high speed output 8-bit pulse width modulator Watchdog timer (Module only)
When module capture mode, monitors CEXx alternate function input appropriate transition (rising edge, falling edge, either edge). When transition detected, value Timer/Counter (CH, transferred module Capture/Compare Register (CCAPxH, CCAPxL). When capture made, module event flag (CCFx) CCON SFR. ECCF module Mode Control Register (CCAPMx), interrupt generated. CCFx cleared hardware. more than transition detected before capture/compare register read, value from first capture lost. When module software timer mode (ECOM CCAPMx set), 16-bit value Timer Counter (CL, compared with 16-bit value pre-loaded module Capture/Compare Register (CCAPxH, CCAPxL). When match occurs, module event flag (CCFx) CCON CCAPMx register. ECCF CCAPMx set, interrupt generated processor. Software must clear event flag. When changing compare value, byte (CCAPxL) should written first, followed high byte (CCAPxH). Writing byte
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ADVANCED CONTROL UNIT MULTI-CHIP MODULE
clears ECOM CCAPMx invalid matches made. Writing high byte (CCAPxH) automatically sets ECOM enabling comparator. high speed output mode, CEXx alternate function output toggled each time match occurs between Timer/Counter (CH, module Capture/Compare Register (CCAPxH, CCAPxL). this mode, ECOM, MAT, bits must module Mode Register (CCAPMx). setting clearing CEXx output software, user control direction transition that happens when match occurs. Again, byte compare value (CCAPxL) should written first, followed high byte (CCAPxH). pulse width modulator mode, module generates 8-bit comparing byte Timer/Counter (CL) with byte module compare register (CCAPxL). When less than CCAPxL, CEXx alternate function output low. When greater than equal CCAPxL, CEXx output high. When rolls over from value found high byte Capture/Compare register (CCAPxH) loaded into byte same register. This way, values changed without producing glitches output. value needs written CCAPxH loaded next time rolls over. CCAPxH written with integer from giving duty cycle range 100% 0.4% increments 0.4%. When mode, module does generate interrupts. addition modes described above, Module watchdog timer sending reset entire chip timer times out. This done setting WDTE CMOD with Module either software timer high speed output mode. There three ways hold reset. Periodically change compare value match will never occur between Timer Compare Register. Periodically change Timer value will never match Compare Register Value. Clear WDTE CMOD before match occurs, then re-enable after Timer passes compare value. first method generally most reliable provides most flexibility when using other modules PCA. 3.2.6.4.4.1 Synchronous Serial Interface 3.2.6.4.4.1.1 Synchronous Serial Port Registers SSBUF Address 9BH, addressable, Reset value XXXXXXXX SSCON Address 9AH, addressable, Reset value 00000000 Synchronous Serial Data Buffer (SSBUF) physically separate receive buffer transmit buffer registers. When data moved SSBUF, goes transmit buffer. When data moved from SSBUF, comes from receive buffer. SSCON, shown TABLE provides control synchronous serial port interface. This register contains interface control synchronous serial interrupt flags that logically ORed interrupt flags asynchronous serial interface.
Memory
TABLE SSCON DEFINITIONS
SSCON Addressable RSEL1 Symbol RSEL1 Function Receiver channel select RSEL0 TSEL1 TSEL0 SSEL SREN Address Reset Value 0000 0000
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RSEL0 Receiver channel select RSEL1 TSEL1 TSEL0 RSEL0 Channel
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
TABLE SSCON DEFINITIONS
Transmitter channel select Transmitter channel select TSEL1 TSEL0 Channel
SSEL SREN
Synchronous serial channel select. SSEL selects channel SSEL selects channel Enables synchronous serial reception. software enable reception. Clear software disable reception. Reception starts only SREN Synchronous serial transmit interrupt flag. hardware time. Must cleared software. Synchronous serial receive interrupt. hardware time Mode Must cleared software.
Memory
3.2.6.4.4.1.2 Synchronous Serial Operation Synchronous Serial Interface consists channels that provide transmit/receive capability. Both channels interface single synchronous serial controller, with selection active channel controlled through SSEL SSCON. Only channel active time, each channel capability transmission reception. baud rate interface fixed 1/12th selected clock rate ACU51. Channel selection provided SSEL SSCON, with SSEL selecting channel SSEL selecting channel Channel zero default reset. Both channels consist clock, data-out, data-in pins that single-ended (unbalanced) non-terminated. voltage swing pins CMOS levels. Interface operate modes operation time: Transmit mode: Transmission initiated instruction that uses SSBUF destination register. full instruction cycle after write SSBUF, transmission data bits commences (LSB first) baud rate 1/12th current ACU51 clock rate. SCLK normally high, drops from S3P1 till S6P1 each transferred. S6P2 each data transfer, SDOUT updated with data bit. (MSB) transfer, signifying completion transfer SDOUT transitions high. Reception mode: Reception initiated condition SREN Either SREN control start transfer. Reception data bits (LSB first) fixed baud rate 1/12th current ACU51 clock rate instruction cycle after above conditions true. SCLK normally high, drops from S3P1 till S6P1 each transferred. Data expected valid ACU51 clock cycle prior rising edge SCLK S6P1. reception (MSB) signifying completion. synchronous serial interrupt flags logically ORed with asynchronous serial interrupt flags create single serial interrupt. initiation serial interrupt, software must verify initiated interrupt clear appropriate flag. level block diagram interface shown FIGURE with associated timing shown FIGURE 3.2.6.4.4.2 Asynchronous Serial Interface
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3.2.6.4.4.2.1Asynchronous Serial Port Registers SCON Address 98H, addressable, Reset value 00000000 SBUF Address 99H, addressable, Reset value XXXXXXXX SADDR Address A9H, addressable, Reset value 00000000 SADEN Address B9H, addressable, Reset value 00000000
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
Asynchronous Serial Data Buffer (SBUF) physically separate receive buffer transmit buffer registers. When data moved SBUF, comes transmit buffer. When data moved from SBUF, comes from receive buffer. Registers SADDR SADEN used define Given Broadcast addresses Automatic Address Recognition. Register SCON, shown TABLE contains control status bits asynchronous serial interface. SCON multiplexed SMOD0 PCON. SMOD0 then access SCON accesses SM0, SM1, SM2, REN, TB8, RB8, order LSB. SMOD0 then access SCON accesses instead SM0. asynchronous interrupt flags logically ORed with synchronous interrupt flags provide overall serial interrupt.
TABLE SCON REGISTER DEFINITION
SCON Addressable SMOD0 SMOD0 Symbol Function Asynchronous Serial port mode Asynchronous Serial port mode Mode Description 8-bit UART 8-bit UART 9-bit UART 9-bit UART Baud Rate 1/64 1/32 oscillator frequency variable 1/64 1/32 oscillator frequency variable Address Reset Value 0000 0000
Memory
Enables automatic address recognition. modes then unless received data (RB8) data byte received Given Broadcast address. Receive enable. Set/cleared software enable/disable data reception. Transmit data that transmitted Modes cleared software desired. Receive Modes data that received. Mode value stop that received. Transmit interrupt flag. hardware beginning stop modes, serial transmission. Must cleared software. Receive interrupt. hardware halfway through stop time modes (except SM2). Must cleared software. Framing error bit. This hardware when invalid stop received. This reset hardware valid stop seen after been set. This must cleared software.
3.2.6.4.4.2.2Asynchronous Serial Operation Asynchronous Serial Interface consists four transmit four receive channels that directly interfaces ACU51 microcontroller (see FIGURE level block diagram). four receive channels multiplexed single UART selected receive channel selects, RSEL1 RSEL0 found SSCON. four transmit channels de-multiplexed from same single UART drive transmit channel selected transmit channel selects, TSEL1 TSEL0 found SSCON. Only receive transmit channel combination active time, with combination allowable.
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ADVANCED CONTROL UNIT MULTI-CHIP MODULE
power constraints, RS-232 RS-422 levels prohibitive interface levels CMOS levels. four channels follows modified RS-232 standard; being single-ended (unbalanced), non-terminated line that voltage swing between CMOS logic levels. Each asynchronous serial interface transmit receive data software programmable formats; 8-bit data transfers shown FIGURE 9-bit data transfers shown FIGURE Each these data formats also baud rate determined oscillator frequency variable baud rate determined timer counters providing total four possible modes operation. time, active transmit receive channels same mode. asynchronous serial port automatically performs framing error detection serial data frames that received. message received that does have valid stop bit, SCON set. cleared subsequent valid frame should cleared software. asynchronous serial interface operate following modes operation time: Mode bits transmitted through channels STRANS(3:0), received from input channels SRCV(3:0). bits are: start (value data bits (LSB first), stop (value receive, stop goes SCON. baud rate this mode determined SMOD1 PCON. SMOD1 high, baud rate 1/32nd oscillator frequency. SMOD1 low, baud rate 1/64th oscillator frequency. Transmission initiated instruction that uses SBUF destination register. going start followed eight data bits high stop completes transfer. interrupt flag, signal completion transfer. Reception enabled setting SCON. Reception initiated detected 1-to-0 transition selected SRCV channel. When transmission detected, divide-by-16 counter reset aligning rollover counter incoming boundaries. Data sampled three times counter states data accepted that which seen least samples providing noise rejection. value accepted during first time receive circuits reset receiver goes back looking 1-to-0 transition. This provide rejection false start bits. reception, SBUF loaded with data word, receives stop bit, only following conditions apply: Either received stop either these conditions met, received word irretrievably lost. this time, receiver goes back looking 1-to0 transition start data frame. Mode identical mode except baud rate variable based either timer timer more information baud rate generation Section 3.2.6.4.4.2.4. Mode Eleven bits transmitted through channels STRANS(3:0), received from input channels SRCV(3:0). bits are: start (value data bits (LSB first), stop (value reception, data goes SCON. transmission, data comes from SCON. baud rate this mode determined SMOD1 PCON. SMOD1 high, baud rate 1/32nd oscillator frequency. SMOD1 low, baud rate 1/64th oscillator frequency. Transmission initiated instruction that uses SBUF destination register. going start followed nine data bits high stop completes transfer. interrupt flag signal completion transfer. Reception enabled setting SCON. Reception initiated detected 1-to-0 transition selected SRCV channel. When transmission detected, divide-by-16 counter reset aligning rollover counter incoming boundaries. Data
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Memory
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©1999 Space Electronics Inc. rights reserved.
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
sampled three times counter states data accepted that which seen least samples providing noise rejection. value accepted during first time receive circuits reset receiver goes back looking 1-to-0 transition. This provide rejection false start bits. reception, SBUF loaded with bits, receives data bit, only following conditions apply: Either received data either these conditions met, received word irretrievably lost. this time receiver goes back looking 1to-0 transition start data frame. Mode identical mode except baud rate variable based either timer timer more information baud rate generation Section 3.2.6.4.4.2.4. 3.2.6.4.4.2.3 Serial Port Automatic Address Recognition Automatic address recognition with serial port uses SADEN SADDR SFRs. enabled setting SCON SFR. modes with set, serial port generates receive interrupt only there valid stop received byte equals Given Broadcast Address. Given address Broadcast address defined values loaded SADEN SADDR registers. value SADDR ACU51 serial port address. value SADEN defines don't care bits SADDR. SADEN position indicates that SADDR don't care used when address recognition check performed. SADDR value with don't care bits inserted Given address. SADEN contains 0's, bits Given address don't care serial port interrupts received byte with valid stop bit. SADEN contains Given address same SADDR serial port interrupts received byte same value SADDR valid stop bit. Broadcast address logical SADDR SADEN, with being don't cares result. serial port interrupts response either Broadcast Given address byte being received. automatic address recognition works same modes except serial port examines received rather than looking valid stop bit. byte matches Given Broadcast address, receive interrupt generated. Otherwise, action taken. modes validity stop checked framing error (FE) SCON SFR. 3.2.6.4.4.2.4 Baud Rate Generation baud rate modes depend value SMOD1 PCON register. SMOD1 frequency 1/64 oscillator frequency. SMOD1 frequency 1/32 oscillator frequency. baud rate modes determined Timer overflow rate, Timer overflow rate, both (one receive, transmit). Timer used receive transmit, both TCLK RCLK bits T2CON must cleared baud rate asynchronous serial port with Timer controlled SMOD1 PCON register. SMOD1 baud rate 1/32 Timer overflow rate. SMOD baud rate 1/16 Timer overflow rate. timer configured timer counter three running modes. Timer selected baud rate generator transmit, receive both. selection controlled RCLK TCLK bits T2CON SFR. When either bits corresponding portion asynchronous serial port uses Timer baud rate generator. When either these bits corresponding portion asynchronous serial port uses Timer baud rate generator. baud rate modes using Timer 1/16th Timer overflow rate. Timer configured either timer counter operation. When operating timer mode with RCLK and/or TCLK set, timer updated oscillator frequency rather than 1/12. Reads writes timer counter (TH2, TL2) capture/reload register (RCAP2H, RCAP2L) should performed while timer running this mode invalid reads, writes, reloads could occur. Also, timer does generate interrupts when timer rolls over when being used baud rate generator. Also, EXEN2 T2CON, transition T2EX alternate input (P1.1) does cause reload timer However, EXF2 still T2CON transition used generate external interrupt.
0916.99Rev0
Memory
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
3.2.6.4.4.3 Interrupt Registers Address A8H, addressable, Reset value 00000000 Address B8H, addressable, Reset value X0000000 Address B7H, addressable, Reset value X0000000
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
There seven interrupt sources ACU51. external interrupts INT0n, INT1n, three timer interrupts Timer Timer Timer2, interrupt, serial port interrupt. Interrupt Enable (IE) register contains individual interrupt enable bits each sources along with global enable bit. TABLE shows definitions SFR. interrupt priority registers IPH) four priorities each seven interrupts. TABLE TABLE show definitions SFRs, respectively. During Power Down mode, Power Counter enabled, PDENB LPS1 SFR, terminal count provide interrupt Power Down mode. With PDENB set, Power Counter terminal count logically ORed with external interrupt INT0n during power down mode.
TABLE DEFINITION
Addressable Address Reset Value 0000 0000
Memory
Enable enables interrupt Enable disables interrupt Symbol Function Global interrupt diable. cleared, interrupts disabled. set, each interrupt individually enabled disabled setting clearing corresponding enable bit. interrupt enable. Timer interrupt enable. Serial port interrupt enable. Timer interrupt enable External interrupt enable. Timer interrupt enable. External interrupt enable.
TABLE DEFINITION
Addressable Symbol Function implemented. interrupt priority bit. Timer interrupt priority bit. Address Reset Value X000 0000
0916.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
Serial port interrupt priority bit. Timer interrupt priority bit. External interrupt priority bit. Timer interrupt priority bit. External interrupt priority bit.
ADVANCED CONTROL UNIT MULTI-CHIP MODULE
TABLE DEFINITION
TABLE DEFINITION
Address Addressable Symbol PPCH PT2H PT1H PX1H PT0H PX0H Function implemented. interrupt priority high bit. Timer interrupt priority high bit. Serial port interrupt priority high bit. Timer interrupt priority high bit. External interrupt priority high bit. Timer interrupt priority high bit. External interrupt priority high bit. PPCH PT2H PT1H PX1H PT0H PX0H Reset Value X000 0000
Memory
Table shows priorities based values registers.
TABLE PRIORITY LEVEL VALUES
PRIORITY BITS IPHX Level (lowest) Level Level Level (highest) INTERRUPT PRIORITY LEVEL
more requests different priority levels received same time, with highest assigned priority serviced first. Table shows order priority within same interrupt level more interrupts same priority occur same time. Table also shows interrupt vector address each interrupt sources.
0916.99Rev0
data sheets subject change without notice
©1999 Space E

ADVANCED CONTROL UNIT MULTI-CHIP MODULE ACU51 Block Four 8-B

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