MEGABIT (512K 32-BIT) SRAM 89C1632RP Megabit (512k 32-bit) S
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SPACE PRODUCTS
MEGABIT (512K 32-BIT) SRAM
89C1632RP
Megabit (512k 32-bit) SRAM
Address
89C1632RP
Power
SRAM
SRAM
SRAM
SRAM
Ground
Memory
8-15
16-23
24-31
FEATURES:
Four 512k SRAM architecture RAD-PAK® technology hardens against natural space radiation technology Total dose hardness: typical krad (Si); dependent upon orbit single event latchup MeV/mg/cm2 threshold MeV/mg/cm2 Package: 68-pin quad flat package Fast access time: Completely static memory clock timing strobe required Internal bypass capacitor High-speed silicon-gate CMOS technology power supply Equal address chip enable access times Three-state outputs inputs outputs compatible
DESCRIPTION:
Space Electronics' 89C1632RP RAD-PAK®) high-performance Megabit Multi-Chip Module (MCM) Static Random Access Memory features typical kilorad (Si) total dose tolerance. four 4-Megabyte SRAM bypass capacitors incorporated into high-reliable hermetic quad flat-pack ceramic package. With high-performance silicongate CMOS technology, 89C1632RP reduces power consumption eliminates need external clocks timing strobes. equipped with output enable (OE) four byte enable (CS1 CS4) inputs allow greater system flexibility. When input high, output forced high impedance. 89C1632RP been specifically designed meet exposure radiation environments. total-dose survivability greater than krad (Si), based GEO-type orbit (actual tolerance depends upon orbit mission duration). Space Electronics' RADPAK® advanced technology incorporates radiation shielding microcircuit package that eliminates shielding. 89C1632RP available Class Class packaging screening.
0604.99Rev0
data sheets subject change without notice
(619) 452-4167 Fax: (619) 452-5499 www.spaceelectronics.com
©1999 Space Electronics Inc. rights reserved.
89C1632RP
A0-A18 I/O0-I/O31
MEGABIT (512K 32-BIT) SRAM
TABLE DESCRIPTION
DESCRIPTION Address Enable Write Enable Output Enable Chip Enable Data Input/Output Connection Power Supply Ground
FIGURE 89C1632RP PINOUT
I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31
Memory
89C1632RP
I/O0
0604.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
89C1632RP
MEGABIT (512K 32-BIT) SRAM
TABLE 89C1632RP ABSOLUTE MAXIMUM RATINGS
(VOLTAGE REFERENCED
PARAMETER Power Supply Voltage Relative Voltage Relative Except Power Dissipation Operating Temperature Storage Temperature
SYMBOL VIN, VOUT TSTG
-0.5 -0.5
+7.0 +0.5 +125 +150
UNITS
TABLE 89C1632RP ABSOLUTE MAXIMUM RATINGS
(VCC 10%, +125 UNLESS OTHERWISE NOTED) PARAMETER Supply Voltage, (Operating Voltage Range) Input High Voltage Input Voltage (max) (pulse width 10ns) (min) -2.0V (pulse width SYMBOL -0.5 UNITS
Memory
TABLE 89C1632RP CAPACITANCE
MHZ, 3.0V, PARAMETER Input Capacitance CS4, I/O0-7, I/O8-15, I/O16-23, I/O24-31 Input Output Capacitance SYMBOL TEST CONDITIONS COUT VI/O UNITS
TABLE 89C1632RP ELECTRICAL CHARACTERISTICS
PARAMETER Input Leakage Current Output Leakage Current Average Operating Current Cycle Time: SYMBOL TEST CONDITIONS VIH, VOUT Min. Cycle, 100% Duty, VIL, IOUT -8.0 -8.0 -MAX +8.0 +8.0 UNITS
0604.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
89C1632RP
PARAMETER Standby Power Supply Current CMOS Standby Power Supply Current Output Voltage Output High Voltage SYMBOL ISB1 TEST CONDITIONS
MEGABIT (512K 32-BIT) SRAM
TABLE 89C1632RP ELECTRICAL CHARACTERISTICS
-2.4 3.95 UNITS VIH, cycle time 25ns 0.2V, MHz, 0.2V 0.2V -4.0
capacitance characteristics.
TABLE OPERATING CONDITIONS CHARACTERISTICS
PARAMETER Input Pulse Level Output Timing Measurement Reference Level Input Rise/Fall Time Input Timing Measurement Reference Level -MAX UNITS
Memory
TABLE 89C1632RP READ CYCLE
PARAMETER Read Cycle Time 89C1632RP-25 89C1632RP-30 Address Access Time 89C1632RP-25 89C1632RP-30 Chip Select Output 89C1632RP-25 89C1632RP-30 Output Enable Output 89C1632RP-25 89C1632RP-30 Output Enable Low-Z Output 89C1632RP-25 89C1632RP-30 Chip Enable Low-Z Output 89C1632RP-25 89C1632RP-30 Output Disable High-Z Output 89C1632RP-25 89C1632RP-30
0604.99Rev0
SYMBOL
UNITS
-tCO -tOE -tOLZ tILZ tOHZ
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
89C1632RP
PARAMETER Chip Disable High-Z Output 89C1632RP-25 89C1632RP-30 Output Hold from Address Change 89C1632RP-25 89C1632RP-30
MEGABIT (512K 32-BIT) SRAM
TABLE 89C1632RP READ CYCLE
SYMBOL -tOH UNITS
TABLE 89C1632RP WRITE CYCLE
PARAMETER Write Cycle Time 89C1632RP-25 89C1632RP-30 Chip Select Write 89C1632RP-25 89C1632RP-30 Address Set-up Time 89C1632RP-25 89C1632RP-30 Address Valid Write 89C1632RP-25 89C1632RP-30 Write Pulse Width High) 89C1632RP-25 89C1632RP-30 Write Pulse Width Low) 89C1632RP-25 89C1632RP-30 Write Recovery Time 89C1632RP-25 89C1632RP-30 Write Output High-Z 89C1632RP-25 89C1632RP-30 Data Write Time Overlap 89C1632RP-25 89C1632RP-30 Data Hold from Write Time 89C1632RP-25 89C1632RP-30 Write Output Low-Z 89C1632RP-25 89C1632RP-30
0604.99Rev0
SYMBOL
UNITS
tWHZ -tDW
Memory
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
89C1632RP
MEGABIT (512K 32-BIT) SRAM
FIGURE TEST LOADS
FIGURE TIMING WAVEFORM READ CYCLE (ADDRESS CONTROLLED)
Memory
FIGURE TIMING WAVEFORM READ CYCLE VIH)
high read cycle. read cycle timing referenced from last valid address first transition address. tOHZ defined time which outputs achieve open circuit condition referenced levels.
0604.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
89C1632RP
Device continuously selected with VIL. Address valid prior coincident with transition low.
MEGABIT (512K 32-BIT) SRAM
given temperature voltage conditions, (max) less than (min) both given device from device device. Transition measured +200mV from steady state voltage with Load(B). This parameter sampled 100% tested.
common applications, minimization elimination contention conditions necessary during read write cycle.
FIGURE TIMING WAVEFORM WRITE CYCLE CLOCK)
Memory
FIGURE TIMING WAVEFORM WRITE CYCLE FIIXED)
0604.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
89C1632RP
MEGABIT (512K 32-BIT) SRAM
FIGURE TIMING WAVEFORM WRITE CYCLE CONTROLLED)
write cycle timing referenced from last valid address first transition address. write occurs during overlap write begins latest transition going going low. write ends earliest transition going high going high. measured from beginning write write. measured from later going write. measured from address valid beginning write. measured from write address change. applied case write ends going high. Read Mode during this period, pins output low-Z state. Inputs opposite phase output must applied because contention occur. common applications, minimization elimination contention conditions necessary during read write cycle. foes simultaneously with going after going low, outputs remain high impedance state. DOUT read data address. When low, pins output state. input signals opposite phase leading output should applied.
Memory
0604.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
89C1632RP
L(SQ) L1(SQ)
MEGABIT (512K 32-BIT) SRAM
D(SQ)
RAD-PAK® QUAD FLAT PACKAGE
SYMBOL -2.485 1.239 1.429 0.206 0.015 0.008 1.479 -2.485 1.690 0.180 DIMENSION 0.225 0.017 0.009 1.494 0.800 2.500 1.700 0.195 0.050 0.339 2.510 1.244 1.434 -2.545 1.249 1.439 0.244 0.018 0.0012 1.509 -2.505 1.710 0.210
Memory
Q68-04 Note: dimensions inches
0604.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
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