Banks Synchronous DRAM Document Title Banks Synchronous DRAM Revi

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Banks Synchronous DRAM Document Title Banks Synchronous DRAM Revi

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A43L2616
Banks Synchronous DRAM
Document Title Banks Synchronous DRAM Revision History
History
Initial issue grade -5.5 spec Full Page Mode Pb-Free package type
Issue Date
August 2001 November 26,2001 January 4,2002 February 21,2002 September 2004
Remark
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Banks Synchronous DRAM
Features
JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks Pulse cycle with address programs Latency (2,3) Burst Length (1,2,4,8 full page) Burst Type (Sequential Interleave) inputs sampled positive going edge system clock
Clock Frequency: 166MHz CL=3 143MHz CL=3 183Mhz CL=3 (183Mhz available only grade) Burst Read Single-bit Write operation masking Auto self refresh 64ms refresh period cycle) TSOP (II) Self Refresh Current version grade
General Description
A43L2616 67,108,864 bits synchronous high data rate Dynamic organized 1,048,576 words bits, fabricated with AMIC's high performance CMOS technology. Synchronous design allows precise cycle control with system clock. transactions possible every clock cycle. Range operating frequencies, programmable latencies allows same device useful variety high bandwidth, high performance memory system applications.
Configuration
TSOP (II)
VDDQ
VSSQ
DQ14
DQ13
DQ11
UDQM
VDDQ
VSSQ
DQ15
DQ12
DQ10
A43L2616V
VDDQ
VSSQ
VSSQ LDQM VDDQ A10/AP
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Block Diagram
Control
Data Input Register Bank Select
Decoder Output Buffer Sense
Buffer Refresh Counter
Address Register
LCBR
LRAS
Column Decoder
Column Buffer
Latency Burst Length
LRAS
LCAS LRAS LCBR
Programming Register LWCBR
Timing Register
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Descriptions
Symbol Name Description
System Clock Chip Select
Active positive going edge sample inputs. Disables Enables device operation masking enabling inputs except CLK, L(U)DQM Masks system clock freeze operation from next clock cycle.
Clock Enable
should enabled least clock prior command. Disable input buffers power down standby. Column addresses multiplexed same pins.
A0~A11
Address address RA0~RA11, Column address: CA0~CA7 Selects bank activated during address latch time.
BS0,
Bank Select Address Selects band read/write during column address latch time. Address Strobe Latches addresses positive going edge with low. Enables access precharge. Column Address Strobe
Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground Connection
Latches column addresses positive going edge with low. Enables column access.
Enables write operation precharge. Makes data output Hi-Z, after clock masks output. Blocks data input when L(U)DQM active. Data inputs/outputs multiplexed same pins. Power Supply: +3.3V±0.3V/Ground Provide isolated Power/Ground improved noise immunity.
L(U)DQM DQ0-15 VDD/VSS VDDQ/VSSQ NC/RFU
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Absolute Maximum Ratings*
Voltage relative (Vin, Vout -1.0V +4.6V Voltage supply relative (VDD, VDDQ .-1.0V +4.6V Storage Temperature (TSTG) -55°C +150°C Soldering Temperature Time (TSLODER) 260°C 10sec Power Dissipation (PD) Short Circuit Current (Ios) 50mA
*Comments
Permanent device damage occur "Absolute Maximum Ratings" exceeded. Functional operation should restricted recommended operating condition. Exposure higher than recommended voltage extended periods time could affect device reliability.
Capacitance (TA=25°C, f=1MHz)
Parameter Symbol Condition Unit
Input Capacitance
A11, BS0, CLK, CKE, DQ15
Data Input/Output Capacitance
CI/O
Electrical Characteristics
Recommend operating conditions (Voltage referenced
Parameter Symbol Unit Note
Supply Voltage Input High Voltage Input Voltage Output High Voltage Output Voltage Input Leakage Current Output Leakage Current Output Loading Condition
VDD,VDDQ
-0.3
VDD+0.3
Note -2mA Note Note
Figure
Note: (min) -1.5V (pulse width 5ns). input 0.3V, other pins under test Dout disabled, Vout
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Decoupling Capacitance Guide Line
Recommended decoupling capacitance added power line board.
Parameter Symbol Value Unit
Decoupling Capacitance between Decoupling Capacitance between VDDQ VSSQ
CDC1 CDC2
0.01 0.01
Note: VDDQ pins separated each other. pins connected chip. VDDQ pins connected chip. VSSQ pins separated each other pins connected chip. VSSQ pins connected chip.
Electrical Characteristics
(Recommended operating condition unless otherwise noted, 70°C
Symbol Parameter Test Conditions -5.5 Speed
Unit
Notes
Icc1 Icc2 Icc2 ICC2N
Operating Current (One Bank Active) Precharge Standby Current power-down mode
Burst Length tRC(min), tCC(min), VIL(max), 15ns VIL(max), VIH(min), VIH(min), 15ns Input signals changed time during 30ns VIH(min), VIL(max), Input signals stable. VIH(min), VIH(min), 15ns Input signals changed time during 30ns 0mA, Page Burst bank Activated, tCCD tCCD (min) (min)
Precharge Standby Current power-down mode
ICC2NS Active Standby current power-down mode (One Bank Active) Operating Current (Burst Mode) Refresh Current
ICC3N
ICC4 ICC5
ICC6 Self Refresh Current 0.2V
Note: Measured with outputs open. Addresses changed only time during tCC(min).
Refresh period 64ms. Addresses changed only time during tCC(min). ICC6 normal version: A43L2616V-6, A43L2616V-7. ICC6 self refresh current version: A43L2616V-5.5V, A43L2616V-6V, A43L2616V-7V.
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Operating Test Conditions
(VDD 3.3V ±0.3V, +70°C)
Parameter Value
input levels Input timing measurement reference level Input rise time (See note3) Output timing measurement reference level Output load condition
VIH/VIL 2.4V/0.4V 1.4V tr/tf 1ns/1ns 1.4V Fig.2
3.3V 1200 Output OUTPUT 50pF VOH(DC) 2.4V, -2mA VOL(DC) 0.4V, =1.4V ZO=50 50pF
(Fig. Output Load Circuit
(Fig. Output Load Circuit
Characteristics
operating conditions unless otherwise noted)
-5.5 Symbol Parameter Latency Unit Note
tSAC
cycle time valid Output delay
1000
1000
1000
tSLZ tSHZ
Output data hold time high pulse width pulse width Input setup time Input hold time output Low-Z output Hi-Z
*All parameters measured from half half.
Note Parameters depend programmed latency. clock rising time longer than 1ns, (tr/2-0.5) should added parameter. Assumed input rise fall time 1ns. longer than 1ns, transient time compensation should considered, i.e., [(tr tf)/2-1]ns should added parameter.
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Operating Parameter operating conditions unless otherwise noted)
Version Symbol Parameter Latency -5.5 Unit Note
tRRD(min) tRCD(min) tRP(min) tRAS(min)
active active delay delay precharge time
16.5 38.5
active time tRAS(max) tRC(min) tCDL(min) tRDL(min) tBDL(min) tCCD(min) cycle time Last data col. Address delay Last data precharge Last data burst stop Col. Address col. Address delay
Note: minimum number clock cycles determined dividing minimum time required with clock cycle time then rounding next higher integer. Minimum delay required complete write.
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Simplified Truth Table
Command CKEn-1 CKEn
A9~A0, Notes
Register Refresh
Mode Register Auto Refresh Self Refresh Entry Exit
CODE Addr. Column Addr. Column Addr.
Bank Active Addr. Read Auto Precharge Disable Column Addr. Auto Precharge Enable Write Auto Precharge Disable Column Addr. Auto Precharge Enable Burst Stop Precharge Bank Selection Both Banks Clock Suspend Active Power Down Entry Exit Entry Precharge Power Down Mode Exit Operation Command
Valid, Don't Care, Logic High, Logic Low)
Note Code: Operand Code A0~A11, BS0, BS1: Program keys. (@MRS) issued only both banks precharge state. command issued after clock cycle MRS. Auto refresh functions same refresh DRAM. automatical precharge without precharge command meant "Auto". Auto/Self refresh issued only both precharge state. BS0, Bank select address. both "Low" read, write, active precharge, bank selected. both "Low" "High" read, write, active precharge, bank selected. both "High" "Low" read, write, active precharge, bank selected. both "High" read, write, active precharge, bank selected. A10/AP "High" precharge, ignored banks selected. During burst read write with auto precharge, read write command cannot issued. Another bank read write command issued every burst length. sampled positive going edge masks data-in very (Write latency masks data-out Hi-Z state after cycles. (Read latency
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Mode Register Filed Table Program Modes
Register Programmed with
Address BS0, A11,
Function
(Note
(Note
W.B.L
Latency
Burst Length
Test Mode Type
Latency Latency
Burst Type Type
Burst Length BT=0 BT=1
Mode Register Vendor Only
Reserved Reserved Reserved Reserved Reserved
Sequential Interleave
Reserved Reserved Reserved 256(Full)
Reserved Reserved Reserved Reserved
Write Burst Length Length
Burst Single
Power Sequence
Apply power start clock, Attempt maintain "H", other pins condition inputs. Maintain stable power, stable clock input condition minimum 200µs. Issue precharge commands banks devices. Issue more auto-refresh commands. Issue mode register command initialize mode register. cf.) Sequence changed. device ready normal operation.
Note RFU(Reserved Future Use) should stay during cycle. high during cycle, "Burst Read Single Write" function will enabled.
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Burst Sequence (Burst Length Initial address Sequential Interleave
Burst Sequence (Burst Length
Initial address Sequential Interleave
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Device Operations
Clock (CLK)
command decoder that address inputs ignored.
Power-Up
clock input used reference SDRAM operations. operations synchronized positive going edge clock. clock transitions must monotonic between VIH. During operation with high inputs assumed valid state (low high) duration hold time around positive edge clock proper functionality specifications.
Clock Enable (CLK)
clock enable (CKE) gates clock onto SDRAM. goes synchronously with clock (set-up hold time same other inputs), internal clock suspended form next clock cycle state output burst address frozen long remains low. other inputs ignored from next clock cycle after goes low. When both banks idle state goes synchronously with clock, SDRAM enters power down mode form next clock cycle. SDRAM remains power down mode ignoring other inputs long remains low. power down exit synchronous internal clock suspended. When goes high least "tSS CLOCK" before high going edge clock, then SDRAM becomes active from same clock edge accepting input commands.
Bank Select (BS0, BS1)
following sequence recommended POWER Power must applied either inputs pull them high other pins condition inputs before along with (and VDDQ) supply. clock signal must also asserted same time. After reaches desired voltage, minimum pause microseconds required with inputs condition. Both banks must precharged now. Perform minimum Auto refresh cycles stabilize internal circuitry. Perform MODE REGISTER cycle program latency, burst length burst type default value mode register undefined. clock cycle from mode register cycle, device ready operation. When above sequence used Power-up, out-puts will high impedance state. high impedance outputs guaranteed other power-up sequence. cf.) Sequence changed.
Mode Register (MRS)
This SDRAM organized independent banks 1,048,576 words bits memory arrays. BS0, inputs latched time assertion select bank used operation. bank select BS0, latched bank activate, read, write mode register precharge operations.
Address Input A11)
mode register stores data controlling various operation modes SDRAM. programs latency, addressing mode, burst length, test mode various vendor specific options make SDRAM useful variety different applications. default value mode register defined, therefore mode register must written after power operate SDRAM. mode register written asserting
address bits required decode 262,144 word locations multiplexed into address input pins (A0~A11). address latched along with during bank activate command. column address latched along with BS1during read write command.
Device Deselect
When high, SDRAM performs operation (NOP). does initiate operation, needed complete operations which require more than single clock like bank activate, burst read, auto refresh, etc. device deselect also entered asserting high. high disables
(The SDRAM should active mode with already high prior writing mode register). state address pins A0~A11, same cycle going data written mode register. clock cycle required complete write mode register. mode register contents changed using same command clock cycle requirements during operation long both banks idle state. mode register divided into various fields depending functionality. burst length field uses A0~A2, burst type uses addressing mode uses A4~A6, A7~A8, A11, used vendor specific options test mode. write burst length programmed using A7~A8, A11, must normal SDRAM operation. Refer table specific codes various burst length, addressing modes latencies.
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Device Operations (continued)
Bank Activate Burst Write
bank activate command used select random idle bank. asserting with desired bank addresses, access initiated. read write operation occur after time delay tRCD(min) from time bank activation. tRCD(min) internal timing parameter SDRAM, therefore dependent operating clock frequency. minimum number clock cycles required between bank activate read write command should calculated dividing tRCD(min) with cycle time clock then rounding result next higher integer. SDRAM internal banks same chip shares part internal circuitry reduce chip area, therefore restricts activation both banks immediately. Also noise generated during sensing each bank SDRAM high requiring some time power supplies recover before other bank sensed reliably. tRRD(min) specifies minimum time required between activating different banks. number clock cycles required between different bank activation must calculated similar tRCD specification. minimum time required bank active initiate sensing restoring complete dynamic cells determined tRAS(min) specification before precharge command that active bank asserted. maximum time bank active state determined tRAS(max). number cycles both tRAS(min) tRAS(max) calculated similar tRCD specification.
Burst Read
burst write command similar burst read command, used write data into SDRAM consecutive clock cycles adjacent addresses depending burst length burst sequence. asserting with valid column address, write burst initiated. data inputs provided initial address same clock cycle burst write command. input buffer deselected burst length, even though internal writing have been completed yet. writing complete burst length. burst write terminated issuing burst read blocking data inputs burst write same other active bank. burst stop command valid only full page burst length where writing continues burst burst wrap around. write burst also terminated using blocking data precharging bank "tRDL" after last data input written into active row. OPERATION also.
Operation
burst read command used access burst data consecutive clock cycles from active active bank. burst read command issued asserting with being high positive edge clock. bank must active least tRCD(min) before burst read command issued. first output appears latency number clock cycles after issue burst read command. burst length, burst sequence latency from burst read command determined mode register which already programmed. burst read initiated column address active row. address wraps around initial address does start from boundary such that number outputs from each equal burst length programmed mode register. output goes into high-impedance burst, unless burst read initiated keep data output gapless. burst read terminated issuing another burst read burst write same bank other active bank precharge command same bank. burst stop command valid every page burst length.
used mask input output operation. works similar during read operation inhibits writing during write operation. read latency cycles from zero cycle write, which means masking occurs cycles later read cycle occurs same cycle during write cycle. operation synchronous with clock, therefore masking occurs complete cycle. signal important during burst interrupts write with read precharge SDRAM. asynchronous nature internal write, operation critical avoid unwanted incomplete writes when complete burst write required.
Precharge
precharge operation performed active bank asserting A10/AP with valid bank precharged. precharge command asserted anytime after tRAS(min) satisfied from bank activate command desired bank. "tRP" defined minimum time required precharge bank. minimum number clock cycles required complete precharge calculated dividing "tRP" with clock cycle time rounding next higher integer. Care should taken make sure that burst write completed used inhibit writing before precharge command asserted. maximum time bank active specified tRAS(max). Therefore, each bank precharged within tRAS(max) from bank activate command. precharge, bank enters idle state ready activated again. Entry Power Down, Auto refresh, Self refresh Mode register etc, possible only when both banks idle state.
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Device Operations (continued)
Auto Precharge
precharge operation also performed using auto precharge. SDRAM internally generates timing satisfy tRAS(min) "tRP" programmed burst length latency. auto precharge command issued same time burst read burst write asserting high A10/AP. burst read burst write command issued with A10/AP, bank left active until command asserted. Once auto precharge command given, commands possible that particular bank until bank achieves idle state.
Four Banks Precharge
operation specified "tRC(min)". minimum number clock cycles required calculated driving "tRC" with clock cycle time then rounding next higher integer. auto refresh command must followed NOP's until auto refresh operation completed. Both banks will idle state auto refresh operation. auto refresh preferred refresh mode when SDRAM being used normal data transactions. auto refresh cycle performed once 15.6us burst 4096 auto refresh cycles once 64ms.
Self Refresh
Both banks precharged same time using Precharge command. Asserting
with high A10/AP after both banks have satisfied tRAS(min) requirement, performs precharge both banks. after performing precharge all, both banks idle state.
Auto Refresh
storage cells SDRAM need refreshed every 64ms maintain data. auto refresh cycle accomplishes refresh single storage cells. internal counter increments automatically every auto refresh cycle refresh rows. auto refresh command issued asserting with high auto refresh command only asserted with both banks being idle state device power down mode (CKE high previous cycle). time required complete auto refresh
self refresh another refresh mode available SDRAM. self refresh preferred refresh mode data retention power operation SDRAM. self refresh mode, SDRAM disables internal clock input buffers except CKE. refresh addressing timing internally generated reduce power consumption. self refresh mode entered from banks idle state asserting with high Once self refresh mode entered, only state being matters, other inputs including clock ignored remain self refresh. self refresh exited restarting external clock then asserting high CKE. This must followed NOP's minimum time "tRC" before SDRAM reaches idle state begin normal operation. system uses burst auto refresh during normal operation, recommended used burst 4096 auto refresh cycles immediately after exiting self refresh.
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Basic feature Function Descriptions CLOCK Suspend
Click Suspended During Write (BL=4)
Clock Suspended During Read (BL=4)
Masked Internal Masked
DQ(CL2) DQ(CL3)
Written
Suspended Dout
Note: disable/enable=1 clock
Operation
Write Mask (BL=4)
Read Mask (BL=4)
Masked DQ(CL2) DQ(CL3) Hi-Z Hi-Z Masked
Data-in Mask 0CLK
Data-out Mask
Read Mask (BL=4)
DQ(CL2) DQ(CL3) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Note makes data Hi-Z after clocks which should masked "L".
masks both data-in data-out.
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Interrupt
Read interrupted Read (BL=4)Note DQ(CL2) DQ(CL3) tCCD
Note2
Write interrupted Write
Note2
Write interrupted Read
tCCD DQ(CL2) DQ(CL3) tCDL Note3
Note2
tCCD
tCDL
Note3
Note "Interrupt", possible stop burst read/write external command before burst. Interrupt", stop burst read/write access; read, write block write. tCCD delay. (=1CLK) tCDL Last data column address delay. 1CLK).
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Interrupt (II) Read Interrupted Write
CL=2, BL=4
iii) CL=3, BL=4
Hi-Z
Hi-Z
Hi-Z
Note
iii)
Hi-Z
Hi-Z
Note
Note prevent contention, there should least between data data out. prevent contention, should issued which makes least between data data out.
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Write Interrupted Precharge
Masked Note
Note
Note inhibit invalid write, should issued. This precharge command burst write command should same bank, otherwise precharge interrupt only another bank precharge dual banks operation.
Precharge
Normal Write (BL=4) tRDL Read (BL=4) DQ(CL2) DQ(CL3)
Auto Precharge
Normal Write (BL=4)
Note Auto Precharge Starts
Read (BL=4) DQ(CL2) DQ(CL3)
Note Auto Precharge Starts
Note active command precharge bank issued after from this point. read/write command other active bank issued from this point. burst read/write with auto precharge, interrupt same/another bank illegal.
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Burst Stop Interrupted Precharge
Normal Write (BL=4)
tRDL Note
Write Burst Stop (BL=8)
STOP
tBDL Note
Read Interrupted Precharge (BL=4) DQ(CL2) DQ(CL3)
Note
Read Burst Stop (BL=4) DQ(CL2)
STOP
DQ(CL3)
Mode Register
Note
2CLK
Note tRDL: 1CLK tBDL: 1CLK; Last data burst stop delay. Read write burst stop command valid every burst length. Number valid output data after precharge burst stop: latency respectively. PRE: banks precharge necessary. issued only when banks precharged state.
Clock Suspend Exit Power Down Exit
Clock Suspend (=Active Power Down) Exit Internal
Note
Power Down (=Precharge Power Down) Exit
Internal
Note
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Auto Refresh Self Refresh
Note
Auto Refresh
Internal
Note
Note
Note
Self Refresh
Note
Note Active power down more bank active state. Precharge power down both bank precharge state. auto refresh same refresh conventional DRAM. precharge commands required after Auto Refresh command. During from auto refresh command, other command accepted. Before executing auto/self refresh command, both banks must idle state. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry. During self refresh mode, refresh interval refresh operation performed internally. After self refresh entry, self refresh mode kept while LOW. During self refresh mode, inputs expect will don't cared, outputs will Hi-Z state. During from self refresh exit command, other command accepted. Before/After self refresh mode, burst auto refresh cycle cycles recommended.
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
About Burst Type Control
Basic MODE Random MODE Sequential counting Interleave counting Random column Access tCCD A3="0". BURST SEQUENCE TABE.(BL=4,8) BL=1,2,4,8 full page wrap around. A3=" BURST SEQUENCE TABE.(BL=4,8) BL=4,8 BL=1,2 Interleave Counting Sequential Counting Every cycle Read/Write Command with random column address realize Random Column Access. That similar Extended Data (EDO) Operation convention DRAM.
About Burst Length Control
Basic MODE Special MODE A2,1,0 "000". auto precharge, tRAS should violated. A2,1,0 "001". auto precharge, tRAS should violated. A2,1,0 "010" A2,1,0 "011".
Interrupt MODE
A9="1". BRSW Read burst 1,2,4,8, full page/write Burst auto precharge write, tRAS should violated. Before burst, precharge command same bank Interrupt Stops read/write burst with precharge. (Interrupted Precharge) tRDL=1 with DQM, valid after burst stop CL=2,3 respectively During read/write burst with auto precharge, interrupt cannot issued. Before burst, read/write stops read/write burst starts read/write burst block write. Interrupt During read/write burst with auto precharge, interrupt issued.
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Power Sequence Auto Refresh
CLOCK
High level necessary
ADDR
BS0,
High level necessary
Precharge (All Banks)
Auto Refresh
Auto Refresh
High-Z
A10/AP
Mode Regiser Active (A-Bank) Don't care
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Single Read-Write-Read Cycles (Same Page) @CAS Latency=3, Burst Length=1
CLOCK High
*Note
tRCD ADDR
*Note *Note
tCCD
*Note *Note *Note *Note
BS0,
*Note
*Note
*Note
*Note
A10/AP
tSHZ
tSLZ
Active
Read
Write
Read Precharge
Active
Don't care
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Note inputs don't care when high high going edge. Bank active read/write controlled BS0, BS1.
Active Read/Write
Bank Bank Bank Bank
Enable disable auto precharge function controlled A10/AP read/write command.
A10/AP Operation
Disable auto precharge, leave bank active burst. Disable auto precharge, leave bank active burst. Disable auto precharge, leave bank active burst. Disable auto precharge, leave bank active burst. Enable auto precharge, precharge bank burst. Enable auto precharge, precharge bank burst. Enable auto precharge, precharge bank burst. Enable auto precharge, precharge bank burst.
A10/AP BS0, control bank precharge when precharge command asserted.
A10/AP Precharge
Bank Bank Bank Bank Banks
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Read Write Cycle Same Bank @Burst Length=4
CLOCK
tRCD *Note
High
*Note
ADDR
A10/AP
tRAC *Note tSAC tRAC *Note tSAC *Note tRDL *Note tRDL
tSHZ
tSHZ
Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Active (A-Bank)
Write (A-Bank)
Precharge (A-Bank) Don't care
*Note Minimum cycle times required complete internal DRAM operation. precharge interrupt burst cycle. [CAS latency-1] valid output data available after enters precharge. Last valid output will Hi-Z after tSHZ from clock. Access time from address. tCC*(tRCD latency-1) tSAC Output will Hi-Z after burst. (1,2,4
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Page Read Write Cycle Same Bank @Burst Length=4
CLOCK
High
tRCD
*Note
ADDR
A10/AP
tCDL tRDL
*Note *Note1 *Note3
(CL=2)
(CL=3)
Active (A-Bank)
Read (A-Bank)
Read (A-Bank)
Write (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
Don't care
*Note write data before burst read ends, should asserted three cycle prior write command avoid contention. precharge will interrupt writing. Last data input, tRDL before precharge, will written. should mask invalid input data precharge command cycle when asserting precharge before burst. Input data after precharge cycle will masked internally.
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Page Read Cycle Different Bank @Burst Length
CLOCK
*Note
High
*Note
ADDR
A10/AP
(CL=2)
QAa0 QAa1
QAa2
QBb0
QBb1 QBb2
QCc0
QCc1
QCc2
QDd0 QDd1 QDd2
(CL=3)
QAa0 QAa1
QAa2
QBb0
QBb1 QBb2
QCc0
QCc1
QCc2
QDd0 QDd1 QDd2
Active (A-Bank)
Read (A-Bank) Active (B-Bank)
Read (B-Bank) Active (C-Bank)
Read (C-Bank) Active (D-Bank) Precharge (B-Bank)
Read (D-Bank) Precharge (C-Bank)
Precharge (D-Bank)
Precharge (A-Bank)
Don't care
Note don't care when RAS,
high clock high going edge.
interrupt burst read precharge, both read precharge banks must same.
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Page Write Cycle Different Bank @Burst Length=4
CLOCK
High
*Note
ADDR
A10/AP
DAa0 DAa1
DAa2
DAa3
DBb0 DBb1
DBb2
DBb3
DCc0
DCc1
DDd0
DDd1
CDd2 tRDL
tCDL
*Note
Active (A-Bank)
Write (A-Bank)
Write (B-Bank)
Active (D-Bank) Write (C-Bank)
Write (D-Bank)
Precharge (All Banks)
Active (B-Bank)
Active (C-Bank)
Don't care
Note: interrupt burst write precharge, should asserted mask invalid input data. interrupt burst write precharge, both write precharge banks must same.
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Read Write Cycle Different Bank @Burst Length=4
CLOCK
High
ADDR
A10/AP
tCDL *Note
(CL=2)
QAa0
QAa1
QAa2 QAa3
DDb0
DDb1
DDb2
DDb3
QBc0
QBc1
QBc2
(CL=3)
QAa0
QAa1 QAa2
QAa3
DDb0 DDb1
DDb2
DDb3
QBc0
QBc1
Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Write (D-Bank)
Read (B-Bank)
Active (D-Bank)
Active (B-Bank) Don't care
Note tCDL should complete write.
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Read Write Cycle with Auto Precharge @Burst Length=4
CLOCK
High
ADDR
A10/AP
(CL=2)
QAa0
QAa1
QAa2 QAa3
DDb0
DDb1
DDb2
DDb3
(CL=3)
QAa0
QAa1 QAa2
QAa3
DDb0 DDb1
DDb2
DDb3
Active (A-Bank)
Read with Auto Precharge (A-Bank) Active (D-Bank)
Auto Precharge Start Point (A-Bank/CL=3) Auto Precharge Start Point (A-Bank/CL=2)
Write with Auto Precharge (D-Bank)
Auto Precharge Start Point (D-Bank)
Don't care
*Note tRCD should controlled meet minimum tRAS before internal precharge start. case Burst Length=1 BRSW mode)
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Clock Suspension Operation Cycle @CAS Latency Burst Length=4
CLOCK
ADDR
A10/AP
Note
tSHZ
tSHZ
Active
Read
Clock Suspension
Read Read Write
Write Clock Suspension
Don't care
Note needed prevent contention.
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Read Interrupted Precharge Command Read Burst Stop Cycle @Burst Length=Full Page
CLOCK
High
ADDR
A10/AP
(CL=2)
QAa0
QAa1
QAa2
QAa3 QAa4
QAb0
QAb1
QAb2
QAb3
QAb4
QAb5
(CL=3)
QAa0
QAa1
QAa2 QAa3
QAa4
QAb0 QAb1
QAb2
QAb3
QAb4
QAb5
Active (A-Bank)
Read (A-Bank)
Burst Stop
Read (A-Bank)
Precharge (A-Bank)
Don't care
Note full page mode, burst wrap-around burst. auto precharge impossible. About valid DQ's after burst stop, same case interrupt.
Both cases illustrated above timing diagram. label them. burst write, burst stop interrupt should compared carefully. Refer timing diagram "Full page write burst stop cycle". Burst stop valid every burst length.
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Write Interrupted Precharge Command Write Burst Stop Cycle Burst Length Full Page
CLOCK
High
ADDR
A10/AP
tBDL
Note
tRDL
DAa0
DAa1
DAa2
DAa3 DAa4
DAb0
DAb1
DAb2
DAb3
DAb4
DAb5
Active (A-Bank)
Write (A-Bank)
Burst Stop
Write (A-Bank)
Precharge (A-Bank)
Don't care
Note full page mode, burst wrap-around burst. auto precharge impossible. Data-in cycle interrupted precharge cannot written into corresponding memory cell. defined parameter tRDL(=2CLK). write interrupted precharge command needed prevent invalid write. should mask invalid input data precharge command cycle when asserting precharge before burst. Input data after precharge cycle will masked internally. Burst stop valid every burst length.
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Active/Precharge Power Down Mode @CAS Lantency=2, Burst Length=4
CLOCK
Note
Note
*Note
A10/AP
ADDR
tSHZ
Precharge Power-down Entry
Precharge Power-down Exit Active Active Power-down Entry Active Power-down Exit
Read
Precharge
Don't care
Note banks should idle state prior entering precharge power down mode. should high least "1CLK tSS" prior active command. Cannot violate minimum refresh specification. (64ms)
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Self Refresh Entry Exit Cycle
CLOCK
Note
Note
Note
Note
Note
Note
min.
Note
Note
Hi-Z
Hi-Z
Self Refresh Entry
Self Refresh Exit
A10/AP
BS0,
ADDR
Note ENTER SELF REFRESH MODE with should same clock cycle. After clock cycle, inputs including system clock don't care except CKE. device remains self refresh mode long stays "Low". (cf.) Once device enters self refresh mode, minimum tRAS required before exit from self refresh. EXIT SELF REFRESH MODE System clock restart stable before returning high. starts from high. Minimum required after going high complete self refresh exit. cycle burst auto refresh required before self refresh entry after self refresh exit. system uses burst refresh.
Auto Refresh Don't care
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Mode Register Cycle Auto Refresh Cycle
CLOCK
*Note
High
High
Note
Note
Hi-Z
Hi-Z
Command
Auto Refresh
ADDR
Command Don't care
Both banks precharge should completed before Mode Register cycle auto refresh cycle.
MODE REGISTER CYCLE Note mode register.
activation same clock cycle with address will internal
Minimum clock cycles should before activation.
Please refer Mode Register table.
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Function Truth Table (Table
Current State
Address
Action
Note
Code
ILLEGAL Active; Latch Address Auto Refresh Self Refresh Mode Register Access ILLEGAL
A10/AP ILLEGAL
IDLE
Active
CA,A10/AP Begin Read; Latch Determine CA,A10/AP Begin Write; Latch Determine CA,AP ILLEGAL Precharge ILLEGAL NOP(Continue Burst Active) NOP(Continue Burst Active) Term burst Active Term burst; Begin Write; Latch Determine ILLEGAL Term Burst; Precharge timing Reads ILLEGAL NOP(Continue Burst EndRow Active) NOP(Continue Burst EndRow Active) Term burst Active
Read
CA,A10/AP Term burst; Begin Read; Latch Determine
Write
CA,A10/AP Term burst; Begin Read; Latch Determine CA,A10/AP Term burst; Begin Read; Latch Determine A10/AP ILLEGAL Term Burst; Precharge timing Writes ILLEGAL NOP(Continue Burst EndPrecharge) NOP(Continue Burst EndPrecharge) ILLEGAL
Read with Auto Precharge
CA,A10/AP ILLEGAL CA,A10/AP ILLEGAL ILLEGAL ILLEGAL
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Function Truth Table (Table Continued)
Current State
Address
Action
Note
NOP(Continue Burst EndPrecharge) NOP(Continue Burst EndPrecharge) ILLEGAL
Write with Auto Precharge
CA,A10/AP ILLEGAL CA,A10/AP ILLEGAL A10/PA A10/PA ILLEGAL ILLEGAL NOPIdle after NOPIdle after ILLEGAL
Precharge
CA,A10/AP ILLEGAL ILLEGAL NOPIdle after ILLEGAL NOPRow Active after tRCD NOPRow Active after tRCD ILLEGAL
Activating
CA,A10/AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOPIdle after NOPIdle after ILLEGAL ILLEGAL ILLEGAL NOPIdle after clocks NOPIdle after clocks ILLEGAL ILLEGAL ILLEGAL
Refreshing
Mode Register Accessing
Abbreviations Address Bank Address Auto Precharge Operation Command Column Address Precharge Note: entries assume that active (High) during preceding clock cycle current clock cycle. Illegal bank specified state Function legal bank indicated depending state that bank. Must satisfy contention, turn around, and/or write recovery requirements. bank precharging idle state. precharge bank indicated (and PA). Illegal banks idle.
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Function Truth Table (Table
Current State
Address
Action
Note
INVALID Exit Self RefreshABI after Exit Self RefreshABI after ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self Refresh) INVALID Exit Power DownABI Exit Power DownABI ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Power Down Mode) Refer Table Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL Refer Operations Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain clock Suspend
Self Refresh Both Bank Precharge Power Down Banks Idle State Other than Listed Above
Abbreviations Banks Idle Note: After CKE's high transition exit self refresh mode. time tRC(min) elapse after CKE's high transition issue command. high transition asynchronous restarts internal clock. minimum setup time "tSS clock" must satisfied before command other than exit. Power-down self refresh entered only from banks idle state. Must legal command.
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Ordering Information
Part Cycle Time (ns) Clock Frequency (MHz) Access Time Package
A43L2616V-6 A43L2616V-6F A43L2616V-7 A43L2616V-7F A43L2616V-5.5V A43L2616V-5.5VF A43L2616V-6V A43L2616V-6VF A43L2616V-7V A43L2616V-7VF
TSOP (II) Pb-Free TSOP (II) TSOP (II) Pb-Free TSOP (II) TSOP (II) Pb-Free TSOP (II) TSOP (II) Pb-Free TSOP (II) TSOP (II) Pb-Free TSOP (II)
Self Refresh Current version grade 183Mhz only available grade (A43L2616V-5.5V).
(September, 2004, Version 3.1)
AMIC Technology, Corp.
A43L2616
Package Information TSOP (Type Outline Dimensions
unit: inches/mm
Detail
0.21
0.665
Detail
Seating Plane
Dimensions inches
Dimensions 0.05 0.95 0.30 0.12 1.00 22.22 0.71 11.76 10.16 0.80 1.20 0.15 1.05 0.45 0.21
Symbol
0.002 0.037 0.012 0.005
0.004 0.039 0.875 0.028 0.463 0.400 0.031
0.047 0.006 0.041 0.018 0.008
0.016 0.005 0.005
0.020 0.031
0.024 0.010
0.40 0.12 0.12
0.50 0.80
0.60 0.25
Notes: maximum value dimension includes flash. Dimension does include resin fins. Dimension includes flash.
(September, 2004, Version 3.1)
AMIC Technology, Corp.

Banks Synchronous DRAM Document Title Banks Synchronous DRAM Revi

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