11/00 Advance Information DSP56364 24-Bit Audio Digital
|
|
|
Top Searches for this datasheet
Order this document DSP56364/D
11/00
Advance Information
DSP56364
24-Bit Audio Digital Signal Processor
DSP56364 supports digital audio applications requiring sound field processing, acoustic equalization, other digital audio algorithms. DSP56364 uses high performance, single-clock-per-cycle DSP56300 core family programmable CMOS digital signal processors (DSPs) combined with audio signal processing capability Motorola SymphonyDSP family, shown Figure This design provides two-fold performance increase over Motorola's popular Symphony family DSPs while retaining code compatibility. Significant architectural enhancements include barrel shifter, 24-bit addressing, instruction cache, direct memory access (DMA). DSP56364 offers million instructions second (MIPS) using internal clock
GPIO
ESAI
PROGRAM 0.5K PROGRAM
MEMORY
MEMORY 1.5K
PIO_EB
PM_EB
XM_EB
YM_EB
PERIPHERAL EXPANSION AREA
ADDRESS GENERATION UNIT CHANNELS UNIT
Bootstrap
MEMORY EXPANSION AREA
ADDRESS EXTERNAL ADDRESS SWITCH
24-BIT DSP56300 CORE
INTERNAL DATA SWITCH
DRAM SRAM INTERFACE
CONTROL
EXTERNAL SWITCH
DATA
POWER MGMT CLOCK PROGRAM INTERRUPT CONT PROGRAM DECODE CONT PROGRAM ADDRESS DATA 24+5656-BIT 56-BIT ACCUMULATORS BARREL SHIFTER
JTAG OnCE
EXTAL
RESET PINIT/NMI
MODA/IRQA MODB/IRQB MODD/IRQD
BITS
Figure DSP56364 Block Diagram
This document contains information product. Specifications information herein subject change without notice.
Advance Information
©2000 MOTOROLA, INC.
DSP56364
PRELIMINARY DSP56364 Advance Information
SIGNAL/CONNECTION DESCRIPTIONS SPECIFICATIONS PACKAGING DESIGN CONSIDERATIONS ORDERING INFORMATION IBIS MODEL INDEX. INDEX-I
TECHNICAL ASSISTANCE:
Telephone: Email: Internet:
1-800-521-6274 dsphelp@dsp.sps.mot.com http://www.motorola-dsp.com
Data Sheet Conventions
This data sheet uses following conventions:
OVERBAR "asserted" "deasserted" Examples: Used indicate signal that active when pulled (For example, RESET active when low.) Means that high true (active high) signal high that true (active low) signal Means that high true (active high) signal that true (active low) signal high Signal/Symbol
Note:
Logic State True False True False
Signal State Asserted Deasserted Asserted Deasserted
Voltage* VIL/VOL VIH/VOH VIH/VOH VIL/VOL
*Values VIL, VOL, VIH, defined individual product specifications.
DSP56362 Advance Information
PRELIMINARY DSP56362/D
DSP56364 Features
FEATURES
Digital Signal Processing Core
Million Instructions Second (MIPS) with clock 3.3V. Object Code Compatible with 56000 core. Data with multiplier-accumulator 56-bit barrel shifter. 16-bit arithmetic support. Program Control with position independent code support instruction cache support. Six-channel controller. based clocking with wide range frequency multiplications 4096), predivider factors power saving clock divider Reduces clock noise. Internal address tracing support OnCEfor Hardware/Software debugging. JTAG port. Very low-power CMOS design, fully static design with operating frequencies down STOP WAIT low-power standby modes.
On-chip Memory Configuration
1.5Kx24 Y-Data RAM. 1Kx24 X-Data RAM. 8Kx24 Program ROM. 0.5Kx24 Program 192x24 Bootstrap ROM. 0.75Kx24 from Data switched Program resulting 1.25Kx24 Program RAM.
Off-chip memory expansion
External Memory Expansion Port with 8-bit data bus. Off-chip expansion 8-bit word Data/Program memory when using DRAM.
DSP56364 Advance Information
DSP56364 Features
Off-chip expansion 256k 8-bit word Data/Program memory when using SRAM. Simultaneous glueless interface SRAM DRAM.
Peripheral modules
Enhanced Serial Audio Interface (ESAI): serial lines, selectable receive transmitt transmitt only, master slave. I2S, Sony, AC97, network other programmable protocols. Unused pins ESAI used GPIO lines. Serial Host Interface (SHI): protocols, 10-word receive FIFO, support 24-bit words. Four dedicated GPIO lines.
Packaging
100-pin plastic TQFP package.
DSP56364 Advance Information
DSP56364 Documentation
DOCUMENTATION
Table lists documents that provide complete description DSP56364 required design properly with part. Documentation available from local Motorola distributor, Motorola semiconductor sales office, Motorola Literature Distribution Center, through Motorola home page Internet (the source latest information). Table
Document Name DSP56300 Family Manual
DSP56364 Documentation
Description Order Number DSP56300FM/AD
Detailed description 56000-family architecture 24-bit core processor instruction Detailed description memory, peripherals, interfaces Electrical timing specifications; package descriptions
DSP56364 User's Manual DSP56364 Technical Data Sheet
DSP56364UM/AD DSP56364/D
There also product brief this chip. DSP56364 Product Brief Brief description chip DSP56364P/D
DSP56364 Advance Information
DSP56364 Documentation
viii
DSP56364 Advance Information
SECTION SIGNAL/CONNECTION DESCRIPTIONS
SIGNAL GROUPINGS
input output signals DSP56364 organized into functional groups, which listed Table 0-1. illustrated Figure 0-1. DSP56364 operated from supply; however, some inputs tolerate special notice this feature added signal descriptions those inputs. Table 1-1. DSP56364 Functional Signal Groupings
Functional Group Power (VCC) Ground (GND) Clock Address Data control Interrupt mode control General Purpose ESAI JTAG/OnCE Port
Notes:
Port Port
Number Signals Port
Detailed Description Table 0-2. Table 0-3. Table 0-4. Table 0-5. Table 0-6. Table 0-7. Table 0-8. Table 0-12 Table 0-9. Table 0-10. Table 0-11.
Port external memory interface port, including external address bus, data bus, control signals. Port signals GPIO signals. Port signals ESAI port signals multiplexed with GPIO signals.
DSP56364 Advance Information
Signal/Connection Descriptions Signal Groupings
PORT ADDRESS
A0-A17 VCCA GNDA
OnCEON-CHIP EMULATION/ JTAG PORT
DSP56364
Port GPIO
PORT DATA
D0-D7 VCCD GNDD
PB0-PB3
PORT CONTROL
AA0-AA1/RAS0-RAS1 VCCC GNDC RESERVED
SERIAL AUDIO INTERFACE (ESAI) Port
SCKT [PC3] [PC4] HCKT [PC5] SCKR [PC0] [PC1] HCKR [PC2] SDO0 [PC11] SDO1 [PC10] SDO2/SDI3 [PC9] SDO3/SDI2 [PC8] SDO4/SDI1 [PC7] SDO5/SDI0 [PC6] VCCSS GNDS
INTERRUPT MODE CONTROL
MODA/IRQA MODB/IRQB MODD/IRQD RESET
CLOCK
PINIT/NMI PCAP VCCP GNDP EXTAL
SERIAL HOST INTERFACE (SHI)
MOSI/HA0 SS/HA2 MISO/SDA SCK/SCL
HREQ
QUIET POWER
VCCHQ VCCLQ GNDQ
Figure 1-1. Signals Identified Functional Group
DSP56364 Advance Information
Signal/Connection Descriptions Power
POWER
Table 1-2. Power Inputs
Power Name Description Power-VCCP dedicated use. voltage should well-regulated input should provided with extremely impedance path power rail. There VCCP input. Quiet Core (Low) Power-VCCQL isolated power internal processing logic. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There four VCCQL inputs. Quiet External (High) Power-VCCQH quiet power source lines. This input must tied externally other chip power inputs. user must provide adequate decoupling capacitors. There four VCCQH inputs. Address Power-VCCA isolated power sections address drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There four VCCA inputs. Data Power-VCCD isolated power sections data drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There VCCD inputs. Control Power-VCCC isolated power control drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There VCCC inputs. ESAI -VCCS isolated power ESAI. This input must tied externally other chip power inputsL. user must provide adequate external decoupling capacitors. There three VCCS inputs.
VCCP
VCCQL
VCCQH
VCCA
VCCD
VCCC
VCCS
DSP56364 Advance Information
Signal/Connection Descriptions Ground
GROUND
Table 1-3. Grounds
Ground Name Description Ground-GNDP ground-dedicated use. connection should provided with extremely low-impedance path ground. VCCP should bypassed GNDP 0.47 capacitor located close possible chip package. There GNDP connection. Quiet Ground-GNDQ isolated ground internal processing logic. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There four GNDQ connections. Address Ground-GNDA isolated ground sections address drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There four GNDA connections. Data Ground-GNDD isolated ground sections data drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There GNDD connections. Control Ground-GNDC isolated ground control drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There connections. ESAI -GNDS isolated ground ESAI. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There three GNDS connections.
GNDP
GNDQ
GNDA
GNDD
GNDC
GNDS
DSP56364 Advance Information
Signal/Connection Descriptions Clock
CLOCK
Table 1-4. Clock Signals
Signal Name Type State during Reset Signal Description
EXTAL
Input
Input
External Clock Input-An external clock source must connected EXTAL order supply clock internal clock generator PLL. Capacitor-PCAP input connecting off-chip capacitor filter. Connect capacitor terminal PCAP other terminal VCCP. used, PCAP tied VCC, GND, left floating. Initial/Nonmaskable Interrupt-During assertion RESET, value PINIT/NMI written into Enable (PEN) control register, determining whether enabled disabled. After RESET assertion during normal instruction processing, PINIT/NMI Schmitt-trigger input negative-edge-triggered nonmaskable interrupt (NMI) request internally synchronized internal system clock. This input tolerant.
PCAP
Input
Input
PINIT/
Input
Input
DSP56364 Advance Information
Signal/Connection Descriptions External Memory Expansion Port (Port
EXTERNAL MEMORY EXPANSION PORT (PORT
When DSP56364 enters low-power standby mode (stop wait), tri-states relevant port signals: D0-D7, AA0, AA1, CAS.
External Address
Table 1-5. External Address Signals
Signal Name Type State during Reset Signal Description
A0-A17
Outp
Keeper active
Address Bus-A0-A17 active-high outputs that specify address external program data memory accesses. Otherwise, signals kept their previous values internal weak keepers. minimize power dissipation, A0-A17 change state when external memory spaces being accessed.
External Data
Table 1-6. External Data Signals
Signal Name Type State during Reset Signal Description Data Bus-D0-D7 active-high, bidirectional input/ outputs that provide bidirectional data external program data memory accesses. D0-D7 tri-stated during hardware reset when stop wait low-power standby mode.
D0-D7
Input/ Output
Tri-stated
DSP56364 Advance Information
Signal/Connection Descriptions External Memory Expansion Port (Port
External Control
Table 1-7. External Control Signals
Signal Name Type State during Reset Signal Description
AA0- AA1/ RAS0- RAS1
Outp
Tristated
Address Attribute Address Strobe-When defined these signals used chip selects additional address lines. When defined RAS, these signals used DRAM interface. These signals tri-statable outputs with programmable polarity. These signals tri-stated during hardware reset when stop wait low-power standby mode. Column Address Strobe- active-low output used DRAM strobe column address. This signal tri-stated during hardware reset when stop wait low-power standby mode. Read Enable-RD active-low output that asserted read external memory data bus. This signal tri-stated during hardware reset when stop wait low-power standby mode. Write Enable- active-low output that asserted write external memory data bus. This signal tri-stated during hardware reset when stop wait low-power standby mode. Transfer Acknowledge-If there external activity, input ignored. input data transfer acknowledge (DTACK) function that extend external cycle indefinitely. number wait states .infinity) added wait states inserted keeping deasserted. typical operation, deasserted start cycle, asserted enable completion cycle, deasserted before next cycle. current cycle completes clock period after asserted synchronous internal system clock. number wait states determined input control register (BCR), whichever longer. used minimum number wait states external cycles. order functionality, must programmed least wait state. zero wait state access cannot extended deassertion, otherwise improper operation result. operate synchronously asynchronously, depending setting operating mode register (OMR). functionality used while performing DRAM type accesses, otherwise improper operation result.
Outp
Tristated
Outp
Tristated
Outp
Tristated
Input
Ignored Input
DSP56364 Advance Information
Signal/Connection Descriptions Interrupt Mode Control
INTERRUPT MODE CONTROL
interrupt mode control signals select chip's operating mode comes hardware reset. After RESET deasserted, these inputs hardware interrupt request lines. Table 1-8. Interrupt Mode Control
Stat duri Rese
Signal Name
Type
Signal Description
MODA/IRQA
Input
Input
Mode Select A/External Interrupt Request A-MODA/IRQA active-low Schmitt-trigger input, internally synchronized internal system clock. MODA/IRQA selects initial chip operating mode during hardware reset becomes level-sensitive negativeedge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODD select initial chip operating modes, latched into when RESET signal deasserted. IRQA asserted synchronous internal system clock, multiple processors synchronized using WAIT instruction asserting IRQA exit wait state. processor stop standby state IRQA asserted, processor will exit stop state. This input tolerant Mode Select B/External Interrupt Request B-MODB/IRQB active-low Schmitt-trigger input, internally synchronized internal system clock. MODB/IRQB selects initial chip operating mode during hardware reset becomes level-sensitive negativeedge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODD select initial chip operating modes, latched into when RESET signal deasserted. IRQB asserted synchronous internal system clock, multiple processors re-synchronized using WAIT instruction asserting IRQB exit wait state. This input tolerant.
MODB/IRQB
Input
Input
DSP56364 Advance Information
Signal/Connection Descriptions Interrupt Mode Control
Table 1-8. Interrupt Mode Control (Continued)
Stat duri Rese
Signal Name
Type
Signal Description
MODD/IRQD
Input
Input
Mode Select D/External Interrupt Request D-MODD/IRQD active-low Schmitt-trigger input, internally synchronized internal system clock. MODD/IRQD selects initial chip operating mode during hardware reset becomes level-sensitive negativeedge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODD select initial chip operating modes, latched into when RESET signal deasserted. IRQD asserted synchronous internal system clock, multiple processors synchronized using WAIT instruction asserting IRQD exit wait state. This input tolerant. Reset-RESET active-low, Schmitt-trigger input. When asserted, chip placed reset state internal phase generator reset. Schmitt-trigger input allows slowly rising input (such capacitor charging) reset chip reliably. When RESET signal deasserted, initial chip operating mode latched from MODA, MODB, MODD inputs. RESET signal must asserted during power stable EXTAL signal must supplied before deassertionof RESET. This input tolerant.
RESET
Input
Input
DSP56364 Advance Information
Signal/Connection Descriptions Serial Host Interface
SERIAL HOST INTERFACE
five signals that configured allow operate either mode. Table 1-9. Serial Host Interface Signals
Signal Name Signal Type State during Reset Signal Description
Input output
Tristated Input output
Serial Clock-The signal output when configured master Schmitt-trigger input when configured slave. When configured master, signal derived from internal clock generator. When configured slave, signal input, clock signal from external master synchronizes data transfer. signal ignored defined slave slave select (SS) signal asserted. both master slave devices, data shifted edge signal sampled opposite edge where data stable. Edge polarity determined transfer protocol. Serial Clock-SCL carries clock transactions mode. Schmitt-trigger input when configured slave open-drain output when configured master. should connected through pull-up resistor. This signal tri-stated during hardware, software, individual reset. Thus, there need external pull-up this state. This input tolerant.
1-10
DSP56364 Advance Information
Signal/Connection Descriptions Serial Host Interface
Table 1-9. Serial Host Interface Signals (Continued)
Signal Name Signal Type State during Reset Signal Description
MISO
Input output
Master-In-Slave-Out-When configured master, MISO master data input line. MISO signal used conjunction with MOSI signal transmitting receiving serial data. This signal Schmitt-trigger input when configured Master mode, output when configured Slave mode, tri-stated configured Slave mode when deasserted. external pull-up resistor required operation. Data Acknowledge-In mode, Schmitt-trigger input when receiving open-drain output when transmitting. should connected through pull-up resistor. carries data transactions. data must stable during high period SCL. data only allowed change when low. When free, high. line only allowed change during time high case start stop events. high-to-low transition line while high unique situation, defined start event. low-to-high transition while high unique situation defined stop event. This signal tri-stated during hardware, software, individual reset. Thus, there need external pull-up this state. This input tolerant. Master-Out-Slave-In-When configured master, MOSI master data output line. MOSI signal used conjunction with MISO signal transmitting receiving serial data. MOSI slave data input line when configured slave. This signal Schmitt-trigger input when configured Slave mode. Tristated Slave Address 0-This signal uses Schmitt-trigger input when configured mode. When configured slave mode, signal used form slave device address. ignored when configured master mode. This signal tri-stated during hardware, software, individual reset. Thus, there need external pull-up this state. This input tolerant.
Input opendrain output
Tristated
MOSI
Input output
Input
DSP56364 Advance Information
1-11
Signal/Connection Descriptions Serial Host Interface
Table 1-9. Serial Host Interface Signals (Continued)
Signal Name Signal Type State during Reset Signal Description
Input Input
Slave Select-This signal active Schmitt-trigger input when configured mode. When configured Slave mode, this signal used enable slave transfer. When configured master mode, this signal should kept deasserted (pulled high). asserted while configured master, error condition flagged. deasserted, ignores clocks keeps MISO output signal highimpedance state. Slave Address 2-This signal uses Schmitt-trigger input when configured mode. When configured Slave mode, signal used form slave device address. ignored master mode. This signal tri-stated during hardware, software, individual reset. Thus, there need external pull-up this state.
This input tolerant.
Input Output Host Request-This signal active Schmitt-trigger input when configured master mode active output when configured slave mode. When configured slave mode, HREQ asserted indicate that ready next data word transfer deasserted first clock pulse data word transfer. When configured master mode, HREQ input. When asserted external slave device, will trigger start data word transfer master. After finishing data word transfer, master will await next assertion HREQ proceed next transfer. This signal tri-stated during hardware, software, personal reset, when HREQ1-HREQ0 bits HCSR cleared. There need external pull-up this state.
HREQ
Tristated
This input tolerant.
1-12
DSP56364 Advance Information
Signal/Connection Descriptions Enhanced Serial Audio Interface
ENHANCED SERIAL AUDIO INTERFACE
Table 1-10. Enhanced Serial Audio Interface Signals
Signal Name Signal Type State during Reset Signal Description High Frequency Clock Receiver-When programmed input, this signal provides high frequency clock source ESAI receiver alternate core clock. When programmed output, this signal serve high-frequency sample clock (e.g., external digital analog converters [DACs]) additional system clock. GPIO disconnected Port 2-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected.
HCKR
Input output
Input, output, disconnected
This input tolerant.
High Frequency Clock Transmitter-When programmed input, this signal provides high frequency clock source ESAI transmitter alternate core clock. When programmed output, this signal serve high frequency sample clock (e.g., external DACs) additional system clock. Port 5-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
HCKT
Input output
Input, output, disconnected
GPIO disconnected
DSP56364 Advance Information
1-13
Signal/Connection Descriptions Enhanced Serial Audio Interface
Table 1-10. Enhanced Serial Audio Interface Signals (Continued)
Signal Name Signal Type State during Reset Signal Description Frame Sync Receiver-This receiver frame sync input/output signal. asynchronous mode (SYN=0), operates frame sync input output used enabled receivers. synchronous mode (SYN=1), operates either serial flag (TEBE=0), transmitter external buffer enable control (TEBE=1, RFSD=1). Input output When this configured serial flag pin, direction determined RFSD RCCR register. When configured output flag OF1, this will reflect value SAICR register, data will show synchronized frame sync normal mode slot network mode. When configured input flag IF1, data value will stored SAISR register, synchronized frame sync normal mode slot network mode. Port 1-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant. Frame Sync Transmitter-This transmitter frame sync input/output signal. synchronous mode, this signal frame sync both transmitters receivers. asynchronous mode, frame sync transmitters only. direction determined transmitter frame sync direction (TFSD) ESAI transmit clock control register (TCCR). GPIO disconnected Input, output, disconnected Port 4-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
GPIO disconnected
Input, output, disconnected
Input output
1-14
DSP56364 Advance Information
Signal/Connection Descriptions Enhanced Serial Audio Interface
Table 1-10. Enhanced Serial Audio Interface Signals (Continued)
Signal Name Signal Type State during Reset Signal Description Receiver Serial Clock-SCKR provides receiver serial clock ESAI. SCKR operates clock input output used enabled receivers asynchronous mode (SYN=0), serial flag synchronous mode (SYN=1). When this configured serial flag pin, direction determined RCKD RCCR register. When configured output flag OF0, this will reflect value SAICR register, data will show synchronized frame sync normal mode slot network mode. When configured input flag IF0, data value will stored SAISR register, synchronized frame sync normal mode slot network mode. Port 0-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant. Transmitter Serial Clock-This signal provides serial rate clock ESAI. SCKT clock input output used enabled transmitters receivers synchronous mode, enabled transmitters asynchronous mode. GPIO disconnected Port 3-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
SCKR
Input output
GPIO disconnected
Input, output, disconnected
SCKT
Input output
Input, output, disconnected
DSP56364 Advance Information
1-15
Signal/Connection Descriptions Enhanced Serial Audio Interface
Table 1-10. Enhanced Serial Audio Interface Signals (Continued)
Signal Name Signal Type State during Reset Signal Description Serial Data Output 5-When programmed transmitter, SDO5 used transmit data from serial transmit shift register. Serial Data Input 0-When programmed receiver, SDI0 used receive serial data into serial receive shift register. Port 6-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant. Serial Data Output 4-When programmed transmitter, SDO4 used transmit data from serial transmit shift register. Serial Data Input 1-When programmed receiver, SDI1 used receive serial data into serial receive shift register. Port 7-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
SDO5
Output
SDI0
Input GPIO disconnected
Input, output, disconnected
SDO4
Output
SDI1
Input GPIO disconnected
Input, output, disconnected
1-16
DSP56364 Advance Information
Signal/Connection Descriptions Enhanced Serial Audio Interface
Table 1-10. Enhanced Serial Audio Interface Signals (Continued)
Signal Name Signal Type State during Reset Signal Description Serial Data Output 3-When programmed transmitter, SDO3 used transmit data from serial transmit shift register. Serial Data Input 2-When programmed receiver, SDI2 used receive serial data into serial receive shift register. Port 8-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant. Serial Data Output 2-When programmed transmitter, SDO2 used transmit data from serial transmit shift register Serial Data Input 3-When programmed receiver, SDI3 used receive serial data into serial receive shift register. Port 9-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant. SDO1 Output Input, output, disconnected Serial Data Output 1-SDO1 used transmit data from serial transmit shift register. Port 10-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
SDO3
Output
SDI2
Input GPIO disconnected
Input, output, disconnected
SDO2
Output
SDI3
Input GPIO disconnected
Input, output, disconnected
PC10
GPIO disconnected
DSP56364 Advance Information
1-17
Signal/Connection Descriptions JTAG/OnCE Interface
Table 1-10. Enhanced Serial Audio Interface Signals (Continued)
Signal Name SDO0 Signal Type State during Reset Signal Description Serial Data Output 0-SDO0 used transmit data from serial transmit shift register. Port 11-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
Output Input, output, disconnected
PC11
GPIO disconnected
JTAG/OnCE INTERFACE
Table 1-11. JTAG/OnCE Interface
Signal Name Signal Type State during Reset Signal Description
Input
Input
Test Clock-TCK test clock input signal used synchronize JTAG test logic. internal pull-up resistor.
This input tolerant.
Test Data Input-TDI test data serial input signal used test instructions data. sampled rising edge internal pull-up resistor. This input tolerant. Test Data Output-TDO test data serial output signal used test instructions data. tri-statable actively driven shift-IR shift-DR controller states. changes falling edge TCK. Test Mode Select-TMS input signal used sequence test controller's state machine. sampled rising edge internal pull-up resistor. This input tolerant.
Input
Input
Output
Tristated
Input
Input
1-18
DSP56364 Advance Information
Signal/Connection Descriptions JTAG/OnCE Interface
Table 1-12. GPIO Signals
Signal Name Signal Type State during Reset Signal Description
GPIO0GPIO3
Input, output disconnecte
disconn ected
GPIO0-3- General Purpose pins used control handshake functions between external circuitry. Each Port GPIO individually programmed input, output disconnected
DSP56364 Advance Information
1-19
Signal/Connection Descriptions JTAG/OnCE Interface
1-20
DSP56364 Advance Information
SECTION SPECIFICATIONS
INTRODUCTION
DSP56364 high density CMOS device with Transistor-Transistor Logic (TTL) compatible inputs outputs. DSP56364 specifications preliminary from design simulations, fully tested guaranteed. Finalized specifications will published after full characterization device qualifications complete.
MAXIMUM RATINGS
CAUTION
This device contains circuitry protecting against damage high static voltage electrical fields. However, normal precautions should taken avoid exceeding maximum voltage ratings. Reliability operation enhanced unused inputs pulled appropriate logic voltage level (e.g., either VCC). suggested value pullup pulldown resistor
Note: calculation timing requirements, adding maximum value specification minimum value another specification does yield reasonable sum. maximum specification calculated using worst case variation process parameter values direction. minimum specification calculated using worst case same parameters opposite direction. Therefore, "maximum" value specification will never occur same device that "minimum" value another specification; adding maximum minimum represents condition that never exist.
DSP56364 Advance Information
Specifications Thermal Characteristics
Table 2-1. Maximum Ratings
Rating1 Supply Voltage input voltages excluding tolerant" inputs3 tolerant" input voltages3 Current drain excluding Operating temperature range Storage temperature
Notes:
Symbol VIN5 TSTG
Value1,
Unit
-0.3 +4.0
-0.3 3.95 +105
+125
0.16 -0°C +105°C, Absolute maximum ratings stress ratings only, functional operation maximum guaranteed. Stress beyond maximum rating affect device reliability cause permanent damage device. CAUTION: Tolerant" input voltages must more than 3.95 greater than supply voltage; this restriction applies "power on", well during normal operation. case, input voltages cannot more than 5.75 Tolerant" inputs inputs that tolerate
THERMAL CHARACTERISTICS
Table 2-2. Thermal Characteristics
Characteristic Junction-to-ambient thermal resistance1 Junction-to-case thermal resistance2 Thermal characterization parameter
Notes:
Symbol
TQFP Value 49.87 9.26
Unit
°C/W °C/W °C/W
Junction-to-ambient thermal resistance based measurements horizontal single-sided printed circuit board SEMI G38-87 natural convection.(SEMI Semiconductor Equipment Materials International, East Middlefield Rd., Mountain View, 94043, (415) 964-5111.) Measurements were done with parts mounted thermal test boards conforming specification EIA/ JESD51-3. Junction-to-case thermal resistance based measurements using cold plate SEMI G30-88, with exception that cold plate temperature used case temperature.
DSP56364 Advance Information
Specifications Electrical Characteristics
ELECTRICAL CHARACTERISTICS
Table 2-3. Electrical Characteristics6
Characteristics Supply voltage Input high voltage D(0:7), MOD1/IRQ1, RESET, PINIT/NMI JTAG/ESAI/GPIO/SHI (SPI mode)pins (I2C mode) pins EXTAL8 Input voltage D(0:7), MOD1/IRQ1, RESET, PINIT JTAG/ESAI/GPIO/SHI (SPI mode)pins (I2C mode) pins EXTAL8 Input leakage current High impedance (off-state) input current Output high voltage (IOH -0.4 mA)5,7 CMOS (IOH µA)5 Output voltage (IOL open-drain pins mA)5,7 CMOS (IOL µA)5 Internal supply current2 internal clock 100Mhz Normal mode Wait mode3 Stop mode4 Symbol VIHP VIHP VIHX 3.14 3.46 3.95 3.95 Unit
-0.3 -0.3 -0.3 -0.3
0.3xVCC
VILP VILP VILX ITSI
0.01
0.01
ICCI ICCW ICCS
DSP56364 Advance Information
Specifications Electrical Characteristics
Table 2-3. Electrical Characteristics6 (Continued)
Characteristics supply current Input capacitance5
Notes:
Symbol
Unit
Refers MODA/IRQA, MODB/IRQB, MODD/IRQD pins Power Consumption Considerations page provides formula compute estimated current requirements Normal mode. order obtain these results, inputs must terminated (i.e., allowed float). Measurements based synthetic intensive benchmarks. power consumption numbers this specification measured results this benchmark. This reflects typical applications. Typical internal supply current measured with 105°C. Maximum internal supply current measured with 3.46 105°C. order obtain these results, inputs must terminated (i.e., allowed float). signal disabled during Stop state. order obtain these results, inputs, which disconnected Stop mode, must terminated (i.e., allowed float). Periodically sampled 100% tested +105°C, This characteristic does apply PCAP. Driving EXTAL VIHX high VILX value cause additional power consumption current). minimize power consumption, minimum VIHX should lower than maximum VILX should higher than VCC.
DSP56364 Advance Information
Specifications Electrical Characteristics
ELECTRICAL CHARACTERISTICS
timing waveforms shown electrical characteristics section tested with maximum minimum pins except EXTAL, which tested using input levels shown Note previous table. timing specifications, which referenced device input signal, measured production with respect point respective input signal's transition. DSP56364 output levels measured with production test machine reference levels respectively. Note: Although minimum value frequency EXTAL MHz, device test conditions rated speed.
DSP56364 Advance Information
Specifications Internal Clocks
INTERNAL CLOCKS
Table 2-4. Internal Clocks
Expression1, Characteristics Symbol
Internal operation frequency with enabled Internal operation frequency with disabled Internal clock high period With disabled With enabled With enabled Internal clock period With disabled With enabled With enabled Internal clock cycle time with enabled Internal clock cycle time with disabled Instruction cycle time Notes: ICYC 0.49 DF/MF 0.47 DF/MF DF/MF 0.51 DF/MF 0.53 DF/MF 0.49 DF/MF 0.47 DF/MF 0.51 DF/MF 0.53 DF/MF
MF)/ (PDF Ef/2
Division Factor External frequency External clock cycle Multiplication Factor Predivision Factor internal clock cycle Clock Generation section DSP56300 detailed discussion PLL.
Family Manual
DSP56364 Advance Information
Specifications EXTERNAL CLOCK OPERATION
EXTERNAL CLOCK OPERATION
DSP56364 system clock externally supplied square wave voltage source connected EXTAL(Figure 2-1.).
VIHC EXTAL VILC Midpoint
Note:
midpoint (VIHC VILC).
Figure 2-1. External Clock Timing
Table 2-5. Clock Operation
Characteristics Frequency EXTAL (EXTAL Frequency) rise fall time this external clock should maximum. EXTAL input high1, With disabled (46.7%-53.3% duty cycle6) With enabled (42.5%-57.5% duty cycle6) EXTAL input low1, With disabled (46.7%-53.3% duty cycle6) With enabled (42.5%-57.5% duty cycle6) EXTAL cycle time2 With disabled With enabled
Notes:
Symbol
100.0
4.67 4.25
157.0
4.67 4.25
157.0 273.1
10.00 10.00
Measured input transition maximum value enabled given minimum maximum
DSP56364 Advance Information
Specifications Phase Lock Loop (PLL) Characteristics
PHASE LOCK LOOP (PLL) CHARACTERISTICS
Table 2-6. Characteristics
Characteristics frequency when enabled 2/PDF) external capacitor (PCAP VCCP) (CPCAP1)
Notes:
Unit
580)
780) 1470
CPCAP value capacitor (connected between PCAP VCCP). recommended value CPCAP computed from following equations: 680)-120, 1100,
DSP56364 Advance Information
Specifications Reset, Stop, Mode Select, Interrupt Timing
RESET, STOP, MODE SELECT, INTERRUPT TIMING
Table 2-7. Reset, Stop, Mode Select, Interrupt Timing6
Characteristics Delay from RESET assertion pins reset value3 Required RESET duration4 Power external clock generator, disabled Power external clock generator, enabled Power internal oscillator During STOP, XTAL disabled (PCTL During STOP, XTAL enabled (PCTL During normal operation Delay from asynchronous RESET deassertion first external address output (internal reset deassertion)5 Minimum Maximum Mode select setup time Mode select hold time Minimum edge-triggered interrupt request assertion width Minimum edge-triggered interrupt request deassertion width Expression 26.0 Unit
1000 75000 75000
500.0 10.0 0.75 0.75 25.0 25.0
3.25 20.25 7.50
34.5 30.0
211.5
Delay from IRQA, IRQB, IRQD, assertion external memory access address valid Caused first interrupt instruction fetch Caused first interrupt instruction execution Delay from IRQA, IRQB, IRQD, assertion general-purpose transfer output valid caused first interrupt instruction execution
4.25 7.25
44.5 74.5
105.0
DSP56364 Advance Information
Specifications Reset, Stop, Mode Select, Interrupt Timing
Table 2-7. Reset, Stop, Mode Select, Interrupt Timing6 (Continued)
Characteristics Expression Unit
Delay from address output valid caused first interrupt instruction execute interrupt request 3.75 10.94 deassertion level sensitive fast interrupts1 Delay from assertion interrupt request deassertion level sensitive fast interrupts1 Delay from assertion interrupt request deassertion level sensitive fast interrupts1 DRAM SRAM SRAM SRAM Duration IRQA assertion recover from Stop state Delay from IRQA assertion fetch first instruction (when exiting Stop)2, active during Stop (PCTL Stop delay enabled (OMR active during Stop (PCTL Stop delay enabled (OMR 3.5) 10.94 3.5) 10.94 10.94 2.5) 10.94 3.25 10.94
(128 PLC/2)
13.6
(23.75 232.5 0.5) 77.5
12.3 87.5
active during Stop (PCTL (8.25 0.5) (Implies Stop Delay) Duration level sensitive IRQA assertion ensure interrupt service (when exiting Stop)2, active during Stop (PCTL Stop delay enabled (OMR active during Stop (PCTL Stop delay enabled (OMR active during Stop (PCTL (implies Stop delay)
(128K PLC/2) (20.5 0.5)
13.6
12.3
55.0
2-10
DSP56364 Advance Information
Specifications Reset, Stop, Mode Select, Interrupt Timing
Table 2-7. Reset, Stop, Mode Select, Interrupt Timing6 (Continued)
Characteristics Interrupt Requests Rate ESAI, IRQ, (edge trigger) IRQ, (level trigger) Requests Rate Data read from ESAI, Data write ESAI, IRQ, (edge trigger) Expression 12TC 12TC 120.0 80.0 80.0 120.0 60.0 70.0 30.0 Unit
DSP56364 Advance Information
2-11
Specifications Reset, Stop, Mode Select, Interrupt Timing
Table 2-7. Reset, Stop, Mode Select, Interrupt Timing6 (Continued)
Characteristics Expression 4.25 44.0 Unit
Delay from IRQA, IRQB, IRQD, assertion external memory (DMA source) access address valid
Notes:
When using fast interrupts IRQA, IRQB, IRQD defined level-sensitive, timings through apply prevent multiple interrupt service. avoid these timing restrictions, deasserted Edge-triggered mode recommended when using fast interrupts. Long interrupts recommended when using Level-sensitive mode. This timing depends several settings: disable, using internal oscillator (PLL Control Register (PCTL) oscillator disabled during Stop (PCTL stabilization delay required assure oscillator stable before executing programs. that case, resetting Stop delay (OMR will provide proper delay. While possible recommended these specifications guarantee timings that case. disable, using internal oscillator (PCTL oscillator enabled during Stop (PCTL 17=1), stabilization delay required recovery time will minimal (OMR setting ignored). disable, using external clock (PCTL stabilization delay required recovery time will defined PCTL settings. enable, PCTL shutdown during Stop. Recovering from Stop requires locked. lock procedure duration, Lock Cycles (PLC), range 1000 cycles. This procedure occurs parallel with stop delay counter, stop recovery will when last these events occurs. stop delay counter completes count lock procedure completion. value disable maximum value 4096 (maximum divided desired internal frequency (i.e., 4096/100 µs). During stabilization period, will constant, their width vary, timing vary well.
Periodically sampled 100% tested external clock generator, RESET duration measured during time which RESET asserted, valid, EXTAL input active valid. internal oscillator, RESET duration measured during time which RESET asserted valid. specified timing reflects crystal oscillator stabilization time after power-up. This number affected both specifications crystal other components connected oscillator reflects worst case conditions. When valid, other "required RESET duration" conditions specified above) have been met, device circuitry will uninitialized state that result significant power consumption heat-up. Designs should minimize this state shortest possible duration.
2-12
DSP56364 Advance Information
Specifications Reset, Stop, Mode Select, Interrupt Timing
Table 2-7. Reset, Stop, Mode Select, Interrupt Timing6 (Continued)
Characteristics
Expression
Unit
external clock generator, RESET duration measured during time which RESET asserted, valid, EXTAL input active valid. internal oscillator, RESET duration measured during time which RESET asserted valid. specified timing reflects crystal oscillator stabilization time after power-up. This number affected both specifications crystal other components connected oscillator reflects worst case conditions. When valid, other "required RESET duration" conditions specified above) have been met, device circuitry will uninitialized state that result significant power consumption heat-up. Designs should minimize this state shortest possible duration. does lose lock 0.16 105°C, number wait states (measured clock cycles, number expression compute maximum value.
RESET Pins Reset Value
A0-A17
First Fetch
AA0460
Figure 2-2. Reset Timing
DSP56364 Advance Information
2-13
Specifications Reset, Stop, Mode Select, Interrupt Timing
A0-A17
First Interrupt Instruction Execution/Fetch
IRQA, IRQB, IRQD,
First Interrupt Instruction Execution
General Purpose IRQA, IRQB, IRQD,
General Purpose
AA0462
Figure 2-3. External Fast Interrupt Timing
2-14
DSP56364 Advance Information
Specifications Reset, Stop, Mode Select, Interrupt Timing
IRQA, IRQB, IRQD, IRQA, IRQB, IRQD,
AA0463
Figure 2-4. External Interrupt Timing (Negative Edge-Triggered)
RESET
MODA, MODB,MODD, PINIT
IRQA, IRQB, IRQD,
AA0465
Figure 2-5. Operating Mode Select Timing
IRQA
First Instruction Fetch
AA0466
A0-A17
Figure 2-6. Recovery from Stop State Using IRQA
DSP56364 Advance Information
2-15
Specifications Reset, Stop, Mode Select, Interrupt Timing
IRQA A0-A17
First IRQA Interrupt Instruction Fetch AA0467
Figure 2-7. Recovery from Stop State Using IRQA Interrupt Service
A0-A17
Source Address
IRQA, IRQB, IRQD, First Interrupt Instruction Execution
AA1104
Figure 2-8. External Memory Access (DMA Source) Timing
2-16
DSP56364 Advance Information
Specifications External Memory Expansion Port (Port
EXTERNAL MEMORY EXPANSION PORT (PORT
SRAM Timing
Table 2-8. SRAM Read Write Accesses3
Characteristics Symbol Expression1 tRC, Address valid assertion 0.25 0.75 1.25 assertion pulse width 16.0 56.0 106.0 10.5 Unit
Address valid assertion pulse width
11.0 frequencies: 0.5) 16.0
31.0
DSP56364 Advance Information
2-17
Specifications External Memory Expansion Port (Port
Table 2-8. SRAM Read Write Accesses3 (Continued)
Characteristics deassertion address valid Symbol Expression1 0.25 1.25 2.25 frequencies: 1.25 2.25 Address valid input data valid assertion input data valid deassertion data valid (data hold time) tAA, tOHZ (tDW) 0.75) 0.25) 0.25 1.25 2.25 deassertion time 0.75 1.75 2.75 0.75) 0.25) 10.5 20.5 Unit
18.5 13.5 10.5 20.5 13.5 23.5
10.5
Address valid deassertion2 Data valid deassertion (data setup time) Data hold time from deassertion
2-18
DSP56364 Advance Information
Specifications External Memory Expansion Port (Port
Table 2-8. SRAM Read Write Accesses3 (Continued)
Characteristics deassertion time Symbol Expression1 Address valid assertion assertion pulse width deassertion address valid 0.25) -4.0 0.25 1.25 2.25 setup before deassertion4 hold after deassertion
Notes:
21.0 31.0 10.5 20.5
Unit
0.25
number wait states specified BCR. Timings 100, guaranteed design, tested. timings measured from case negation: timing relative deassertion edge were remain active
DSP56364 Advance Information
2-19
Specifications External Memory Expansion Port (Port
A0-A17 AA0-AA1 D0-D7 Data
AA0468
Figure 2-9. SRAM Read Access
2-20
DSP56364 Advance Information
Specifications External Memory Expansion Port (Port
A0-A17 AA0-AA3 D0-D23 Data
AA0469
Figure 2-10. SRAM Write Access
DSP56364 Advance Information
2-21
Specifications External Memory Expansion Port (Port
DRAM Timing
selection guides provided Figure 2-11. Figure 2-14. should used primary selection only. Final selection should based timing provided following tables. example, selection guide suggests that wait states must used operation when using Page Mode DRAM. However, using information appropriate table, designer choose evaluate whether fewer wait states might used determining which timing prevents operation MHz, running chip slightly lower frequency (e.g., MHz), using faster DRAM becomes available), control factors such capacitive resistive load improve overall system performance.
DRAM Type (tRAC
Note:
This figure should primary selection. exact detailed timings following tables.
Chip Frequency (MHz)
Wait States Wait States
Wait States Wait States
AA047
Figure 2-11. DRAM Page Mode Wait States Selection Guide
2-22
DSP56364 Advance Information
Specifications External Memory Expansion Port (Port
Table 2-9. DRAM Page Mode Timings, Wait State (Low-Power Applications)1,
MHz6 Characteristics Symbol Expression Page mode cycle time consecutive accesses same direction Page mode cycle time mixed (read write) accesses assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) Last assertion deassertion Previous deassertion deassertion assertion pulse width Last deassertion deassertion4 BRW[1:0] BRW[1:0] BRW[1:0] BRW[1:0] deassertion pulse width Column address valid assertion assertion column address valid Last column address valid deassertion tASC tCAH tRAL 1.25 62.5 41.7 MHz6 Unit
100.0
66.7
tCAC tOFF tRSH tRHCP tCAS tCRP
42.5 67.5
21.0 62.7 21.0 52.3 102.2 135.5
25.8 42.5
0.75 0.75 1.75
33.5 96.0 33.5 81.5
3.25 156.5 4.25 206.5 6.25 306.5 0.75 21.0 21.0 33.5 96.0
202.1 12.7 12.7 21.0 62.7
DSP56364 Advance Information
2-23
Specifications External Memory Expansion Port (Port
Table 2-9. DRAM Page Mode Timings, Wait State (Low-Power Applications)1,
MHz6 Characteristics Symbol Expression
Notes:
MHz6 Unit 21.2 12.5 45.5 54.0 54.0 21.0 29.0 46.0 24.7 25.8
42.5 12.5
deassertion assertion deassertion assertion assertion deassertion assertion pulse width Last assertion deassertion assertion deassertion Data valid assertion (Write) assertion data valid (write) assertion assertion Last assertion deassertion assertion data valid deassertion data valid assertion data active deassertion data high impedance
tRCS tRCH tWCH tRWL tCWL tWCS tROH
0.75 0.25 1.75 1.75 0.25 0.75
33.7 20.8 70.5 83.2 83.2 33.5 45.7 71.0
0.75 0.25
37.2
number wait states Page mode access specified DCR. refresh period specified DCR. timings calculated worst case. Some timings better specific cases (e.g., equals read-after-read write-after-write sequences). BRW[1:0] (DRAM control register bits) defines number wait states that should inserted each DRAM out-of-page access. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. Reduced clock speed allows Page Mode DRAM with Wait state (See Figure 2-14.).
2-24
DSP56364 Advance Information
Specifications External Memory Expansion Port (Port
Table 2-10. DRAM Page Mode Timings, Wait States1,
Characteristics Page mode cycle time consecutive accesses same direction Page mode cycle time mixed (read write) accesses assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) Last assertion deassertion Previous deassertion deassertion 1.25 41.1 1.75 3.25 tASC tCAH 1.25 1.75 22.5 45.2 18.7 24.4 47.2 62.4 92.8 14.9 11.2 22.5 15.2 30.4 34.4 17.9 36.6 14.8 19.0 37.8 50.3 75.3 11.6 17.9 12.3 24.8 Symbol Expression Unit
45.4
37.5
tCAC
tOFF tRSH tRHCP tCAS tCRP
assertion pulse width Last deassertion deassertion5 BRW[1:0] BRW[1:0] BRW[1:0] BRW[1:0] deassertion pulse width Column address valid assertion assertion column address valid
DSP56364 Advance Information
2-25
Specifications External Memory Expansion Port (Port
Table 2-10. DRAM Page Mode Timings, Wait States1, (Continued)
Characteristics Last column address valid deassertion deassertion assertion deassertion assertion assertion deassertion Symbol Expression tRAL tRCS tRCH tWCH tRWL tCWL 1.25 2.75 0.25 0.25 1.75 1.75 assertion data valid 1.75 deassertion data valid6 0.75 0.25 11.1 15.4 41.5 15.1 18.5 33.5 33.4 33.6 22.5 10.9 33.9 19.0 33.5 11.8 14.6 26.8 26.8 27.0 17.9 27.3 Unit
assertion pulse width Last assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion assertion Last assertion deassertion
tWCS tROH
assertion data active deassertion data high impedance
2-26
DSP56364 Advance Information
Specifications External Memory Expansion Port (Port
Table 2-10. DRAM Page Mode Timings, Wait States1, (Continued)
Notes:
Unit
Characteristics
Symbol
Expression
number wait states Page mode access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56364. timings calculated worst case. Some timings better specific cases (e.g., equals read-after-read write-after-write sequences). BRW[1:0] (DRAM Control Register bits) defines number wait states that should inserted each DRAM out-of-page access. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. There DRAMs fast enough wait states Page mode 100MHz (See Figure 2-11.)
Table 2-11. DRAM Page Mode Timings, Three Wait States1,
Characteristics Page mode cycle time consecutive accesses same direction Page mode cycle time mixed (read write) accesses assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) Last assertion deassertion Previous deassertion deassertion assertion pulse width Last deassertion assertion5 BRW[1:0] BRW[1:0] BRW[1:0] BRW[1:0] deassertion pulse width Column address valid assertion assertion column address valid tASC tCAH 1.25 tCAC tOFF tRSH tRHCP tCAS tCRP 35.0 21.0 41.0 2.25 3.75 16.0 13.0 23.0 Symbol Expression Unit 40.0
4.75 41.5 6.75 61.5 11.0
21.0
DSP56364 Advance Information
2-27
Specifications External Memory Expansion Port (Port
Table 2-11. DRAM Page Mode Timings, Three Wait States1, (Continued)
Characteristics Symbol tRAL tRCS tRCH tWCH tRWL tCWL tWCS tROH Expression Unit 36.0 18.0
Last column address valid deassertion deassertion assertion deassertion assertion assertion deassertion assertion pulse width Last assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion assertion Last assertion deassertion assertion data valid deassertion data valid6 assertion data active deassertion data high impedance
Notes:
1.25 0.75
2.25 18.3 30.5 3.75 33.2 3.25 28.2
21.0 1.25 31.0 0.75 0.25
number wait states Page mode access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56364. timings calculated worst case. Some timings better specific cases (e.g., equals read-after-read write-after-write sequences). BRW[1:0] (DRAM control register bits) defines number wait states that should inserted each DRAM out-of page-access. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ.
2-28
DSP56364 Advance Information
Specifications External Memory Expansion Port (Port
Table 2-12. DRAM Page Mode Timings, Four Wait States1,
Characteristics Page mode cycle time consecutive accesses same direction. Page mode cycle time mixed (read write) accesses assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) Last assertion deassertion Previous deassertion deassertion assertion pulse width Last deassertion assertion5 BRW[1:0] BRW[1:0] BRW[1:0] BRW[1:0] deassertion pulse width Column address valid assertion assertion column address valid Last column address valid deassertion deassertion assertion deassertion assertion assertion deassertion assertion pulse width Last assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion assertion tASC tCAH tRAL tRCS tRCH tWCH tRWL tCWL tWCS 1.25 tCAC tOFF tRSH tRHCP tCAS tCRP 2.75 4.25 2.75 3.75 45.0 31.0 56.0 21.0 20.5 30.5 Symbol Expression 50.0
5.25 46.5 7.25 66.5 1.25 1.25 16.0 31.0 46.0
3.25 28.3 40.5
4.75 43.2 3.75 33.2 1.25 31.0
DSP56364 Advance Information
2-29
Specifications External Memory Expansion Port (Port
Table 2-12. DRAM Page Mode Timings, Four Wait States1, (Continued)
Characteristics Symbol tROH 0.75 0.25 Expression 3.25 41.0 25.5
Last assertion deassertion assertion data valid deassertion data valid6 assertion data active deassertion data high impedance
Notes:
number wait states Page mode access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56364. timings calculated worst case. Some timings better specific cases (e.g., equals read-after-read write-after-write sequences). BRW[1:0] (DRAM control register bits) defines number wait states that should inserted each DRAM out-of-page access. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ.
2-30
DSP56364 Advance Information
Specifications External Memory Expansion Port (Port
A0-A17
Column Address Column Address
Last Column Address
D0-D7
Data Data Data AA0473
Figure 2-12. DRAM Page Mode Write Accesses
DSP56364 Advance Information
2-31
Specifications External Memory Expansion Port (Port
A0-A17
Column Address
Column Address
Last Column Address
D0-D7
Data Data Data AA0474
Figure 2-13. DRAM Page Mode Read Accesses
2-32
DSP56364 Advance Information
Specifications External Memory Expansion Port (Port
DRAM Type (tRAC
Note:
This figure should primary selection. exact detailed timings following tables.
Wait States Wait States
Chip Frequency (MHz)
Wait States Wait States
AA0475
Figure 2-14. DRAM Out-of-Page Wait States Selection Guide
Table 2-13. DRAM Out-of-Page Refresh Timings, Four Wait States1,
Characteristics3 Random read write cycle time assertion data valid (read) assertion data valid (read) Column address valid data valid (read) Symbol Expression MHz4 tRAC tCAC 2.75 1.25 250.0 130.0 55.0 67.5 MHz4 166.7 84.2 34.2 42.5 Unit
DSP56364 Advance Information
2-33
Specifications External Memory Expansion Port (Port
Table 2-13. DRAM Out-of-Page Refresh Timings, Four Wait States1, (Continued)
Characteristics3 deassertion data valid (read hold time) deassertion assertion Symbol Expression MHz4 tOFF tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH 1.75 3.25 1.75 2.75 1.25 1.25 2.25 1.75 1.75 1.25 0.25 1.75 3.25 0.75 83.5 158.5 83.5 133.5 58.5 73.0 60.5 108.5 83.5 83.5 58.5 83.5 158.5 96.0 71.2 33.8 77.0 64.5 MHz4 54.3 104.3 54.3 87.7 37.7 48.0 39.7 71.0 54.3 54.3 37.7 54.3 104.3 62.7 46.2 21.3 52.0 43.7 Unit
assertion pulse width assertion deassertion assertion deassertion
assertion pulse width assertion assertion assertion column address valid deassertion assertion
deassertion pulse width address valid assertion assertion address valid Column address valid assertion assertion column address valid assertion column address valid Column address valid deassertion deassertion assertion deassertion assertion
2-34
DSP56364 Advance Information
Specifications External Memory Expansion Port (Port
Table 2-13. DRAM Out-of-Page Refresh Timings, Four Wait States1, (Continued)
Characteristics3 deassertion assertion assertion deassertion assertion deassertion Symbol Expression MHz4 tRRH tWCH tWCR tRWL tCWL tDHR tWCS tCSR tRPC tROH 0.75 0.25 0.25 4.75 4.25 2.25 1.75 3.25 1.25 70.8 145.8 220.5 233.2 208.2 108.5 83.5 158.5 145.7 21.0 58.5 221.0 37.2 192.5 12.5 MHz4 45.8 95.8 145.5 154.0 137.4 71.0 54.3 104.3 95.7 12.7 37.7 146.0 24.7 125.8 Unit
assertion pulse width assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion data valid (write)
assertion assertion assertion assertion (refresh) deassertion assertion (refresh) assertion deassertion
assertion data valid deassertion data valid3
assertion data active deassertion data high impedance
DSP56364 Advance Information
2-35
Specifications External Memory Expansion Port (Port
Table 2-13. DRAM Out-of-Page Refresh Timings, Four Wait States1, (Continued)
Notes:
Characteristics3
Symbol
Expression
MHz4
MHz4
Unit
number wait states page access specified DCR. refresh period specified DCR. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. Reduced clock speed allows DRAM out-of-page access with four Wait states (See Figure 2-17.).
Table 2-14. DRAM Out-of-Page Refresh Timings, Eight Wait States1,
Characteristics4 Random read write cycle time assertion data valid (read) assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) deassertion assertion Symbol Expression3 4.75 4.75 2.25 2.25 136.4 3.25 5.75 3.25 4.75 2.25 45.2 83.1 45.2 68.0 30.1 35.9 64.5 26.6 40.0 39.9 112.5 36.6 67.9 36.6 55.5 24.1 29.3 52.9 21.6 31.0 33.3 Unit
tRAC
tCAC
tOFF tRAS tRSH tCSH tCAS tRCD
assertion pulse width assertion deassertion assertion deassertion
assertion pulse width assertion assertion
2-36
DSP56364 Advance Information
Specifications External Memory Expansion Port (Port
Table 2-14. DRAM Out-of-Page Refresh Timings, Eight Wait States1, (Continued)
Characteristics4 assertion column address valid deassertion assertion Symbol Expression3 tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH 1.75 4.25 2.75 3.25 1.75 0.75 3.25 5.75 1.25 0.25 0.25 8.75 7.75 24.5 59.8 37.7 45.2 22.5 45.2 83.1 56.6 26.5 15.2 41.3 79.1 124.3 128.3 113.1 28.5 19.9 49.1 30.4 36.6 17.9 36.6 67.9 46.0 21.2 11.9 33.3 64.6 101.8 105.1 92.6 23.9 Unit
deassertion pulse width address valid assertion assertion address valid Column address valid assertion assertion column address valid assertion column address valid Column address valid deassertion deassertion assertion deassertion assertion deassertion assertion assertion deassertion assertion deassertion
tRRH
tWCH tWCR tRWL tCWL
assertion pulse width assertion deassertion assertion deassertion
DSP56364 Advance Information
2-37
Specifications External Memory Expansion Port (Port
Table 2-14. DRAM Out-of-Page Refresh Timings, Eight Wait States1, (Continued)
Characteristics4 Data valid assertion (write) assertion data valid (write) assertion data valid (write) Symbol Expression3 tDHR tWCS tCSR tRPC tROH 4.75 3.25 5.75 1.75 0.75 0.25 68.0 45.2 83.1 79.0 18.7 22.5 124.8 11.1 106.1 55.4 36.6 67.9 64.5 14.8 17.9 102.3 87.3 Unit
assertion assertion assertion assertion (refresh) deassertion assertion (refresh) assertion deassertion
assertion data valid deassertion data valid4
assertion data active deassertion data high impedance
Notes:
number wait states out-of-page access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56364. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. Either tRCH tRRH must satisfied read cycles.
2-38
DSP56364 Advance Information
Specifications External Memory Expansion Port (Port
Table 2-15. DRAM Out-of-Page Refresh Timings, Eleven Wait States1,
Characteristics4 Symbol tRAC tCAC tOFF tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWCR 4.25 7.75 5.25 6.25 3.75 1.75 5.75 4.25 4.25 1.75 0.75 5.25 7.75 1.75 0.25 Expression3 6.25 3.75 120.0 38.5 73.5 48.5 58.5 33.5 21.0 13.5 53.5 38.5 38.5 13.5 48.5 73.5 56.0 26.0 13.5 45.8 70.8 55.5 30.5 38.0 29.0 21.5 Unit
Random read write cycle time assertion data valid (read) assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time)
deassertion assertion assertion pulse width assertion deassertion assertion deassertion assertion pulse width assertion assertion assertion column address valid deassertion assertion deassertion pulse width address valid assertion assertion address valid Column address valid assertion assertion column address valid assertion column address valid Column address valid deassertion deassertion assertion deassertion assertion deassertion assertion assertion deassertion assertion deassertion assertion pulse width
11.5 110.5
DSP56364 Advance Information
2-39
Specifications External Memory Expansion Port (Port
Table 2-15. DRAM Out-of-Page Refresh Timings, Eleven Wait States1, (Continued)
Characteristics4 Symbol tRWL tCWL tDHR tWCS tCSR tRPC tROH 0.75 0.25 Expression3 93.0 Unit
assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion data valid (write) assertion assertion assertion assertion (refresh) deassertion assertion (refresh) assertion deassertion assertion data valid deassertion data valid4 assertion data active deassertion data high impedance
Notes:
11.75 113.2 10.25 103.2 5.75 5.25 7.75 2.75 53.5 48.5 73.5 60.7 11.0 23.5
11.5 111.0
number wait states out-of-page access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56364. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. Either tRCH tRRH must satisfied read cycles.
2-40
DSP56364 Advance Information
Specifications External Memory Expansion Port (Port
Table 2-16. DRAM Out-of-Page Refresh Timings, Fifteen Wait States1,
Characteristics3 Symbol tRAC tCAC tOFF tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWCR Expression 8.25 4.75 6.25 9.75 6.25 8.25 4.75 2.75 7.75 6.25 6.25 2.75 0.75 6.25 9.75 1.75 0.25 160.0 58.5 93.5 58.5 78.5 43.5 33.0 25.5 73.5 58.5 58.5 23.5 58.5 93.5 66.0 46.2 13.8 55.8 90.8 76.8 41.8 49.3 37.0 29.5 Unit
Random read write cycle time assertion data valid (read) assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time)
deassertion assertion assertion pulse width assertion deassertion assertion deassertion assertion pulse width assertion assertion assertion column address valid deassertion assertion deassertion pulse width address valid assertion assertion address valid Column address valid assertion assertion column address valid assertion column address valid Column address valid deassertion deassertion assertion deassertion assertion deassertion assertion assertion deassertion assertion deassertion
DSP56364 Advance Information
2-41
Specifications External Memory Expansion Port (Port
Table 2-16. DRAM Out-of-Page Refresh Timings, Fifteen Wait States1, (Continued)
Characteristics3 Symbol tRWL tCWL tDHR tWCS tCSR tRPC tROH 0.75 0.25 Expression 15.5 15.75 14.25 8.75 6.25 9.75 4.75 15.5 150.5 153.2 138.2 83.5 58.5 93.5 90.7 11.0 43.5 151.0 134.3 Unit
assertion pulse width assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion data valid (write) assertion assertion assertion assertion (refresh) deassertion assertion (refresh) assertion deassertion assertion data valid deassertion data valid3 assertion data active deassertion data high impedance
Notes:
number wait states out-of-page access specified DCR. refresh period specified DCR. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. Either tRCH tRRH must satisfied read cycles.
2-42
DSP56364 Advance Information
Specifications External Memory Expansion Port (Port
A0-A17
Address Column Address
Data AA0476
D0-D7
Figure 2-15. DRAM Out-of-Page Read Access
DSP56364 Advance Information
2-43
Specifications External Memory Expansion Port (Port
A0-A17 Address D0-D7 Data
AA0477
Column Address
Figure 2-16. DRAM Out-of-Page Write Access
2-44
DSP56364 Advance Information
Specifications External Memory Expansion Port (Port
AA0478
Figure 2-17. DRAM Refresh Access
DSP56364 Advance Information
2-45
Specifications Serial Host Interface Protocol Timing
SERIAL HOST INTERFACE PROTOCOL TIMING
Table 2-17. Serial Host Interface Protocol Timing
Characteristics Mode Filter Mode Bypassed Tolerable spike width clock data Narrow Wide Bypassed Minimum serial clock cycle tSPICC(min) Master Narrow Wide Bypassed Master Serial clock high period Bypassed Slave Narrow Wide Bypassed Master Serial clock period Bypassed Slave Narrow Wide Master Serial clock rise/fall time Slave 2000 Narrow Wide Narrow Wide Expression Unit
2-46
DSP56364 Advance Information
Specifications Serial Host Interface Protocol Timing
Table 2-17. Serial Host Interface Protocol Timing (Continued)
Characteristics Mode Filter Mode Bypassed assertion first edge CPHA Slave CPHA Bypassed Narrow Wide Bypassed Last edge asserted Slave Narrow Wide Bypassed Data input valid edge (data input set-up time) Master /Slave Narrow Wide Bypassed last sampling edge data input Master valid /Slave assertion data active deassertion data high impedance Slave Slave Narrow Wide Bypassed edge data valid (data delay time) Master /Slave Narrow Wide Bypassed edge data valid (data hold time) assertion data valid (CPHA Master /Slave Narrow Wide Slave MAX{(20-TC), MAX{(40-TC), TC+5 TC+55 TC+106 TC+33 Narrow Slave Wide Expression Unit
DSP56364 Advance Information
2-47
Specifications Serial Host Interface Protocol Timing
Table 2-17. Serial Host Interface Protocol Timing (Continued)
Characteristics Mode Filter Mode Bypassed First sampling edge HREQ output deassertion Slave Narrow Wide Bypassed Last sampling edge HREQ output deasserted (CPHA deassertion HREQ output deasserted (CPHA deassertion pulse width (CPHA Slave Narrow Wide Slave Slave Bypassed HREQ assertion first edge Master Narrow Wide HREQ deassertion last sampling edge (HREQ set-up time) Master (CPHA First edge HREQ asserted (HREQ hold time)
Note: Periodically sampled, 100% tested
Expression TC+6 tSPICC
Unit
Master
2-48
DSP56364 Advance Information
Specifications Serial Host Interface Protocol Timing
(Input) (CPOL (Output) (CPOL (Output) MISO (Input)
Valid
Valid
MOSI (Output) HREQ (Input)
AA0271
Figure 2-18. Master Timing (CPHA
DSP56364 Advance Information
2-49
Specifications Serial Host Interface Protocol Timing
(Input) (CPOL (Output) (CPOL (Output) MISO (Input)
Valid Valid
MOSI (Output) HREQ (Input)
AA0272
Figure 2-19. Master Timing (CPHA
2-50
DSP56364 Advance Information
Specifications Serial Host Interface Protocol Timing
(Input) (CPOL (Input) (CPOL (Input) MISO (Output) MOSI (Input)
Valid Valid
HREQ (Output)
AA0273
Figure 2-20. Slave Timing (CPHA
DSP56364 Advance Information
2-51
Specifications Serial Host Interface Protocol Timing
(Input) (CPOL (Input) (CPOL (Input) MISO (Output) MOSI (Input)
Valid Valid
HREQ (Output)
AA0274
Figure 2-21. Slave Timing (CPHA
2-52
DSP56364 Advance Information
Specifications Serial Host Interface (SHI)
Protocol Timing
SERIAL HOST INTERFACE (SHI) PROTOCOL TIMING
Table 2-18. Protocol Timing
Standard I2C* StandardMode Tolerable spike width Filters bypassed Narrow filters enabled Wide filters enabled clock frequency free time Start condition set-up time Start condition hold time period high period rise time fall time Data set-up time Data hold time Stop condition set-up time Capacitive load each line clock frequency Filters bypassed Narrow filters enabled Wide filters enabled FDSP 10.6 11.8 13.1 28.5 39.7 61.0 FSCL TBUF TSU;STA THD;STA TLOW THIGH TSU;DAT THD;DAT TSU;STO 1000 Fast-Mode Unit
Characteristics
Symbol/ Expression
DSP56364 Advance Information
2-53
Specifications Serial Host Interface (SHI) Protocol Timing
Table 2-18. Protocol Timing (Continued)
Standard I2C* StandardMode HREQ deassertion last edge (HREQ set-up time) First sampling edge HREQ output deassertion2 Filters bypassed Narrow filters enabled Wide filters enabled Last edge HREQ output deasserted2 Filters bypassed Narrow filters enabled Wide filters enabled HREQ assertion first edge TAS;RQI TI2CCP Narrow filters enabled Filters bypassed Wide filters enabled
Note: (min)
Fast-Mode
Characteristics
Symbol/ Expression
Unit
tSU;RQI
TNG;RQO TAS;RQO
4327 4282 4238
2-54
DSP56364 Advance Information
Specifications Serial Host Interface (SHI)
Protocol Timing
Programming Serial Clock
programmed serial clock cycle, I2CCP specified value HDM[5:0] bits HCKR (SHI clock control register). expression I2CCP I2CCP (HDM[7:0] HRS)
where prescaler rate select bit. When cleared, fixed divide-by-eight prescaler operational. When set, prescaler bypassed. HDM[7:0] divider modulus select bits. divide ratio from (HDM[5:0] $3F) selected.
mode, user select value programmed serial clock cycle from 4096 HDM[7:0] HDM[5:0]
programmed serial clock cycle (TI2CCP rise time (TR), filters selected should chosen order achieve desired frequency, shown Table 2-23. Table 2-19. Serial Clock Cycle generated Master
Filters bypassed
TI2CCP 45ns
Narrow filters enabled TI2CCP 135ns Wide filters enabled
TI2CCP 223ns
EXAMPLE: clock frequency (i.e. 10ns), operating standard-mode environment (FSCL (i.e. TSCL 10µs), 1000ns), with filters bypassed TI2CCP 10µs 45ns 1000ns 8930ns
DSP56364 Advance Information
2-55
Specifications Serial Host Interface (SHI) Protocol Timing
Choosing gives HDM[7:0] 8930ns 55.8 Thus HDM[7:0] value should programmed (=56).
Stop Start Stop
HREQ
AA0275
Figure 2-22. Timing
2-56
DSP56364 Advance Information
Specifications Enhanced Serial Audio Interface Timing
ENHANCED SERIAL AUDIO INTERFACE TIMING
Table 2-20. Enhanced Serial Audio Interface Timing
Characteristics1, Symbol Expression Clock cycle5 tSSICC TXC:max[3*tc; t454] Clock high period internal clock external clock Clock period internal clock external clock rising edge (bl) high rising edge (bl) rising edge (wr) high6 rising edge (wr) low6 rising edge (wl) high rising edge (wl) Data setup time before (SCK synchronous mode) falling edge 10.0 10.0 40.0 30.0 40.0 10.0 15.0 10.0 15.0 19.0 23.0 23.0 37.0 22.0 37.0 22.0 39.0 24.0 39.0 24.0 36.0 21.0 37.0 22.0 CondUnit ition4
Data hold time after falling edge input (bl, high before falling edge input (wl) high before falling edge
DSP56364 Advance Information
2-57
Specifications Enhanced Serial Audio Interface Timing
Table 2-20. Enhanced Serial Audio Interface Timing (Continued)
Characteristics1, input hold time after falling edge Flags input setup before falling edge Flags input hold time after falling edge Symbol Expression 19.0 21.0 29.0 15.0 31.0 17.0 31.0 17.0 33.0 19.0 30.0 16.0 31.0 17.0 31.0 17.0 34.0 20.0 28.0 21.0 31.0 16.0 34.0 20.0 27.0 CondUnit ition4
21.0
rising edge (bl) high rising edge (bl) rising edge (wr) high6 rising edge (wr) low6 rising edge (wl) high rising edge (wl) rising edge data enable from high impedance rising edge transmitter drive enable assertion
rising edge data valid rising edge data high impedance7 rising edge transmitter drive enable deassertion7 input (bl, setup time before falling edge6 input (wl) data enable from high impedance
2-58
DSP56364 Advance Information
Specifications Enhanced Serial Audio Interface Timing
Table 2-20. Enhanced Serial Audio Interface Timing (Continued)
Characteristics1, input (wl) transmitter drive enable assertion input (wl) setup time before falling edge input hold time after falling edge Symbol Expression CondUnit ition4
21.0 40.0
31.0 32.0 18.0 27.5 27.5
Flag output valid after rising edge HCKR/HCKT clock cycle HCKT input rising edge output HCKR input rising edge output
Notes:
3.16 0.16 +105°C, internal clock external clock internal clock, asynchronous mode (asynchronous implies that different clocks) internal clock, synchronous mode (synchronous implies that same clock) length word length word length relative TXC(SCKT pin) transmit clock RXC(SCKR pin) receive clock FST(FST pin) transmit frame sync FSR(FSR pin) receive frame sync HCKT(HCKT pin) transmit high speed clock HCKR(HCKR pin) receive high speed clock internal clock, external clock cycle defined Icyc ESAI control register. word-relative frame sync signal waveform relative clock operates same manner bit-length frame sync signal waveform, spreads from serial clock before first clock (same length frame sync signal), until before last clock first word frame. Periodically sampled 100% tested
DSP56364 Advance Information
2-59
Specifications Enhanced Serial Audio Interface Timing
(Input/ Output)
(Bit)
(Word)
First Last
Data
Transmitter Drive Enable
(Bit) (Word)
Note
Flags Note: network mode, output flag transitions occur start each time slot within frame. normal mode, output flag state asserted entire frame period.
AA0490
Figure 2-23. ESAI Transmitter Timing
2-60
DSP56364 Advance Information
Specifications Enhanced Serial Audio Interface Timing
(Input/Output) (Bit) (Word) Data (Bit) (Word) Flags
AA0491
First
Last
Figure 2-24. ESAI Receiver Timing
DSP56364 Advance Information
2-61
Specifications Enhanced Serial Audio Interface Timing
HCKT
SCKT(output)
Figure 2-25. ESAI HCKT Timing
HCKR
SCKR (output)
Figure 2-26. ESAI HCKR Timing
2-62
DSP56364 Advance Information
Specifications GPIO Timing
GPIO TIMING
Table 2-21. GPIO Timing
Characteristics1 Expression 10.2 6.75 TC-1.8 65.7 Unit 32.8
4902 EXTAL edge GPIO valid (GPIO delay time) EXTAL edge GPIO valid (GPIO hold time) GPIO valid EXTAL edge (GPIO set-up time) EXTAL edge GPIO valid (GPIO hold time) 4942 Fetch EXTAL edge before GPIO change GPIO rise time GPIO fall time
Notes:
0.16 +105°C, Valid only when enabled with multiplication factor equal one.
EXTAL (Input) GPIO (Output) GPIO (Input) Valid
A0-A17 Fetch instruction MOVE X0,X:(R0); contains value GPIO contains address GPIO data register.
GPIO (Output)
Figure 2-27. GPIO Timing
DSP56364 Advance Information
2-63
Specifications JTAG Timing
JTAG TIMING
Table 2-22. JTAG Timing
frequencies Characteristics frequency operation (1/(TC maximum MHz) cycle time Crystal mode clock pulse width measured rise fall times Boundary scan input data setup time Boundary scan input data hold time output data valid output high impedance TMS, data setup time TMS, data hold time data valid high impedance
Notes:
Unit 22.0 40.0 40.0 44.0 44.0
45.0 20.0 24.0 25.0
0.16 +105°C, timings apply OnCE module data transfers because uses JTAG port interface.
(Input)
AA0496
Figure 2-28. Test Clock Input Timing Diagram
2-64
DSP56364 Advance Information
Specifications JTAG Timing
(Input)
Data Inputs Data Outputs Data Outputs Data Outputs
Input Data Valid
Output Data Valid
Output Data Valid
AA0497
Figure 2-29. Boundary Scan (JTAG) Timing Diagram
(Input) (Input)
Input Data Valid
(Output) (Output) (Output)
Output Data Valid
Output Data Valid
AA0498
Figure 2-30. Test Access Port Timing Diagram
DSP56364 Advance Information
2-65
Specifications JTAG Timing
2-66
DSP56364 Advance Information
SECTION PACKAGING
PIN-OUT PACKAGE INFORMATION
This section provides information about available package this product, including diagrams package pinouts tables describing signals described Section allocated package. DSP56364 available 100-pin TQFP package. Tables show pin/name assignments packages.
TQFP Package Description
view 100-pin TQFP package shown Figure with pin-outs. 100-pin TQFP package mechanical drawing shown Figure 3-2.
DSP56364 Advance Information
Packaging Pin-out Package Information
VCCHQ
VCCLQ
GPIO3
GPIO2
GPIO1
GPIO0
GNDQ
GNDD
GNDS
VCCD
VCCS
MODD MODB MODA SCKT SCKR VCCS GNDS HCKT VCCLQ GNDQ HCKR SDO0 VCCHQ SDO1 SDO2/SDI3 SDO3/SDI2 SDO4/SDI1 SDO5/SDI0 VCCS GNDS SS/HA2 MOSI/HA0 MISO/SDA
GNDA VCCA VCCLQ GNDQ GNDA VCCA VCCQH GNDA VCCA
DSP56364 100-Pin TQPF
PINIT/NMI
PCAP
VCCP
VCCQL
GNDP
EXTAL
VCCA
SCK/SCL
RESET
VCCHQ
Figure DSP56364 100-Pin Thin Quad Flat Pack (TQFP), View
DSP56364 Advance Information
GNDQ
GNDC
GNDA
HREQ
VCCC
Packaging Pin-out Package Information
Table DSP56364 100-Pin TQFP Signal Identification Number
Note:
Signal Name
MODD/IRQD MODB/IRQB MODA/IRQA SCKT SCKR VCCS GNDS HCKT VCCLQ GNDQ HCKR SDO0 VCCHQ SDO1 SDO2/SDI3 SDO3/SDI2 SDO4/SDI1 SDO5/SDI0 VCCS GNDS SS/HA2 MOSI/HA0 MISO/SDA
Signal Name
SCK/SCL HREQ PINIT/NMI RESET Connect VCCP PCAP GNDP EXTAL VCCHQ GNDQ VCCLQ VCCC GNDC AA1/RAS1 AA0/RAS0 VCCQ GNDQ
VCCA GNDA VCCHQ VCCA GNDA GNDQ VCCLQ VCCA GNDA
Signal Name
VCCD GNDD Connect Connect VCCLQ GNDQ VCCHQ Connect GPIO0 VCCS GNDS GPIO1 GPIO2 GPIO3
Signal names based configured functionality. Most pins supply single signal. Some pins provide signal with dual functionality, such MODx/IRQx pins that select operating mode after RESET deasserted, interrupt lines during operation.
DSP56364 Advance Information
Packaging Pin-out Package Information
Table DSP56364 100-Pin TQFP Signal Identification Name
Signal Name Signal Name EXTAL GNDA GNDA GNDA GNDA GNDC GNDD GNDP GNDQ GNDQ GNDQ GNDQ GNDS GNDS GNDS GPIO0 GPIO1 GPIO2 GPIO3 Signal Name HCKR HCKT HREQ MISO/SDA MODA/IRQA MODB/IRQB MODD/IRQD MOSI/HA0 Connect Connect Connect Connect PCAP PINIT/NMI RESET SCK/SCL SCKR SCKT SDO0 SDO1 SDO5/SDI0 SS/HA2 SDO2/SDI3 SDO3/SDI2 Signal Name SDO4/SDI1 VCCA VCCA VCCA VCCA VCCC VCCD VCCHQ VCCHQ VCCHQ VCCHQ VCCLQ VCCLQ VCCLQ VCCLQ VCCP VCCS VCCS VCCS
DSP56364 Advance Information
Packaging Pin-out Package Information
TQFP Package Mechanical Drawing
Figure DSP56364 100-pin TQFP Package
DSP56364 Advance Information
Packaging Ordering Drawings
ORDERING DRAWINGS
detailed package drawing available Motorola page package search.
DSP56364 Advance Information
Packaging Ordering Drawings
DSP56364 Advance Information
Packaging Ordering Drawings
DSP56364 Advance Information
Packaging Ordering Drawings
IDENT
0.20
TIPS
0.20
VIEW
108X
X=L,
VIEW
0.13
BASE METAL
SECTION J1±J1
ROTATED COUNTERCLOCKWISE
0.050
VIEW 0.10
112X
SEATING PLANE
NOTES: DIMENSIONS TOLERANCES ASME Y14.5M, 1994. DIMENSIONS MILLIMETERS. DATUMS DETERMINED SEATING PLANE, DATUM DIMENSIONS DETERMINED SEATING PLANE, DATUM DIMENSIONS INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION 0.25 SIDE. DIMENSIONS INCLUDE MOLD MISMATCH. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL CAUSE DIMENSION EXCEED 0.46. MILLIMETERS 20.000 10.000 20.000 10.000 1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 0.090 0.170 0.500 0.325 0.100 0.200 0.100 0.200 22.000 11.000 22.000 11.000 0.250 1.000 0.090 0.160
0.25
GAGE PLANE
VIEW
CASE 987±01 ISSUE
DATE 01/30/96
DSP56364 Advance Information
Packaging Ordering Drawings
3-10
DSP56364 Advance Information
SECTION DESIGN CONSIDERATIONS
THERMAL DESIGN CONSIDERATIONS
estimation chip junction temperature, obtained from following equation:
Where:
ambient temperature RqJA package junction-to-ambient thermal resistance °C/W power dissipation package
Historically, thermal resistance been expressed junction-to-case thermal resistance case-to-ambient thermal resistance.
Where:
package junction-to-ambient thermal resistance °C/W package junction-to-case thermal resistance °C/W package case-to-ambient thermal resistance °C/W
device-related cannot influenced user. user controls thermal environment change case-to-ambient thermal resistance, RCA. example, user change flow around device, heat sink, change mounting arrangement printed circuit board (PCB), otherwise change thermal dissipation capability area surrounding device PCB. This model most useful ceramic packages with heat sinks; some heat flow dissipated through case heat sink ambient environment. ceramic packages, situations where heat flow split between path case alternate path through PCB, analysis device thermal performance need additional modeling capability system level thermal simulation tool. thermal performance plastic packages more dependent temperature which package mounted. Again, estimations obtained from satisfactorily answer whether thermal performance adequate, system level model appropriate.
DSP56364 Advance Information
Design Considerations Thermal Design Considerations
complicating factor existence three common ways determining junction-tocase thermal resistance plastic packages. minimize temperature variation across surface, thermal resistance measured from junction outside surface package (case) closest chip mounting area when that surface proper heat sink. define value approximately equal junction-to-board thermal resistance, thermal resistance measured from junction where leads attached case. temperature package case (TT) determined thermocouple, thermal resistance computed using value obtained equation TT)/PD.
noted above, junction-to-case thermal resistances quoted this data sheet determined using first definition. From practical standpoint, that value also suitable determining junction temperature from case thermocouple reading forced convection environments. natural convection, using junction-to-case thermal resistance estimate junction temperature from thermocouple reading case package will estimate junction temperature slightly hotter than actual temperature. Hence, thermal metric, thermal characterization parameter been defined TT)/ This value gives better estimate junction temperature natural convection when using surface temperature package. Remember that surface temperature readings packages subject significant errors caused inadequate attachment sensor surface errors caused heat loss sensor. recommended technique attach 40-gauge thermocouple wire bead center package with thermally conductive epoxy.
DSP56364 Advance Information
Design Considerations Electrical Design Considerations
ELECTRICAL DESIGN CONSIDERATIONS
CAUTION
This device contains circuitry protecting against damage high static voltage electrical fields. However, normal precautions should taken avoid exceeding maximum voltage ratings. Reliability operation enhanced unused inputs tied appropriate logic voltage level (e.g., either VCC). suggested value pullup pulldown resistor ohm.
following list recommendations assure correct operation: Provide low-impedance path from board power supply each from board ground each pin. least 0.01-0.1 bypass capacitors positioned close possible four sides package connect power source GND. Ensure that capacitor leads associated printed circuit traces that connect chip pins less than (0.5 inch) capacitor lead. least four-layer with inner layers GND. Because output signals have fast rise fall times, trace lengths should minimal. This recommendation particularly applies address data buses well IRQA, IRQB, IRQD, pins. Maximum trace lengths order inches) recommended. Consider device loads well parasitic capacitance traces when calculating capacitance. This especially critical systems with higher capacitive loads that could create higher transient currents circuits. inputs must terminated (i.e., allowed float) using CMOS levels, except three pins with internal pull-up resistors (TMS, TDI, TCK). Take special care minimize noise levels GNDP pins. multiple DSP56364 devices same board, check cross-talk excessive spikes supplies synchronous operation devices. RESET must asserted when chip powered stable EXTAL signal must supplied before deassertion RESET.
DSP56364 Advance Information
Design Considerations Power Consumption Considerations
power-up, ensure that voltage difference between tolerant pins chip never exceeds 3.95
POWER CONSUMPTION CONSIDERATIONS
Power dissipation issue portable applications. Some factors which affect current consumption described this section. Most current consumed CMOS devices alternating current (ac), which charging discharging capacitances pins internal nodes. Current consumption described following formula:
where
node/pin capacitance voltage swing frequency node/pin toggle
Example Current Consumption
Port address loaded with capacitance, operating with clock, toggling maximum possible rate MHz), current consumption
8.25mA
maximum internal current (ICCImax) value reflects typical possible switching internal buses best-case operation conditions, which necessarily real application case. typical internal current (ICCItyp) value reflects average switching internal buses typical operating conditions. applications that require very current consumption, following: when accessing external memory. Minimize external memory accesses internal memory accesses. Minimize number pins that switching. Minimize capacitive load pins. Connect unused inputs pull-up pull-down resistors. Disable unused peripherals.
DSP56364 Advance Information
Design Considerations Performance Issues
evaluate power consumption current MIPS measurement methodology minimize specific board effects (i.e., compensate measured board current caused DSP). benchmark power consumption test algorithm listed Appendix test algorithm, specific test current measurements, following equation derive current MIPS value.
MIPS typF2 typF1
where
ItypF2 ItypF1
current current high frequency (any specified operating frequency) frequency (any specified operating frequency lower than
Note: should significantly less than example, could could MHz. degree difference between determines amount precision with which current rating determined application.
PERFORMANCE ISSUES
following explanations should considered general observations expected behavior. There testing that verifies these exact numbers. These observations were measured limited number parts were verified over entire temperature voltage ranges.
Input (EXTAL) Jitter Requirements
allowed jitter frequency EXTAL 0.5%. rate change frequency EXTAL slow (i.e., does jump between minimum maximum values cycle) frequency jitter fast (i.e., does stay extreme value long time), then allowed jitter phase frequency jitter performance results only valid input jitter less than prescribed values.
DSP56364 Advance Information
Design Considerations Performance Issues
DSP56364 Advance Information
SECTION ORDERING INFORMATION
Consult Motorola Semiconductor sales office authorized distributor determine product availability place order. Table Ordering Information
Part DSP56364 Notes: Supply Voltage Package Type Thin quad flat pack (TQFP) Quad flat pack (QFP) Count Frequency (MHz) Order Number XCB56364FU100 XCB56364PV100
DSP56364 include factory-programmed ROM. listed code generic unused available customer. Variations will supported Dolby digital (AC-3), DTS, MPEG2, other features. These products only available authorized licensees those technologies. Please consult site www.dspaudio.motorola.com current availability. Future products DSP56364 family include other ROM-based options. additional information future part development, request customer-specific ROMbased support, call your local Motorola Semiconductor sales office authorized distributor.
DSP56364 Advance Information
Ordering Information
DSP56364 Advance Information
APPENDIX IBIS MODEL
[IBIS ver] [File name] 56364.ibs [File Rev] [Date] 29/6/2000 [Component] 56364 [Manufacturer] Motorola [Package] |variable R_pkg L_pkg 2.5nH C_pkg 1.3pF
1.1nH 1.2pF
4.3nH 1.4pF
[Pin]signal_name model_name irqc_ ip5b_i irqb_ ip5b_i irqa_ ip5b_i ip5b_io ip5b_io sckt ip5b_io sckr ip5b_io svcc power sgnd hsckt ip5b_io qvccl power qgnd hsckr ip5b_io sdo0 ip5b_io qvcch power sdo1 ip5b_io sdo2 ip5b_io sdo3 ip5b_io sdo4 ip5b_io sdo5 ip5b_io svcc power sgnd ip5b_io mosi ip5b_io ip5b_io ip5b_io hreq_ ip5b_io nmi_ ip5b_i ires_ ip5b_i pvcc power pcap power
DSP56364 Advance Information
Appendix
IBIS Model
pgnd cxtldis_ qvcch qgnd qvccl cas_ cvcc cgnd eab0 eab1 avcc agnd eab2 eab3 eab4 eab5 eab6 avcc agnd eab7 eab8 eab9 eab10 qvcch eab11 avcc agnd qgnd qvccl eab12 eab13 eab14 eab15 avcc agnd eab16 eab17 edb0 edb1 edb2 edb3 dvcc dgnd edb4 edb5 edb6 edb7 qvccl
iexlh_i power power icbc_o icbc_o icbc_o icbc_o power icbc_o icbc_o icba_o icba_o power icba_o icba_o icba_o icba_o icba_o power icba_o icba_o icba_o icba_o power icba_o power power icba_o icba_o icba_o icba_o power icba_o icba_o icba_io icba_io icba_io icba_io power icba_io icba_io icba_io icba_io power
Appendix
DSP56364 Advance Information
IBIS Model
qgnd qvcch power edb8 ip5b_io svcc power sgnd edb9 ip5b_io edb10 ip5b_io edb11 ip5b_io ip5b_o ip5b_i ip5b_i ip5b_i [Model] ip5b_i Model_type Input Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF [Voltage Range] 3.3v 3.6v [GND_clamp] |voltage I(typ) I(min) I(max) -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03 -7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04 -5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05 -3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09 -1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11 0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11 [End]| [Model] ip5b_io Model_type Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF
DSP56364 Advance Information
Appendix
IBIS Model
[Voltage Range] 3.3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.69e+00 -9.00e-01 -5.10e-02 -1.18e+00 -5.63e-02 -7.00e-01 -3.65e-02 -2.25e-02 -4.28e-02 -5.00e-01 -2.65e-02 -1.38e-02 -3.12e-02 -3.00e-01 -1.62e-02 -8.35e-03 -1.91e-02 -1.00e-01 -5.49e-03 -2.80e-03 -6.52e-03 1.000e-01 5.377e-03 2.744e-03 6.427e-03 3.000e-01 1.516e-02 7.871e-03 1.823e-02 5.000e-01 2.370e-02 1.252e-02 2.869e-02 7.000e-01 3.098e-02 1.667e-02 3.776e-02 9.000e-01 3.700e-02 2.026e-02 4.544e-02 1.100e+00 4.175e-02 2.324e-02 5.171e-02 1.300e+00 4.531e-02 2.553e-02 5.660e-02 1.500e+00 4.779e-02 2.709e-02 6.023e-02 1.700e+00 4.935e-02 2.803e-02 6.271e-02 1.900e+00 5.013e-02 2.851e-02 6.419e-02 2.100e+00 5.046e-02 2.876e-02 6.494e-02 2.300e+00 5.063e-02 2.892e-02 6.525e-02 2.500e+00 5.075e-02 2.904e-02 6.540e-02 2.700e+00 5.085e-02 2.912e-02 6.549e-02 2.900e+00 5.090e-02 2.876e-02 6.555e-02 3.100e+00 4.771e-02 2.994e-02 6.561e-02 3.300e+00 4.525e-02 3.321e-02 6.182e-02 3.500e+00 4.657e-02 3.570e-02 6.049e-02 3.700e+00 4.904e-02 3.801e-02 6.178e-02 3.900e+00 5.221e-02 4.029e-02 6.450e-02 4.100e+00 5.524e-02 4.253e-02 6.659e-02 4.300e+00 5.634e-02 4.463e-02 6.867e-02 4.500e+00 5.751e-02 4.645e-02 6.970e-02 4.700e+00 5.634e-02 4.786e-02 6.938e-02 4.900e+00 5.648e-02 4.881e-02 6.960e-02 5.100e+00 5.664e-02 4.912e-02 6.983e-02 5.300e+00 5.679e-02 4.795e-02 7.005e-02 5.500e+00 5.693e-02 4.679e-02 7.026e-02 5.700e+00 5.707e-02 4.688e-02 7.049e-02 5.900e+00 5.722e-02 4.700e-02 7.074e-02 6.100e+00 5.741e-02 4.712e-02 7.105e-02 6.300e+00 5.766e-02 4.723e-02 7.147e-02
Appendix
DSP56364 Advance Information
IBIS Model
6.500e+00 6.600e+00 [Pullup] |voltage -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00
5.801e-02 5.824e-02
4.733e-02 4.737e-02
7.205e-02 7.242e-02
I(typ) 2.922e-04 2.881e-04 2.853e-04 2.836e-04 2.825e-04 2.819e-04 2.815e-04 2.813e-04 2.812e-04 2.811e-04 2.810e-04 2.809e-04 2.808e-04 2.997e-04 1.750e-02 1.048e-02 3.487e-03 -3.40e-03 -9.69e-03 -1.52e-02 -2.02e-02 -2.46e-02 -2.84e-02 -3.14e-02 -3.37e-02 -3.55e-02 -3.68e-02 -3.78e-02 -3.85e-02 -3.91e-02 -3.96e-02 -4.01e-02 -4.04e-02 -4.08e-02 -4.11e-02 -4.14e-02 -4.17e-02 -4.32e-02 -4.08e-01 -2.73e+01 -6.13e+01 -9.54e+01 -1.38e+02 -1.89e+02 -2.40e+02 -2.91e+02 -3.42e+02
I(min) 2.177e-04 2.175e-04 2.173e-04 2.172e-04 2.171e-04 2.170e-04 2.169e-04 2.167e-04 2.520e-04 3.078e-02 2.684e-02 2.277e-02 1.864e-02 1.447e-02 1.031e-02 6.181e-03 2.084e-03 -2.03e-03 -5.71e-03 -8.99e-03 -1.19e-02 -1.43e-02 -1.62e-02 -1.77e-02 -1.88e-02 -1.95e-02 -2.00e-02 -2.04e-02 -2.07e-02 -2.10e-02 -2.12e-02 -2.15e-02 -2.17e-02 -2.18e-02 -2.20e-02 -2.78e-02 -1.20e+00 -2.15e+01 -4.52e+01 -6.89e+01 -9.25e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.59e+02 -2.94e+02
I(max)
4.123e-04 4.021e-04 3.946e-04 3.893e-04 3.857e-04 3.834e-04 3.820e-04 3.812e-04 3.808e-04 3.806e-04 3.804e-04 3.802e-04 3.801e-04 3.799e-04 3.797e-04 3.776e-04 4.568e-03 -4.22e-03 -1.24e-02 -1.95e-02 -2.61e-02 -3.21e-02 -3.73e-02 -4.18e-02 -4.55e-02 -4.85e-02 -5.09e-02 -5.27e-02 -5.41e-02 -5.51e-02 -5.60e-02 -5.67e-02 -5.74e-02 -5.79e-02 -5.84e-02 -5.89e-02 -5.94e-02 -5.98e-02 -6.10e-02 -6.84e-02 -7.73e+00 -4.18e+01 -7.59e+01 -1.11e+02 -1.61e+02 -2.12e+02 -2.63e+02
DSP56364 Advance Information
Appendix
IBIS Model
6.100e+00 -3.93e+02 -3.30e+02 -3.14e+02 6.300e+00 -4.44e+02 -3.65e+02 -3.65e+02 6.500e+00 -4.95e+02 -4.01e+02 -4.16e+02 6.600e+00 -5.21e+02 -4.18e+02 -4.41e+02 [GND_clamp] |voltage I(typ) I(min) I(max) -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03 -7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04 -5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05 -3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09 -1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11 0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11 [Ramp] R_load 50.00 |voltage I(typ) I(min) I(max) dV/dt_r 1.030/0.465 0.605/0.676 1.320/0.366 dV/dt_f 1.290/0.671 0.829/0.122 1.520/0.431 [End]| [Model] ip5b_o Model_type 3-state Polarity Non-Inverting C_comp 5.00pF 5.00pF 5.00pF [Voltage Range] 3.3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02
Appendix
DSP56364 Advance Information
IBIS Model
-2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 [Pullup] |voltage -3.30e+00 -3.10e+00 -2.90e+00
-2.65e+02 -2.14e+02 -1.63e+02 -1.13e+02 -7.83e+01 -4.43e+01 -1.02e+01 -5.10e-02 -3.65e-02 -2.65e-02 -1.62e-02 -5.49e-03 5.377e-03 1.516e-02 2.370e-02 3.098e-02 3.700e-02 4.175e-02 4.531e-02 4.779e-02 4.935e-02 5.013e-02 5.046e-02 5.063e-02 5.075e-02 5.085e-02 5.090e-02 4.771e-02 4.525e-02 4.657e-02 4.904e-02 5.221e-02 5.524e-02 5.634e-02 5.751e-02 5.634e-02 5.648e-02 5.664e-02 5.679e-02 5.693e-02 5.707e-02 5.722e-02 5.741e-02 5.766e-02 5.801e-02 5.824e-02
-1.88e+02 -1.52e+02 -1.17e+02 -9.25e+01 -6.88e+01 -4.52e+01 -2.15e+01 -1.18e+00 -2.25e-02 -1.38e-02 -8.35e-03 -2.80e-03 2.744e-03 7.871e-03 1.252e-02 1.667e-02 2.026e-02 2.324e-02 2.553e-02 2.709e-02 2.803e-02 2.851e-02 2.876e-02 2.892e-02 2.904e-02 2.912e-02 2.876e-02 2.994e-02 3.321e-02 3.570e-02 3.801e-02 4.029e-02 4.253e-02 4.463e-02 4.645e-02 4.786e-02 4.881e-02 4.912e-02 4.795e-02 4.679e-02 4.688e-02 4.700e-02 4.712e-02 4.723e-02 4.733e-02 4.737e-02
-2.63e+02 -2.12e+02 -1.61e+02 -1.10e+02 -7.58e+01 -4.17e+01 -7.69e+00 -5.63e-02 -4.28e-02 -3.12e-02 -1.91e-02 -6.52e-03 6.427e-03 1.823e-02 2.869e-02 3.776e-02 4.544e-02 5.171e-02 5.660e-02 6.023e-02 6.271e-02 6.419e-02 6.494e-02 6.525e-02 6.540e-02 6.549e-02 6.555e-02 6.561e-02 6.182e-02 6.049e-02 6.178e-02 6.450e-02 6.659e-02 6.867e-02 6.970e-02 6.938e-02 6.960e-02 6.983e-02 7.005e-02 7.026e-02 7.049e-02 7.074e-02 7.105e-02 7.147e-02 7.205e-02 7.242e-02
I(typ) 2.922e-04 2.881e-04 2.853e-04
I(min) 2.177e-04 2.175e-04 2.173e-04
I(max)
4.123e-04 4.021e-04 3.946e-04
DSP56364 Advance Information
Appendix
IBIS Model
-2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 [GND_clamp] |voltage -3.30e+00
2.836e-04 2.825e-04 2.819e-04 2.815e-04 2.813e-04 2.812e-04 2.811e-04 2.810e-04 2.809e-04 2.808e-04 2.997e-04 1.750e-02 1.048e-02 3.487e-03 -3.40e-03 -9.69e-03 -1.52e-02 -2.02e-02 -2.46e-02 -2.84e-02 -3.14e-02 -3.37e-02 -3.55e-02 -3.68e-02 -3.78e-02 -3.85e-02 -3.91e-02 -3.96e-02 -4.01e-02 -4.04e-02 -4.08e-02 -4.11e-02 -4.14e-02 -4.17e-02 -4.32e-02 -4.08e-01 -2.73e+01 -6.13e+01 -9.54e+01 -1.38e+02 -1.89e+02 -2.40e+02 -2.91e+02 -3.42e+02 -3.93e+02 -4.44e+02 -4.95e+02 -5.21e+02
2.172e-04 2.171e-04 2.170e-04 2.169e-04 2.167e-04 2.520e-04 3.078e-02 2.684e-02 2.277e-02 1.864e-02 1.447e-02 1.031e-02 6.181e-03 2.084e-03 -2.03e-03 -5.71e-03 -8.99e-03 -1.19e-02 -1.43e-02 -1.62e-02 -1.77e-02 -1.88e-02 -1.95e-02 -2.00e-02 -2.04e-02 -2.07e-02 -2.10e-02 -2.12e-02 -2.15e-02 -2.17e-02 -2.18e-02 -2.20e-02 -2.78e-02 -1.20e+00 -2.15e+01 -4.52e+01 -6.89e+01 -9.25e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.59e+02 -2.94e+02 -3.30e+02 -3.65e+02 -4.01e+02 -4.18e+02
3.893e-04 3.857e-04 3.834e-04 3.820e-04 3.812e-04 3.808e-04 3.806e-04 3.804e-04 3.802e-04 3.801e-04 3.799e-04 3.797e-04 3.776e-04 4.568e-03 -4.22e-03 -1.24e-02 -1.95e-02 -2.61e-02 -3.21e-02 -3.73e-02 -4.18e-02 -4.55e-02 -4.85e-02 -5.09e-02 -5.27e-02 -5.41e-02 -5.51e-02 -5.60e-02 -5.67e-02 -5.74e-02 -5.79e-02 -5.84e-02 -5.89e-02 -5.94e-02 -5.98e-02 -6.10e-02 -6.84e-02 -7.73e+00 -4.18e+01 -7.59e+01 -1.11e+02 -1.61e+02 -2.12e+02 -2.63e+02 -3.14e+02 -3.65e+02 -4.16e+02 -4.41e+02
I(typ) -5.21e+02
I(min) -3.65e+02
I(max)
-5.18e+02
Appendix
DSP56364 Advance Information
IBIS Model
-3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03 -7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04 -5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05 -3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09 -1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11 0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11 [Ramp] R_load 50.00 |voltage I(typ) I(min) I(max) dV/dt_r 1.030/0.465 0.605/0.676 1.320/0.366 dV/dt_f 1.290/0.671 0.829/0.122 1.520/0.431 [End]| [Model] icba_io Model_type Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF [Voltage Range] 3.3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.68e+00
DSP56364 Advance Information
Appendix
IBIS Model
-9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 [Pullup] |voltage -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00
-2.70e-02 -1.32e-02 -9.33e-03 -5.75e-03 -1.97e-03 1.945e-03 5.507e-03 8.649e-03 1.136e-02 1.364e-02 1.547e-02 1.688e-02 1.299e-01 1.366e-01 1.404e-01 1.423e-01 1.433e-01 1.440e-01 1.445e-01 1.450e-01 1.454e-01 1.458e-01 1.461e-01 1.464e-01 1.469e-01 1.490e-01 1.501e+00 1.813e+01 3.540e+01 5.269e+01 7.541e+01 1.012e+02 1.270e+02 1.527e+02 1.785e+02 2.043e+02 2.301e+02 2.559e+02 2.688e+02
-1.19e+00 -1.25e-02 -4.69e-03 -2.81e-03 -9.48e-04 9.285e-04 2.640e-03 4.168e-03 5.504e-03 6.636e-03 7.551e-03 8.240e-03 6.458e-02 6.746e-02 6.916e-02 7.006e-02 7.059e-02 7.098e-02 7.128e-02 7.154e-02 7.176e-02 7.196e-02 7.223e-02 8.810e-02 2.589e+00 1.451e+01 2.658e+01 3.866e+01 5.076e+01 6.461e+01 8.261e+01 1.006e+02 1.186e+02 1.366e+02 1.546e+02 1.726e+02 1.906e+02 2.086e+02 2.176e+02
-2.90e-02 -1.63e-02 -1.10e-02 -6.76e-03 -2.32e-03 2.307e-03 6.599e-03 1.048e-02 1.393e-02 1.693e-02 1.950e-02 2.162e-02 2.331e-02 1.755e-01 1.847e-01 1.907e-01 1.940e-01 1.958e-01 1.970e-01 1.979e-01 1.986e-01 1.993e-01 1.999e-01 2.004e-01 2.009e-01 2.015e-01 2.030e-01 2.385e-01 9.563e+00 2.682e+01 4.409e+01 6.258e+01 8.836e+01 1.141e+02 1.399e+02 1.657e+02 1.915e+02 2.173e+02 2.302e+02
I(typ) 2.686e+02 2.428e+02 2.170e+02 1.912e+02 1.655e+02 1.397e+02 1.139e+02 8.814e+01 6.237e+01 4.389e+01
I(min) 1.905e+02 1.725e+02 1.545e+02 1.365e+02 1.185e+02 1.005e+02 8.253e+01 6.454e+01 5.068e+01 3.859e+01
I(max)
2.686e+02 2.428e+02 2.170e+02 1.912e+02 1.655e+02 1.397e+02 1.139e+02 8.814e+01 6.237e+01 4.389e+01
Appendix A-10
DSP56364 Advance Information
IBIS Model
-1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 [GND_clamp] |voltage -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00
2.662e+01 9.360e+00 4.275e-02 8.208e-03 5.635e-03 3.370e-03 1.118e-03 -1.09e-03 -3.12e-03 -4.96e-03 -6.60e-03 -8.04e-03 -9.26e-03 -1.03e-02 -1.25e-01 -1.31e-01 -1.36e-01 -1.40e-01 -1.42e-01 -1.44e-01 -1.46e-01 -1.48e-01 -1.49e-01 -1.50e-01 -1.52e-01 -1.53e-01 -1.54e-01 -1.57e-01 -5.25e-01 -2.74e+01 -6.14e+01 -9.55e+01 -1.38e+02 -1.89e+02 -2.
Other recent searches
XR16V2650 - XR16V2650 XR16V2650 Datasheet
TEA5767 - TEA5767 TEA5767 Datasheet
TEA5767HL - TEA5767HL TEA5767HL Datasheet
TEA5768HL - TEA5768HL TEA5768HL Datasheet
TEA5767HN - TEA5767HN TEA5767HN Datasheet
TDA1220B - TDA1220B TDA1220B Datasheet
ROS-2150VW+ - ROS-2150VW+ ROS-2150VW+ Datasheet
RB160L-60 - RB160L-60 RB160L-60 Datasheet
KM2520ZGC01 - KM2520ZGC01 KM2520ZGC01 Datasheet
2N869A - 2N869A 2N869A Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
