PCnetTM-ISA Single-Chip Ethernet Controller DISTINCTIVE CHARACTER
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Am79C960
PCnetTM-ISA Single-Chip Ethernet Controller
DISTINCTIVE CHARACTERISTICS
Single-chip Ethernet controller Industry Standard Architecture (ISA) Extended Industry Standard Architecture (EISA) buses Supports IEEE 802.3/ANSI 8802-3 Ethernet standards Direct interface EISA Software compatible with AMD's Am7990 LANCE register descriptor architecture power, CMOS design with sleep mode allows reduced power consumption critical battery powered applications Individual 136-byte transmit 128-byte receive FIFOs provide packet buffering increased system latency, support following features: Automatic retransmission with FIFO reload Automatic receive stripping transmit padding (individually programmable) Automatic runt packet rejection Automatic deletion received collision frames Dynamic transmit generation programmable frame-by-frame basis Single power supply Internal/external loopback capabilities Supports optional Boot PROM diskless node applications
Advanced Micro Devices
Provides integrated Attachment Unit Interface (AUI) 10BASE-T transceiver with modes port selection: Automatic selection 10BASE-T Software selection 10BASE-T Jumper selection 10BASE-T Automatic Twisted Pair receive polarity detection automatic correction receive polarity Supports bus-master shared-memory architectures application Supports edge level-sensitive interrupts Buffer Management Unit reduced intervention Integral controller allows higher throughput by-passing platform JTAG Boundary Scan (IEEE 1149.1) test access port interface board level production test Integrated Manchester Encoder/Decoder Supports following types network interfaces: external 10BASE2, 10BASE5, 10BASE-T 10BASE-F Internal 10BASE-T transceiver with Smart Squelch Twisted Pair medium Supports LANCE General Purpose Serial Interface (GPSI) 120-pin PQFP package
GENERAL DESCRIPTION
PCnet-ISA controller, single-chip Ethernet controller, highly integrated system solution PC-AT Industry Standard Architecture (ISA architecture. designed provide flexibility compatibility with existing application. This highly integrated 120-pin VLSI device specifically designed reduce parts count cost, addresses applications where higher system throughput desired. PCnet-ISA controller fabricated with AMD's advanced low-power CMOS process provide stand current power sensitive applications. PCnet-ISA controller DMA-based device with dual architecture that configured different
Publication# 16907 Rev. Issue Date: 1994 Amendment
operating modes suit particular application. Master Mode transfers performed using integrated controller. This configuration enhances system performance allowing PCnet-ISA controller bypass platform controller directly address full 24-bit memory space. implementation Master Mode allows minimum parts count majority applications. PCnet-ISA controller configured perform Shared Memory operations compatibility with lowend machines, such PC/XTs that support Master high-end machines that require local packet buffering increased system latency. 1-343
This document contains information product under development Advanced Micro Devices, Inc. information intended help evaluate this product. reserves right change discontinue work this proposed product without notice.
PRELIMINARY time. individual 136-byte transmit 128-byte receive FIFOs optimize system overhead, providing sufficient latency during packet transmission reception, minimizing intervention during normal network error recovery. integrated Manchester encoder/decoder eliminates need external Serial Interface Adapter (SIA) node system. support external encoding/decoding scheme desired, embedded General Purpose Serial Interface (GPSI) allows direct access to/from MAC. addition, device provides programmable on-chip drivers transmit, receive, collision, receive polarity, link integrity, jabber status. PCnet-ISA controller also provides External Address Detection Interface(EADITM) allow external hardware address filtering internetworking applications.
PCnet-ISA controller designed directly interface with EISA system bus. contains interface unit, Buffer Management Unit, IEEE 802.3 Media Access Control function, individual 136-byte transmit 128-byte receive FIFOs, IEEE 802.3 defined Attachment Unit Interface (AUI), Twisted Pair Transceiver Media Attachment Unit. PCnet-ISA controller also register compatible with LANCE (Am7990) Ethernet controller. Buffer Management Unit supports LANCE descriptor software model. External remote boot Ethernet physical address PROMs also supported. This advanced Ethernet controller built-in capability automatically selecting either port Twisted Pair transceiver. Only interface active
RELATED PRODUCTS
Part Am79C98 Am79C100 Am7996 Am79C981 Am79C987 Am79C940 Am7990 Am79C90 Am79C900 Am79C961 Am79C965 Am79C970 Am79C974 Description Twisted Pair Ethernet Transceiver (TPEX) Twisted Pair Ethernet Transceiver Plus (TPEX+) IEEE 802.3/Ethernet/Cheapernet Transceiver Integrated Multiport Repeater Plus(IMR+TM) Hardware Implemented Management Information Base(HIMIBTM) Media Access Controller Ethernet (MACETM) Local Area Network Controller Ethernet (LANCE) CMOS Local Area Network Controller Ethernet (C-LANCE) Integrated Local Area Communications Controller(ILACCTM) PCnet-ISA+ Single-Chip Ethernet Controller (with Microsoft® Plug Play® Support) PCnet-32 Single-Chip 32-Bit Ethernet Controller PCnet-PCI Single-Chip Ethernet Controller (for bus) PCnet-SCSI Combination Ethernet SCSI Controller Systems
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Am79C960
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination AM79C960 ALTERNATE PACKAGING OPTION Trimmed Formed Tray (PQJ120) OPTIONAL PROCESSING Blank Standard Processing TEMPERATURE RANGE Commercial +70°C) PACKAGE TYPE (per Prod. Nomenclature/16-038) Plastic Quad Flat Pack (PQR120) SPEED Applicable DEVICE NUMBER/DESCRIPTION Am79C960 PCnetTM-ISA Single Chip Ethernet Controller
Valid Combinations AM79C960 KC\W
Valid Combinations Valid Combinations table lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Am79C960
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TABLE CONTENTS
DISTINCTIVE CHARACTERISTICS 1-343 GENERAL DESCRIPTION 1-343 RELATED PRODUCTS 1-344 ORDERING INFORMATION 1-345 BLOCK DIAGRAM: MASTER MODE 1-352 CONNECTION DIAGRAM: MASTER 1-353 DESIGNATIONS: MASTER LISTED NUMBER 1-354 LISTED NAME 1-355 LISTED GROUP 1-356 DESCRIPTION: MASTER MODE 1-358 INTERFACE 1-358 BOARD INTERFACE 1-359 BLOCK DIAGRAM: SHARED MEMORY 1-361 CONNECTION DIAGRAM: SHARED MEMORY 1-362 DESIGNATIONS: SHARED MEMORY LISTED NUMBER 1-363 LISTED NAME 1-364 LISTED GROUP 1-365 DESCRIPTION: SHARED MEMORY MODE 1-367
INTERFACE 1-367 BOARD INTERFACE 1-368 DESCRIPTION: NETWORK INTERFACES (mode independent) 1-370 INTERFACE 1-370 TWISTED PAIR INTERFACE 1-370 IEEE 1149.1 TEST ACCESS PORT INTERFACE 1-370 DESCRIPTION: POWER SUPPLIES (mode independent) 1-371 FUNCTIONAL DESCRIPTION 1-372 MASTER MODE 1-372 SHARED MEMORY MODE 1-373 NETWORK INTERFACE 1-373
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Am79C960
DETAILED FUNCTIONS 1-374 INTERFACE UNIT (BIU) 1-374 Transfers 1-374 Initialization Block Transfers 1-374 Descriptor Transfers 1-374 Burst-Cycle Transfers 1-374 BUFFER MANAGEMENT UNIT (BMU) 1-374 Initialization 1-374 Reinitialization 1-374 Buffer Management 1-375 Descriptor Rings 1-375 Descriptor Ring Access Mechanism 1-375 Polling 1-376 Transmit Descriptor Table Entry (TDTE) 1-377 Receive Descriptor Table Entry (RDTE) 1-378 MEDIA ACCESS CONTROL 1-379 Transmit Receive Message Data Encapsulation 1-379 Media Access Management 1-380 MANCHESTER ENCODER/DECODER (MENDEC) 1-382 External Crystal Characteristics 1-382 External Clock Drive Characteristics 1-382 MENDEC Transmit Path 1-382 Transmitter Timing Operation 1-383 Receive Path 1-383 Input Signal Conditioning 1-383 Clock Acquisition 1-383 Tracking 1-384 Carrier Tracking Message 1-384 Data Decoding 1-384 Jitter Tolerance Definition 1-384 Attachment Unit Interface (AUI) 1-384 Differential Input Terminations 1-384 Collision Detection 1-384 TWISTED PAIR TRANSCEIVER (T-MAU) 1-385 Twisted Pair Transmit Function 1-385 Twisted Pair Receive Function 1-385 Link Test Function 1-385 Polarity Detection Reversal 1-385 Twisted Pair Interface Status 1-386 Collision Detect Function 1-386 Signal Quality Error (SQE) Test (Heartbeat) Function 1-386 Jabber Function 1-386 Power Down 1-386 EADI(External Address Detection InterfaceTM) 1-387
Am79C960
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PRELIMINARY GENERAL PURPOSE SERIAL INTERFACE (GPSI) 1-388 IEEE 1149.1 TEST ACCESS PORT INTERFACE 1-389 Boundary Scan Circuit 1-389 1-389 Supported Instructions 1-389 Instruction Register Decoding Logic 1-389 Boundary Scan Register (BSR) 1-389 Other Data Register 1-389 POWER SAVINGS MODES 1-390 ACCESS OPERATIONS (SOFTWARE) Resources 1-390 Register Access 1-390 Address PROM Access 1-390 Boot PROM Access 1-390 Static Access 1-390 CYCLES (HARDWARE) 1-390 Master Mode 1-391 Refresh Cycles 1-392 Address PROM Cycles 1-392 Ethernet Controller Register Cycles 1-392 RESET Cycles 1-392 Configuration Register Cycles 1-392 Boot PROM Cycles 1-392 Current Master Operation 1-393 Master Mode Memory Read Cycle 1-393 Master Mode Memory Write Cycle 1-393 Shared Memory Mode 1-394 Address PROM Cycles 1-394 Ethernet Controller Register Cycles 1-394 RESET Cycles 1-394 Configuration Register Cycles 1-394 Boot PROM Cycles 1-394 Static Cycles 1-395 TRANSMIT OPERATION 1-396 Transmit Function Programming 1-396 Automatic Generation 1-396 Transmit Generation 1-397 Transmit Exception Conditions 1-397 Loss Carrier 1-397 RECEIVE OPERATION 1-398 Receive Function Programming 1-398 Automatic Stripping 1-398 Receive Checking 1-399 Receive Exception Conditions 1-399
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Am79C960
LOOPBACK OPERATION 1-399 LEDs 1-399 PCnet-ISA CONTROLLER REGISTERS 1-401 REGISTER ACCESS 1-401 CONTROL STATUS REGISTERS 1-401 CSR0: PCnet-ISA Controller Status Register 1-401 CSR1: IADR[15:0] 1-403 CSR2: IADR[23:16] 1-403 CSR3: Interrupt Masks Deferral Control 1-403 CSR4: Test Features Control 1-404 CSR6: RCV/XMT Descriptor Table Length 1-405 CSR8: Logical Address Filter, LADRF[15:0] 1-405 CSR9: Logical Address Filter, LADRF[31:16] 1-405 CSR10: Logical Address Filter, LADRF[47:32] 1-405 CSR11: Logical Address Filter, LADRF[63:48] 1-405 CSR12: Physical Address Register, PADR[15:0] 1-406 CSR13: Physical Address Register, PADR[31:16] 1-406 CSR14: Physical Address Register, PADR[47:32] 1-406 CSR15: Mode Register 1-406 CSR16: Initialization Block Address 1-408 CSR17: Initialization Block Address 1-408 CSR18-19: Current Receive Buffer Address 1-408 CSR20-21: Current Transmit Buffer Address 1-408 CSR22-23: Next Receive Buffer Address 1-408 CSR24-25: Base Address Receive Ring 1-409 CSR26-27: Next Receive Descriptor Address 1-409 CSR28-29: Current Receive Descriptor Address 1-409 CSR30-31: Base Address Transmit Ring 1-409 CSR32-33: Next Transmit Descriptor Address 1-409 CSR34-35: Current Transmit Descriptor Address 1-409 CSR36-37: Next Next Receive Descriptor Address 1-409 CSR38-39: Next Next Transmit Descriptor Address 1-409 CSR40-41: Current Receive Status Byte Count 1-409 CSR42-43: Current Transmit Status Byte Count 1-410 CSR44-45: Next Receive Status Byte Count 1-410 CSR46: Poll Time Counter 1-410 CSR47: Polling Interval 1-410 CSR48-49: Temporary Storage 1-411 CSR50-51: Temporary Storage 1-411 CSR52-53: Temporary Storage 1-411 CSR54-55: Temporary Storage 1-411 CSR56-57: Temporary Storage 1-411 CSR58-59: Temporary Storage 1-411 CSR60-61: Previous Transmit Descriptor Address 1-411 CSR62-63: Previous Transmit Status Byte Count 1-411 CSR64-65: Next Transmit Buffer Address 1-411 Am79C960 1-349
PRELIMINARY CSR66-67: Next Transmit Status Byte Count 1-411 CSR68-69: Transmit Status Temporary Storage 1-412 CSR70-71: Temporary Storage 1-412 CSR72: Receive Ring Counter 1-412 CSR74: Transmit Ring Counter 1-412 CSR76: Receive Ring Length 1-412 CSR78: Transmit Ring Length 1-412 CSR80: Burst FIFO Threshold Control 1-412 CSR82: Activity Timer 1-413 CSR84-85: Address 1-414 CSR86: Buffer Byte Counter 1-414 CSR88-89: Chip 1-414 CSR92: Ring Length Conversion. 1-414 CSR94: Transmit Time Domain Reflectometry Count 1-414 CSR96-97: Interface Scratch Register 1-415 CSR98-99: Interface Scratch Register 1-415 CSR104-105: SWAP 1-415 CSR108-109: Buffer Management Scratch 1-415 CSR112: Missed Frame Count 1-415 CSR114: Receive Collision Count 1-415 CSR124: Buffer Management Unit Test 1-415 CONFIGURATION REGISTERS 1-416 INITIALIZATION BLOCK 1-419 RLEN TLEN 1-419 RDRA TDRA 1-419 LADRF PADR MODE 1-419 1-420 1-420
RECEIVE DESCRIPTORS 1-420 RMD0 RMD1 RMD2 RMD3 1-420 1-420 1-421 1-421
TRANSMIT DESCRIPTORS 1-421 TMD0 TMD1 TMD2 TMD3 1-422 1-422 1-422 1-423
REGISTER SUMMARY 1-424
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Am79C960
SYSTEM APPLICATION 1-427 INTERFACE 1-427 Compatibility Consideration 1-427 Masters 1-427 Shared Memory 1-427 ADDRESS PROM INTERFACE 1-428 BOOT PROM INTERFACE 1-428 STATIC INTERFACE 1-428 INTERFACE 1-428 10BASE-T INTERFACE 1-429 ABSOLUTE MAXIMUM RATINGS 1-430 OPERATING RANGES 1-430 CHARACTERISTICS 1-431 SWITCHING CHARACTERISTICS 1-433 MASTER MODE 1-433 SHARED MEMORY MODE 1-436 EADI 1-439 JTAG (IEEE 1149.1) INTERFACE 1-439 GPSI 1-440 1-441 10BASE-T INTERFACE 1-442 SWITCHING TEST CIRCUITS 1-443 SWITCHING WAVEFORMS 1-445 MASTER MODE 1-445 SHARED MEMORY MODE 1-451 GPSI 1-458 EADI 1-459 JTAG (IEEE 1149.1) INTERFACE 1-459 1-460 10BASE-T INTERFACE 1-463 APPENDIX PCnet-ISA COMPATIBLE MEDIA INTERFACE MODULES 10BASE-T FILTERS TRANSFORMERS 1-465 ISOLATION TRANSFORMERS 1-465 MANUFACTURER CONTACT INFORMATION 1-466 APPENDIX RECOMMENDATION REDUCING NOISE INJECTION DECOUPLING LOW-PASS FILTER DESIGN 1-467 APPENDIX ALTERNATIVE METHOD INITIALIZATION 1-469 DATA SHEET REVISION SUMMARY 1-470
Am79C960
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BLOCK DIAGRAM: MASTER MODE
DACK IOCHRDY IOCS16 MASTER MEMR MEMW RESET SBHE SMEMR FIFO Control FIFO Interface Unit FIFO
802.3 Core
DXCVR MAUSEL/EAR
CI+/Encoder/ Decoder (PLS) Port DI+/XTAL1 XTAL2 DO+/RXD+/10BASE-T TXD+/TXP+/-
APCS Private Control PRDB0-7 BPCS LED0-3
SD0-15
LA17-23 SA0-19
Buffer Management Unit
IOAM0-1 SLEEP
Config Control
JTAG Port Control
16907B-1
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Am79C960
CONNECTION DIAGRAM: MASTER
DVDD2 APCS BPCS LA17 LA18 LA19 DVSS3 LA20 LA21 LA22 LA23 SBHE DVSS4 DVSS10 DVSS5 SA10 SA11 DVDD3 SA12
PRDB0 PRDB1 PRDB2 DVSS2 PRDB3 PRDB4 PRDB5 PRDB6 PRDB7 DVDD1 LED0 LED1 DVSS1 LED2 LED3 MAUSEL/EAR DXCVR AVDD2 CIDI+ DIAVDD1 DOAVSS1
XTAL2 AVSS2 XTAL1 AVDD3 TXD+ TXP+ TXDTXPAVDD4 RXD+ RXDDVSS12 SD15 SD14 DVSS9 SD13 SD12 DVDD6 SD11 SD10 DVSS8
SA13 SA14 SA15 DVSS6 SA16 SA17 SA18 SA19 MEMW MEMR MASTER DVSS7 DACK IOCS16 DVDD4 SMEMR DVSS11 IOCHRDY RESET SLEEP IOAM0 IOAM1 DVDD5
16907B-3
Am79C960
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DESIGNATIONS: MASTER Listed Number
Name DVDD2 APCS BPCS LA17 LA18 LA19 DVSS3 LA20 LA21 LA22 LA23 SBHE DVSS4 DVSS10 DVSS5 SA10 SA11 DVDD3 SA12 Name SA13 SA14 SA15 DVSS6 SA16 SA17 SA18 SA19 MEMW MEMR MASTER DVSS7 DACK IOCS16 DVDD4 SMEMR DVSS11 IOCHRDY RESET SLEEP IOAM0 IOAM1 DVDD5 Name DVSS8 SD10 SD11 DVDD6 SD12 SD13 DVSS9 SD14 SD15 DVSS12 RXD- RXD+ AVDD4 TXP- TXD- TXP+ TXD+ AVDD3 XTAL1 AVSS2 XTAL2 Name AVSS1 AVDD1 AVDD2 DXCVR MAUSEL/EAR LED3 LED2 DVSS1 LED1 LED0 DVDD1 PRDB7 PRDB6 PRDB5 PRDB4 PRDB3 DVSS2 PRDB2 PRDB1 PRDB0
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Am79C960
DESIGNATIONS: MASTER Listed Name
Name APCS AVDD1 AVDD2 AVDD3 AVDD4 AVSS1 AVSS2 BPCS DACK DVDD1 DVDD2 DVDD3 DVDD4 DVDD5 DVDD6 DVSS1 DVSS2 DVSS3 DVSS4 DVSS5 DVSS6 DVSS7 Name DVSS8 DVSS9 DVSS10 DVSS11 DVSS12 DXCVR IOAM0 IOAM1 IOCHRDY IOCS16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LED0 LED1 LED2 LED3 MASTER MAUSEL/EAR MEMR MEMW PRDB0 PRDB1 Name PRDB2 PRDB3 PRDB4 PRDB5 PRDB6 PRDB7 RESET RXD- RXD+ SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 Name SBHE SD10 SD11 SD12 SD13 SD14 SD15 SLEEP SMEMR TXD- TXD+ TXP- TXP+ XTAL1 XTAL2
Am79C960
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DESIGNATIONS: MASTER Listed Group
Name Interface DACK IOCHRDY IOCS16 LA17-23 MASTER MEMR MEMW RESET SA0-19 SBHE SD0-15 SMEMR Board Interfaces APCS BPCS DXCVR IOAM0-1 LED0 LED1 LED2 LED3 MAUSEL/EAR PRDB0-7 SLEEP XTAL1 XTAL2 Address PROM Chip Select Boot PROM Chip Select Disable Transceiver Input/Output Address LED0/LNKST LED1/SFBD/RCVACT LED2/SRD/RXPOL LED3/SRDCLK/XMTACT SELect/External Address Reject PROM Data Sleep Mode Test Enable Crystal Input Crystal Output Address Enable Acknowledge Request Channel Ready Chip Select Read Select Write Select Interrupt Request Unlatched Address Master Transfer Progress Memory Read Select Memory Write Select Memory Refresh Active System Reset System Address System Byte High Enable System Data System Memory Read Select Function Driver
1-356
Am79C960
DESIGNATIONS: MASTER (continued) Listed Group
Name Attachment Unit Interface (AUI) RXD± TXD± TXP± Power Supplies AVDD AVSS DVDD DVSS Analog Power Analog Ground Digital Power Digital Ground Collision Inputs Receive Data Transmit Data 10BASE-T Receive Data 10BASE-T Transmit Data 10BASE-T Predistortion Control Test Clock Test Data Input Test Data Output Test Mode Select Function Driver
Twisted Pair Transceiver Interface (10BASE-T)
IEEE 1149.1 Test Access Port Interface (JTAG)
Table: Output Driver Types
Name Type Tri-State Tri-State Tri-State Open Drain (mA) (mA)
Am79C960
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PRELIMINARY data reads that data been latched writes. When PCnet-ISA controller Current Master bus, extends cycle long IOCHRDY LOW.
DESCRIPTION: MASTER MODE
These pins part master mode. order understand descriptions, definition some terms from draft IEEE P996 included.
IOCS16 IEEE P996 Terminology
Alternate Master: device that take control through assertion MASTER signal. ability generate addresses control signals order perform operations. Alternate Masters must devices drive SBHE. Ownership: Current Master possesses ownership assert control, address data lines. Current Master: Permanent Master, Temporary Master Alternate Master which currently ownership bus. Permanent Master: Each P996 will have device known Permanent Master that provides certain signals control functions described Section IEEE P996 spec), "Permanent Master". Permanent Master function reside Adapter backplane itself. Temporary Master: device that capable generating request obtain control directly asserting only memory strobes during transfer. Addresses generated device Permanent Master. Chip Select Input/Output When read write operation performed, PCnet-ISA controller will drive IOCS16 indicate that chip supports 16-bit operation this address. motherboard does receive this signal, then motherboard will convert 16-bit access 8-bit accesses.) IOCS16 also input must HIGH least once after reset PCnetISA controller perform 16-bit operations. this grounded then PCnet-ISA controller only performs 8-bit operations. PCnet-ISA controller follows IEEE P996 specification that recommends this function implemented pure decode SA0-9 AEN, with dependency SMEMR, MEMR, MEMW, IOR, IOW; however, some PC/AT clone systems compatible with this approach. this reason, PCnet-ISA controller recommended configured 8-bit machines. Since data moved memory cycles there virtually performance loss incurred running 8-bit compatibility problems virtually eliminated. PCnet-ISA controller configured 8-bit-only disconnecting IOCS16 from tying IOCS16 ground instead.
Interface
Address Enable Input This signal must driven when performs access device.
Read Input driven host indicate that Input/ Output Read operation taking place. only valid signal external address matches PCnet-ISA controller's predefined address location. valid, indicates that slave read operation performed.
DACK
Acknowledge Input Asserted when Permanent Master acknowledges request. When DACK asserted PCnet-ISA controller becomes Current Master asserting MASTER signal.
Write Input driven host indicate that Input/ Output Write operation taking place. only valid signal external address matches PCnet-ISA controller's predefined address location. valid, indicates that slave write operation performed.
Request Output When PCnet-ISA controller needs perform transfer, asserts DRQ. Permanent Master acknowledges with assertion DACK. When PCnet-ISA controller does need deasserts DRQ.
Interrupt Request Output attention signal which indicates that more following status flags set: BABL, MISS, MERR, RINT, IDON, RCVCCO, JAB, MFCO, TXSTRT. status flags have mask which allows suppression INTR assertion. These flags have following meaning:
IOCHRDY
Channel Ready Input/Output When PCnet-ISA controller being accessed, IOCHRDY HIGH indicates that valid data exists
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Am79C960
BABL RCVCCO MISS MERR MFCO RINT IDON TXSTRT Babble Receive Collision Count Overflow Jabber Missed Frame Memory Error Missed Frame Count Overflow Receive Interrupt Initialization Done Transmit Start
refresh periods. DACK asserted when active, DACK assertion ignored. monitored eliminate arbitration problem observed some platforms.
RESET
Reset Input When RESET asserted HIGH PCnet-ISA controller performs internal system reset. RESET must held minimum XTAL1 periods before being deasserted. While reset state, PCnet-ISA controller will tristate deassert outputs predefined reset levels. PCnet-ISA controller resets itself upon power-up.
LA17-23
Unlatched Address Output unlatched address driven PCnet-ISA controller during master cycle. functions these unlatched address pins will change when GPSI mode invoked. table below shows configuration GPSI mode. Please refer section General Purpose Serial Interface detailed information accessing this mode.
Number Function Master Mode LA17 LA18 LA19 LA20 LA21 LA22 LA23 Function GPSI Mode RXDAT SRDCLK RXCRS CLSN STDCLK TXEN TXDAT
SA0-19
System Address Input/Output This contains address information, which stable during operation, regardless source. SA17-19 contain same values unlatched address LA17-19. When PCnet-ISA controller Current Master, SA0-19 will driven actively. When PCnet-ISA controller Current Master, SA0-19 lines continuously monitored determine address match exists slave transfers Boot PROM accesses.
SBHE
System Byte High Enable Input/Output This signal indicates high byte system data used. SBHE driven PCnet-ISA controller when performing mastering operations.
SD0-15
System Data Input/Output These pins used transfer data from PCnet-ISA controller system resources data bus. SD0-15 driven PCnet-ISA controller when performing master writes slave read operations. Likewise, data SD0-15 latched PCnet-ISA controller when performing master reads slave write operations.
MASTER
Master Mode Output This signal indicates that PCnet-ISA controller become Current Master bus. After PCnet-ISA controller received Acknowledge (DACK) response Request (DRQ), Ethernet controller asserts MASTER signal indicate Permanent Master that PCnet-ISA controller becoming Current Master.
SMEMR
System Memory Read Input This used during Boot PROM access. Boot PROM disabled connecting this pin.
MEMR
Memory Read Output MEMR goes perform memory read operation.
MEMW
Memory Write Output MEMW goes perform memory write operation.
Board Interface APCS
Address PROM Chip Select Output This signal asserted when external Address PROM read. When read operation performed first bytes PCnet-ISA controller's space, APCS asserted. outputs external Address PROM drive PROM Data Bus. PCnet-ISA controller buffers contents PROM data drives them lower eight bits System Data Bus.
Memory Refresh Input When asserted, memory refresh active. PCnet-ISA controller uses this signal mask inadvertent Acknowledge assertion during memory
Am79C960
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BPCS
Boot PROM Chip Select Output This signal asserted when Boot PROM read. SA0-19 lines match predefined address block SMEMR active inactive, BPCS signal will asserted. outputs external Boot PROM drive PROM Data Bus. PCnet-ISA controller buffers contents PROM data drives them lower eight bits System Data Bus.
MAUSEL/EAR
Select/ External Address Reject Input This selects 10BASE-T when HIGH interface when XMAUSEL register ISACSR2 (ISA Configuration Register) set. XMAUSEL register cleared, MAUSEL ignored network interface software selected. This default value HIGH left unconnected. EADI mode selected, this becomes input. incoming frame will checked against internally active address detection mechanisms result this check will OR'd with value pin. defind REJECT. EADI section details regarding function timing this signal.
DXCVR
Disable Transceiver Output This disables transceiver. DXCVR output configured initialization sequence. HIGH level indicates Twisted Pair port active port inactive, SLEEP mode been entered. level indicates port active Twisted Pair port inactive.
PRDB0-7
Private Data Input This data Boot PROM Address PROM.
IOAM0-1
Input/Output Address Input These inputs configure address space PCnet-ISA controller memory address space optional Remote Boot PROM with user selectable jumpers. pins pulled HIGH internally. SA1-9 inputs used address comparisons SA14-19 inputs used Boot PROM matching.
IOAM1,0 Base Memory Base C8000 CC000 D0000 D4000
SLEEP
Sleep Input When SLEEP asserted (active LOW), PCnetISA controller performs internal system reset proceeds into power savings mode. outputs will placed their normal reset condition. PCnet-ISA controller inputs will ignored except SLEEP itself. Deassertion SLEEP results wake-up. system must delay starting network controller seconds allow internal analog circuits stabilize.
Test Enable Input This factory only. default value HIGH left unconnected. recommended that this always connected VDD.
LED0-3
Drivers Output These pins sink each driving LEDs. Their meaning software configurable (see section Configuration Registers) they active LOW. When EADI mode selected, pins named LED1, LED2, LED3 change function while LED0 continues indicate 10BASE-T Link Status. MAUSEL input becomes input.
EADI Function SF/BD SRDCLK
XTAL1
Crystal Connection Input internal clock generator uses crystal that attached pins XTAL1 XTAL2. Alternatively, external CMOS-compatible clock signal used drive this pin. Refer section External Crystal Characteristics more details.
XTAL2
Crystal Connection Output internal clock generator uses crystal that attached pins XTAL1 XTAL2. external clock used, this should left unconnected.
1-360
Am79C960
BLOCK DIAGRAM: SHARED MEMORY MODE
IOCHRDY 802.3 Core DXCVR MAUSEL/EAR
IOCS16 MEMR MEMW RESET SBHE Interface Unit
FIFO
CI+/Encoder/ Decoder (PLS) Port DI+/XTAL1 XTAL2 DO+/-
FIFO 10BASE-T
RXD+/TXD+/TXP+/-
SD0-15
FIFO Control Private
ABOE APCS BPCS LED0-3 PRAB0-15 PRDB0-7 SROE SRWE JTAG Port Control
16907B-2
SA0-9
Buffer Management Unit
Control
IOAM0-1 BPAM SMAM SLEEP
Config Control
Am79C960
1-361
CONNECTION DIAGRAM: SHARED MEMORY
DVDD2 APCS BPCS DVSS3 SBHE PRAB0 PRAB1 DVSS4 PRAB2 PRAB3 PRAB4 DVSS10 PRAB5 PRAB6 PRAB7 PRAB8 DVSS5 PRAB9 PRAB10 PRAB11 DVDD3 PRAB12
PRDB0 PRDB1 PRDB2 DVSS2 PRDB3 PRDB4 PRDB5 PRDB6 PRDB7 DVDD1 LED0 LED1 DVSS1 LED2 LED3 MAUSEL/EAR DXCVR AVDD2 CIDI+ DIAVDD1 DOAVSS1
XTAL2 AVSS2 XTAL1 AVDD3 TXD+ TXP+ TXDTXPAVDD4 RXD+ RXDDVSS12 SD15 SD14 DVSS9 SD13 SD12 DVDD6 SD11 SD10 DVSS8
PRAB13 PRAB14 PRAB15 DVSS6 ABOE MEMW MEMR SROE DVSS7 SRWE IOCS16 DVDD4 SMAM BPAM DVSS11 IOCHRDY RESET SLEEP IOAM0 IOAM1 DVDD5
16907B-4
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Am79C960
DESIGNATIONS: SHARED MEMORY Listed Number
Name DVDD2 APCS BPCS DVSS3 SBHE PRAB0 PRAB1 DVSS4 PRAB2 PRAB3 PRAB4 DVSS10 PRAB5 PRAB6 PRAB7 PRAB8 DVSS5 PRAB9 PRAB10 PRAB11 DVDD3 PRAB12 Name PRAB13 PRAB14 PRAB15 DVSS6 ABOE MEMW MEMR SROE DVSS7 SRWE IOCS16 DVDD4 SMAM BPAM DVSS11 IOCHRDY RESET SLEEP IOAM0 IOAM1 DVDD5 Name DVSS8 SD10 SD11 DVDD6 SD12 SD13 DVSS9 SD14 SD15 DVSS12 RXD- RXD+ AVDD4 TXP- TXD- TXP+ TXD+ AVDD3 XTAL1 AVSS2 XTAL2 Name AVSS1 AVDD1 AVDD2 DXCVR MAUSEL/EAR LED3 LED2 DVSS1 LED1 LED0 DVDD1 PRDB7 PRDB6 PRDB5 PRDB4 PRDB3 DVSS2 PRDB2 PRDB1 PRDB0
Am79C960
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DESIGNATIONS: SHARED MEMORY Listed Name
Name ABOE APCS AVDD1 AVDD2 AVDD3 AVDD4 AVSS1 AVSS2 BPAM BPCS DVDD1 DVDD2 DVDD3 DVDD4 DVDD5 DVDD6 DVSS1 DVSS2 DVSS3 DVSS4 DVSS5 DVSS6 DVSS7 Name DVSS8 DVSS9 DVSS10 DVSS11 DVSS12 DXCVR IOAM0 IOAM1 IOCHRDY IOCS16 LED0 LED1 LED2 LED3 MAUSEL/EAR MEMR MEMW PRAB0 PRAB1 PRAB2 PRAB3 PRAB4 PRAB5 PRAB6 PRAB7 PRAB8 PRAB9 Name PRAB10 PRAB11 PRAB12 PRAB13 PRAB14 PRAB15 PRDB0 PRDB1 PRDB2 PRDB3 PRDB4 PRDB5 PRDB6 PRDB7 RESET RXD- RXD+ SBHE Name SD10 SD11 SD12 SD13 SD14 SD15 SLEEP SMAM SROE SRWE TXD- TXD+ TXP- TXP+ XTAL1 XTAL2
1-364
Am79C960
DESIGNATIONS: SHARED MEMORY Listed Group
Name Interface IOCHRDY IOCS16 MEMR MEMW RESET SA0-9 SBHE SD0-15 Board Interfaces ABOE APCS BPAM BPCS DXCVR IOAM0-1 LED0 LED1 LED2 LED3 MAUSEL/EAR PRAB0-15 PRDB0-7 SLEEP SMAM SROE SRWE XTAL1 XTAL2 Address Buffer Output Enable Address PROM Chip Select Boot PROM Address Match Boot PROM Chip Select Disable Transceiver Input/Output Address LED0/LNKST LED1 LED2 LED3 SELect/External Address Reject PRivate Address PRivate Data Sleep Mode Shared Memory Architecture Shared Memory Address Match Static Output Enable Static Write Enable Test Enable Crystal Oscillator Input Crystal Oscillator OUTPUT Address Enable Channel Ready Chip Select Read Select Write Select Interrupt Request Memory Read Select Memory Write Select System Reset System Address System Byte High Enable System Data Function Driver
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DESIGNATIONS: SHARED MEMORY (continued) Listed Group
Name Attachment Unit Interface (AUI) Collision Inputs Receive Data Transmit Data Function Driver
Twisted Pair Transceiver Interface (10BASE-T) RXD± TXD± TXP± 10BASE-T Receive Data 10BASE-T Transmit Data 10BASE-T Predistortion Control
IEEE 1149.1 Test Access Port Interface (JTAG) Power Supplies AVDD AVSS DVDD DVSS Analog Power Analog Ground Digital Power Digital Ground Test Clock Test Data Input Test Data Output Test Mode Select
Table: Output Driver Types
Name Type Tri-State Tri-State Tri-State Open Drain (mA) (mA)
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Am79C960
DESCRIPTION: SHARED MEMORY MODE Interface
Address Enable Input This signal must driven when performs access device.
Interrupt Request Output attention signal which indicates that more following status flags set: BABL, MISS, MERR, RINT, IDON TXSTRT. status flags have mask which allows suppression INTR assertion. These flags have following meaning:
BABL RCVCCO MISS MERR MFCO RINT IDON TXSTRT Babble Receive Collision Count Overflow Jabber Missed Frame Memory Error Missed Frame Count Overflow Receive Interrupt Initialization Done Transmit Start
IOCHRDY
Channel Ready Output When PCnet-ISA controller being accessed, HIGH IOCHRDY indicates that valid data exists data reads that data been latched writes.
IOCS16
Chip Select Input/Output When read write operation performed, PCnet-ISA controller will drive this indicate that chip supports 16-bit operation this address. motherboard does receive this signal, then motherboard will convert 16-bit access 8-bit accesses.) IOCS16 also input must HIGH least once after reset PCnet-ISA controller perform 16-bit operations. this grounded then PCnet-ISA controller only performs 8-bit operations. PCnet-ISA controller follows IEEE P996 specification that recommends this function implemented pure decode SA0-9 AEN, with dependency SMEMR, MEMR, MEMW, IOR, IOW; however, some PC/AT clone systems compatible with this approach. this reason, PCnet-ISA controller recommended configured 8-bit machines. Since data moved memory cycles there virtually performance loss incurred running 8-bit compatibility problems virtually eliminated. PCnet-ISA controller configured 8-bit-only disconnecting IOCS16 from tying IOCS16 ground instead.
MEMR
Memory Read Input MEMR goes perform memory read operation.
MEMW
Memory Write Input MEMW goes perform memory write operation.
RESET
Reset Input When RESET asserted HIGH, PCnet-ISA controller performs internal system reset. RESET must held minimum XTAL1 periods before being deasserted. While reset state, PCnet-ISA controller will tristate deassert outputs predefined reset levels. PCnet-ISA controller resets itself upon power-up.
SA0-9
System Address Input This carries address inputs from system address bus. Address data stable during command active cycle.
Read Input perform Input/Output Read operation device must asserted. only valid signal external address matches PCnet-ISA controller predefined address location. valid, indicates that slave read operation performed.
SBHE
System High Enable Input This signal indicates HIGH byte system data used. There weak pull-up resistor this pin. PCnet-ISA controller installed 8-bit only system like PC/XT, SBHE will always HIGH PCnet-ISA controller will perform only 8-bit operations. There must least going edge this signal before PCnet-ISA controller will perform 16-bit operations.
Write Input perform Input/Output write operation device must asserted. only valid signal external address matches PCnet-ISA controller's predefined address location. valid, indicates that slave write operation performed.
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SD0-15
System Data Input/Output This used transfer data from PCnetISA controller system resources data bus. SD0-15 driven PCnet-ISA controller when performing slave read operations. Likewise, data SD0-15 latched PCnet-ISA controller when performing slave write operations.
IOAM0-1
Input/Output Address Input These inputs configure address space PCnet-ISA controller. pins have on-chip pullup resistor pulled HIGH internally. SA1-9 inputs used address comparisons.
IOAM1,0 Base
Board Interface ABOE
Address Buffer Output Enable Output This goes enable external octal buffer drive contents SA10-15 onto PRAB10-15. Only eight buffers needed.
LED0-3
Drivers Output These pins sink each driving LEDs. Their meaning software configurable (see section Configuration Registers) they active LOW. When EADI mode selected, pins named LED1, LED2, LED3 change function while LED0 continues indicate 10BASE-T Link Status. MAUSEL input becomes input.
EADI Function SF/BD SRDCLK
APCS
Address PROM Chip Select Output This signal asserted when external Address PROM read. When read operation performed first bytes PCnet-ISA controller's space, APCS asserted. outputs external Address PROM drive PROM Data Bus. PCnet-ISA controller buffers contents PROM data drives them lower eight bits System Data Bus. IOCS16 asserted during this cycle.
BPAM
Boot PROM Address Match Input This indicates Boot PROM access cycle. Boot PROM installed, this default value HIGH thus left connected VDD.
MAUSEL/EAR
Select/ Input External Address Reject This selects 10BASE-T when HIGH interface when XMAUSEL register ISACSR2 (ISA Configuration Register) set. XMAUSEL register cleared, MAUSEL ignored network interface software selected. This default value HIGH left unconnected. EADI mode selected, this becomes input. incoming frame will checked against internally active address detection mechanisms result this check will OR'd with value pin. defined REJECT. EADI section details regarding function timing this signal.
BPCS
Boot PROM Chip Select Output This signal asserted when Boot PROM read. BPAM active MEMR active, BPCS signal will asserted. outputs external Boot PROM drive PROM Data Bus. PCnet-ISA controller buffers contents PROM data drives them System Data Bus. IOCS16 asserted during this cycle. 16-bit cycles performed, responsibility external logic assert MEMCS16 signal.
DXCVR
Disable Transceiver Output This disables transceiver. high level indicates Twisted Pair Interface active interface inactive, SLEEP mode been entered. level indicates interface active Twisted Pair interface inactive.
PRAB0-15
Private Address Input/Output Private Address address used drive Address PROM, Remote Boot PROM, SRAM. PRAB10-15 required buffered Buffer with ABOE control SA10-15 inputs.
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PRDB0-7
Private Data Input/Output This data static RAM, Boot PROM, Address PROM.
SROE
Static Output Enable Output This directly controls external SRAM's pin.
SLEEP
Sleep Input When SLEEP input asserted (active LOW), PCnet-ISA controller performs internal system reset proceeds into power savings mode. outputs will placed their normal reset condition. PCnetISA controller inputs will ignored except SLEEP itself. Deassertion SLEEP results wake-up. system must delay starting network controller seconds allow internal analog circuits stabilize.
SRWE
Static Write Enable Output This directly controls external SRAM's pin.
Test Enable Input This factory only. default value HIGH left unconnected. strongly recommended that this always connected VDD.
XTAL1
Crystal Connection Input internal clock generator uses crystal that attached pins XTAL1 XTAL2. Alternatively, external CMOS-compatible clock signal used drive this pin. Refer section External Crystal Characteristics more details.
Shared Memory Architecture Input This sampled after hardware RESET sequence. must pulled permanently operation shared memory mode.
SMAM
Shared Memory Address Match Input This indicates access shared memory when active. type access decided MEMR MEMW.
XTAL2
Crystal Connection Output internal clock generator uses crystal that attached pins XTAL1 XTAL2. external clock used, this should left unconnected.
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DESCRIPTION: NETWORK INTERFACES Interface CI+,
Control Input Input This differential input pair used detect Collision (Signal Quality Error Signal).
TXP+, TXP-
Transmit Predistortion Control Output These 10BASE-T transmit waveform pre-distortion control differential outputs.
DESCRIPTION IEEE 1149.1 (JTAG) TEST ACCESS PORT
Test Clock Input This clock input boundary scan test mode operation. operate MHz. left unconnected, this default value HIGH.
DI+,
Data Input This differential receive data input pair PCnetISA controller.
DO+,
Data Output This differential transmit data output pair from PCnet-ISA controller.
Test Data Input Input This test data input path PCnet-ISA controller. left unconnected, this default value HIGH.
Twisted Pair Interface RXD+, RXD-
Receive Data Input This 10BASE-T port differential receive input pair.
Test Data Output Output This test data output path from PCnet-ISA controller. tri-stated when JTAG port inactive.
TXD+, TXD-
Transmit Data Output These 10BASE-T port differential transmit drivers.
Test Mode Select Input This serial input stream used define specific boundary scan test executed. left unconnected, this default value HIGH.
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DESCRIPTION: POWER SUPPLIES
power pins with prefix digital pins connected digital circuitry digital buffers. power pins with prefix analog power pins connected analog circuitry. analog pins quiet special precaution must taken when doing board layout. Some analog pins more noisy than others must separated from other analog pins.
printed circuit board layout avoid excessive noise these lines. These supply lines should kept separate from DVSS ground pins back power supply practically possible. AVSS1 exception should connected DVSS supply away from remaining AVSS supply pins. table below more details.
DVDD1-6
Digital Power Pins) Power Supplies power digital portions PCnet-ISA controller. Four pins used Input/Output buffer drivers used internal digital circuitry.
AVDD1-4
Analog Power Pins) Power Supplies power analog portions PCnet-ISA controller. Special attention should paid printed circuit board layout avoid excessive noise these lines. These supply lines should kept separate from DVDD supply pins back power supply practically possible. AVDD3 exception should connected DVDD supply away from remaining AVDD supply pins. table below more details.
DVSS1-12
Digital Ground Pins) Power Supplies ground reference digital portions PCnet-ISA controller. pins used Input/Output buffer drivers used internal digital circuitry.
AVSS1-2
Analog Ground Pins) Power Supplies ground reference analog portions PCnet-ISA controller. Special attention should paid Analog Power Pins Circuits Which They Connected
Analog Power AVDD2 AVDD4 AVDD1 Analog Ground AVSS2 Circuit These pins connected analog voltage reference circuit VCO. These pins connected analog circuits such Twisted Pair receive logic. AVSS1 These pins connected Twisted Pair drivers. Comments These pins should kept quiet. They should kept separated with low- high-frequency by-pass capacitors. These pins moderately quiet should connected supply short distance away from DVDD pins. These pins more noisy should connected DVDD/DVSS supplies.
AVDD3
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PRELIMINARY with very low-end machines, such PC/XTs that support mastering, very high machines which require local packet buffering increased system latency. network interface provides Attachment Unit Interface Twisted-Pair Transceiver functions. Only interface active particular time. allows connection isolation transformer 10BASE5 10BASE2, thick thin based coaxial cables. Twisted-Pair Transceiver interface allows connection unshielded twisted-pair cables specified Section supplement IEEE 802.3 Standard (Type 10BASE-T).
FUNCTIONAL DESCRIPTION
PCnet-ISA controller highly integrated system solution PC-AT architecture. provides Ethernet controller, port, 10BASE-T transceiver. PCnet-ISA controller directly interfaced system bus. PCnet-ISA controller contains interface unit, Buffer Management Unit, 802.3 Media Access Control function, separate 136-byte transmit 128-byte receive FIFOs, IEEE defined Attachment Unit Interface (AUI), Twisted-Pair Transceiver Media Attachment Unit. addition, Sleep function been incorporated which provides standby current power sensitive applications. PCnet-ISA controller register compatible with LANCE (Am7990) Ethernet controller PCnet-ISA+ controller (Am79C961). Buffer Management Unit supports LANCE descriptor software model PCnet-ISA controller software compatible with Novell NE2100 NE1500T add-in cards. External remote boot Ethernet physical address PROMs supported. location registers PROMs configured selected pins internal address comparators master mode) external logic shared memory mode). PCnet-ISA controller's master architecture brings system manufacturers (adapter card motherboard makers alike) something they have been able enjoy with other architectures-a low-cost system solution that provides lowest parts count highest performance. bus-mastering device, costly power-hungry external SRAMs needed packet buffering. This results lower system cost fewer components, less real-estate less power. PCnet-ISA controller's advanced mastering architecture also provides high data throughput utilization even better performance. offer greater flexibility, PCnet-ISA controller shared memory mode meet varying application needs. shared memory architecture compatible
Master Mode
System Interface PCnet-ISA controller fundamental operating modes, Master Shared Memory. selection either Master mode Shared Memory mode must done through hard wiring; software configurable. Master mode provides Am7990 (LANCE) compatible Ethernet controller, Ethernet Address PROM, Boot PROM, device configuration registers. optional Boot PROM memory address space expected kilobytes less size. memory address always related address. example, 0x300 always associated with 0xC8000. On-chip address comparators control device selection based value input pins IOAM0 IOAM1. SMEMR input left unconnected applications where Remote Boot PROM needed. address PROM, board configuration registers, Ethernet controller occupy bytes space located four different starting addresses. Data buffers located motherboard memory accessed PCnet-ISA controller when device becomes Current Master.
16-Bit System Data 24-Bit System Address
SD0-15
PRDB0-7 APCS PCnet-ISA BPCS
8-Bit Private Data
Controller
D0-7 A0-X
Ethernet Address PROM
SA0-19 LA17-23
D0-7 A0-X
Boot PROM
16907B-5
Master Block Diagram 1-372 Am79C960
Shared Memory Mode
System Interface Shared Memory mode other fundamental operating mode available PCnet-ISA controller. PCnet-ISA controller uses same descriptor buffer architecture LANCE, these data structures stored static controlled PCnet-ISA controller. static visible memory resource other resources look same Master mode. Boot PROM selected external device which drives Boot PROM Address Match (BPAM) input PCnet-ISA controller. PCnet-ISA controller perform 8-bit accesses from 8-bit Boot PROM present16-bits data. shared memory works same way, with external device generating Shared Memory Address Match PCnet-ISA controller performing read write 16-bit data conversion. Converting shared memory accesses from 8-bit cycles 16-bit cycles allows much faster 16-bit cycle timing while cutting number cycles half. This raises performance more than 400% what could achieved with 8-bit cycles. Converting boot PROM accesses 16-bit cycles allows memory resources same Kbyte block memory without clash between devices with different data widths. Note that external address buffer must drive bits PRAB10-15 even static less than Kbytes. PCnet-ISA controller uses internal
address comparator perform SRAM prefetches Private Data Bus; PRAB0-15 signals used internally determine whether SRAM read cycle prefetch match miss. Access Ethernet controller registers, board configuration registers, Address PROM done with on-chip address comparators. Network Interface PCnet-ISA controller connected IEEE 802.3 network network interface ports. Attachment Unit Interface (AUI) provides IEEE 802.3 compliant differential interface remote transceiver system board. 10BASE-T interface provides twisted-pair Ethernet port. PCnet-ISA controller provides three modes network interface selection: automatic selection, software selection, jumper selection 10BASE-T interface. automatic selection mode, PCnet-ISA controller will select interface that connected network checking Link Status state machine. both 10BASE-T interfaces connected, 10BASE-T interface selected over AUI. PCnet-ISA controller initialized software selection network interface, will read PORTSEL [1:0] bits Mode register (CSR15.8 CSR15.7) determine which interface needs activated. jumper selection network interface, MAUSEL used. When XMAUSEL ISACSR2 set, HIGH will select 10BASE-T interface, will select interface.
16-Bit Private Address 16-Bit System Data
PRAB0-15 PRDB0-7
A0-X D0-7
8-Bit Private Data
Ethernet Address PROM
System Address
APCS SROE BPCS ABOE BPAM SMAM SRWE
PCnet-ISA Controller
A0-X D0-7
8-Bit SRAM
Address Buffer Address Compare
A0-X
Boot
D0-7 PROM 16907B-6
Shared Memory Block Diagram
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DETAILED FUNCTIONS Interface Unit (BIU)
interface unit mixture state machine asynchronous logic. handles types accesses: accesses where PCnet-ISA controller slave accesses where PCnet-ISA controller Current Master. slave mode, signals like IOCS16 asserted deasserted soon appropriate inputs received. IOCHRDY asynchronously driven PCnet-ISA controller needs wait state. released synchronously when PCnet-ISA controller ready. When PCnet-ISA controller Current Master, signals generates synchronous on-chip clock. Transfers will initiate transfers according type operation being performed. There three primary types transfers: Initialization Block Transfers Once been granted mastership, will perform four data transfer cycles (eight bytes) before relinquishing bus. four transfers within mastership period will always read cycles contiguous addresses. There words transfer there will three mastership periods. Descriptor Transfers Once been granted mastership, will perform appropriate number data transfer cycles before relinquishing bus. transfers within mastership period will always same type (either read write), noncontiguous addresses. Only bytes which need read written accessed. Burst-Cycle Transfers Once been granted mastership, will perform series consecutive data transfer cycles before relinquishing bus. Each data transfer will performed sequentially, with issue address, transfer data with appropriate output signals indicate selection active data bytes during transfer. transfers within mastership cycle will either read write cycles, will contiguous addresses. number data transfer cycles within burst dependent programming DMAPLUS option (CSR4, 14). DMAPLUS maximum transfers will performed. This changed writing burst register (CSR80), default takes same amount time Am2100 family LANCE-based boards, little over microseconds. DMAPLUS burst will continue until FIFO filled high threshold bytes transmit operation) emptied threshold bytes receive operation). exact number transfer cycles this 1-374
case will dependent latency system BIU's mastership request speed operation.
Buffer Management Unit (BMU)
buffer management unit micro-coded state machine which implements initialization block descriptor architecture. Initialization PCnet-ISA controller initialization includes reading initialization block memory obtain operating parameters. initialization block read when INIT CSR0 set. INIT should before concurrent with STRT insure correct operation. Four words time read released each block reads, total three arbitration cycles. Once initialization block been read processed, knows where receive transmit descriptor rings are. completion read operation after internal registers have been updated, IDON will CSR0, interrupt generated IENA set. Initialization Block vectored contents CSR1 (least significant bits address) CSR2 (most significant bits address). block contains user defined conditions PCnet-ISA controller operation, together with address length information allow linkage transmit receive descriptor rings. There alternative method initialize PCnet-ISA controller. Instead initialization initialization block memory, data written directly into appropriate registers. Either method used discretion programmer. registers written directly, INIT must set, initialization block will read thus overwriting previously written information. Please refer Appendix details this alternative method. Reinitialization transmitter receiver section PCnet-ISA controller turned initialization block (MODE Register DTX, bits CSR15[1:0]). state transmitter receiver monitored through CSR0 (RXON, TXON bits). PCnet-ISA controller should reinitialized transmitter and/or receiver were turned during original initialization subsequently required activate them, either section shut detection error condition (MERR, UFLO, BUFF error). Reinitialization done initialization block setting STOP CSR0, followed writing CSR15, then setting START CSR0. Note that this form restart will perform same PCnet-ISA controller LANCE. particular, PCnet-ISA controller reloads transmit receive descriptor pointers with their respective base
Am79C960
PRELIMINARY dresses. This means that software must clear descriptor bits reset descriptor ring pointers before restart PCnet-ISA controller. reload descriptor base addresses performed LANCE only after initialization, restart LANCE without initialization leaves LANCE pointing same descriptor locations before restart. Buffer Management Buffer management accomplished through message descriptor entries organized ring structures memory. There rings, receive ring transmit ring. size message descriptor entry words bytes). Descriptor Rings Each descriptor ring must organized contiguous area memory. initialization time (setting INIT CSR0), PCnet-ISA controller reads user-defined base address transmit receive descriptor rings, which must 8-byte boundary, well number entries contained descriptor rings. default, maximum ring entries permitted when utilizing initialization block, which uses values TLEN RLEN specify transmit receive descriptor ring lengths. However, ring lengths manually defined 65535) writing transmit receive ring length registers (CSR76,78) directly. Each ring entry contains following information:
address actual message data buffer
Status information indicating condition
buffer Receive descriptor entries similar (but identical) transmit descriptor entries. Both composed four registers, each bits wide total bytes. permit queuing de-queuing message buffers, ownership each buffer allocated either PCnet-ISA controller host. within descriptor status information, either (see section RMD), used this purpose. "Deadly Embrace" conditions avoided ownership mechanism. Only owner permitted relinquish ownership write field descriptor entry. device that current owner descriptor entry cannot assume ownership change field entry. Descriptor Ring Access Mechanism initialization, PCnet-ISA controller reads base address both transmit receive descriptor rings into CSRs PCnet-ISA controller during subsequent operation. When transmit receive functions begin, base address each ring loaded into current descriptor address registers address next descriptor entry transmit receive rings computed loaded into next descriptor address registers.
user host memory length message buffer
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24-Bit Base Address Pointer Initialization Block CSR2 IADR[23:16] CSR1 IADR[15:0]
Descriptor Ring DESCRIPTOR RINGS desc. start
desc. start
RMD0
RMD0 RMD1 RMD2 RMD3
Initialization Block MODE PADR[15:0] PADR[31:16] PADR[47:32] LADRF[15:0] LADRF[31:16] LADRF[47:32] LADRF[63:48] RDRA[15:0] RLEN RDRA[23:16] TDRA[15:0] TLEN TDRA[23:16] Buffers Data Buffer Data Buffer Data Buffer
DESCRIPTOR RINGS Descriptor DESCRIPTOR RINGS Ring desc. start 16907B-7 TMD0 TMD0 TMD1 TMD2 TMD3 desc. start
Buffers
Data Buffer
Data Buffer
Data Buffer 16907B-7
Initialization Block Descriptor Rings Polling When there channel activity there pre- post-receive transmit activity being performed PCnet-ISA controller, then PCnet-ISA controller will periodically poll current receive transmit descriptor entries order ascertain their ownership. DPOLL CSR4 set, then transmit polling function disabled. typical polling operation consists following: PCnet-ISA controller will current receive descriptor address stored internally vector appropriate Receive Descriptor Table Entry (RDTE). will then current transmit descriptor address (stored internally) vector appropriate Transmit Descriptor Table Entry (TDTE). These accesses will made RMD1 RMD0 current RDTE TMD1 TMD0 current TDTE periodic polling intervals. information collected during polling activity will stored internally appropriate CSRs. (i.e. CSR18-19, CSR20-21, CSR40, CSR42, CSR50, CSR52). UnOWNed descriptor status will internally ignored.
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PRELIMINARY typical receive poll occurs under following conditions: PCnet-ISA controller does possess ownership current RDTE poll time elapsed RXON PCnet-ISA controller does possess ownership next RDTE poll time elapsed RXON RXON PCnet-ISA controller will never poll RDTE locations. RXON=1, system should always have least RDTE available possibility receive event. When there only RDTE, there polling next RDTE. typical transmit poll occurs under following conditions: PCnet-ISA controller does possess ownership current TDTE DPOLL TXON poll time elapsed, PCnet-ISA controller does possess ownership current TDTE DPOLL TXON packet just been received, PCnet-ISA controller does possess ownership current TDTE DPOLL TXON packet just been transmitted. poll time interval nominally defined 32,768 crystal clock periods, However, poll time register controlled internally microcode, other microcode controlled operation will interrupt incrementing poll count register. example, when receive packet accepted PCnet-ISA controller, device suspends execution polltime-incrementing microcode that receive microcode routine instead executed. Poll-timeincrementing code resumed when receive operation completely finished. Note, however, that following completion receive transmit operation, poll operation will always performed. poll time count register never reset. Note that nondefault value desired, then strict sequence setting INIT CSR0, waiting INITDONE, then writing CSR47, then setting STRT CSR0 must observed, otherwise default value will overwritten. CSR47 section details.
Setting TDMD CSR0 will cause microcode controller exit poll counting code immediately perform polling operation. RDTE ownership been previously established, then RDTE poll will performed ahead TDTE poll. Transmit Descriptor Table Entry (TDTE) after TDTE access, PCnet-ISA controller finds that that TDTE set, then PCnet-ISA controller resumes poll time count reexamines same TDTE next expiration poll time count. TDTE set, PCnet-ISA controller will immediately request order reset this descriptor; this condition would normally found following LCOL RETRY error that occurred middle transmit packet chain buffers. After resetting this descriptor, PCnet-ISA controller will again immediately request order access next TDTE location ring. buffer length will reset. LANCE buffer length interpreted 4096-byte buffer. acceptable have length buffer transmit with acceptable have length buffer with start packet (STP) set, then microcode control proceeds routine that will enable transmit data transfers FIFO. transmit buffers data chained (ENP=0 first buffer), then PCnet-ISA controller will look ahead next transmit descriptor after performed least transmit data transfer from first buffer. More than transmit data transfer possibly take place, depending upon state transmitter. transmit descriptor lookahead reads TMD0 first TMD1 second. contents TMD0 TMD1 will stored Next Descriptor Address (CSR32), Next Byte Count (CSR66) Next Status (CSR67) regardless state bit. This transmit descriptor lookahead operation performed only once. PCnet-ISA controller does next TDTE (i.e. second TDTE this packet), then will complete transmission current buffer then update status current (first) TDTE with BUFF UFLO bits being set. This will cause transmitter disabled (CSR0, TXON PCnet-ISA controller will have restarted restore transmit function. situation that matches this description implies that system been able stay ahead PCnet-ISA controller transmit descriptor ring and, therefore, condition treated fatal error. avoid this situation, system should always transmit chain descriptor bits reverse order.
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PRELIMINARY TINT CSR0 indicate completion transmission. This causes interrupt signal IENA CSR0 been TINbit CSR3 reset. Receive Descriptor Table Entry (RDTE) PCnet-ISA controller does both current next Receive Descriptor Table Entry, then PCnet-ISA controller will continue poll according polling sequence described above. receive descriptor ring length there next descriptor, look ahead poll will take place. poll operation revealed that current next RDTE belongs PCnet-ISA controller, then additional poll accesses necessary. Future poll operations will include RDTE accesses long PCnet-ISA controller retains ownership current next RDTE. When receive activity present channel, PCnet-ISA controller waits complete address message arrive. then decides whether accept reject packet based active addressing schemes. packet accepted PCnet-ISA controller checks current receive buffer status register CRST (CSR40) determine ownership current buffer. ownership lacking, then PCnet-ISA controller will immediately perform (last ditch) poll current RDTE. ownership still denied, then PCnet-ISA controller buffer which store incoming message. MISS will CSR0 interrupt will generated IENA (CSR0) MISSM (CSR3). Another poll current RDTE will occur until packet finished. PCnet-ISA controller sees that last poll (either normal poll last-ditch effort described above paragraph) current RDTE shows valid ownership, then proceeds poll next RDTE. Following this poll, regardless outcome this poll, transfers receive data from FIFO begin. Regardless ownership second receive descriptor, PCnet-ISA controller will continue perform receive data transfers first buffer, using burst-cycle transfers. packet length exceeds length first buffer, PCnet-ISA controller does second buffer, ownership current descriptor will passed back system writing zero RMD1 status will written indicating buffer (BUFF possibly overflow (OFLO errors. packet length exceeds length first (current) buffer, PCnet-ISA controller does second (next) buffer, ownership will passed back system writing zero RMD1 when first buffer full. Receive data transfers second buffer occur before PCnet-ISA controller proceeds look ahead ownership third buffer. Such action will depend upon state FIFO when status been updated first
PCnet-ISA controller does second TDTE chain, will gradually empty contents first buffer bytes needed transmit operation), perform single-cycle transfer update status (reset TMD1) first descriptor, then perform data access second buffer chain before executing another lookahead operation. (i.e. lookahead third descriptor.) PCnet-ISA controller queue packets transmit FIFO. Call them packet packet "Y", where after "X". Assume that packet currently being transmitted. Because PCnet-ISA controller perform lookahead data transfer over ENP, possible PCnet-ISA controller update TDTE buffer belonging packet while packet being transmitted packet uses data chaining. This operation will result non-sequential TDTE accesses packet completes transmission PCnet-ISA controller writes status, since packet "X"'s TDTE before TDTE accessed part lookahead data transfer from packet "Y". This should cause problem properly written software which processes buffers sequence, waiting ownership before proceeding. error occurs transmission before bytes current buffer have been transferred, then TMD2 TMD1 current buffer will written; that case, data transfers from next buffer will commence. Instead, following TMD2/TMD1 update, PCnet-ISA controller will next transmit packet, any, skipping over rest packet which experienced error, including chained buffers. This done returning polling microcode where will immediately access next descriptor find condition described earlier. that case, PCnet-ISA controller will reset this descriptor continue like manner until descriptor with more transmit packets ring) (the first buffer packet) reached. transmit operation, whether successful with errors, completion descriptor updates, PCnet-ISA controller will always perform another poll operation. described earlier, this poll operation will begin with check current RDTE, unless PCnet-ISA controller already owns that descriptor. Then PCnet-ISA controller will proceed polling next TDTE. transmit descriptor zero value, then PCnet-ISA controller will resume poll time count incrementation. transmit descriptor value ONE, then PCnet-ISA controller will begin filling FIFO with transmit data initiate transmission. This end-ofoperation poll avoids inserting poll time counts between successive transmit packets. Whenever PCnet-ISA controller completes transmit packet (either with without error) writes status information current descriptor, then 1-378
Am79C960
PRELIMINARY scriptor. case, lookahead will performed third buffer information gathered will stored chip, regardless state ownership bit. transmit flow, lookahead operations performed only once. This activity continues until PCnet-ISA controller recognizes completion packet (the last byte this receive message been removed from FIFO). PCnet-ISA controller will subsequently update current RDTE status with packet (ENP) indication set, write message byte count (MCNT) complete packet into RMD2 overwrite "current" entries CSRs with "next" entries.
ridden allow illegally short (less than bytes packet data) messages transmitted and/ received.
Media Access Control
Media Access Control engine incorporates essential protocol requirements operation compliant Ethernet/802.3 node, provides interface between FIFO sub-system Manchester Encoder/Decoder (MENDEC). engine fully compliant Section ISO/ 8802-3 (ANSI/IEEE Standard 1990 Second Edition) ANSI/IEEE 802.3 (1985). engine provides programmable enhanced features designed minimize host supervision post-message processing. These features include ability disable retries after collision, dynamic generation packet-by-packet basis, automatic field insertion deletion enforce minimum frame size attributes. primary attributes engine are:
Transmit receive message data encapsulation
Framing (Frame Boundary Delimitation, Frame Synchronization) engine will autonomously handle construction transmit frame. Once Transmit FIFO been filled predetermined threshold (set XMTSP CSR80), providing access channel currently permitted, engine will commence 7-byte preamble sequence (10101010b, where first transmitted engine will subsequently append Start Frame Delimiter (SFD) byte (10101011b) followed serialized data from Transmit FIFO. Once data been completed, engine will append (most significant first) which computed entire data portion message.
Note that user responsible correct ordering content each fields frame, including destination address, source address, length/type packet data. receive section engine will detect incoming preamble sequence lock encoded clock. internal MENDEC will decode serial stream present this engine. will discard first bits information before searching sequence. Once detected, subsequent bits treated part frame. engine will inspect length field ensure minimum frame size, strip unnecessary characters enabled), pass remaining bytes through Receive FIFO host. stripping performed, engine will also strip received bytes, although normal computation checking will occur. Note that apart from stripping, frame will passed unmodified host. length field value greater, engine will attempt validate length against number bytes contained message. frame terminates suffers collision before bytes information (after SFD) have been received, engine will automatically delete frame from Receive FIFO, without host intervention.
Framing (frame boundary delimitation, frame synchronization) Addressing (source destination address handling) Error detection (physical medium transmission errors) Media access management Medium allocation (collision avoidance) Contention resolution (collision handling) Transmit Receive Message Data Encapsulation engine provides minimum frame size enforcement transmit receive packets. When APAD_XMT (bit CSR4), transmit messages will padded with sufficient bytes (containing 00h) ensure that receiving station will observe information field (destination address, source address, length/type, data FCS) bytes. When ASTRP_RCV (bit CSR4), receiver will automatically strip bytes from received message observing value length field, stripping excess bytes this value below minimum data size bytes). Both features independently over-
Addressing (Source Destination Address Handling) first bytes information after will interpreted destination address field. engine provides facilities physical, logical, broadcast address reception. addition, multiple physical addresses constructed (perfect address filtering) using external logic conjunction with EADIinterface. Error Detection (Physical Medium Transmission Errors) engine provides several facilities which report recover from errors medium. addition,
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PRELIMINARY number dribbling bits there error, then there Framing error (FRAM number dribbling bits less than there error, then there also Framing error (FRAM number dribbling bits then there Framing error. There (FCS) error. Counters provided report Receive Collision Count Runt Packet Count used network statistics utilization calculations. Note that engine detects received packet which pattern preamble (after first bits, which ignored), entire packet will ignored. engine will wait network inactive before attempting receive next packet. Media Access Management basic requirement stations network provide fairness channel allocation. 802.3/Ethernet protocol defines media access mechanism which permits stations access channel with equality. node attempt contend channel waiting predetermined time (Inter Packet interval) after last activity, before transmitting medium. channel multidrop communications medium (with various topological configurations permitted) which allows single station transmit other stations receive. nodes simultaneously contend channel, their signals will interact, causing loss data (defined collision). responsibility attempt avoid recover from collision, guarantee data integrity end-to-end transmission receiving station.
network protected from gross errors inability host keep pace with engine activity. completion transmission, following transmit status available appropriate areas:
exact number transmission retry attempts
(ONE, MORE, RTRY)
Whether engine Defer (DEF)
channel activity
Loss Carrier, indicating that there
interruption ability engine monitor transmission. Repeated LCAR errors indicate potentially faulty transceiver network connection.
Late Collision (LCOL) indicates that
transmission suffered collision after slot time. This indicative badly configured network. Late collisions should occur normal operating network.
Collision Error (CERR) indicates that
transceiver respond with Test message within predetermined time after transmission completed. This failed transceiver, disconnected faulty transceiver drop cable, fact transceiver does support this feature feature disabled). addition reporting network errors, engine will also attempt prevent creation network error inability host service engine. During transmission, host fails keep Transmit FIFO filled sufficiently, causing underflow, engine will guarantee message either sent runt packet (which will deleted receiving station) invalid (which will also cause receiver reject message). status each receive message available appropriate areas. Framing errors (FRAM) reported, although received frame still passed host. FRAM error will only reported error detected there nonintegral number bits message. engine will ignore seven additional bits message (dribbling bits), which occur under normal network operating conditions. reception eight additional bits will cause engine de-serialize entire byte, will result received message being modified. PCnet-ISA controller handle dribbling bits when received packet terminates. During reception, generated every serial (including dribbling bits) coming from cable, although internally saved value only updated eighth each byte boundary). framing error reported user follows:
Medium Allocation (Collision Avoidance) IEEE 802.3 Standard (ISO/IEC 8802-3 1990) requires that CSMA/CD monitor medium traffic looking carrier activity. When carrier detected medium considered busy, should defer existing message.
IEEE 802.3 Standard also allows optional part deferral after receive message.
ANSI/IEEE 802.3-1990 Edition, 4.2.3.2.1: "Note: possible carrier sense indication fail asserted during collision media. deference process simply times interpacket based this indication possible short interFrame generated, leading potential reception failure subsequent frame. enhance system robustness following optional measures, specified 4.2.8, recom-
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mended when InterFrameSpacingPart1 other than zero: Upon completing transmission, start timing interpacket gap, soon transmitting carrierSense both false. When timing interpacket following reception, reset interpacket timing carrier Sense becomes true during first interpacket timing interval. During final interval timer shall reset ensure fair access medium. initial period shorter than interval permissible including zero." engine implements optional receive part deferral algorithm, with first part inter-frame-spacing time second part inter-frame-spacing interval therefore
PCnet-ISA controller will perform two-part deferral algorithm specified Section 4.2.8 (Process Deference). Inter Packet (IPG) timer will start timing InterFrameSpacing after receive carrier de-asserted. During first part deferral (InterFrameSpacingPart1 IFS1) PCnet-ISA controller will defer pending transmit frame respond receive message. counter will reset zero continuously until carrier de-asserts, which point counter will resume count once again. Once IFS1 period elapsed, PCnet-ISA controller will begin timing second part deferral (InterFrameSpacingPart2 IFS2) Once IFS1 completed, IFS2 commenced, PCnet-ISA controller will defer receive packet transmit packet pending. This means that PCnet-ISA controller will attempt receive receive packet, since will start transmit, generate collision PCnet-ISA controller will guarantee complete preamble (64-bit) (32-bit) sequence before ceasing transmission invoking random backoff algorithm. addition, transmit part deferral implemented option which disabled using DXMT2PD (CSR3). Two-part deferral after transmission useful ensuring that severe shrinkage cannot occur specific circumstances, causing transmit message follow receive message closely make them indistinguishable. During time period immediately after transmission been completed, external transceiver case standard connected device), should generate Test message nominal burst 5-15 Times duration) pair (within after transmission ceases). During time period which Test message expected PCnet-ISA controller will respond receive carrier sense.
conclusion output function, opens time window during which expects signal_quality_error signal asserted Control circuit. time window begins when CARRIER_STATUS becomes CARRIER_OFF. execution output function does cause CARRIER_ON occur, test occurs DTE. duration window shall least more than During time window Carrier Sense Function inhibited."
PCnet-ISA controller implements carrier sense "blinding" period within from deassertion carrier sense after transmission. This effectively means that when transmit part deferral enabled (DXMT2PD cleared) IFS1 time from after transmission. However, since shrinkage below will rarely encountered correctly configured network, since fragment size will larger than blinding window, then counter will reset worst case shrinkage/fragment scenario PCnet-ISA controller will defer transmission. addition, PCnet-ISA controller will restart "blinding" period carrier detected within IFS1 period, will commence timing entire IFS1 period.
Contention Resolution (Collision Handling) Collision detection performed reported engine integrated Manchester Encoder/ Decoder (MENDEC).
collision detected before complete preamble/ sequence been transmitted, Engine will complete preamble/SFD before appending sequence. collision detected after preamble/SFD been completed, prior bits being transmitted, Engine will abort transmission, append sequence immediately. sequence 32-bit zeroes pattern. Engine will attempt transmit frame total times (initial attempt plus retries) normal collisions (those within slot time). Detection collision will cause transmission re-scheduled, dependent backoff time that Engine computes. single retry required, will Transmit Frame Status (TMD1 Transmit Descriptor Ring). more than retry required, MORE will set. attempts experienced collisions, RTRY TMD2) will (ONE MORE will clear), transmit message will flushed from FIFO. retries have been disabled setting DRTY MODE register (CSR15), Engine will abandon transmission frame detection first collision. this case, only RTRY will transmit message will flushed from FIFO. collision detected after times have been transmitted, collision termed late collision.
ANSI/IEEE 802.3-1990 Edition, 7.2.4.6 (1)):
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PRELIMINARY External Crystal Characteristics When using crystal drive oscillator, crystal specification shown table used ensure less than ±0.5 jitter DO±. Table External Crystal Characteristics
Parameter 1.Parallel Resonant Frequency 2.Resonant Frequency Error 3.Change Resonant Frequency With Respect Temperature pF)* 4.Crystal Capacitance 5.Motional Crystal Capacitance (C1) 6.Series Resistance 7.Shunt Capacitance 8.Drive Level 0.022 Units
Engine will abort transmission, append sequence, LCOL bit. retry attempt will scheduled detection late collision, FIFO will flushed. IEEE 802.3 Standard requires "truncated binary exponential backoff" algorithm which provides controlled pseudo-random mechanism enforce collision backoff interval, before re-transmission attempted.
ANSI/IEEE 802.3-1990 Edition, 4.2.3.2.5: enforcing collision (jamming), CSMA/CD sublayer delays before attempting re-transmit frame. delay integer multiple slotTime. number slot times delay before re-transmission attempt chosen uniformly distributed random integer range: where (n,10)."
PCnet-ISA controller provides alternative algorithm, which suspends counting slot time/IPG during time that receive carrier sense detected. This algorithm aids networks where large numbers nodes present, numerous nodes collision. algorithm effectively accelerates increase backoff time busy networks, allows nodes involved collision access channel while colliding nodes await reduction channel activity. Once channel activity reduced, nodes resolving collision time their slot time counters normal.
Requires trimming crystal spec; trim total
External Clock Drive Characteristics When driving oscillator from external clock source, XTAL2 must left floating (unconnected). external clock having following characteristics must used ensure less than ±0.5 jitter DO±:
Clock Frequency: Rise/Fall Time (tR/tF): XTAL1 HIGH/LOW Time (tHIGH/tLOW): XTAL1 Falling Edge Falling Edge Jitter: ±0.01% from VDD-0.5 ±0.2 input (VDD/2)
Manchester Encoder/Decoder (MENDEC)
integrated Manchester Encoder/Decoder provides (Physical Layer Signaling) functions required fully compliant IEEE 802.3 station. MENDEC provides encoding function data transmitted network using high accuracy on-board oscillator, driven either crystal oscillator external CMOS-level compatible clock. MENDEC also provides decoding function from data received from network. MENDEC contains Power Reset (POR) circuit, which ensures that analog portions PCnet-ISA controller forced into their correct state during power-up, prevents erroneous data transmission and/or reception during this time.
MENDEC Transmit Path transmit section encodes separate clock data input signals into standard Manchester encoded serial stream. transmit outputs (DO±) designed operate into terminated transmission lines. When operating into terminated transmission line, transmit signaling meets required output levels skew Cheapernet, Ethernet, IEEE-802.3.
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PRELIMINARY Transmitter Timing Operation fundamental-mode crystal oscillator provides basic timing reference MENDEC portion PCnet-ISA controller. crystal input divided create internal transmit clock reference. Both clocks into Manchester Encoder generate transitions encoded data stream. internal transmit clock used MENDEC internally synchronize Internal Transmit Data (ITXDAT) from controller Internal Transmit Enable (ITXEN). internal transmit clock also used stable bit-rate clock receive section MENDEC controller. oscillator requires external 0.005% crystal, external 0.01% CMOS-level input reference. accuracy requirements, external crystal used, tighter because allowance on-chip oscillator must made deliver final accuracy 0.01%. Transmission enabled controller. long ITXEN request remains active, serial output controller will Manchester encoded appear DO±. When internal request dropped controller, differential transmit outputs idle states, dependent TSEL Mode Register (CSR15,
TSEL LOW: idle state yields "zero" differential operate transformercoupled loads. this idle state, positive with respect (logical HIGH).
receiver. Both receivers share common bias networks allow operation over wide input common mode range. Input Signal Conditioning Transient noise pulses input data stream rejected Noise Rejection Filter. Pulse width rejection proportional transmit data rate. inputs more negative than minus also suppressed. Carrier Detection circuitry detects presence incoming data packet discerning rejecting noise from expected Manchester data, controls stop start phase-lock loop during clock acquisition. Clock acquisition requires valid Manchester pattern 1010b lock onto incoming message. When input amplitude pulse width conditions DI±, clock acquisition cycle initiated. Clock Acquisition When there activity (receiver idle), receive oscillator phase-locked internal transmit clock. first negative clock transition (bit cell center first valid Manchester "0") after IRXCRS asserted interrupts receive oscillator. oscillator then restarted second Manchester (bit time phase-locked result, MENDEC acquires clock from incoming Manchester pattern times with "1010" Manchester pattern. ISRDCLK IRXDAT enabled time after clock acquisition cell IRXDAT HIGH state when receiver idle ISRDCLK). IRXDAT however, undefined when clock acquired remain HIGH change state whenever ISRDCLK enabled. time through cell controller portion PCnet-ISA controller sees first ISRDCLK transition. This also strobes incoming fifth MENDEC Manchester "1". IRXDAT make transition after ISRDCLK rising edge cell state still undefined. Manchester clocked IRXDAT output time cell
IRXDAT* ISRDCLK
TSEL HIGH:
Receive Path principal functions receiver signal PCnet-ISA controller that there information receive pair, separate incoming Manchester encoded data stream into clock data. receiver section (see Receiver Block Diagram) consists parallel paths. receive data path zero threshold, wide bandwidth line receiver. carrier path offset threshold bandpass detecting line
DI±/RXD±
Data Receiver
Manchester Decoder
Noise Reject Filter
Carrier Detect Circuit
IRXCRS*
*Internal signal
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Receiver Block Diagram
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Tracking
PRELIMINARY connects MAU. differential interface provided PCnet-ISA controller fully compliant with Section 8802-3 (ANSI/IEEE 802.3). After PCnet-ISA controller initiates transmission, will expect data "looped-back" pair (when port selected). This will internally generate "carrier sense", indicating that integrity data path from intact, that operating correctly. This "carrier sense" signal must asserted within sometime before transmission. "carrier sense" does become active response data transmission, becomes inactive before transmission, loss carrier (LCAR) error will Transmit Descriptor Ring (TMD3, after packet been transmitted. Differential Input Terminations differential input Manchester data (DI±) externally terminated 40.2 resistors optional common-mode bypass capacitor, shown Differential Input Termination diagram below. differential input impedance, ZIDF, common-mode input impedance, ZICM, specified that Ethernet specification cable termination impedance using standard resistor terminators. devices used, nearest usable equivalent value. differential inputs terminated exactly same pair.
Isolation Transformer PCnet-ISA
After clock acquisition, phase-locked clock compared incoming transition cell center (BCC) resulting phase error applied correction circuit. This circuit ensures that phase-locked clock remains locked received signal. Individual cell phase corrections Voltage Controlled Oscillator (VCO) limited phase difference between phase-locked clock. Hence, input data jitter reduced ISRDCLK Carrier Tracking Message carrier detection circuit monitors inputs after IRXCRS asserted message. IRXCRS de-asserts times after last positive transition incoming message. This initiates reception cycle. time delay from last rising edge message IRXCRS deassert allows last strobed ISRDCLK transferred controller section, prevents extra bit(s) message. Data Decoding data receiver comparator with clocked output minimize noise sensitivity DI±/RXD± inputs. Input error less than minimize sensitivity input rise fall time. ISRDCLK strobes data receiver output time determine value Manchester bit, clocks data IRXDAT following ISRDCLK. data receiver also generates signal used phase detector comparison internal MENDEC voltage controlled oscillator (VCO). Jitter Tolerance Definition MENDEC utilizes clock capture circuit align internal data strobe with incoming stream. clock acquisition circuitry requires four valid bits with values 1010b. Clock phase-locked negative transition cell center second pattern. Since data strobed time, Manchester transitions which shift from their nominal placement through time will result improperly decoded data. With this criteria error, definition "Jitter Handling" peak deviation approaching crossing cell position from nominal input transition, which MENDEC section will properly decode data.
40.2
40.2
0.01
16907B-9
Differential Input Termination Collision Detection detects collision condition network generates differential signal inputs. This collision signal passes through input stage which detects signal levels pulse duration. When signal detected MENDEC sets ICLSN line HIGH. condition continues approximately times after last LOW-to-HIGH transition CI±.
Attachment Unit Interface (AUI)
(Physical Layer Signaling) (Physical Medium Attachment) interface which
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Twisted Pair Transceiver (T-MAU)
T-MAU implements Medium Attachment Unit (MAU) functions Twisted Pair Medium, specified supplement IEEE 802.3 standard (Type 10BASE-T). T-MAU provides twisted pair driver receiver circuits, including on-board transmit digital predistortion receiver squelch, number additional features including Link Status indication, Automatic Twisted Pair Receive Polarity Detection/ Correction indication, Receive Carrier Sense, Transmit Active Collision Present indication. Twisted Pair Transmit Function differential driver circuitry TXD± TXP± pins provides necessary electrical driving capability pre-distortion control transmitting signals over maximum length Twisted Pair cable, specified 10BASE-T supplement IEEE 802.3 Standard. transmit function data output meets propagation delays jitter specified standard. Twisted Pair Receive Function receiver complies with receiver specifications IEEE 802.3 10BASE-T Standard, including noise immunity received signal rejection criteria (`Smart Squelch'). Signals meeting this criteria appearing RXD± differential input pair routed MENDEC. receiver function meets propagation delays jitter requirements specified standard. receiver squelch level drops half threshold value after unsquelch allow reception minimum amplitude signals offset carrier fade event worst case signal attenuation conditions. Note that 10BASE-T Standard defines receive input amplitude external Media Dependent Interface (MDI). Filter transformer loss specified. T-MAU receiver squelch levels designed account insertion loss type receive filters transformers usually used. Normal 10BASE-T compatible receive thresholds invoked when (CSR15, LOW. When set, Receive Threshold option invoked, sensitivity T-MAU receiver increased. Increasing T-MAU sensitivity allows lines longer than target distance standard 10BASE-T (assuming typical cable). Increased receiver sensitivity compensates increased signal attenuation caused additional cable distance. However, making receiver more sensitive means that also more susceptible extraneous noise, primarily caused coupling from co-resident services (crosstalk). this reason, users wish invoke Receive Threshold option 4-pair cable only. Multi-pair cables within same outer sheath have lower crosstalk attenuation, allow noise emitted from adjacent pairs couple into receive pair, sufficient amplitude falsely unsquelch T-MAU.
Link Test Function link test function implemented specified 10BASE-T standard. During periods transmit pair inactivity, 'Link beat pulses' will periodically sent over twisted pair medium constantly monitor medium integrity. When link test function enabled (DLNKTST CSR15 cleared), absence link beat pulses receive data RXD± pair will cause TMAU into Link Fail state. Link Fail state, data transmission, data reception, data loopback collision detection functions disabled remain disabled until valid data greater than consecutive link pulses appear RXD± pair. During Link Fail, Link Status (LNKST indicated LED0) signal inactive. When link identified functional, LNKST signal asserted, LED0 output will activated. order inter-operate with systems which implement Link Test, this function disabled setting DLNKTST bit. With Link Test disabled, Data Driver, Receiver Loopback functions well Collision Detection remain enabled irrespective presence absence data link pulses RXD± pair. Link Test pulses continue sent regardless state DLNKTST bit. Polarity Detection Reversal T-MAU receive function includes ability invert polarity signals appearing RXD± pair polarity received signal reversed (such case wiring error). This feature allows data packets received from reverse wired RXD± input pair corrected T-MAU prior transfer MENDEC. polarity detection function activated following reset Link Fail, will reverse receive polarity based both polarity previous link beat pulses polarity subsequent packets with valid Transmit Delimiter (ETD). When Link Fail state, T-MAU will recognize link beat pulses either positive negative polarity. Exit from Link Fail state occurs reception consecutive link beat pulses identical polarity. entry Link Pass state, polarity last link beat pulses used determine initial receive polarity configuration receiver reconfigured subsequently recognize only link beat pulses previously recognized polarity. Positive link beat pulses defined transmitted signal with positive amplitude greater than (LRT HIGH) with pulse width ns-200 This positive excursion followed negative excursion. This definition consistent with expected received signal correctly wired receiver, when link beat pulse, which fits template Figure 14-12 10BASE-T Standard, generated transmitter passed through twisted pair cable.
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PRELIMINARY Collision Detect Function Activity both twisted pair signals RXD± TXD± constitutes collision, thereby causing signal asserted. (COL used control circuits.) will remain asserted until colliding signals changes from active idle. During collision condition, data presented pair will sourced from RXD± input. stays active times collision. Signal Quality Error (SQE) Test (Heartbeat) Function function disabled when 10BASE-T port selected Link Fail state. Jabber Function Jabber function inhibits twisted pair transmit function T-MAU theTXD± circuit active excessive period (20-150 ms). This prevents node from disrupting network `stuck-on' faulty transmitter. this maximum transmit time exceeded, T-MAU transmitter circuitry disabled, (CSR4, signal asserted. Once transmit data stream T-MAU removed, "unjab" time 250-750 will elapse before T-MAU deasserts re-enables transmit circuitry. Power Down T-MAU circuitry made into power mode. This feature useful battery powered duty cycle systems. T-MAU will into power down mode when RESET active, coma mode active, T-MAU selected. Refer Power Down Mode section description various power down modes. three conditions listed above resets internal logic T-MAU places device into power down mode. this mode, Twisted Pair driver pins (TXD±,TXP±) asserted LOW, internal TMAU status signals (LNKST, RCVPOL, XMT, COLLISION) inactive. Once SLEEP deasserted, T-MAU will forced into Link Fail state. T-MAU will move Link Pass state only after link beat pulses and/or single received message detected RXD± pair. snooze mode, T-MAU receive circuitry will remain enabled even while SLEEP driven LOW. T-MAU circuitry will always into power down mode RESET asserted, coma mode enabled, T-MAU selected.
Negative link beat pulses defined transmitted signals with negative amplitude greater than with pulse width ns-200 This negative excursion followed positive excursion. This definition consistent with expected received signal reverse wired receiver, when link beat pulse which fits template Figure 14-12 10BASE-T Standard generated transmitter passed through twisted pair cable. polarity detection/correction algorithm will remain "armed" until consecutive packets with valid identical polarity detected. When "armed," receiver capable changing initial previous polarity configuration according detected polarity. receipt first packet with valid following reset Link Fail, T-MAU will inferred polarity information configure RXD± input, regardless previous state. receipt second packet with valid with correct polarity, detection/correction algorithm will "lock-in" received polarity. second subsequent) packet detected confirming previous polarity decision, most recently detected polarity will used default. Note that packets with invalid have effect updating previous polarity decision. Once consecutive packets with valid have been received, T-MAU will lock correction algorithm until either Link Fail condition occurs RESET asserted. During polarity reversal, internal signal will active. During normal polarity conditions, this internal signal inactive. state this signal read software and/or displayed when enabled control bits Configuration Registers (ISACSR5, Twisted Pair Interface Status Three signals (XMT, COL) indicate whether T-MAU transmitting, receiving, collision state. These signals internal signals behavior outputs depends output circuitry programmed. T-MAU will power Link Fail state normal algorithm will apply allow enter Link Pass state. Link Pass state, transmit receive activity will indicated assertion signal going active. T-MAU selected using PORTSEL bits CSR15 MAUSEL pin, then when moving from T-MAU selection T-MAU will forced into Link Fail state. Link Fail state, XMT, inactive.
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EADI (External Address Detection Interface)
This interface provided allow external address filtering. selected setting EADISEL ISACSR2. This feature typically utilized terminal servers, bridges and/or router type products. external logic required capture serial stream from PCnet-ISA controller, compare with table stored addresses identifiers, perform desired function. EADI interface operates directly from decoded data clock recovered Manchester decoder input GPSI, allowing external address detection performed parallel with frame reception address comparison Station Address Detection (SAD) block. SRDCLK provided allow clocking receive stream into external address detection logic. SRDCLK runs only during frame reception activity. Once received frame commences data clock available, EADI logic will monitor alternating ("1,0") preamble pattern until ones Start Frame Delimiter ("1,0,1,0,1,0,1,1") detected, which point SF/BD output will driven HIGH. After SF/BD asserted serial data from should de-serialized sent content addressable memory (CAM) other address detection device. allow simple serial parallel conversion, SF/BD provided strobe and/or marker indicate delineation bytes, subsequent SFD. This provides mechanism allow only capture and/or decoding physical logical (group) address, also facilitates capture header information determine protocol inter-networking information. driven external address comparison logic reject frame.
internal address match detected comparison with either Physical Logical Address field, frame will accepted regardless condition EAR. Incoming frames which pass internal address comparison will continue received. This allows approximately byte times after last destination address available generate signal, assuming device configured accept runt packets. will ignored after byte times after SFD, frame will accepted been asserted before this time. Runt Packet Accept configured, signal must generated prior receive message completion, which could short byte times (assuming bytes source address, bytes length, data, bytes FCS) after last destination address available. must have pulse width least Note that setting PROM (CSR15, will cause receive frames received, regardless state input. DRCVPA (CSR15.13) logical address (LADRF) zero, only frames which rejected will received. EADI interface will operate long STRT CSR0 set, even receiver and/or transmitter disabled software (DTX bits CSR15 set). This situation useful power down mode that PCnet-ISA controller will perform operations; this saves power utilizing driver circuits. However, external circuitry could still respond specific frames network facilitate remote node control. table below summarizes operation EADI features.
Table: Internal/External Address Recognition Capabilities
PROM Required Timing timing requirements timing requirements within bits after Received Messages Received Frames Received Frames Physical/Logical Matches
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PRELIMINARY invoke GPSI signals, follow procedure below: After reset read Reset Address, write PORTSEL bits CSR15. ENTST CSR4 GPSIEN CSR124 (see note below) (The pins LA17-LA23 will change function after completion above three steps.) Clear ENTST CSR4 Clear both media select bits ISACSR2 Define PORTSEL bits MODE register (CSR15) define GPSI port. MODE register image initialization block.
General Purpose Serial Interface (GPSI)
PCnet-ISA controller contains General Purpose Serial Interface (GPSI) designed testing digital portions chip. MENDEC, AUI, twisted pair interface by-passed once device special "test mode" accessing GPSI functions. Although this access intended only testing device, some users find non-encoded data functions useful some special applications. Note, however, that GPSI functions accessed only when PCnet-ISA devices operate master. PCnet-ISA GPSI signals consistent with LANCE digital serial interface. Since GPSI functions accessed only through special test mode, expect some loss functionality device when GPSI invoked. 10BASE-T analog interfaces disabled along with internal MENDEC logic. (unlatched address) pins removed become GPSI signals, therefore, only bits address space available. table below shows GPSI configuration:
Note: pins will tristated before writing CORETST bit. After writing GPSIEN, LA[17-21] will inputs, LA[22-23] will outputs.
Table: GPSI Configurations
GPSI Function Receive Data Receive Clock Receive Carrier Sense Collision Transmit Clock Transmit Enable Transmit Data GPSI Type LANCE/ C-LANCE GPSI RCLK RENA CLSN TCLK TENA PCnet-ISA GPSI Function RXDAT SRDCLK RXCRS CLSN STDCLK TXEN TXDAT PCnet-ISA Number PCnet-ISA Normal Function LA17 LA18 LA19 LA20 LA21 LA22 LA23
Note: GPSI function only available Master mode operation.
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IEEE 1149.1 Test Access Port Interface
IEEE 1149.1 compatible boundary scan Test Access Port provided board-level continuity test diagnostics. digital input, output, input/output pins tested. Analog pins, including differential driver (DO±) receivers (DI±, CI±), crystal input (XTAL1/XTAL2) pins, tested. T-MAU drivers TXD±, TXP±, receiver RXD± also tested. following brief summary IEEE 1149.1 compatible test functions implemented PCnet-ISA controller. Boundary Scan Circuit boundary scan test circuit requires four extra pins (TCK, TMS, defined Test Access Port (TAP). includes finite state machine (FSM), instruction register, data register array, power-on reset circuit. Internal pull-up resistors provided TDI, TCK, pins. must left unconnected. boundary scan circuit remains active during sleep. engine 16-state FSM, driven Test Clock (TCK) Test Mode Select (TMS) pins. This reset state power-up RESET. independent power-on reset circuit provided ensure TEST_LOGIC_RESET state power-up. Supported Instructions addition minimum IEEE 1149.1 requirements (BYPASS, EXTEST SAMPLE instructions), three additional instructions (IDCODE, TRIBYP SETBYP) provided further ease board-level testing.
unused instruction codes reserved. table below summary supported instructions. Instruction Register Decoding Logic After hardware software RESET, IDCODE instruction always invoked. decoding logic gives signals control data flow DATA registers according current instruction. Boundary Scan Register (BSR) Each cell stages. flip-flop latch used SERIAL SHIFT STAGE PARALLEL OUTPUT STAGE, respectively. There four possible operational modes cell:
Capture Shift Update System Function
Other Data Registers BYPASS BIT) bits)
Bits 31-28: Bits 27-12: Bits 11-1: Version Part number (0003H) Manufacturer manufacturer code 00000000001 according JEDEC Publication 106-A. Always logic
Table: IEEE 1149.1 Supported Instruction Summary
Instruction Name EXTEST IDCODE SAMPLE TRIBYP SETBYP BYPASS Description External Test Code Inspection Sample Boundary Force Tristate Control Boundary Bypass Scan Selected Data Bypass Bypass Bypass Mode Test Normal Normal Normal Test Normal Instruction Code 0000 0001 0010 0011 0100 1111
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PRELIMINARY separate 8-bit hardware cycles. motherboard accesses byte before high byte PCnet-ISA controller circuitry specifically support this type access. reset register causes reset when read. value will accepted cycle bits wide. Writes ignored. PCnet-ISA controller register accesses should coded 16-bit operations.
Power Savings Modes
PCnet-ISA controller supports hardware power-savings modes. Both entered asserting SLEEP LOW. coma mode, PCnet-ISA controller will into deep sleep with support automatically wake itself Coma mode enabled when AWAKE ISACSR2 reset. This mode default power down mode. snooze mode, enabled setting AWAKE ISACSR2 driving SLEEP LOW, T-MAU receive circuitry will remain enabled even while SLEEP driven LOW. LED0 output will also continue function, indicating good 10BASE-T link there link beat pulses valid frames present. This LED0 used drive and/or external hardware that directly controls SLEEP PCnet-ISA controller. This configuration effectively wakes system when there activity 10BASE-T link.
*Note that cleared Reset.
Address PROM Access address PROM external memory device that contains node's unique physical Ethernet address other data stored board manufacturer. software accesses 16-bit. Boot PROM Access boot PROM external memory resource located address selected IOAM0 IOAM1 pins master mode, BPAM input shared memory mode. software accessed 16-bit resource latter recommended best performance. Static Access static only present shared memory mode. located address selected SMAM input. accessed 16-bit resource latter recommended best performance.
Access Operations (Software)
begin describing byte word data addressed bus, including conversion cycles where 16-bit accesses turned into 8-bit accesses because resource accessed support 16-bit operations. Then describe registers other resources accessed. This section device programmer, while next section (bus cycles) hardware designer. Resources PCnet-ISA controller both memory resources. space resources organized indicated following table:
Offset #Bytes Register IEEE Address PROM (shared IDP) Reset
Cycles (Hardware)
PCnet-ISA controller supports both 16-bit hardware cycles. following sections outline where limitations apply based upon architecture mode and/or resource that being accessed (PCnet-ISA controller registers, address PROM, boot PROM, shared memory SRAM). completeness, following sections arranged architecture (Bus Master Mode Shared Memory Mode). SRAM resources apply only Shared Memory Mode. resources (registers, PROMs, SRAM) presented PCnet-ISA controller. With exceptions, these resources configured either 8-bit 16-bit cycles. resources (registers, address PROM) width configured using IOCS16 PCnet-ISA controller. memory resources (boot PROM, SRAM) width configured external hardware. 16-bit memory accesses, hardware external PCnet-ISA controller asserts MEMCS16 when either memory resources selected. requires that memory resources within block Kbytes same width, either 16-bits. reason this that MEMCS16 signal generally decode LA17-23 address lines. 16-bit memory
PCnet-ISA controller does respond addresses outside offset range 0-17h. offsets used PCnet-ISA controller. Register Access register address port (RAP) shared register data port (RDP) ISACSR data port (IDP) save registers. access Ethernet controller's IDP, should written first, followed read write access IDP. register accesses should coded 16-bit accesses, even PCnet-ISA controller hardware configured 8-bit cycles. acceptable (and transparent) motherboard turn 16-bit software access into 1-390
Am79C960
PRELIMINARY capability desirable since 8-bit accesses take same amount time four 16-bit accesses. accesses 8-bit resources (which return MEMCS16 IOCS16) SD0-7. byte accessed, Current Master swap buffer turns During byte read swap buffer copies data from SD0-7 high byte. During byte write Current Master swap buffer copies data from high byte SD0-7. PCnet-ISA controller configured 8-bit resource even 16-bit system; this accomplished disconnecting IOCS16 from tying IOCS16 ground. recommended that PCnet-ISA controller hardware configured 8-bit only cycles maximum compatibility with PC/AT clone motherboards. When PCnet-ISA controller 8-bit system such PC/XT, SBHE IOCS16 must left unconnected (these signals exist PC/XT). This will force resources (I/O memory) support only 8-bit cycles. PCnet-ISA controller will function 8-bit system only configured Shared Memory Mode. Accesses 16-bit resources (which return MEMCS16 IOCS16) either both SD0-7 SD8-15. word access indicated A0=0 SBHE=0 data transferred data lines. even byte access indicated A0=0 SBHE=1
data transferred SD0-7. odd-byte access indicated A0=1 SBHE=0 data transferred SD8-15. illegal have A0=1 SBHE=1 cycle. PCnet-ISA controller returns only IOCS16; MEMCS16 must generated external hardware desired. MEMCS16 applies only Shared Memory Mode. following table describes possible types accesses, including Permanent Master Current Master PCnet-ISA controller Current Master. PCnet-ISA controller will work with 8-bit memory while Current Master. descriptions 8-bit memory accesses when Permanent Master Current Master. byte columns (D0-7 D8-15) indicate whether master slave driving byte. CS16 shorthand MEMCS16 IOCS16. Master Mode PCnet-ISA controller configured Master only systems that support mastering. addition, system assumed support 16-bit memory (DMA) cycles (the PCnet-ISA controler does MEMCS16 signal bus). This does preclude PCnet-ISA controller from doing 8-bit transfers. PCnet-ISA controller will function master 8-bit platforms such PC/XT.
Table: Accesses
SBHE CS16 D0-7 Slave Slave Slave Float Slave Master Float* Master Float Master D8-15 Float Float* Float Slave Slave Float Master Master Master Master Comments byte High byte with swap 16-Bit converted byte High byte 16-Bit byte High byte with swap 16-Bit converted byte High byte 16-Bit
*Motherboard SWAP logic drives
Am79C960
1-391
PRELIMINARY 8-bit accesses, even byte access followed immediately byte access. access cycle begins with Permanent Master driving LOW, driving address valid, driving active. PCnet-ISA controller detects this combination signals drives IOCHRDY LOW. IOCS16 will also driven 16-bit cycles enabled. When register data ready, IOCHRDY will released HIGH. This condition maintained until goes inactive, which time cycle ends.
Refresh Cycles Although PCnet-ISA controller neither originator receiver refresh cycles, does need avoid unintentional activity during refresh cycle master mode. refresh cycle performed follows: First, signal goes active. Then valid refresh address placed address bus. MEMR goes active, refresh performed, MEMR goes inactive. refresh address held short time then goes invalid. Finally, goes inactive. During refresh cycle, indicated being active, PCnet-ISA controller inhibits SMEMR inputs ignores DACK goes active until goes inactive. necessary ignore DACK during refresh because some motherboards generate false DACK that time. Address PROM Cycles Address PROM small bytes) 8-bit PROM connected PCnet-ISA controller Private Data Bus. PCnet-ISA controller will support only 8-bit cycles address PROM; this limitation transparent software does preclude 16-bit software accesses. access cycle begins with Permanent Master driving LOW, driving addresses valid, driving active. PCnet-ISA controller detects this combination signals arbitrates Private Data (PRDB) necessary. IOCHRDY driven during accesses address PROM.
When Private Data becomes available, PCnet-ISA controller drives APCS active, releases IOCHRDY, turns data path from PRD0-7, enables SD0-7 drivers (but SD8-15)
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