Power Requirements: Actel A54SX08 Altera CPLDs FPGAs have traditi

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Power Requirements: Actel A54SX08 Altera CPLDs
FPGAs have traditionally been perceived inferior performance CPLDs. Actel's high-performance antifuse family, however, offers both superior speed reduced power single device. well family compares against CPLD, Actel performed laboratory comparison between Actel A54SX08 FPGA Altera EPM7256A CPLD using four typical designs selected highlight worst-case conditions various scenarios.
requirements, best determine actual power performance through physical device measurements. Four designs were generated programmed into devices. shift-register design demonstrated sequential logic functionality; multiplier design used combinatorial logic; counter design used sequential combinatorial logic; clock-tree design compared clock functionalities. Each device used same design. four designs were "self-exciting" with global clock their only input. Each design also used small number outputs ensure valid circuit operation. socket module each device constructed testing purposes. terminated connection, consisting coaxial cable connected closely possible clock-input reduce noise level setup, routed input device. Hewlett-Packard E3615A Digital Power Supply driving 3.3V powered devices. LeCroy 9210 300MHz Function Generator with maximum frequency 300MHz drove clock. Fluke 8050A Digital Multimeter used measure power terms device power-supply current (Icc), which then converted into power dissipation (measured Watts).
Altera EPM7256A CPLD selected comparison Actel A54SX08 FPGA because both feature similar capacity (Table Although device architecturally FPGA, achieve same functionality 7000A CPLD. Table Device Comparison
Altera EPM7256A Number Logic Elements Dedicated Flip-Flops Actel A54SX08
Altera's 7000A CPLDs have power-saving mode that supports power reduction macrocell basis. macrocells running low-power mode incur additional delay least This comparison used both high-speed (turbo) mode low-power (nonturbo) modes. speed grades considered were fastest available time this experiment. EPM7256A fastest speed grade A54SX08 fastest speed grade Faster devices available both devices.
Semiconductor power requirements depend multitude factors, including power supply voltage, technology, operating performance, switching activity. Mathematical models useful tools estimating power, they cannot replace measured data. Most power models approximations, simplified general usability. Although these models provide adequate guide power
2000 Actel Corporation
Measured Power Dissipation Shift Register Design
Power
EPM7256A-7 (turbo)
0.01
A54SX08-2
EPM7256A-7 (nonturbo)
Frequency (MHz)
Figure Power Requirements Shift-Register Design
256-bit shift-register design highest power dissipation design measurements suite. required 100% flip-flops switch every clock pulse, providing indication absolute worst-case power dissipation each device. turbo Altera EPM7256A significantly alter power consumption shift-register design. This because every logic element switching
each clock pulse. turbo effective reducing power designs with multiple bits. Actel A54SX08 device consumed less power 50MHz than Altera EPM7256A device (Figure EPM7256A reached maximum operating frequency 110MHz this design. power requirements A54SX08 operating 300MHz approximately equal requirements EPM7256A operating 30MHz.
Measured Power Dissipation Multiplier Design
EPM7256A-7 (turbo) A54SX08-2
Power
0.01
EPM7256A-7 (nonturbo)
Frequency (MHz)
Figure Power Requirements Multiplier Design
multiplier design provided comparison between devices implementing combinatorial logic. disabling turbo Altera EPM7256A device resulted slightly lower power than with turbo enabled.
A54SX08 device consumed approximately less power than EPM7256A 50MHz high-speed mode less power than EPM7256A 50MHz low-power mode. maximum operating frequency, EPM7256A consumed much times more power than A54SX08 device.
Measured Power Dissipation Counter Design
EPM7256A-7 (turbo) A54SX08-2
Power
0.01
EPM7256A-7 (nonturbo)
Frequency (MHz)
Figure Power Requirements Counter Design
This design used multiple instances 8-bit counter provided excellent comparison power requirements devices implementing both sequential combinatorial logic. disabling turbo EPM7256A resulted drop power when compared device with turbo
enabled. This because majority bits counter design change often enough affect results. A54SX08 consumed less power than EPM7256A 50MHz high-speed mode less power low-power mode. EPM7256A high-speed mode reached maximum operating frequency 140MHz. this frequency EPM7256A consumed much times more power than A54SX08.
Measured Power Dissipation Clock Tree Design
EPM7256A-7 (turbo) A54SX08-2 EPM7256A-7 (nonturbo)
Power
0.01
Frequency (MHz)
Figure Power Requirements Clock-Tree Design
clock-tree design compared power efficiency global clock-tree each device. Although A54SX08 physically larger clock-tree, consumed considerably less power than EPM7256A, part much higher standby current EPM7256A. A54SX08 device consumed less power than EPM7256A device 50MHz high-speed mode less power low-power mode. EPM7256A high-speed mode ceased function operating frequency 120MHz, where consumed approximately times power A54SX08.
A54SX08 FPGA able achieve both higher performance lower power than EPM7256A CPLD. Based suite four designs tested, Actel A54SX08 consumed average less power than EPM7256A operating high-speed mode. same time, A54SX08 also operated frequencies well above maximum operating frequency EPM7256A. Only hardware limitations test equipment restrict maximum operating frequency 300MHz A54SX08.
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