benefits Actel's nonvolatile antifuse FPGA technology ability devices

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Power-Up Power-Down Behavior 54SX RT54SX Devices
benefits Actel's nonvolatile antifuse FPGA technology ability devices live power-up. Since configuration PROMs required download design information device, Actel FPGAs ready soon power-up sequence complete. However, there restrictions that need considered while designing with these devices. This Application Note explains requirements Actel's 54SX RT54SX devices during power-up power-down. addition, this Application Note also discusses behavior outputs during power-up, explains when device functional, provides recommended ramp rates power-up. This report measured laboratory environment. values reported typical values, therefore, guaranteed maximum minimum values.
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operation mode. flip-flops design initialized known state during power-up. Thus, user needs provide external signal reset flip-flops upon power-up.
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Table lists specific power supply requirements 54SX RT54SX FPGAs. Table Power Supply
VCCA 54SX RT54SX 3.3V 3.3V 54SX16P 3.3V 3.3V VCCI 3.3V 3.3V 3.3V 5.0V VCCR 5.0V 3.3V 5.0V 5.0V Input Tolerance 5.0V 3.3V 5.0V 5.0V Output Drive 3.3V 3.3V 3.3V 5.0V
order fully understand power-up characteristics Actel 54SX RT54SX FPGAs, user must first learn some background information about power-up circuitry understand function each power supply. three power supplies available 54SX RT54SX devices are: VCCI: This power supply I/Os device VCCR: This reference voltage used input tolerance VCCA: This power supply internal array
During power-up, pull-up transistor between each VCCI will turned Therefore, I/Os will appear drive until device active. amount time I/Os drive depends ramp rates board's power supplies time delta between VCCR VCCA. After I/Os drive LOW, they will behave according design. Table page summarizes VCCA voltage which I/Os behave according user's design 54SX RT54SX devices room temperature. Table page assumes linear ramp-up profile 3.3V. reset process that enables outputs begins when VCCA reaches nominal value about 2.0V (+/- 0.5V). Table page characterizes voltage which outputs become active against VCCA value listed power-up rate. example, user powers-up 54SX32 device 0.66V/ms, outputs become active when VCCA reaches about 2.1V. point which I/Os become enabled depends power-up rate process variations between different devices. Note, results vary from those presented here these dependencies.
During power-up, VCCA voltage used initiate sequence events that puts device into functional mode. Once VCCA reaches approximately 2.0V (See "I/O Behavior" minimum values their dependency ramp rate), sensing circuit enables internal charge pump. charge pump provides high voltage (5-8V) that used turn isolation devices throughout FPGA. These isolation devices reside input output every logic module chip used isolate logic modules from high voltages during programming. During normal operation, isolation transistors turned which allows logic array I/Os function according design. VCCA-controlled sensing circuit also places JTAG circuitry TEST-LOGIC-RESET mode, device normal
2000 Actel Corporation
Transient Current
When VCCA reaches voltage about 2.0V, VCCA power supply will experience transient current approximately 500ns. This current sudden switching internal logic modules when device initialization applied. Table VCCA Voltage where I/Os Become Active
Ramp Rate 54SX08 54SX16 54SX16P 54SX32 RT54SX16 RT54SX32 0.33V/µs 0.033V/µs 6.6V/ms
value transient current highly dependent VCCA ramp-up rate size device. Table summarizes typical values transient current different ramp rates device sizes room temperature.
3.3V/ms
0.66V/ms
0.33V/ms
0.132V/ms
0.033V/ms
Table Typical Peak Transient Current (mA)
Ramp Rate 54SX08 54SX16 54SX16P 54SX32 RT54SX16 RT54SX32 0.33V/µs 0.033V/µs 6.6V/ms 3.3V/ms 0.66V/ms 0.33V/ms 0.132V/ms 0.033V/ms
equen
order which power supplies ramped ramped down critical 54SX RT54SX devices. avoid device damage, VCCR must greater than equal VCCI times. This guideline applies both power-up power-down sequences. junction exists between VCCI VCCR power supplies circuitry JTAG pins. When VCCI greater than VCCR 0.6V, junction will forward bias cause excessive current flow. This condition cannot violated period time. excessive current through junction damage circuitry.
state machine power-up unknown state, I/Os will most likely tristated. This does cause damage device, FPGA functional after power-up. RT54SX devices, this avoided connecting TRST ground during power-up. Actel recommends this always connected ground normal operation.
Actel 54SX16, 54SX16P, RT54SX16, RT54SX32 FPGA, important that VCCA does rise above 0.0V before initiating power-up sequence. VCCA must begin power-up from 0.0V. This power-up consideration does apply 54SX08 54SX32 devices differences power-up circuitry. amount residual voltage present VCCA before power-up, sensing circuit generate appropriate reset signal, thus causing FPGA power-up unknown state. Should JTAG
stated earlier, 54SX RT54SX I/Os drive during power-up. Actel recommends that voltage only applied inputs after power-up sequence been completed power supplies. Applying voltage greater than VCCI pins 54SX RT54SX devices cause residual voltage appear VCCA. This cause symptoms described previous section, "Complete Power-Down" 54SX16, 54SX16P, RT54SX16, RT54SX32 devices. This current path that exists from pins VCCA uses same power supply VCCI). VCCA VCCI directly connected together board, this
condition does occur. External pull-up resistors from these pins VCCI acceptable; however, pull-up resistors VCCR cause this condition.
power-up requirements 54SX RT54SX devices defined this Application Note. order keep transient current during power-up minimum, VCCA ramp rate 0.66V/ms slower recommended. above power sequencing, prevention residual VCCA voltage, driving guidelines met, 54SX RT54SX devices will function correctly after power-up. Specific board level power-up solutions left designer.
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