ADSP-21535 308K Bytes On-Chip Memory: Bytes Instruction SRAM/Cach

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ADSP-21535 308K Bytes On-Chip Memory: Bytes Instruction SRAM/Cach

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Preliminary Technical DatSUMMARY High-Performance Blackfin Core 16-Bit MACs 32-Bit ALUs Four 8-Bit Video ALUs Dual 40-Bit Accumulators 40-Bit Shifter RISC-Like Register Instruction Model Ease Programming Compiler-Friendly Support Advanced Debug, Trace, PerformanceMonitoring Support Memory 4G-Byte Unified Address Range 32-Bit DAGs General Addressing Circular Buffer Support
ADSP-21535
308K Bytes On-Chip Memory: Bytes Instruction SRAM/Cache Bytes Data SRAM/Cache Bytes Scratchpad SRAM 256K Bytes Full Speed, Latency SRAM Memory Controller Memory Management Unit Providing Memory Protection Synchronous External Memory Controller with Glueless SDRAM Support Asynchronous External Memory Controller with Glueless Support SRAM, FLASH, Flexible Memory Booting Options From External Memory
JTAG TEST EMULATION
INTERRUPT CONTROLLER/ TIMER
WATCHDOG TIMER
BLACKFIN CORE 256K BYTES SRAM REAL TIME CLOCK UART PORT IrDA® UART PORT SYSTEM INTERFACE UNIT TIMER0, TIMER1, TIMER2 GPIO CONTROLLER INTERFACE SERIAL PORTS PORTS
BOOT
INTERFACE
EXTERNAL PORT FLASH SDRAM CONTROL
Figure ADSP-21535 Block Diagram
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This information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacturing unless otherwise agreed writing. Technology Way, .O.Box 9106, Norwood, 02062-9106, U.S.A. Tel:781/329-4700 World Wide Site: http://www.analog.com Fax:781/326-8703 ©Analog Devices,Inc., 2001
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PERIPHERALS 32-Bit, 33-MHz, 2.2-compliant Interface with Master Slave Support Integrated 1.1-compliant Device Interface Event Controller UARTs, with Support IrDA® Three Timer/counters with Support SPI-compatible Ports 6-pin Full-Duplex Synchronous Serial Ports Real-Time Clock Watchdog Timer General Purpose Pins Debug/JTAG Interface Chip Capable Frequency Multiplication Core with Dynamic Power Management V-Tolerant Case Temperature Range 256-Lead PBGA Package
solutions quickly without need costly external components. ADSP-21535 system peripherals include UARTs, SPIs, SPORTs, General Purpose Timers, Real-Time Clock, Watchdog Timer, buses glueless peripheral expansion.
ADSP-21535 Peripherals
GENERAL NOTE This data sheet provides preliminary information ADSP-21535 Blackfin DSP.
GENERAL DESCRIPTION
ADSP-21535 member Blackfin family products, incorporating ADI's Blackfin core architecture. Blackfin architecture combines dual-MAC state-of-the engine, advantages clean, orthogonal RISC-like microprocessor instruction set, single-instruction, multiple-data (SIMD) multimedia capabilities into single instruction architecture. integrating rich industry leading system peripherals memory, Blackfin DSPs platform choice next generation applications that require RISC like programmability, multimedia support leading edge signal processing integrated DSP.
Portable Low-Power Architecture
ADSP-21535 contains rich peripherals connected core several high bandwidth buses, providing flexibility system configuration well excellent overall system performance. Figure page base peripherals include general purpose functions such UARTs, Timers with (Pulse Width Modulator) pulse measurement capability, general purpose flag pins, Real-Time Clock, Watchdog Timer. This functions satisfies wide variety typical system support needs augmented system expansion capabilities part. addition these general purpose peripherals, ADSP-21535 contains high speed serial ports interfaces variety audio modem CODEC functions, interrupt controller flexible management interrupts from on-chip peripherals well external sources power management control functions tailor performance power characteristics processor system many application scenarios. on-chip peripherals easily augmented many system designs with little glue logic inclusion several interfaces providing expansion industry-standard buses. These include 32-bit, 33-MHz, V2.2-compliant bus, serial expansion ports device type port. These enable connection large variety peripheral devices tailor system design specific applications with minimum design complexity. peripherals supported flexible structure with individual channels integrated into peripherals appropriate their needs. There also separate memory channel dedicated data transfers between DSP's various memory spaces including external SDRAM asynchronous memory, internal Level SRAM memory spaces. Multiple on-chip 32-bit buses running provide adequate bandwidth keep processor core running along with activity on-chip external peripherals.
Blackfin Core Architecture
Blackfin DSPs provide world class power consumption performance compared other Digital Signal Processors. Blackfin DSPs designed Low-Power Low-Voltage Design Methodology feature Dynamic Power Management, ability vary both voltage frequency operation significantly lower overall power consumption. Varying voltage frequency result three-fold reduction power consumption, comparison just varying frequency operation. This translates into longer battery life portable appliances.
System Integration
ADSP-21535 highly integrated system-on-a-chip solution next generation digital communication portable Internet appliances. combining industry-standard interfaces with high performance Digital Signal Processing core, users develop cost effective
shown Figure page Blackfin core contains multiplier/accumulators (MACs), 32-bit ALUs, four video ALUs, single shifter. computational units process 8-bit, 16-bit, 32-bit data from register file. Each performs 16-bit 16-bit multiply every cycle, with accumulation 40-bit result, providing bits extended precision.
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ALUs perform standard arithmetic logical operations. With ALUs capable operating 32-bit data, flexibility computation units covers signal processing requirements varied application needs. Each 32-bit input registers regarded 16-bit halves, each accomplish
very flexible single 16-bit arithmetic operations. viewing registers pairs 16-bit operands, dual 16-bit single 32-bit operations accomplished single cycle. further taking advantage second ALU, quad 16-bit operations accomplished simply, accelerating cycle throughput.
ADDRESS ARITHMETIC UNIT
DAG0
DAG1
SEQUENCER
ALIGN
DECODE
LOOP BUFFER CONTROL UNIT
BARREL SHIFTER
DATA ARITHMETIC UNIT
Figure Blackfin Core Architecture
powerful 40-bit shifter extensive capabilities performing shifting, rotating, normalization, extraction, depositing data. data computational units found multi-ported register file sixteen 16-bit entries eight 32-bit entries. powerful program sequencer controls flow instruction execution, including instruction alignment decoding. sequencer supports conditional jumps subroutine calls, well zero-overhead looping. loop buffer stores instructions locally, eliminating instruction memory accesses tight looped code. data address generators (DAGs) provide addresses simultaneous dual operand fetches from memory. DAGs share register file containing four sets 32-bit Index, Modify, Length, Base registers. Eight additional 32-bit registers provide pointers general indexing variables stack locations. REV.
Blackfin DSPs support modified Harvard architecture combination with hierarchical memory structure. Level (L1) memories those that typically operate full processor speed with little latency. Level (L2) memories other memories on-chip off-chip, that take multiple processor cycles access. level, instruction memory holds instructions only. data memories hold data, dedicated scratchpad data memory stores stack local variable information. level, there single unified memory space, holding both instructions data. addition, instruction memory data memories configured either Static RAMs (SRAMs) caches. Memory Management Unit (MMU) provides memory protection individual tasks that operating core protect system registers from unintended access.
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architecture provides modes operation, user mode supervisor mode. User mode restricted access certain system resources, thus providing protected software environment, while supervisor mode unrestricted access system core resources. Blackfin instruction been optimized that 16-bit op-codes represent most frequently used instructions, resulting excellent compiled code density. Complex instructions encoded into 32-bit op-codes, representing fully featured multifunction instructions. Blackfin DSPs support limited multi-issue capability, where 32-bit instruction issued parallel with 16-bit instructions, allowing programmer many core resources single instruction cycle. Blackfin assembly language uses algebraic syntax ease coding readability. architecture been optimized conjunction with C-compiler, resulting fast efficient software implementations.
Memory Architecture
0xFFFF FFFF CORE REGISTERS BYTE) 0xFFE0 0000 SYSTEM REGISTERS BYTE) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCH SRAM BYTE) 0xFFB0 0000 RESERVED 0xFFA0 4000 CODE SRAM (16K BYTE) 0xFFA0 0000 RESERVED 0xFF90 4000 DATA BANK SRAM (16K BYTE) 0xFF90 0000 RESERVED 0xFF80 4000 DATA BANK SRAM (16K BYTE) 0xFF80 0000 RESERVED 0xF003 FFFF SRAM MEMORY (256K BYTE) 0xF000 0000 RESERVED 0xEF00 0000 CONFIG SPACE PORT BYTE) 0xEEFF FFFC CONFIG REGISTERS (64K BYTE) 0xEEFF FF00 RESERVED 0xEEFE FFFF SPACE (64K BYTE) RESERVED 0xE7FF FFFF MEMORY SPACE (128M BYTE) 0xE000 0000 RESERVED 0x2FFF FFFF ASYNC MEMORY BANK (64M BYTE) 0x2C00 0000 ASYNC MEMORY BANK (64M BYTE) 0x2800 0000 ASYNC MEMORY BANK (64M BYTE) 0x2400 0000 ASYNC MEMORY BANK (64M BYTE) 0x2000 0000 0x1800 0000 0x1000 0000 0x0800 0000 0x0000 0000 SDRAM MEMORY BANK MB)* SDRAM MEMORY BANK MB)* SDRAM MEMORY BANK MB)* SDRAM MEMORY BANK MB)* 0xEEFE 0000
memory system primary highest-performance memory available Blackfin core. memory provides much more capacity; however, read latency higher. Lastly, off-chip memory system, accessed through External Memory Controller (EMC), provides expansion with SDRAM, flash memory, SRAM, optionally accessing more than 768M bytes physical memory. memory controller provides high-bandwidth, multi-channel, data-movement capability. perform block transfers code data between internal L1/L2 memories external memory spaces (including memory space).
Internal (On-chip) Memory
*THE ADDRESSES SHOWN SDRAM BANKS REFLECT FULLY POPULATED SDRAM ARRAY WITH 512M BYTE MEMORY. BANKS CONTAIN LESS THAN 128M BYTE MEMORY, WOULD EXTEND ONLY LENGTH REAL MEMORY SYSTEMS ADDRESS WOULD BECOME START ADDRESS NEXT BANK. THIS WOULD CONTINUE FOUR BANKS WITH REMAINING SPACE BETWEEN MEMORY BANK BEGINNING ASYNC MEMORY BANK ADDRESS 0x2000 0000 TREATED RESERVED ADDRESS SPACE.
ADSP-21535 four blocks on-chip memory providing high-bandwidth access core. first instruction memory consisting bytes 4-way set-associative cache memory. addition memory configured SRAM. This memory accessed full processor speed.
Figure ADSP-21535 Internal/External Memory
second on-chip memory block data memory, consisting blocks bytes each. Each data memory configured set-associative cache SRAM, accessed full speed core.
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EXTERNAL MEMORY
ADSP-21535 views memory single unified 4G-byte address space, using 32-bit addresses. resources including internal memory, external memory, address spaces, control registers occupy separate sections this common address space. memory portions this address space arranged hierarchical structure provide good cost/performance balance some very fast, low-latency memory cache SRAM very close processor, larger, lower-cost performance-memory systems farther away from processor. Figure
INTERNAL MEMORY
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third memory block 4K-byte scratchpad which runs same speed memories, only accessible data SRAM cannot configured cache memory. fourth on-chip memory system SRAM memory array which provides KBytes high speed SRAM full bandwidth core, slightly longer latency than memory blocks. memory unified instruction data memory hold mixture code data required system design. Blackfin core dedicated low-latency 64-bit wide datapath port into SRAM memory. example, core frequency MHz, peak data transfer rate across this interface excess 2.4G bytes second.
External (Off-Chip) Memory
memory region 4G-byte space that appears used memory devices bus. ADSP-21535 uses 128M-byte window memory space portion memory space. base address register provided position this window anywhere gigabyte memory space while position with respect processor addresses remains fixed. region also 4G-byte space. However, most systems devices only 64K-byte subset this space mapped addresses. ADSP-21535 implements 64K-byte window into this space along with base address register which used position anywhere address space, while window remains same address processor's address space. configuration space limited address space, which used system enumeration initialization which very low-performance communication mode between processor devices. ADSP-21535 provides one-value window access single data value address configuration space. This window fixed receives address value, value operation write. Otherwise device returns value into same address read operation.
Memory Space
External memory accessed External Memory Controller. This interface provides glueless connection four banks synchronous DRAM (SDRAM) well four banks asynchronous memory devices including flash, EPROM, ROM, SRAM, memory mapped devices. PC133-compliant SDRAM controller programmed interface four banks SDRAM, with each bank containing between bytes 128M bytes providing access 512M bytes SDRAM. Each bank independently programmable contiguous with adjacent banks regardless sizes different banks their placement. This allows flexible configuration upgradability system memory while allowing core view single, contiguous, physical address space. asynchronous memory controller also programmed control four banks devices with very flexible timing parameters wide variety devices. Each bank occupies 64M-byte segment regardless size devices used that these banks will only contiguous fully populated with bytes memory.
defines three separate address spaces, which accessed through windows ADSP-21535 memory space. These memory, I/O, configuration space. addition, interface either used bridge from processor core controlling system, host port where another system host ADSP-21535 functioning intelligent device bus. When ADSP-21535 acts system controller, views address spaces through mapped windows initialize devices system maintain topology environment. REV.
Blackfin DSPs define separate space. resources mapped through flat 32-bit address space. On-chip devices have their control registers mapped into memory-mapped registers (MMRs) addresses near 4G-byte address space. These separated into smaller blocks, which contains control MMRs core functions, other which contains registers needed setup control on-chip peripherals outside core. core MMRs accessible only core only supervisor mode appear reserved space on-chip peripherals, well external devices accessing resources through bus. system MMRs accessible core supervisor mode mapped either visible reserved other devices, depending system protection model desired.
Boot Memory Space
internal boot contains small boot kernel, which configures appropriate peripheral booting. ADSP-21535 configured boot from boot memory space, starts executing from on-chip boot ROM. more information, "Booting Modes" page
Event Handling
event controller ADSP-21535 handles asynchronous synchronous events processor. ADSP-21535 provides event handling that supports both
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Entry
nesting prioritization. Nesting allows multiple event service routines active simultaneously. Prioritization ensures that servicing higher-priority event takes precedence over servicing lower-priority event. controller provides support five different types events: Emulation emulation event causes processor enter emulation mode, allowing command control processor JTAG interface. Reset This event resets processor. Non-Maskable Interrupt (NMI) event generated software watchdog timer input signal processor. event frequently used power-down indicator allow orderly shut down system. Exceptions Exceptions events that occur synchronously program flow, i.e., exception will taken before instruction allowed complete. Conditions such data alignment violations, undefined instructions, etc. cause exceptions. Interrupts Interrupts events that occur asynchronously program flow. They caused timers, peripherals, input pins, etc.
Table Core Interrupt Controller (CIC) Priority Highest) Event Class
Emulation/Test Control Reset Non-Maskable Interrupt Exceptions Global Interrupt Enable Hardware Error Core Timer General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt
EMUN IRST EVSW IVHW IVTMR IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG13 IVG14 IVG15
Each event associated register hold return address associated return-from-event instruction. When event triggered, state processor saved kernel stack. ADSP-21535 event controller consists stages, Core Interrupt Controller (CIC) System Interrupt Controller (SIC). Core Interrupt Controller works with System Interrupt Controller prioritize control system events. Conceptually, interrupts from peripherals enter into SIC, then routed directly into general-purpose interrupts CIC.
Core Interrupt Controller (CIC)
Table System Interrupt Controller (SIC) Peripheral Interrupt Event Peripheral Interrupt Default Mapping
supports nine general-purpose interrupts (IVG7:15), addition dedicated interrupt exception events. these general-purpose interrupts, lowest-priority interrupts (IVG14:15) recommended reserved software interrupt handlers, leaving seven prioritized interrupt inputs support peripherals ADSP-21535. Table describes inputs CIC, identifies their names Event Vector Table (EVT), lists their priorities.
System Interrupt Controller (SIC)
Real-Time Clock Interrupt Reserved Interrupt Interrupt SPORT Interrupt SPORT Interrupt SPORT Interrupt
IVG7 IVG7 IVG7 IVG8 IVG8 IVG8
System Interrupt Controller provides mapping routing events from many peripheral interrupt sources, prioritized general-purpose interrupt inputs CIC. Although ADSP-21535 provides default mapping, user alter mappings priorities interrupt events writing appropriate values into Interrupt Assignment Registers (IAR). Table describes inputs into ECIC default mappings into
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Table System Interrupt Controller (SIC) (Continued) Peripheral Interrupt Default Mapping
SPORT Interrupt Interrupt Interrupt UART Interrupt UART Interrupt UART Interrupt UART Interrupt Timer Interrupt Timer Interrupt Timer Interrupt GPIO Interrupt GPIO Interrupt Memory Interrupt Software Watchdog Timer Interrupt Reserved Software Interrupt Software Interrupt
Event Control
21:26
IVG8 IVG9 IVG9 IVG10 IVG10 IVG10 IVG10 IVG11 IVG11 IVG11 IVG12 IVG12 IVG13 IVG13 IVG14 IVG15
servicing event even though event latched ILAT register. This register read from written while supervisor mode. (Note that general-purpose interrupts globally enabled disabled with instructions, respectively.) Interrupt Pending Register (IPEND) IPEND register keeps track nested events. IPEND register indicates event currently active nested some level. This register updated automatically controller read while supervisor mode.
allows further control event processing providing three 32-bit interrupt control status registers. Each register contains corresponding each peripheral interrupt events shown Table page Interrupt Mask Register This register controls masking unmasking each peripheral interrupt event. When register, that peripheral event unmasked will processed system when asserted. cleared register masks peripheral event thereby preventing processor from servicing event. Interrupt Status Register multiple peripherals mapped single event, this register allows software determine which peripheral event source triggered interrupt. indicates peripheral asserting interrupt, cleared indicates peripheral asserting event. Interrupt Wakeup Enable Register enabling corresponding this register, each peripheral configured wake processor, should processor powered down mode when event generated. (For more information, "Low-Power Operation" page 12.)
ADSP-21535 provides user with very flexible mechanism control processing events. CIC, three registers used coordinate control events. Each register 16-bits wide, while each represents particular event class: Interrupt Latch Register (ILAT) ILAT register indicates when events have been latched. appropriate when processor latched event cleared when event been accepted into system. This register updated automatically controller read while supervisor mode. Interrupt Mask Register (IMASK) IMASK register controls masking unmasking individual events. When IMASK register, that event unmasked will processed system when asserted. cleared IMASK register masks event thereby preventing processor from
Because multiple interrupt sources single general-purpose interrupt, multiple pulse assertions occur simultaneously, before during interrupt processing interrupt event already detected this interrupt input. IPEND register contents monitored interrupt acknowledgement. appropriate ILAT register when interrupt rising edge detected (detection requires processor clock cycles). cleared when respective IPEND register set. IPEND indicates that event entered into processor pipeline. this point will recognize queue next rising edge event corresponding event input. minimum latency from rising edge transition general-purpose interrupt IPEND output asserted three processor clock cycles; however, latency much higher, depending activity within mode processor.
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Controller
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ADSP-21535 controller that supports automated data transfers with minimal overhead core. Cycle stealing transfers occur between ADSP-21535's internal memories DMA-capable peripherals. Additionally, transfers accomplished between DMA-capable peripherals external devices connected external memory interfaces, including SDRAM controller, asynchronous memory controller interface. DMA-capable peripherals include SPORTs, ports, UARTs, port. Each individual DMA-capable peripheral dedicated channel. from accomplished memory channel. describe each sequence, controller uses parameters, called transfer control block (TCB). When successive sequences needed, these TCBs linked chained together, completion sequence auto-initiates starts next sequence. TCBs include full 32-bit addresses base pointers source destination enabling access entire ADSP-21535 address space. addition dedicated peripheral channels, there separate memory channel provided transfers between various memories ADSP21535 system. This enables transfers blocks data between memories including on-chip Level memory, external SDRAM, ROM, SRAM flash memory, address spaces with little processor intervention.
External Memory Controller
programmable timing parameters available configure SDRAM banks support slower memory devices. memory banks configured either 32-bits wide maximum performance bandwidth 16-bits wide minimum device count lower system cost. four banks share common SDRAM control signals have their bank select lines providing completely glueless interface most system configurations.
Asynchronous Controller
asynchronous memory controller provides configurable interface four separate banks memory devices. Each bank independently programmed with different timing parameters, enabling connection wide variety memory devices including SRAM, ROM, flash EPROM, well devices that interface with standard memory control lines. Each bank occupies 64M-byte window processor's address space but, fully populated, these made contiguous memory controller logic. banks also configured 16-bit wide 32-bit wide buses ease interfacing range memories devices tailored either high performance cost power.
Interface
ADSP-21535 provides glueless logical electrical, 33-Mhz, 32-bit (Peripheral Component Interconnect), Revision 2.2-compliant interface. interface provides bridge function between processor core on-chip peripherals external bus. interface ADSP-21535 supports functions: Host Bridge function, which ADSP-21535 resources (the processor core, internal external memory, memory controller) provide necessary hardware components emulate host interface, from perspective target device. Target function, which ADSP-21535 based intelligent peripheral designed easily interface Revision 2.2-compliant bus.
external memory controller ADSP-21535 provides high performance, glueless interface wide variety industry-standard memory devices. controller made sections: first SDRAM controller connection industry-standard synchronous DRAM devices DIMMs, while second asynchronous memory controller intended interface variety memory devices.
PC133 SDRAM Controller
SDRAM controller provides interface four separate banks industry-standard SDRAM devices DIMMs, speeds fSCLK. Fully compliant with PC133 SDRAM standard, each bank configured contain between bytes 128M bytes memory. controller maintains banks contiguous address space that processor sees this single address space, even different size devices used different banks. This enables system designs that delivered with initial configuration that upgraded future time with either similar different memories.
Host Function
host, ADSP-21535 provides necessary host (platform) functions required support control variety off-the-shelf devices (e.g., Ethernet controllers, bridges, etc.) system which ADSP-21535 processor host. Note that Blackfin architecture defines only memory space config address spaces). three memory spaces space (memory, configuration space) mapped into flat 32-bit memory space ADSP-21535. Since memory space large ADSP-21535 memory address space, segmented, windowed, approach employed, with separate windows REV.
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ADSP-21535
ADSP-21535 address space used accessing three address spaces. Base address registers provided that these windows positioned view range address spaces while they remain fixed position ADSP-21535 processor's address range. devices viewing ADSP-21535's resources, several mapping registers provided enable resources viewed address space. ADSP-21535's external memory space, internal some MMRs selectively enabled memory spaces that devices targets memory transactions.
Target Function
When enabled, alarm function generates interrupt when output timer matches programmed value alarm control register. There alarms: first alarm time day. second alarm time that day. stopwatch function counts down from programmed value, with minute resolution. When stopwatch enabled counter underflows, interrupt generated. Like other peripherals, wake ADSP-21535 processor from low-power state upon generation interrupt.
Watchdog Timer
target device, host processor configure ADSP-21535 subsystem during enumeration system. Once configured, ADSP-21535 subsystem acts intelligent device. When configured target device, controller uses memory controller perform transfers required host.
Port
ADSP-21535 provides 1.1- compliant device type interface support direct connection host system. core interface provides flexible programmable environment with eight endpoints. Each endpoint support data types including Control, Bulk, Interrupt, Isochronous. Each endpoint provides memory-mapped buffer transferring data application. ADSP-21535 port dedicated controller interrupt input minimize processor polling overhead enable asynchronous requests attention only when transfer management required.
Real-Time Clock
ADSP-21535 includes 32-bit timer, which used implement software watchdog function. software watchdog improve system availability forcing processor known state, generation hardware reset, non-maskable interrupt (NMI), general purpose interrupt, timer expires before being reset software. programmer initializes count value timer, enables appropriate interrupt, then enables timer. Thereafter, software must reload counter before counts zero from programmed value. This protects system from remaining unknown state where software, which would normally reset timer, stopped running external noise condition software error. configured generate hardware reset, timer programmed reset only ADSP-21535 CPU, both ADSP-21535 peripherals. After reset, software determine watchdog source hardware reset interrogating status timer control register, which only upon watchdog generated reset. timer clocked system clock (SCLK), maximum frequency fSCLK.
Timers
ADSP-21535 Real-Time Clock (RTC) provides robust digital watch features, including current time, stop watch, alarm. clocked 32.768 crystal external ADSP-21535. peripheral dedicated power supply pins, that remain powered clocked, even when rest processor low-power state. provides several programmable interrupt options, including interrupt second, minute, clock ticks, interrupt programmable stopwatch countdown, interrupt programmed alarm time. 32.768 input clock frequency divided down signal prescaler. counter function timer consists four counters: 6-bit second counter, 6-bit minute counter, 5-bit hours counter, 8-bit counter.
There three general-purpose programmable timer units ADSP-21535. Each timer external that configured either Pulse Width Modulator (PWM) timer output, input clock timer, measuring pulse widths external events. Each three timer units independently programmed PWM, internally externally clocked timer, pulse width counter. timer units used conjunction with UARTs measure width pulses data stream provide auto-BAUD detect function serial channel. timers generate interrupts processor core providing periodic events synchronization, either processor clock count external signals.
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addition three general-purpose programmable timers, fourth timer also provided. This extra timer clocked internal processor clock typically used system tick clock generation operating system periodic interrupts.
Serial Ports (SPORTs)
Serial Peripheral Interface (SPI) Ports
ADSP-21535 SPI-compatible ports that enable processor communicate with multiple SPI-compatible devices. interface uses three pins transferring data: data pins (Master Output-Slave Input, MOSIx, Master Input-Slave Output, MISOx) clock (Serial Clock, SCKx). chip select input pins (SPISSx) other devices select DSP, fourteen chip select output pins (SPIxSEL7-1) select other devices. select pins reconfigured Programmable Flag pins. Using these pins, ports provide full duplex, synchronous serial interface, which supports both master slave modes multimaster environments. Each port's baud rate clock phase/polarities programmable (see Figure each integrated controller, configurable support both transmit receive data streams. SPI's controller only service unidirectional accesses given time.
ADSP-21535 incorporates complete synchronous serial ports (SPORT0 SPORT1) serial multiprocessor communications. SPORTs support following features: Bidirectional operation each SPORT independent transmit receive pins. Buffered (8-deep) transmit receive ports each port data register transferring data words from other components shift registers shifting data data registers. Clocking each transmit receive port either external serial clock (fSCLK) generate own, frequencies ranging from (fSCLK/131070) (fSCLK/2) Word length each SPORT supports serial data words from bits length transferred Endian (MSB) Little Endian (LSB) format. Framing each transmit receive port with without frame sync signals each data word. Frame sync signals generated internally externally, active high low, with either pulsewidths early late frame sync. Companding hardware each SPORT perform A-law µ-law companding according recommendation G.711. Companding selected transmit and/or receive channel SPORT without additional latencies. operations with single-cycle overhead each SPORT automatically receive transmit multiple buffers memory data, data word each cycle. Either DSP's core host processor link chain sequences transfers between SPORT memory. chained dynamically allocated updated through Transfer Control Blocks (TCBs, parameters) that chain. Interrupts each transmit receive port generates interrupt upon completing transfer data word after transferring entire data buffer buffers through DMA. Multichannel capability each SPORT supports channels compatible with H.100, H.110, MVIP-90, HMVIP standards.
fSCLK HCLK Clock Rate SPIBAUD
Figure Clock Rate Calculation
During transfers, ports simultaneously transmit receive serially shifting data their serial data lines. serial clock line synchronizes shifting sampling data serial data lines. master mode, performs following sequence initiate transfers: Enables configures port's operation (data size, transfer format). Selects target slave with SPIxSELy output (reconfigured Programmable Flag pin). Defines more TCBs DSP's memory space (optional mode only). Enables engine specifies transfer direction (optional mode only). non-DMA mode only, reads writes port receive transmit data buffer.
SCKx line generates programmed clock pulses simultaneously shifting data MOSIx shifting data MISOx. mode only, transfers continue until word count transitions from
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slave mode, performs following sequence port receive data from master transmitter: Enables configures slave port match operation parameters master (data size transfer format) transmitter. Defines generates receive DSP's memory space interrupt data transfer (optional mode only). Enables engine receive access (optional mode only). Starts receiving data appropriate SCKx edges after receiving chip select SPISSx input (reconfigured Programmable Flag pin) from master. mode only, reception continues until word count transitions from continue, queuing next command TCB. slave mode transmit operation similar, except specifies data buffer memory from which transmit data, generates relinquishes control transmit TCB, begins filling port's data buffer. controller isn't ready time transmit, transmit "zero" word.
UART Port
Each UART port's baud rate (see Figure serial data format, error code generation status, interrupts programmable: Supporting rates ranging from (fSCLK/ 1048576) (fSCLK/16) bits second. Supporting data formats from bits frame. Both transmit receive operations configured generate maskable interrupts processor.
fSCLK HCLK UART Clock Rate
Figure UART Clock Rate Calculation1
Where 65536
conjunction with general purpose timer functions, autobaud detection supported. capabilities UART0 further extended with support InfraRed Data Association (IrDA®) Serial InfraRed Physical Layer Link Specification (SIR) protocol.
Programmable Flags (PFx)
ADSP-21535 provides full duplex Universal Asynchronous Receiver/Transmitter (UART) ports (UART0 UART1) fully compatible with 16450 standard. UART ports provide simplified UART interface other peripherals hosts, supporting full duplex, supported, asynchronous transfers serial data. Each UART port includes support data bits; stop bits; none, even, parity. UART ports support modes operation: (Programmed I/O) processor sends receives data writing reading I/O-mapped UATX UARX registers, respectively. data double-buffered both transmit receive. (Direct Memory Access) controller transfers both transmit receive data. This reduces number frequency interrupts required transfer data from memory. Each UART dedicated channels, transmit recieve. These channels have lower priority than most channels because their relatively service rates.
ADSP-21535 bi-directional, general-purpose I/O, Programmable Flag (PF0:15) pins. Programmable Flag pins have special functions clock multiplier selection, SROM boot mode, port operation. more information, "Serial Peripheral Interface (SPI) Ports" page "Clock Signals" page Each programmable flag individually controlled manipulation flag control, status interrupt registers: Flag Direction Control Register Specifies direction each individual input output. Flag Control Status Registers Rather than forcing software read-modify-write process control setting individual flags, ADSP-21535 employs "write set" "write clear" mechanism that allows combination individual flags cleared single instruction, without affecting level other flags. control registers provided, register written order flag values while another register written order clear flag values. Reading flag status register allows software interrogate sense flags. Flag Interrupt Mask Registers Flag Interrupt Mask Registers allow each individual function interrupt processor. Similar Flag Control Registers that used clear individual flag values, Flag Interrupt Mask Register sets bits enable interrupt function, other Flag Interrupt Mask register clears bits disable interrupt function. pins defined inputs
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configured generate hardware interrupts, while output pins configured generate software interrupts. Flag Interrupt Sensitivity Registers Flag Interrupt Sensitivity Registers specify whether individual pins level- edge-sensitive specify-if edge-sensitive-whether just rising edge both rising falling edges signal significant. register selects type sensitivity, register selects which edges significant edge-sensitivity.
Full Operating Mode power savings
Full mode, enabled, bypassed, providing maximum operational frequency. This normal execution state which maximum performance achieved. processor core enabled peripherals full speed.
Active Operating Mode power savings
Low-Power Operation
ADSP-21535 four low-power operating modes described below that significantly reduce power consumption when processor operates reduced performance conditions. addition, extended core power management controller provides control functions, with appropriate external power regulation capability, dynamically alter processor core supply voltage, further reducing power consumption. Control clocking each ADSP-21535 peripherals also reduces power consumption. Table summary power settings each mode.
Table Power Settings Mode
Active mode, enabled, bypassed. input clock (CLKIN) used directly generate clocks processor core (CCLK) peripherals (SCLK). Significant power savings achieved with processor running one-half CLKIN frequency. this mode multiplication ratio changed setting appropriate values SSEL fields control register (PLLCTL). lock counter (PLL LOCKCNT) determines when multiplier ratio takes effect. When Active mode, system access appropriately configured memory supported.
Bypassed
Core Clock (CCLK)
System Clock (SCLK)
Full Active Relaxed Sleep Deep Sleep
Enabled Enabled Disabled Disabled Disabled
Enabled Enabled Enabled Disabled Disabled
Enabled Enabled Enabled Enabled Disabled
Relaxed Operating Mode Medium power savings
Sleep Operating Mode High power savings
Relaxed mode reduces power consumption only bypassing also disabling input clock (CLKIN) directly used generate clocks processor core (CCLK) peripherals (SCLK). Active mode, significant dynamic power savings achieved with processor running one-half CLKIN frequency and, unlike Active mode, further power savings accomplished with being disabled. this mode multiplication ratio changed setting appropriate values SSEL fields control register (PLLCTL). lock counter (PLL LOCKCNT) determines when multiplier ratio takes effect. When Relaxed mode, system access appropriately configured memory supported.
Sleep mode reduces power consumption disabling clock processor core (CCLK). system clock (SCLK) however, continues operate this mode. interrupt, typically some external event activity, will wake processor. When Sleep mode, assertion interrupt will cause processor sense value bypass (BYPASS) control register (PLLCTL). bypass disabled, processor will transition Full mode. bypass enabled, processor will transition Active mode. When Sleep mode, system access memory supported.
Deep Sleep Operating Mode Maximum power savings
Deep Sleep mode maximizes power savings disabling clocks processor core (CCLK) synchronous systems (SCLK). Asynchronous systems, such
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DEEP
RTC, still running will able access internal resources external memory. This powered down mode only exited assertion reset interrupt (RESET) asynchronous interrupt generated RTC. When Deep Sleep mode, assertion RESET causes processor sense value BYPASS pin. bypass disabled, processor will transition Full mode. bypass enabled, processor will transition Active mode. When Deep Sleep mode, assertion asynchronous interrupt causes processor transition Full mode, regardless value BYPASS pin. SLEEP output asserted this mode, thereby enabling external power regulator determine when safe vary processor core's VDD.
Mode Transitions
RELAXED
available mode transitions diagrammed Figure accomplished either interrupt events described sections below programming PLLCTL register with appropriate values then executing following instruction sequence: CLI; IDLE; SSYNC; STI; disable interrupts source NOPs into pipeline assert IDLE output SSYNC drain pipeline, IDLE asserts after system acknowledge re-enable interrupts after wakeup
RESET CONF GURAT
Figure Mode Transitions
This instruction sequence takes processor known, idle state, with interrupts disabled. Note that activity should disabled during mode transitions.
Dynamic Power Management
power consumed processor largely function clock frequency processor square operating voltage. example, reducing clock frequency results reduction power consumption, while reducing voltage reduces power consumption more than 40%. Further, these power savings additive, that clock frequency power both reduced power savings dramatic. Dynamic Power Management feature ADSP21535 allows both processor's input voltage (VDDINT) clock frequency (fCLK) dynamically controlled. explained above, savings power consumption modeled following equation: Power Consumption Factor=(fCCLKRED /fCCLKNOM) (VDDINTRED /VDDINTNOM)2 where fCCLKNOM nominal core clock frequency (300 MHz) fCCLKRED reduced core clock frequency VDDINTNOM nominal internal supply voltage (1.5 VDDINTRED reduced internal supply voltage
shown Table ADSP-21535 supports five different power domains. multiple power domains maximizes flexibility, while maintaining compliance with industry standards conventions. isolating internal logic ADSP-21535 into power domain, separate from PLL, RTC, PCI, other I/O, processor take advantage dynamic power management, without affecting PLL, RTC, other devices.
Table ADSP-21535 Power Domains Power Domain Range
internal logic, except Analog internal logic internal logic crystal other I/O, including CLKIN input buffer
VDDINT VDDPLL VDDRTC VDDPCIEXT VDDEXT
example significant power savings Dynamic Power Management are, when both frequency voltage reduced, consider example where frequency reduced from nominal value voltage reduced from nominal value this reduced frequency voltage, processor consumes about power consumed nominal frequency voltage.
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Peripheral Power Control
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ADSP-21535 provides additional power control capability allowing dynamic scheduling clock inputs each peripherals. This allows finer control power enabling disabling clocking each peripherals. Clocking each peripherals listed below enabled disabled appropriately setting peripheral's control Peripheral Clock Enable Register (IOCKREG). Peripheral Clock Enable Register allows individual control each following peripherals: EBIU controller GPIO MemDMA controller SPORT SPORT UART UART Timer Timer Timer
CLKIN MSEL0 (PF0) MSEL1 (PF1) MSEL2 (PF2) MSEL3 (PF3) MSEL4 (PF4) MSEL5 (PF5) MSEL6 (PF6) (PF7)
CLKOUT
ADSP-21535
PULL-UP/PULLDOWN RESISTORS MSEL, BYPASS PINS SELECT CORE CLOCK RATIO. HERE, SELECTION (6:1) 25MHz INPUT CLOCK PRODUCE 150MHz CORE CLOCK.
BYPASS
RESET SOURCE
RESET
Clock Signals
Figure Clock Ratio Example
ADSP-21535 clocked sine wave input, buffered, shaped clock derived from external clock oscillator. buffered, shaped clock used, this external clock connects DSP's CLKIN pin. CLKIN input cannot halted, changed, operated below specified frequency during normal operation. This clock signal should TTL-compatible signal. provides user-programmable multiplication input clock, support external internal (DSP core) clock ratios. MSEL6-0, BYPASS, pins decide multiplication factor reset. runtime, multiplication factor controlled software. combination pullup pull-down resistors Figure sets core clock ratio 6:1, which, example, produces 150-MHz core clock from 25-MHz input. other clock multiplier settings, ADSP-21535 Hardware Reference. peripheral clock supplied CLKOUT_SCLK0 pin. on-chip peripherals operate rate system clock (SCLK). system clock frequency programmable means SSEL pins. time system clock frequency controlled software writing SSEL ields control register (PLLCTL).
values programmed into SSEL fields define divide ratio between core clock (CLKIN) system clock. Table illustrates system clock ratios:
Table System Clock Ratios Signal Name SSEL [1:0] Divider Ratio CCLK/ SCLK Example Frequency Ratios (MHz) CCLK SCLK
2.5:1
maximum frequency system clock fSCLK. Note that divisor ratio must chosen limit system clock frequency maximum fSCLK. reset value SSEL [1:0] determined sampling Programmable Flag input pins (PF[9:8]) during reset. SSEL value changed dynamically writing appropriate values control register (PLLCTL), described ADSP-21535 Hardware Reference.
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Booting Modes
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ADSP-21535 three mechanisms (listed Table automatically loading internal memory after reset. fourth mode provided execute from external memory, bypassing boot sequence.
Table Booting Modes BMODE[2:0] Description
augment boot modes described above, secondary software loader provided that adds additional booting mechanisms. This secondary loader provides capability boot from 16-bit flash memory, fast flash, variable baud rate, etc.
Instruction Description
-111
Execute from 16-bit external memory (Bypass Boot ROM) Boot from 8-bit flash Boot from SPI0 serial (8-bit address range) Boot from SPI0 serial (16-bit address range) Reserved
BMODE pins Reset Configuration Register, sampled during power resets software initiated resets, implement following modes: Execute from 16-bit external memory Execution starts from address 0x2000000 with 16-bit packing. boot bypassed this mode. Boot from 8-bit external flash memory 8-bit flash boot routine located boot memory space using asynchronous Memory Bank configuration settings slowest device possible (3-cycle hold time; 15-cycle access times; 4-cycle setup). Boot from serial EEPROM (8-bit addressable) SPI0 uses PF10 output select single EPROM device, submits read command address 0x00, begins clocking data into beginning memory. 8-bit addressable SPI-compatible EPROM must used. Boot from serial EEPROM (16-bit addressable) SPI0 uses PF10 output select single EPROM device, submits read command address 0x0000, begins clocking data into beginning memory. 16-bit addressable SPI-compatible EPROM must used.
Blackfin family assembly language instruction employs algebraic syntax that designed ease coding readability. instructions have been specifically tuned provide flexible, densely encoded instruction that compiles very small final memory size. instruction also provides fully featured multifunction instructions that allow programmer many core resources single instruction. Coupled with many features more often seen microcontrollers, this instruction very efficient when compiling source code. addition, architecture supports both user (algorithm/application code) supervisor (O/S kernel, device drivers, debuggers, ISRs) mode operations, allowing multiple levels access core resources. assembly language, which takes advantage processor's unique architecture, offers following advantages: Seamlessly integrated DSP/CPU features optimized both 8-bit 16-bit operations. super-pipelined multi-issue load/store modified-Harvard architecture, which supports 16-bit four 8-bit load/store pointer updates cycle. registers, I/O, memory mapped into unified 4-Gbyte memory space providing simplified programming model.
Microcontroller features, such arbitrary bit-field manipulation, insertion, extraction; integer operations 16-, 32-bit data-types; separate user kernel stack pointers. Code density enhancements, which include intermixing 32-bit instructions mode switching, code segregation). Frequently used instructions encoded 16-bits.
each boot modes described above, four-byte value first read from memory device. This value used specify subsequent number bytes read into beginning memory space. Once each loads complete, processor jumps beginning space begins execution. addition, Reset Configuration Register application code bypass normal boot sequence during software reset. this case, processor jumps directly beginning memory space.
Development Tools
ADSP-21535 supported with complete software hardware development tools, including Analog Devices' emulators VisualDSP++® development environment. same emulator hardware that supports other Analog Devices DSPs, also fully emulates ADSP-21535. VisualDSP++ project management environment lets programmers develop debug application. This environment includes easy-to-use assembler that based algebraic syntax, archiver (librarian/library builder),
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linker, loader, cycle-accurate instruction-level simulator, C/C++ compiler, C/C++ run-time library that includes mathematical functions. point these tools C/C++ code efficiency. compiler been developed efficient translation C/C++ code Blackfin assembly. Blackfin architectural features that improve efficiency compiled C/C++ code. Debugging both C/C++ assembly programs with VisualDSP++ debugger, programmers can: View mixed C/C++ assembly code (interleaved source object information) Insert break-points conditional breakpoints registers, memory, stacks Trace instruction execution Perform linear statistical profiling program execution Fill, dump, graphically plot contents memory Perform source level debugging Create custom debugger windows
resources, automating generation various based objects, visualizing system state, when debugging application that uses VDK. Analog Devices' emulators IEEE 1149.1 JTAG test access port ADSP-21535 monitor control target board processor during emulation. emulator provides full-speed emulation, allowing inspection modification memory, registers, processor stacks. Nonintrusive in-circuit emulation assured processor's JTAG interface-the emulator does affect target system loading timing. addition software hardware development tools available from Analog Devices, third parties provide wide range tools supporting Blackfin family. Hardware tools include ADSP-21535 EZ-Kit standalone evaluation/development cards. Third Party software tools include libraries, real-time operating systems, block diagram design tools.
Designing Emulator-Compatible Board (Target)
VisualDSP++ lets programmers define manage software development. dialog boxes property pages programmers configure manage development tools, including Color Syntax Highlighting VisualDSP++ editor. These capabilities permit programmers Control development tools process inputs generate outputs. Maintain one-to-one correspondence with tool's command line switches.
Analog Devices family emulators tools that every developer needs test debug hardware software systems. Analog Devices supplied IEEE 1149.1 JTAG Test Access Port (TAP) ADSP-21535. emulator uses access internal features DSP, allowing developer load code, breakpoints, observe variables, observe memory, examine registers. must halted send data commands, once operation been completed emulator, system running full speed with impact system timing. these emulators, target's design must include interface between Analog Devices' JTAG emulation header custom target board.
Target Board Header
VisualDSP++ Kernel (VDK) incorporates scheduling resource management tailored specifically address memory timing constraints programming. These capabilities enable engineers develop code more effectively, eliminating need start from very beginning, when developing application code. features include Threads, Critical Unscheduled regions, Semaphores, Events, Device flags. also supports Priority-based, Pre-emptive, Cooperative Time -Sliced scheduling approaches. addition, designed scalable. application does specific feature, support code that feature excluded from target system. Because library, developer decide whether not. integrated into VisualDSP++ development environment, also used standard command line tools. When used, development environment assists developer with many error-prone tasks assists managing system
emulator interface Analog Devices' JTAG 14-pin header, shown Figure page customer must supply this header target board order communicate with emulator. interface consists standard dual 0.025" square post header, 0.1" 0.1" spacing, with minimum post length 0.235". position used prevent from being inserted backwards. This must clipped target board. Also, clearance (length, width, height) around header must considered. Leave clearance least 0.15" 0.10" around length width header, reserve height clearance attach detach connector. seen Figure there sets signals header. There standard JTAG signals TMS, TCK, TDI, TDO, TRST, used emulation
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PIN) BTCK BTRST
0.24" 0.88"
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header. This board area should contain components (chips, resistors, capacitors, etc.). dimensions referenced center 0.25" square post pin.
0.64"
Figure JTAG Connector Dimensions
VIEW
0.10"
Figure JTAG Target Board Connector JTAG Equipped Analog Devices (Jumpers Place)
purposes (via emulator). There also secondary JTAG signals BTMS, BTCK, BTDI, BTRST that optionally used board-level (boundary scan) testing. When emulator connected this header, place jumpers across BTMS, BTCK, BTRST, BTDI shown Figure This holds JTAG signals correct state allow free. Remove jumpers when connecting emulator JTAG header.
0.15"
Figure JTAG Connector Keep-Out Area Design-for-Emulation Circuit Information
details target board design issues including: single processor connections, multiprocessor scan chains, signal buffering, signal termination, emulator logic, EE-68: Analog Devices JTAG Emulation Technical Reference Analog Devices website (www.analog.com)- site search "EE-68". This document updated regularly keep pace with improvements emulator support.
ADDITIONAL INFORMATION
This data sheet provides general overview ADSP-21535 architecture functionality. detailed information Blackfin Family core architecture instruction set, refer ADSP-21535 Hardware Reference Blackfin Family Instruction Reference.
Figure JTAG Target Board Connector with Local Boundary Scan JTAG Emulator Connector
Figure details dimensions JTAG connector 14-pin target end. Figure displays keep-out area target board header. keep-out area allows connector properly seat onto target board REV.
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DESCRIPTIONS
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Unused inputs should tied pulled VDDEXT GND. ADSP-21535 definitions listed Table following pins asynchronous: ARDY, PF[15:0], USB_CLK, NMI, TRST, RESET, PCI_CLK, XTALI, XTALO.
Table Descriptions Type Function
following symbols appear Type column Table Input, Output, Three-State, Power, Ground.
ADDR DATA /SDQM ARDY CLKOUT /SCLK1 SCLK0 SCKE SA10 SRAS SCAS TMR0 TMR1 TMR2 PF[15] /SPI1SEL[7] PF[14] /SPI0SEL[7]
I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T
External address bus. External data bus. Asynchronous memory byte enables, SDRAM data masks. Chip selects asynchronous memories. Acknowledge signal asynchronous memories. Memory output enable asynchronous memories. Read enable asynchronous memories. Write enable asynchronous memories. SDRAM clock output pin. Same frequency timing SCLK0. Provided reduce capacitance loading SCLK0. Connect SDRAM's pin. SDRAM clock output Switches system clock frequency. Connect SDRAM's pin. SDRAM clock enable pin. Connect SDRAM's pin. SDRAM pin. SDRAM interface uses this retain control SDRAM device during host requests. Connect SDRAM's pin. SDRAM address strobe pin. Connect SDRAM's pin. SDRAM column address select pin. Connect SDRAM's pin. SDRAM write enable pin. Connect SDRAM's buffer pin. Memory select external memory bank configured SDRAM. Connect SDRAM's chip select pin. Timer pin. Functions output PWMOUT mode input WIDTH_CNT EXT_CLK modes. Timer pin. Functions output PWMOUT mode input WIDTH_CNT EXT_CLK modes. Timer pin. Functions output PWMOUT mode input WIDTH_CNT EXT_CLK modes. General purpose pins. output select pin. General purpose pins. output select pin.
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Table Descriptions (Continued) Function
PF[13] /SPI1SEL[6] PF[12] /SPI0SEL[6] PF[11] /SPI1SEL[5] PF[10] /SPI0SEL[5] PF[9] /SPI1SEL[4] /SSEL[1] PF[8] /SPI0SEL[4] /SSEL[0] PF[7] /SPI1SEL[3] PF[6] /SPI0SEL[3] /MSEL[6] PF[5] /SPI1SEL[2] /MSEL[5] PF[4] /SPI0SEL[2] /MSEL[4] PF[3] /SPI1SEL[1] /MSEL[3] PF[2] /SPI0SEL[1] /MSEL[2] PF[1] /SPISS1 /MSEL[1] PF[0] /SPISS0 /MSEL[0] RSCLK0 RFS0 REV.
I/O/T I/O/T I/O/T I/O/T
General purpose pins. output select pin. General purpose pins. output select pin. General purpose pins. output select pin. General purpose pins. output select pin. General purpose pins. output select pin. Sampled during reset determine core clock system clock ratio. General purpose pins. output select pin. Sampled during reset determine core clock system clock ratio. General purpose pins. output select pin.Sensed configuration state during hardware reset, used configure PLL. DF=1 high frequency clock divides input clock DF=0 passes input clock directly phase detector. General purpose pins. output select pin. Sensed configuration state during hardware reset, used configure PLL. Selects CLKIN ratio. General purpose pins. output select pin. Sensed configuration state during hardware reset, used configure PLL. Selects CLKIN ratio. General purpose pins. output select pin. Sensed configuration state during hardware reset, used configure PLL. Selects CLKIN ratio. General purpose pins. output select pin. Sensed configuration state during hardware reset, used configure PLL. Selects CLKIN ratio. General purpose pins. output select pin. Sensed configuration state during hardware reset, used configure PLL. Selects CLKIN ratio. General purpose pins. slave select input pin. Sensed configuration state during hardware reset, used configure PLL. Selects CLKIN ratio. General purpose pins. slave select input pin. Sensed configuration state during hardware reset, used configure PLL. Selects CLKIN ratio. Receive serial clock SPORT0. Receive frame synchronization SPORT0. Serial data receive SPORT0.
I/O/T I/O/T
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Table Descriptions (Continued) Function
TSCLK0 TFS0 RSCLK1 RFS1 TSCLK1 TFS1 MOSI0 MISO0 SCK0 MOSI1 MISO1 SCK1 USB_CLK XVER_DATA DPLS DMNS TXDPLS TXDMNS TXEN SUSPEND
I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T
Transmit serial clock SPORT0. Transmit frame synchronization SPORT0. Serial data transmit SPORT0. Receive serial clock SPORT1. Receive frame synchronization SPORT1. Serial data receive SPORT1. Transmit serial clock SPORT1. Transmit frame synchronization SPORT1. Serial data transmit SPORT1. Master slave SPI0. Supplies output data from master device receives input data slave device. Master slave SPI0. Supplies output data from slave device receives input data master device. Clock line SPI0. Master device output clock signal. Slave device input clock signal. Master slave SPI1. Supplies output data from master device receives input data slave device. Master slave SPI1. Supplies output data from slave device receives input data master device. Clock line SPI1. Master device output clock signal. Slave device input clock signal. UART0 receive pin. UART0 transmit pin. UART1 receive pin. UART1 transmit pin. clock. Single ended receive data output from transceiver USBD module. Differential receive data output from transceiver module. Differential receive data output from transceiver USBD module. Transmitted from USBD module transceiver. Transmitted from USBD module transceiver. Transmit enable from USBD module transceiver. Suspend mode enable output from USBD module transceiver. This signal also routed internally support power operations. Non-maskable interrupt.
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Type
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Table Descriptions (Continued) Function
TRST RESET CLKIN1 BYPASS SLEEP BMODE[2:0] PCI_AD PCI_CBE PCI_FRAME PCI_IRDY PCI_TRDY PCI_DEVSEL PCI_STOP PCI_PERR PCI_PAR PCI_REQ PCI_SERR PCI_RST PCI_GNT PCI_IDSEL PCI_LOCK PCI_CLK
I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T
JTAG clock. JTAG serial data out. JTAG serial data JTAG master slave. JTAG reset. ground used. When this asserted logic zero level least CLKIN cycles, hardware reset initiated. TShe minimum pulse width power-on reset µsec. Clock Dedicated mode pin. permanently strapped VSS. Bypasses on-chip PLL. Denotes that Blackfin Core Deep Sleep mode. Dedicated mode pin. permanently strapped VSS. Configures boot mode that employed following hardware reset software reset. address data bus. byte enables. frame signal. Used initiators signalling beginning transaction. initiator ready signal. target ready signal. device select signal. Asserted targets transactions claim transaction. stop signal. parity error signal. parity signal. request signal. Used requesting bus. system error signal. Requires pullup system board. reset signal. grant signal. Used granting access bus. initialization device select signal. Individual device selects targets configuration transactions. lock signal. Used lock target entire master that asserts lock. clock.
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Table Descriptions (Continued) Function
PCI_INTA
I/O/T
interrupt line bus. Asserted ADSP-21535 device signal interrupt system processor. Monitored ADSP-21535 when acting system processor. interrupt line. Monitored ADSP-21535 when acting system processor. interrupt line. Monitored ADSP-21535 when acting system processor. interrupt line. Monitored ADSP-21535 when acting system processor. Real-Time Clock oscillator input. Real-Time Clock oscillator output. Emulator acknowledge, open drain. Must connected ADSP-21535 emulator target board connector only. power supply (1.5 nominal). Real-Time Clock power supply (3.3 nominal). (except PCI) power supply (3.3 nominal). power supply (3.3 nominal). Internal power supply (1.5 nominal). Power supply return.
PCI_INTB PCI_INTC PCI_INTD XTALI XTALO VDDPLL VDDRTC VDDEXT VDDPCIEXT VDDINT
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ADSP-21535-SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS
Parameter Grade Parameter Nominal Unit
VDDINT VDDEXT VDDPLL VDDRTC VDDPCIEXT TCASE
Internal (Core) Supply Voltage External (I/O) Supply Voltage Power Supply Voltage Real Time Clock Power Supply Voltage Power Supply Voltage High Level Input Voltage1, VDDINT Level Input Voltage1, VDDINT Case Operating Temperature
0.86 1.425 3.15 3.15 -0.3
1.575 3.45 1.575 3.45 3.45 VDDEXT +0.5
Applies input bidirectional pins.
Specifications subject change without notice
ELECTRICAL CHARACTERISTICS
Parameter Test Conditions Unit
IOZH IOZL
High Level Output Voltage1 Level Output Voltage1 High Level Input Current2 Level Input Current2 Three-State Leakage Current3 Three-State Leakage Current3 Input Capacitance4,
VDDEXT min, -0.5 VDDEXT min, VDDEXT max, VDDEXT max, VDDEXT max, VDDEXT max, MHz, TCASE 25°C,
Applies output bidirectional pins. Applies input pins. Applies three-statable pins. Applies signal pins. Guaranteed, tested.
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June 2001
Parameter1
Absolute Maximum Rating
Internal (Core) Supply Voltage (VDDINT) External (I/O) Supply Voltage (VDDEXT) Input Voltage Output Voltage Swing Load Capacitance Core Clock Peripheral Clock (SCLK) Storage Temperature Range Lead Temperature seconds)
-0.3 +1.8 -0.3 +4.0 -0.5 VDDEXT -0.5 VDDEXT
Stresses greater than those listed above cause permanent damage device. These stress ratings only, functional operation device these other conditions greater than those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Specifications subject change without notice
SENSITIVITY
CAUTION: (electrostatic discharge) sensitive device. Electrostatic charges high 4000V readily accumulate human body test equipment discharge without detection. Although ADSP-21535 features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
TIMING SPECIFICATIONS
Table Table page describe timing requirements ADSP-21535 clocks. Take care selecting MSEL SSEL ratios exceed maximum core clock system clock operating frequencies, described ABSOLUTE MAXIMUM RATINGS.
Table Core System Clock Requirements Parameter Description Unit
tCCLK1.5 tCCLK1.4 tCCLK1.3 tCCLK1.2 tCCLK1.1 tCCLK1.0
Core Cycle Period (VDDINT =1.5 V-5%) Core Cycle Period (VDDINT =1.4 V-5%) Core Cycle Period (VDDINT =1.3 V-5%) Core Cycle Period (VDDINT =1.2 V-5%) Core Cycle Period (VDDINT =1.1 V-5%) Core Cycle Period (VDDINT =1.0 V-5%)
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Parameter Description
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Unit
Table Core System Clock Requirements (Continued)
tCCLK0.9 fCCLKNN tSCLK fSCLK
Core Cycle Period (VDDINT =0.9 V-5%) Core Clock Frequency tCCLKNN System Clock Period System Clock Frequency
1/tCCLKNN
Max. (7.5 tCCLKNN 1/tSCLK
Table Clock Timing Requirements Parameter Description Unit
tCKIN
Clock Period
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Power Dissipation
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Total power dissipation components, internal circuitry switching external output drivers. Table shows power dissipation
Table Internal Power Dissipation Parameter Test Conditions
internal circuitry. Internal power dissipation dependent instruction execution sequence data operands involved. Table lists conditions under which values Table obtained.
Typical (VDDINT =1.5
Typical (VDDINT =1.0
Units
IDDHIGH IDDTYP IDDLOW IDDSYS IDDEFR IDDACTIVE IDDRELAXED IDDSLEEP IDDDEEPSLEEP
tCCLKMIN, tCCLKMIN, tCCLKMIN, tCCLKMIN, tCCLKMIN,
Typical data specified nominal VDDINT typical process parameters.Maximum within TBD% typical values.
Table Internal Power Dissipation Conditions Parameter Mode CCLK SCLK Activity
IDDHIGH1 IDDTYP1 IDDLOW1 IDDSYS2 IDDEFR3 IDDACTIVE IDDRELAXED IDDSLEEP IDDDEEPSLEEP
Full-On Full-On Full-On Full-On Full-On Active Relaxed Sleep Deep Sleep
Enabled Enabled Enabled Enabled Enabled Enabled/Bypassed Disabled /Bypassed Disabled Disabled
Enabled Enabled Enabled Enabled Enabled Enabled Enabled Disabled Disabled
Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Disabled
Algorithm dependent
instruction mix. instruction system every cycle. Implementation Enhanced Full Rate (EFR) algorithm, instruction data fetch from L1/L2 memories cache.
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ADSP-21535 256-Lead PBGA Pinout
Table lists PBGA pinout signal name.
Table 256-Lead PBGA Assignment (Alphabetically Signal) SIGNAL
Table 256-Lead PBGA Assignment (Alphabetically Signal) (Continued) SIGNAL
AMS0 AMS1 AMS2 AMS3 ARDY BMODE0 BMODE1 BMODE2 BYPASS CLKIN1 CLKOUT DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15
ABE0 ABE1 ABE2 ABE3 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 ADDR24 ADDR25
REV.
This information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacturing unless otherwise agreed writing.
PRELIMINARY TECHNICAL DATA ADSP-21535
SIGNAL
current information contact Analog Devices 800-262-5643
June 2001
Table 256-Lead PBGA Assignment (Alphabetically Signal) (Continued)
Table 256-Lead PBGA Assignment (Alphabetically Signal) (Continued) SIGNAL
DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DMNS DPLS MISO0 MISO1 MOSI0 MOSI1 PCI_AD0 PCI_AD1
PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
This information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacturing unless otherwise agreed writing.
REV.
PRELIMINARY TECHNICAL DATA June 2001
current information contact Analog Devices 800-262-5643
ADSP-21535
Table 256-Lead PBGA Assignment (Alphabetically Signal) (Continued) SIGNAL
Table 256-Lead PBGA Assignment (Alphabetically Signal) (Continued) SIGNAL
PCI_CBE0 PCI_CBE1 PCI_CBE2 PCI_CBE3 PCI_CLK PCI_DEVSEL PCI_FRAME PCI_GNT PCI_IDSEL PCI_INTA PCI_INTB PCI_INTC PCI_INTD PCI_IRDY PCI_LOCK PCI_PAR PCI_PERR PCI_REQ PCI_RST PCI_SERR PCI_STOP PCI_TRDY /SPISS0 /MSEL0 /SPISS1 /MSEL1 /SPI0SEL1 /MSEL2 /SPI1SEL1 /MSEL3 REV.
/SPI0SEL2 /MSEL4 /SPI1SEL2 /MSEL5 /SPI0SEL3 /MSEL6 /SPI1SEL3 /SPI0SEL4 /SSEL0 /SPI1SEL4 /SSEL1 PF10 /SPI0SEL5 PF11 /SPI1SEL5 PF12 /SPI0SEL6 PF13 /SPI1SEL6 PF14 /SPI0SEL7 PF15 /SPI1SEL7 RESET RFS0
RFS1 RSCLK0 RSCLK1 SA10
This information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacturing unless otherwise agreed writing.
PRELIMINARY TECHNICAL DATA ADSP-21535
SIGNAL
current information contact Analog Devices 800-262-5643
June 2001
Table 256-Lead PBGA Assignment (Alphabetically Signal) (Continued)
Table 256-Lead PBGA Assignment (Alphabetically Signal) (Continued) SIGNAL
SCAS SCK0 SCK1 SCKE SCLK0 SCLK1 SLEEP SMS0 SMS1 SMS2 SMS3 SUSPEND TFS0 TFS1 TMR0 TMR1 TMR2 TRST TSCLK0 TSCLK1 TXDPLS TXDMNS TXEN
USB_CLK XTALI XTALO XVER_DATA
This information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacturing unless otherwise agreed writing.
REV.
PRELIMINARY TECHNICAL DATA June 2001
current information contact Analog Devices 800-262-5643
ADSP-21535
OUTLINE DIMENSIONS
Dimensions Figure shown millimeters.
DRAWING VIEWS DIMENSIONS
Figure 256-Lead Metric Plastic Ball Grid Array (PBGA) (B-256) ORDERING GUIDE Part Number1 Case Temperature Range Instruction Rate Operating Voltage
ADSP-21535PKCA-300
0.95 1.575 internal, V-tolerant
Plastic Ball Grid Array (PBGA).
REV.
This information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacturing unless otherwise agreed writing.
PRELIMINARY TECHNICAL DATA June 2001
current information contact Analog Devices 800-262-5643
ADSP-21535
REV.
This information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacturing unless otherwise agreed writing.

ADSP-21535 308K Bytes On-Chip Memory: Bytes Instruction SRAM/Cach

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