Application Note PETER ALFKE BERNIE XAPP 027.001 Summary

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Application Note PETER ALFKE BERNIE XAPP 027.001 Summary

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Implementing State Machines Devices
Application Note PETER ALFKE BERNIE
XAPP 027.001
Summary
This Application Note discusses various approaches that available implementing state machines devices. particular, one-hot-encoding scheme medium-sized state machines discussed.
Family
XC3000/XC3100/XC3100A
Demonstrates
State Machine Design One-hot Encoding
Introduction
State-machine methodology defines contents every flip-flop design under every circumstance that might arise. also defines possible transitions that cause design from these states another. simplest form, this just rigorous designing synchronous logic, like 4-bit counters. more complex designs, state-machine approach gives designer tool analyze possible operating conditions, avoid overlooked hang-up states undesired transitions. devices with their abundance flip-flops lend themselves well state-machine designs. Using 5-input function generator XC3000 family devices 32-bit ROM, state machine with states with conditional jumps uses only five CLBs. Five registered outputs drive five function generator inputs five CLBs parallel. This implements fully programmable sequencer such synchronous counter. smaller number states, some inputs used conditional jump inputs. Encoding these condition codes, however, require additional level logic which reduces maximum clock rate.
Synchronous Counters
Using only CLBs, possible construct fully synchronous 4-bit counters with arbitrary count sequences, Figure Clock Enable inputs even provide countenable control. count length, count direction, even code sequence determined configuration. number possible count sequences factorial i.e., more than 1012. four outputs available, while counter cannot preset arbitrary value, cleared asynchronous input. Table shows four common count sequences. particular interest Gray code, which offers glitch-less decoding, since only changes transition. Gray-code counter also reliably read asynchronously. contrast, binary counter read during transition between example, code might detected. Decimal Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Gray 0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010 1011 1001 1000 Binary 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Gray 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010
Function Generator
Sequence: Binary Gray
X3-Gray Biquinary Etc.
Function Generator
X3086
Figure Synchronous 4-Bit Counter CLBs
Table Four Common Binary Count Sequences
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Implementing State Machines Devices
Four-bit counters constructed described above easily concatenated into longer, four-bits-at-a-time ripplecarry counters. each 4-bit digit, third used detect arbitrary terminal count value, this with incoming Count Enable provide Count Enable next digit.
following examples demonstrate arbitrary nature waveforms that generated. Example counter with output High times T10, through Example counter with output times T12, T15, T18.
Waveform Generator
Arbitrary binary waveforms length clock periods generated using only three XC3000 series CLBs, Figure waveform generation fully synchronous, paused time, using Clock Enable. also restarted, using asynchronous clear. Five flip-flops, Q0-4, form linear feedback shift-register counter. 5-input combinatorial function generator, determines both modulus count sequence; there illegal hang-up states. function generator, operates ROM, programmed provide conceivable decode counter. Flip-flop, synchronizes de-glitches decoder output.
Simple State Machines
simple state machine shown Figure uses only CLBs, states. Each eight outputs decode/encode combination states. state machine based 5-CLB next-state look-up table. Each state corresponds look-up table locations that store arbitrarily defined next states. From state, input controls two-way branching selecting which possible next states asserted. hold loops, next states should current state; avoid branching, both destination states should made equal.
Encoded Output (any pattern)
e.g.
X3087
Figure Synchronous 5-Bit Waveform Generator CLBs
Word Next-State Look-Up Table CLBs) CONTROL INPUTS
State
Decode/ Encode CLBs)
State Machine Output
CLB) Activate 8-Way Branch
X3085
Figure Simple Sate Machine
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state machine also perform 8-way branches from state programmed. branch destinations must fall quadrants (0.3, 4.7, 8.11 12.15). choice quadrants arbitrarily programmed into look-up table; selects between quadrants, select state within quadrant. Activation 8-way branch mechanism controlled fifth state that during transition into state. This controls multiplexer that replaces destination state with control inputs Note that fifth independent must set, not, quadrant basis during 8-way branch. Examples:
(but log2N), unique combination these flip-flops each state; each flip-flop several states. While this minimizes number flip-flops, increases complexity logic controlling each flip-flop. devices, flip-flops plentiful, there need conserve them. Consequently, medium-sized state machines, better One-Hot encoding scheme (OHE). increases number flip-flops required, reduces logic complexity associated with each them, thereby boosting performance. state machine, flip-flop assigned each state. during that state, only during that state. state machine implemented shift-register-like structure, where single passed from flip-flop flipflop, sometimes holding same flip-flop, skipping bits shift register moving parallel shift register, Figure control logic associated with each state involves ORing transitions into state, including hold loop. Each these transitions will involve previous state, which, design, represented single bit. This may, not, ANDed with some decode control bits inputs. localization control logic that leads performance increase. each state bit, control logic only involves limited number state bits from which there transitions conditions that control those transitions. This permits shallow logic structures between flip-flops, often only requiring function generator associated with state-bit flip-flop. addition, state decoding necessary, state encoding only require ORing state bits.
From state High, else From state High, else stay From state unconditionally From state execute truth table below
Truth Table High
One-Hot Encoded State Machines
state machines described have encoded state bits. N-state state machine, fewer than flip-flops used
Control Bits
X3088
Figure Prototype State Machine
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Implementing State Machines Devices
XC3220
State Machine Outputs Control Inputs
EPROM
Data Addrs
X5315
Figure Rudimentary Complex State Machine
encoding state-machine outputs. registered state bits also form part EPROM address, defining block possible next states. 7-bit condition code completes EPROM address selects which next states actually asserted.
X3089
Figure State Diagram Prototype State Machine
Each transition effect, 128-way branch. However, branching complexity will normally reduced assigning identical values many possible next states. Since address locations used configuration data, state codes, which form MSBs EPROM address, limited different values, 0.239. control inputs provide seven LSBs EPROM address. control inputs asynchronous, they must registered reliable operation. This rudimentary state machine thus have different states, jump from state arbitrarily defined next states, according 7-bit condition code. simplest form, this basic design consumes resources LCA, just flip-flops state register. Even permits number states multiway branch complexity excess normal need. user logic resources available features like following. State decoding/encoding Stack registers Loop counters More sophisticated branch logic, etc. This design straightforward, inexpensive, compact extremely flexible. speed limited primarily control store access time; faster access times obtained using SRAMs place EPROMs.
Complex State Machines
Small- medium-sized state machines easily implemented within device, shown above. large, complex state machines, however, better device implement simple microsequencer, store control program externally, Figure fastest operation, high-speed SRAM should used control program. This loaded from microprocessor, shadowed EPROM. slower operation requiring non-volatility, EPROM used directly. When EPROM used, number components reduced storing both configuration data state-machine control program same device. XC3020 configured Master Parallel mode reads configuration data 256K (32K EPROM, only requires addresses, from location 7FFF (32K) through 77FF (about 30K). remaining EPROM used next-state look-up table with capacity states. Eight state bits read EPROM registered device which perform required decoding
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Application Note PETER ALFKE BERNIE XAPP 027.001 Summary

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