N-channel clamped TO-220 fully protected SAFeFETPower MOSFET Type
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STP180NS04ZC
N-channel clamped TO-220 fully protected SAFeFETPower MOSFET
Type STP180NS04ZC
VDSS Clamped
RDS(on)
capacitance gate charge 100% avalanche tested 175°C maximum junction temperature
TO-220
Applications
Switching application
Description
This fully clamped Power MOSFET produced using latest advanced company's mesh OVERLAY process which based novel strip layout. inherent benefits technology coupled with extra clamping capabilities make this product particularly suitable harshest operation conditions such those encountered automotive environment. other application requiring extra ruggedness also recommended. Figure Internal schematic diagram
Table
Device summary
Marking P180NS04ZC Package TO-220 Packaging Tube
Order code STP180NS04ZC
April 2008
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www.st.com
Contents
STP180NS04ZC
Contents
Electrical ratings Electrical characteristics
Electrical characteristics (curves)
Test circuit
Package mechanical data Revision history
2/12
STP180NS04ZC
Electrical ratings
Electrical ratings
Table
Symbol
Absolute maximum ratings
Parameter Drain-source voltage (VGS Drain-gate voltage Gate-source voltage Drain current (continuous) Drain current (continuous) TC=100 Drain gate current (continuous) Gate-source current (continuous) Drain current (pulsed) Total dissipation Derating factor Value
Unit W/°C
PTOT
VESD(G-S) VESD(G-D) VESD(D-S) Tstg
Gate-source (HBM-C=100 R=1.5 Gate-drain (HBM-C=100 R=1.5 Drain-source (HBM-C=100 R=1.5 Operating junction temperature Storage temperature
Voltage limited zener diodes Current limited wire bonding Pulse width limited safe operating area
Table
Symbol Rthj-case Rthj-amb
Thermal data
Parameter Thermal resistance junction-case Thermal resistance junction-ambient Maximum lead temperature soldering purpose Value 0.50 62.5 Unit °C/W °C/W
Table
Symbol
Avalanche data
Parameter Avalanche current, repetitive repetitive (pulse width limited Tjmax Single pulse avalanche energy (starting Tj=25 ID=IAS, VDD=21 (see Figure Figure 14.) Value Unit
1000
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Electrical characteristics
STP180NS04ZC
Electrical characteristics
(TCASE=25°C unless otherwise specified) Table
Symbol V(BR)DG VDSR(CL)
On/off states
Parameter Clamped voltage Drain-source clamping voltage (DC) Zero gate voltage drain current (VGS Gate-body leakage current (VDS Gate-source breakdown voltage Gate threshold voltage Static drain-source resistance Internal gate resistor Test conditions IGS(CL) V,Tj V,Tj ±100 VGS, Min. Typ. Max. Unit
IDSS
IGSS
VGSS VGS(th) RDS(on)
Gate Oxide, without zener diodes, tested wafer sorting (IGSS Tj=25°). Figure 17.: Unclamped Inductive load test circuit electrical schematics
Table
Symbol Ciss Coss Crss tr(Voff)
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance voltage rise time Fall time Cross-over time Total gate charge Gate-source charge Gate-drain charge Test conditions Min. Typ. 4560 1700 Max. Unit
MHz, VGS=0
VCLAMP=30 ID=80 VGS=10 RG=4.7 (see Figure VDD=20 (see Figure
Pulsed: pulse duration=300µs, duty cycle 1.5%
4/12
STP180NS04ZC
Electrical characteristics
Table
Symbol ISDM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD=120 VGS=0 ISD=120 di/dt A/µs, VDD= Tj=150 (see Figure Test conditions Min. Typ. Max. Unit
VSD(2) IRRM
Pulse width limited safe operating area Pulsed: pulse duration=300 duty cycle 1.5%
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Electrical characteristics
STP180NS04ZC
Figure
Electrical characteristics (curves)
Safe operating area Figure Thermal impedance
Figure
Output characteristics
Figure
Transfer characteristics
Figure
Transconductance
Figure
Static drain-source resistance
6/12
STP180NS04ZC Figure Gate charge gate-source voltage Figure
Electrical characteristics Capacitance variations
Figure Normalized gate threshold voltage temperature
Figure Normalized resistance temperature
Figure Source-drain diode forward characteristics
Figure Normalized BVDSS temperature
7/12
Test circuit
STP180NS04ZC
Test circuit
Figure Gate charge test circuit
Figure Unclamped inductive waveform
Figure Test circuit inductive load Figure Unclamped Inductive load test switching diode recovery times circuit
8/12
STP180NS04ZC
Package mechanical data
Package mechanical data
order meet environmental requirements, offers these devices ECOPACK® packages. These packages have Lead-free second level interconnect. category second level interconnect marked package inner label, compliance with JEDEC Standard JESD97. maximum ratings related soldering conditions also marked inner label. ECOPACK trademark. ECOPACK specifications available www.st.com
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Package mechanical data
STP180NS04ZC
TO-220 mechanical data
4.40 0.61 1.14 0.48 15.25 1.27 2.40 4.95 1.23 6.20 2.40 3.50 16.40 28.90 3.75 2.65 3.85 2.95 0.147 0.104 10.40 2.70 5.15 1.32 6.60 2.72 3.93 0.393 0.094 0.194 0.048 0.244 0.094 0.511 0.137 4.60 0.88 1.70 0.70 15.75 0.173 0.024 0.044 0.019
inch 0.181 0.034 0.066 0.027 0.62 0.050 0.409 0.106 0.202 0.051 0.256 0.107 0.551 0.154 0.645 1.137 0.151 0.116
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STP180NS04ZC
Revision history
Revision history
Table
Date 03-Apr-2008
Document revision history
Revision First release Changes
11/12
STP180NS04ZC
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