High-voltage high side driver High voltage rail dV/dt immunity V/
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L6392
High-voltage high side driver
High voltage rail dV/dt immunity V/nsec full temperature range Driver current capability: source sink Switching times 75/35 nsec rise/fall with load TTL/CMOS inputs with hysteresis Integrated bootstrap diode Operational amplifier advanced current sensing Adjustable dead-time Interlocking function Compact simplified layout Bill material reduction Flexible, easy fast design DIP-14 SO-14
Description
L6392 high-voltage device, manufactured with "OFF-LINE" technology. monolitich half-bridge gate driver N-channel Power MOSFET IGBT. high side (floating) section designed stand voltage rail logic inputs CMOS/TTL compatible down easy interfacing microcont roller/DSP embeds suitable advanced current sensing applications such field oriented motor control.
Application
Table
Device summary
Order codes L6392 L6392D L6392D013TR Package DIP-14 SO-14 SO-14 Packaging Tube Tube Tape reel
March 2008
1/19
www.st.com
This preliminary information product development undergoing evaluation. Details subject change without notice.
Contents
L6392
Contents
Block diagram connection Truth table Electrical data
Absolute maximum ratings Thermal data Recommended operating conditions
Electrical characteristics
operation operation
Waveforms definitions Typical application diagram Bootstrap driver
CBOOT selection charging
Package mechanical data Revision history
2/19
L6392
Block diagram
Block diagram
Figure Block diagram
BOOTSTRAP DRIVER DETECTION from FLOATING STRUCTURE
BOOT
DETECTION DRIVER
LEVEL SHIFTER
LOGIC SHOOT THROUGH PREVENTION DRIVER
DEAD TIME
OPOUT
OPAMP
3/19
connection
L6392
connection
Figure Pins connection (top view)
OPOUT BOOT OPOP+
Table
description
name
Type
Function side driver logic input (active low) Shut down logic input (active low) High side driver logic input (active high) Lower section supply voltage Dead time setting Opamp output Ground Opamp inverting input Opamp inverting input side driver output connected
OPOUT OPLVG
High side (floating) common voltage High side driver output Bootstrapped supply voltage
BOOT
circuit guarantees less than pins Isink mA), with This allows omitting "bleeder" resistor connected between gate source external MOSFET normally used hold low; gate driver assures impedance also condition.
4/19
L6392
Truth table
Truth table
Table Truth table
Inputs Outputs
Note:
don't care
5/19
Electrical data
L6392
Electrical data
Absolute maximum ratings
Table
Symbol Vout Vop+ VopVboot Vhvg VIvg dVout/dt Ptot Tstg Output voltage Supply voltage Opamp non-inverting input Opamp inverting input Floating supply voltage High side gate output voltage side gate output voltage Logic input voltage Allowed output slew rate Total power dissipation (TA= Junction temperature Storage temperature
Absolute maximum rating
Parameter Value Vboot Vboot +0.3 -0.3 +0.3 -0.3 +0.3 Vout Vboot -0.3 -0.3 Unit V/ns
Note:
immunity pins guaranteed (Human Body Model)
Thermal data
Table
Symbol Rth(JA)
Thermal data
Parameter Thermal resistance junction ambient SO-14 DIP-14 Unit °C/W
Recommended operating conditions
Table
Symbol Vout
Recommended operating conditions
Parameter Output voltage Floating supply voltage Switching frequency Supply voltage Junction temperature
Test condition
Unit
HVG, load
condition TBDV< Vboot Vout Vboot guaranteed, Vout range from Vboot -Vout
6/19
L6392
Electrical characteristics
Table
Symbol toff
Electrical characteristics
operation
operation electrical characteristics (VCC 15V; =+25
Parameter Test condition Rdt=0; CL=1 =100 Rdt=37 k;CL=1 nF;CDT=100 Rdt=136 k;CL=1 nF;CDT=100 Rdt=260 k;CL=1 nF;CDT=100 Rdt=0 CL=1 =100 Rdt=37 k;CL=1 nF;CDT=100 Rdt=136 k;CL=1 nF;CDT=100 Rdt=26 0k;CL=1 nF;CDT=100 0.15 Unit
High/low side driver turnVout propagation delay High/low side driver turn- boot propagation delay Shut down high/low Figure page side propagation delay Delay matching, turn-on/off
Dead time setting range
Matching dead time
Rise time Fall time
Figure
Timing characteristics
toff
toff
LVG/HVG
toff
7/19
Electrical characteristics
L6392
Table
Symbol
operation
operation electrical characteristics (VCC V;TJ
Parameter Test condition Unit
supply voltage section Vcc_hys Vcc_thON Vcc_thOFF hysteresis turn threshold turn threshold GND; GND; GND; GND; 1400 11.8 10.4
Iqccu
Undervoltage quiescent supply current
Iqcc
Quiescent current
1060
Bootstrapped supply voltage section VBS_hys VBS_thON VBS_thOFF hysteresis turn threshold turn threshold Undervoltage quiescent current GND; GND; 1400 11.6 10.2
IQBSU
IQBS
quiescent current
8/19
L6392 Table
Symbol Rdson
Electrical characteristics operation electrical characteristics (VCC V;TJ
Parameter High voltage leakage current Bootstrap driver resistance Test condition Vhvg Vout Vboot Unit
Driving buffers section Logic inputs IHINh IHINl ILINh ILINl ISDh ISDl logic input bias current logic input bias current logic input bias current logic input bias current logic input bias current High level logic threshold voltage logic input bias current 2.21 level logic threshold voltage 0.83 High/low side source short circuit current High/low side sink short circuit current
RDSon tested following way: RDSon [(VCC VCBOOT1) (VCC VCBOOT2)] [I1(VCC,VCBOOT1) I2(VCC,VCBOOT2)] where current when VCBOOT VCBOOT1, when VCBOOT VCBOOT2
9/19
Electrical characteristics
L6392
Table
Symbol Vicm
OPAMP characteristics (VCC
Parameter Input offset voltage Input bias current Input common mode voltage range Output voltage swing level Output voltage swing high level Isink Isource Source, TBD; Sink TBD; Slew rate Gain bandwith product Large signal voltage gain Power supply rejection ratio Common mode rejection ratio TBD; TBD; unity gain TBD; 13.5 14.3 Test condition TBD; Vicm -TBD V/µs Unit
Output short circuit current
GBWP CMRR
direction input current
10/19
L6392
Waveforms definitions
Figure
Waveforms definitions
Dead time timing waveforms
gate driver outputs (HALF-BRIDGE TRI-STATE)
INTE
INTE
CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING DEAD TIME
CKIN
CKIN
gate driver outputs (HALF-BRIDGE TRI-STATE)
CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME
gate driver outputs (HALF-BRIDGE TRI-STATE) gate driver outputs (HALF-BRIDGE TRI-STATE)
CONTROL SIGNALS EDGES OVERLAPPED, INSIDE DEAD TIME: DEAD TIME
gate driver outputs (HALF-BRIDGE TRI-STATE) gate driver outputs (HALF-BRIDGE TRI-STATE)
CONTROL SIGNALS EDGES OVERLAPPED, OUTSIDE DEAD TIME: DIRECT DRIVING
gate driver outputs (HALF-BRIDGE TRI-STATE) gate driver outputs (HALF-BRIDGE TRI-STATE)
connected togheter driven just control signal
11/19
Typical application diagram
L6392
Figure
Typical application diagram
Application diagram
BOOTSTRAP DRIVER DETECTION from
FLOATING STRUCTURE
BOOT
DETECTION DRIVER
H.V.
Cboot
LEVEL SHIFTER
LOGIC SHOOT THROUGH PREVENTION DRIVER LATCH LOAD
DEAD TIME OPAMP
OPOUT
12/19
L6392
Bootstrap driver
Bootstrap driver
bootstrap circuitry needed supply high voltage section. This function normally accomplished high voltage fast recovery diode (Figure L6392 patented integrated structure replaces external diode. realized high voltage DMOS, driven synchronously with side driver (LVG), with diode series, shown Figure internal charge pump (Figure provides DMOS driving voltage.
CBOOT selection charging
choose proper CBOOT value external seen equivalent capacitor. This capacitor CEXT related total gate charge:
gate gate
ratio between capacitors CEXT CBOOT proportional cyclical voltage loss.
CBOOT CEXT e.g.: Qgate Vgate CEXT With CBOOT drop would supplied long time, CBOOT selection take into account also leakage quiescent losses. e.g.: steady state consumption lower than CBOOT supply CEXT. This charge capacitor means voltage drop internal bootstrap driver gives agreat advantage: external fast recovery diode avoided usually great leakage current). This structure work only VOUT close lower) meanwhile charging time (Tcharge CBOOT time which both conditions fulfilled long enough charge capacitor. bootstrap driver introduces voltage drop DMOS RDSON (typical value: frequency this drop neglected. Anyway increasing frequency must taken account. following equation useful compute drop bootstrap DMOS:
gate drop dson drop dson
where Qgate gate charge external power MOS, Rdson resistance bootstrap DMOS, Tcharge charging time bootstrap capacitor.
13/19
Bootstrap driver example: using power with total gate charge drop bootstrap DMOS about Tcharge fact:
L6392
30nC drop 0.7V
Vdrop taken into account when voltage drop CBOOT calculated: this drop high, circuit topology doesn't allow sufficient charging time, external diode used. Figure Bootstrap driver
DBOOT
BOOT H.V.
BOOT H.V.
CBOOT VOUT LOAD
CBOOT VOUT LOAD
D99IN1067
14/19
L6392
Package mechanical data
Package mechanical data
order meet environmental requirements, offers these devices ECOPACK® packages. These packages have lead-free second level interconnect category second level interconnect marked package inner label, compliance with JEDEC Standard JESD97. maximum ratings related soldering conditions also marked inner label. ECOPACK trademark. ECOPACK specifications available www.st.com
15/19
Package mechanical data Figure DIP-14 mechanical data package dimensions
L6392
DIM. MIN. 1.27 0.51 1.39
TYP. MAX. MIN. 0.020 1.65 0.25 2.54 15.24 2.54 0.050 0.055
inch TYP. MAX.
OUTLINE MECHANICAL DATA
0.065 0.020 0.010 0.787 0.335 0.100 0.600 0.280 0.201 0.130 0.100
16/19
L6392 Figure
Package mechanical data SO-14 mechanical data package dimensions
DIM. MIN.
inch MAX. 1.75 0.30 1.65 0.51 0.25 8.75 MIN. 0.053 0.004 0.043 0.013 0.007 0.337 0.150 0.050 6.20 0.50 1.27 0.228 0.01 0.016 0.244 0.02 0.050 TYP. MAX. 0.069 0.012 0.065 0.020 0.01 0.344 0.157
TYP.
OUTLINE MECHANICAL DATA
1.35 0.10 1.10 0.33 0.19 8.55 3.80 1.27 0.25 0.40
(min.), (max.) 0.10 0.004
dimension does include mold flash, protusions gate burrs. Mold flash, protusions gate burrs shall exceed 0.15mm side.
SO-14
0016019
17/19
Revision history
L6392
Revision history
Table
Date 29-Feb-2008 18-Mar-2008
Document revision history
Revision Initial release Cover page updated Changes
18/19
L6392
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