N-channel 1200 TO-220 IPAK Zener protected SuperMESHPower MOSFET
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STP1N120 STU1N120
N-channel 1200 TO-220 IPAK Zener protected SuperMESHPower MOSFET
Type STP1N120 STU1N120
VDSS 1200 1200
RDS(on)
100% avalanche tested Extremely high dv/dt capability improved capability high voltage benchmark Gate charge minimized
TO-220
IPAK
Application
Switching applications
Figure
Internal schematic diagram
Description
SuperMESHseries obtained through extreme optimization ST's well established strip-based PowerMESHlayout. addition pushing on-resistance significantly down, special care taken ensure very good dv/dt capability most demanding applications. Such series complements full range high voltage Power MOSFETs including revolutionary MDmeshproducts.
Table
Device summary
Marking 1N120 1N120 Package TO-220 IPAK Packaging Tube Tube
Order codes STP1N120 STU1N120
March 2008
1/11
www.st.com
This preliminary information product development undergoing evaluation. Details subject change without notice.
Contents
STP1N120 STU1N120
Contents
Electrical ratings Electrical characteristics Test circuits
Package mechanical data Revision history
2/11
STP1N120 STU1N120
Electrical ratings
Electrical ratings
Table
Symbol
Absolute maximum ratings
Parameter Drain-source voltage (VGS=0) Gate-source voltage Drain current (continuous) Drain current (continuous) Drain current (pulsed) Derating factor Value 1200 0.36 Unit W/°C
PTOT Tstg
Total dissipation Storage temperature operating junction temperature
Pulse width limited safe operating area
Table
Symbol Rthj-case Rthj-amb
Thermal data
Value Parameter TO-220 Thermal resistance junction-case Thermal resistance junction-amb Maximum lead temperature soldering purpose 62.5 2.78 IPAK °C/W °C/W Unit
Table
Symbol
Avalanche characteristics
Parameter Avalanche current, repetitive notrepetitive (pulse width limited max) Single pulse avalanche energy (starting Tj=25 ID=IAS, VDD= value Unit
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Electrical characteristics
STP1N120 STU1N120
Electrical characteristics
(TCASE=25 unless otherwise specified) Table
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS Gate body leakage current (VDS Gate threshold voltage Static drain-source resistance Test conditions VGS= rating, rating,Tc=125 VDS= VGS, VGS= 0.25 Min. 1200 Typ. Max. Unit
Table
Symbol gfs(1) Ciss Coss Crss Coss eq.(2)
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Equivalent output capacitance Total gate charge Gate-source charge Gate-drain charge Intrinsic gate resistance Test conditions 0.25 Min. Typ. Max. Unit
MHz, VGS=0
VDD=960 (see Figure open drain
Pulsed: pulse duration=300µs, duty cycle 1.5% Coss defined constant equivalent capacitance giving same charging time Coss when increases from VDSS
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STP1N120 STU1N120
Electrical characteristics
Table
Symbol td(on) td(off)
Switching times
Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD=600 ID=0.25 RG=4.7 VGS=10 (see Figure Min. Typ. 10.7 28.5 Max. Unit
Table
Symbol ISDM VSD(1) IRRM IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward voltage Reverse recovery time Reverse recovery charge Reverse recovery current Reverse recovery time Reverse recovery charge Reverse recovery current ISD= VGS=0 ISD=500 mA,VDD=100 di/dt A/µs (see Figure ISD=500 mA,VDD=100 di/dt=50 A/µs,Tj=150 (see Figure 0.56 0.58 Test conditions Typ. Unit
Pulsed: pulse duration 300µs, duty cycle 1.5%
Table
Symbol
Gate-source Zener diode
Parameter Test conditions Typ. Unit
BVGSO Gate-source breakdown voltage (open drain)
built-in-back Zener diodes have specifically been designed enhance only device's capability, also make them safely absorb possibile voltage transients that occasionally applied from gate source. this respect zener voltage appropriate achieve efficient osteffective intervention protect device's integrity. These integrated zener diodes thus avoid usage external components.
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Test circuits
STP1N120 STU1N120
Figure
Test circuits
Switching times test circuit resistive load Figure Gate charge test circuit
Figure
Test circuit inductive load Figure switching diode recovery times
Unclamped inductive load test circuit
Figure
Unclamped inductive waveform
Figure
Switching time waveform
6/11
STP1N120 STU1N120
Package mechanical data
Package mechanical data
order meet environmental requirements, offers these devices ECOPACK® packages. These packages have Lead-free second level interconnect category second level interconnect marked package inner label, compliance with JEDEC Standard JESD97. maximum ratings related soldering conditions also marked inner label. ECOPACK trademark. ECOPACK specifications available www.st.com
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Package mechanical data
STP1N120 STU1N120
TO-220 mechanical data
4.40 0.61 1.14 0.48 15.25 1.27 2.40 4.95 1.23 6.20 2.40 3.50 16.40 28.90 3.75 2.65 3.85 2.95 0.147 0.104 10.40 2.70 5.15 1.32 6.60 2.72 3.93 0.393 0.094 0.194 0.048 0.244 0.094 0.511 0.137 4.60 0.88 1.70 0.70 15.75 0.173 0.024 0.044 0.019
inch 0.181 0.034 0.066 0.027 0.62 0.050 0.409 0.106 0.202 0.051 0.256 0.107 0.551 0.154 0.645 1.137 0.151 0.116
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STP1N120 STU1N120
Package mechanical data
TO-251 (IPAK) mechanical data
DIM. (L1) 9.00 0.80 0.80 4.40 16.10 9.40 1.20 5.20 0.45 0.48 6.00 6.40 2.28 4.60 min. 2.20 0.90 0.64 max. 2.40 1.10 0.90 0.95 5.40 0.60 0.60 6.20 6.60
0068771_H
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Revision history
STP1N120 STU1N120
Revision history
Table
Date 11-Oct-2006 20-Mar-2008
Document revision history
Revision First release Added IPAK package, preliminary version Changes
10/11
STP1N120 STU1N120
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