INTRODUCTION CORE, MEMORY, CLOCK, RESET, INTERRUPT, POWER MODES A
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MICROCONTROLLER TRAINING
INTRODUCTION
CORE, MEMORY, CLOCK, RESET, INTERRUPT, POWER MODES ADDRESSING MODES III. PERIPHERALS
iii. PORTS CONVERTER TIMERS EEPROM COMMUNICATION
SOFTWARE TOOLS HARDWARE TOOLS TIPS TRICKS
ST62 PORT
BLOCK DIAGRAM
CONTROLS
RESET
DATA REGISTER DIRECTION
INPUT/OUTPUT DATA REGISTER SHIFT REGISTER OPTION REGISTER
INTERRUPT
ST62 PORT REGISTERS
Data direction registers (DDRPA/PB/PC)
Mapped C4h, respectively Allow selection data direction each (input output)
Option registers (ORPA/ORPB/ORPC)
mapped CCh, respectively Allow selection available modes (push-pull open drain)
Data registers (DDRA/RB/RC)
mapped C0h, respectively port output, writes logic status pins port input, reads logic status from pins Also used modify configuration write input mode
ST62 MODES
ll-u terru ll-u terru ll-u terru rain
Notes:
means don't care PA4-PA7 PC4-PC7 available ST6210/E10, ST6220/E20
AUTHORIZED TRANSITIONS
ST62 PORTS
Avoid certain port state transitions
result unwanted side effects
set/res carefully data register
Only when whole port output mode other cases, keep copy register
Interrupt pull-up Input pull-up Reset state) Output Open Drain Output Push-pull Input Analog Input
Output Open Drain Output Push-pull
PORTS Application Tips
Open drain
Useful driving
Where several devices drive same
WIRE-ORed TOGETHER increase current drive capability
Interrupt
lines have interrupt capability
Ideal real time control
Clamp diodes
pins have clamp diode protection
connected directly external voltage
PORTS RECOMMENDATION
single instruction DEC) port
Data register when port contains input pins:
read-modify-write cycle done register port configuration change
ASSUME FOLLOWING CONFIGURATION
Port B0-3: output open drain Port B4-6: input with pull Port input with interrupt pull-up Instruction:
0,DRB
PORTS
RECOMMENDATION Description instruction:
Read Port Data Register
input mode, read instruction always reads state pin, while output mode contents data register read
Modify specified
'OR' (SET) 'AND' (RES) operation with single mask operand performed whole byte
Write modified byte back into
whole byte (for input output mode) written back into data register. Thus have changed value therefore configuration:
PB6: Input with pull Input without pull PB7: Interrupt-Input Analog Input
RECOMMENDATION
PORTS
Port data registers input mode form part configuration Either: dedicate entire port either avoid using reset instructions ports shadow register technique
Application note available AN432
PORTS
APPLICATION TIPS
SOLUTION: SHADOW REGISTER TECHNIQUE ACCU
SET/RES JRR/JRS
MIXED PORT WRITE ONLY REGISTER
SHADOW COPY REGISTER
SET/RES
5,DRB A,DRB DRB,A
5,SHADOWREG A,SHADOWREG DRB,A 5,DRB,LABEL
Recommendations unbounded pins
Leave reset state unbounded pins change their configuration. When write operation followed compare performed port register, mask. Take into account that unbounded pins could have undefined state. safe operations,unbounded pins have considered non-existing pins. NOTES:
avoid non-compatibility between versions,the above recommendations have followed. uncompleted ports, emulator doesn't reflect behavior device because unbouded pins stuck logical level
SERIAL IMPEDANCE PORT
CMOS device,it recommended connect high impedance input pins. choice these impedance done with respect maximum leakage current defined data sheet. risk closed specification input levels applied device.
Ports Configuration Example
Fill dedicated port registers order have following configuration, micro reset state:
PA0, PA3,
Push-Pull Output (high level) Analog Input Input with Interrupt Push-Pull Output (low level) Open drain Output(High Impedance)
DDRA
MICROCONTROLLER TRAINING
INTRODUCTION
CORE, MEMORY, CLOCK, RESET, INTERRUPT, POWER MODES ADDRESSING MODES III. PERIPHERALS
iii. PORTS CONVERTER TIMERS EEPROM COMMUNICATION
SOFTWARE TOOLS HARDWARE TOOLS TIPS TRICKS
ST62 BLOCK DIAGRAM
INTERRUPT CLOCK RESET AVSS ANALOG AVDD ANALOG
CONVERTER
CONTROL REGISTER
RESULT REGISTER
CORE CONTROL SIGNALS
CORE
ST62 CONVERTER
Conversion successive approximations resolution with Total accuracy Conversion time: Interrupt issued conversion powered down software reduce power consumption Example: conversion 0010 0000
Result: result 6-bit resolution:
0001 1110 0001 1111 0010 0001 0010 0010 0010 0000 0010 0001 0010 0010 0010 0011
CONVERTER
APPLICATION TIPS Accuracy decreases below clock frequency (e.g. 32kHz, accuracy 8BITS LSB) Never configure more than channel time analog input Leave least instruction between power start conversion (setting time) best results, wait mode enable ADC-interrupt, avoid toggling outputs Clear interrupt condition software prevent further interrupts (disable interrupt start conversion) minimum power consumption power down (PDS=0)
CONFIGURATION EXAMPLE Fill ADCR register order power peripheral, enable interrupt start conversion.
RESERVED
ADCR
RESERVED
EXAMPLE CONFIGURATION
CSEG 880h
ANALOG INPUT. Start Conversion. Output result PORTB reset: ddra, 00000000b dra, 00000001b ora, 00000001b ddrb, 0FFh orb, 000h drb, 000h adcr, adcr, 0B0h reti ior,10h loop: loop PORTA input with pullup Only input without pullup Only Analog input PORTB Output Opendrain change change Power enable interrupt conversion Quit mode after reset Enables interrupts.
wait interrupt
EXAMPLE
CONFIGURATION
INTERRUPT ROUTINE
adc_it: adcr, a,adr drb,a reti disable interrupt Conversion result Output Result PORTB
INTERRUPT VECTORS
CSEG 0ff0h
adc: timer: res: adc_it reti reset CSEG 0ffeh
CURRENT INJECTION ANALOG PINS
Care taken about negative current injection pins which have analog feature.
small leakage induced adjacent pins.
negative current injection performed close analog input selected decrease accuracy A/Dconverter. RECOMMENDATION: -1ma current injection maximum impedance recommended analog sources.
Application notes available: AN420 AN672
MICROCONTROLLER TRAINING
INTRODUCTION
CORE, MEMORY, CLOCK, RESET, INTERRUPT, POWER MODES ADDRESSING MODES III. PERIPHERALS
iii. PORTS CONVERTER TIMERS EEPROM COMMUNICATION
SOFTWARE TOOLS HARDWARE TOOLS TIPS TRICKS
ST62 WATCHDOG
Block diagram
RESET
RSFF
DB1.7 LOAD
OSCILLATOR CLOCK
WRITE RESET DATA
ST62 WATCHDOG
Provides controlled recovery from soft- hardware upset watchdog options:
Hardware activation: Maximum safety Software activation: watchdog needed (STOP mode requested)
Auto decrementing counter Generates reset when reaches zero
Software must reload watchdog avoid Reset
Watchdog period adjusted selecting reload value
From 3072 196608 clock cycles between successive reload 384µs 24.576ms with Quartz
ST62 WATCHDOG
USAGE watchdog should reloaded only point main program. account should reloaded interrupt routine subroutine loop. Therefore necessary calculate exactly timing subroutines interrupt routines. each external signal "time out"-condition must assigned. flags each subroutine they were finished correctly. Check flags before reloaded next time. they set, make reset!
ST62 WATCHDOG
PROPER Control watchdog status beginning program
reset generated otherwise
instructions:
DWDR, DWDR, 0FDh
unexpectedly activated YES, generate reset
When watchdog used (hardware software):
value beginning program
high security applications use:
0FEh DWDR 0FEh DWDR, 0FDh
Check WDtimer content
maximum 111111xx? NOT, generate reset
ST62 TIMER
BLOCK DIAGRAM
DATA
8-BIT COUNTER SELECT
STATUS/CONTROL REGISTER
TOUT DOUT
TIMER SYNCHRONIZATION LOGIC INTERRUPT LINE
LATCH
OSCILLATOR CLOCK
:-12
ST62 STANDARD TIMER
down counter programmable prescaler maskable interrupt line count External timer operating modes:
Input gated mode pulse width measurement Input event counter mode event counting Output mode time base generation
Timer stopped software
ST62 TIMER
WORKING PRINCIPLE PRESCALER Prescaler input
On-chip oscillator (F/12) External clock TIMER
Decrements rising edge input clock Outputs multiplexed bits clock) TSCR register determines division factor 128) TSCR activates prescaler when high Prescaler value (00h 7fh) loaded into register Multiplexer output decrements 8-bit counter
ST62 TIMER
WORKING PRINCIPLE TIMER COUNTER Decremented rising edge from prescaler read/written register TSCR count TSCR enables end-of-count INT3 Interrupt routine two-timer devices (ST624X) must poll both bits automatically continues count from 0ffh
Note: Interrupts must enabled also register
ST62 TIMER OPERATING MODES
Timer configuration made through TSCR register Clock input mode (TOUT=0,DOUT=0)
Prescaler decremented incoming rising edges from TIMER Allows event counting TIMER frequency must less than Fosc MHz)
Gated mode (TOUT=0,DOUT=1)
Prescaler decremented timer clock only whenTIMER high. Allows pulse width measurement
Output mode (TOUT=1,DOUT=data out)
TIMER connected DOUT latch Prescaler decremented timer clock When goes high, DOUT copied into TIMER pin, allowing external signal generation
ST62 TIMER
EXAMPLE
PSCR
PSCR (TSCR)
START TIMER (PSI='1')
TIMER OVERFLOW
ST62 TIMER
OVERFLOW TIMING FREQUENCY RANGE
Fosc
Frequency overflow
EXAMPLE:
384u 768u 1.536m 3.072m 6.14m 12.28m 24.57m 49.15m 2.604K 1.302K 651H 325H 162H 81.5H 40.7H 20.3H 768u 1.536m 3.072m 6.14m 12.28m 24.57m 49.15m 98.3m
10.416K 5.208K 2.604K 1.302K 651H 325.5H 162.76H 81.38H
TIMER EXAMPLE
Fill TSCR registers order configure timer that outputs when interrupt occurs after 10ms
TOUT DOUT
TSCR
EXAMPLE TIMER
CONFIGURATION CSEG 0880h
TIMER Output mode output '0', '1', '0', after certain time
reset: reti ior,10h tcr,count tscr,01101100b
Enables interrupts. (prescaler div) (count) Configure Start timer. Enable Timer interrupt, Output '0', count 0fah
loop: wait loop
Wait interrupt. Continue.
EXAMPLE TIMER
CONFIGURATION
TIMER INTERRUPT ROUTINE
timer_it: tcr,count tmz,tscr dout,tscr,lo_hi hi_lo: lo_hi: end_tim: dout,tscr end_tim dout,tscr reti Reload counter. Refresh Timer Interrupt (bit7). Check status dout (bit4). low, high next time. dout next time. dout next time.
INTERRUPT VECTORS
CSEG 0ff2h
timer: timer_it
AUTO-RELOAD TIMER
BLOCK DIAGRAM
PRESCALER
CAPT RELOAD
OVERFLOW
ARTIMin
COUNTER
ARTIMout COMPARE
ST62 AUTO-RELOAD TIMER
counter with programmable prescaler Maximum clock frequency: Fosc
Enables high frequency
Maskable interrupt line operating modes
Autoreload, Time basis Output compare Input capture, time measurement Output compare Input capture, reset, period measurement Output compare Reload external event,
used stop mode with external clock
Autoreload timer used wake
AUTO-RELOAD TIMER
AUTORELOAD MODE WITH Output when overflow occurs Output reset when compare Interrupts generated overflow and/or compare Clock source Fint, Fint/3, ARTIMin
Application note available: AN590
AUTO-RELOAD TIMER
EXAMPLE AUTORELOAD WITH
COUNT
EXAMPLE: need
Fpwm 12Khz Duty Fosc 4Mhz
COMP.
Clock Presc. 2Mhz
RELOAD
Resol 0.6%
Fosc/(Clock Prescaler div) Fpwm Fin/(255-RC) Resolution 1/(255-RC) must small possible small possible
Duty Cycle (CP-RC)/(255-RC)
AUTO-RELOAD TIMER
CAPTURE MODE WITH Input "captured" active edge ARTIMin Output when overflow occurs Output reset when compare Interrupts generated overflow/compare/capture Clock source Fint, Fint/3
Application note available: AN591
AUTO-RELOAD TIMER
EXAMPLE CAPTURE MODE WITH
COUNT COMP CAPT-1 CAPT-2 RELOAD
INPUT
PULSE WIDTH (255 CAPT1) (CAPT2 -RELOAD)
AUTO-RELOAD TIMER
CAPTURE/COMPARE/RESET MODE Input "captured" active edge ARTIMin Capture event resets counter prescaler Output overflow Output reset when compare Interrupts generated overflow/compare/capture Clock source Fint, Fint/3
AUTO-RELOAD TIMER
EXAMPLE CAPTURE/RESET MODE
COUNT CAPT-2 CAPT-1 COMP
INPUT PERIOD CAPT2
AUTO-RELOAD TIMER
EXTERNAL LOAD/COMPARE MODE Counter reloaded active edge ARTIMin Output overflow Output reset when compare Interrupts generated overflow and/or compare Clock source Fint, Fint/3 Application: external synchronization
Application note available: AN592
AUTO-RELOAD TIMER
EXAMPLE EXTERNAL LOAD MODE
COUNT COMP
RELOAD
INPUT
SHIFT PHASE
EXAMPLE: GENERATION
TIMIN input receives 15Khz digital signal Fosc 8Mhz) NEED: 15Khz signal with 19us delay duty cycle
TIMIN
211.255 211.255 161,
TIMOUT
PERIOD1 PHASE SHIFT DELAY PERIOD TVAR DUTY CYCLE =100% PERIOD 15Khz PERIOD 66.7us BEST RESOL. 66.7us 0.26us PRESC RATIO PERIOD 66.7us 0.375us DUTY CYCLE 19us TVAR
TVAR
PERIOD2 CONDITION: TVAR PERIOD
0.125 0.375us
AUTO-RELOAD TIMER
FEATURES High speed
Maximum resolution 125ns @8mhz clock
High degree accuracy
jitter
software overhead
Capture compare reset hardware
Variety interrupt sources
Overflow, capture, compare
ST62 8-BIT ARTIMER
OVERFLOW TIMING FREQUENCY RANGE
Fosc
Frequency overflow
(256 RLCP)
125n 250n 500n 500K 250K 125K 62.5K
192u 384u 768u 1.536m 3.072m 6.144m 12.288m 10.416K 5.208K 2.604K 1.302K 651H 325.5H 162.76H 81.38H
AUTO-RELOAD
TIMER EXAMPLE Configure ARTIMER auto-reload mode with PWM. Fpwm=100KHz Duty cycle= Fosc= 8MHz
TCLD PWMOE CPIE OVIE ARMC1 ARMC0
ARMC
ARSC1 ARRC ARCP
MICROCONTROLLER TRAINING
INTRODUCTION
CORE, MEMORY, CLOCK, RESET, INTERRUPT, POWER MODES ADDRESSING MODES III. PERIPHERALS
iii. PORTS CONVERTER TIMERS EEPROM COMMUNICATION
SOFTWARE TOOLS HARDWARE TOOLS TIPS TRICKS
ST62 EEPROM
write cycles guaranteed Internal charge pump
Provides required high voltage
Read access: user transparent
Behaviour like normal access
Write access: typical
erase required before writing
write access modes: Byte Parallel
Application note available: AN671
ST62 EEPROM
PARALLEL MODE Used write consecutive bytes
Same time writing byte
Parallel programming:
parallel mode enable EECTL Write data into (partially fully) parallel start EECTL start operation
ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0
38H-3FH 30H-37H 28H-2FH 20H-27H 18H-1FH 10H-17H 08H-0FH 00H-07H
EEPROM Parallel Write Structure
ST62 EEPROM
REGISTERS EECTL: EEPROM Control Register (Address EAh)
Unused E2OFF Reserved Reserved E2PAR1 E2PAR2 E2BUSY E2ENA Stand-by Enable Must Must Parallel Start Parallel Mode Enable EEPROM Busy EEPROM Enable
DRBR: Data Bank Register (Address
Unused Data Bank (page Unused EEPROM Bank (page EEPROM Bank (page Don't SET/RES instructions these registers, because some bits WRITE only
EEPROM CONFIGURATION EXAMPLE
Fill DRBR EECTL registers order select EEPROM page power EEPROM enable parallel writing.
DRBR4
DRBR1
DRBR0
DRBR
E2PA E2PA E2BU E2OFF
EECTL
EXAMPLE EEPROM
CONFIGURATION
EEPROM READ/WRITE ROUTINE
start: address eectl, drbr, Select eeprom address Turn eeprom (e2off '0') Select Page EEPROM
read: busyread:
eectl, busyread eectl, content eectl, 00000001b eectl, busyrd (x), eectl, endwrite eectl,
Check eeprom currently busy Read content selected address eeprom consumption mode value programmed Enable eeprom writing (e2ena '1') Check eeprom currently busy Load content check busy writing eeprom consumption mode
write1: busyrd: endwrite:
EXAMPLE EEPROM
CONFIGURATION
EEPROM PARALLEL WRITE ROUTINE
start: eectl, drbr, Turn eeprom (e2off '0') Select Page EEPROM
Pwrite: busyrd:
eectl, busyrd eectl, 00000101b 06h, 01h, 04h, eectl, 00001101b
Check eeprom currently busy Enable eeprom parallel writing e2ena e2par2 row0: write address row0: write address row0: write address Start eeprom Parallel writing (e2par1) check busy writing eeprom consumption mode
endwrite:
eectl, endwrite eectl,
MICROCONTROLLER TRAINING
INTRODUCTION
CORE, MEMORY, CLOCK, RESET, INTERRUPT, POWER MODES ADDRESSING MODES III. PERIPHERALS
iii. PORTS CONVERTER TIMERS EEPROM COMMUNICATION
SOFTWARE TOOLS HARDWARE TOOLS TIPS TRICKS
SERIAL COMMUNICATIONS INTRODUCTION
Serial communications used for:
Remote Diagnostics/Control e.g. RS232 Interfacing peripherals e.g. Microwire/I2C EEPROMs Interprocessor communications e.g. Synchronous exchanges with host
done?
Software standard port Serial Peripheral Interface ST624X Enhanced ST626X UART ST623X ST628X (UART1) Enhanced UART ST6218 ST6228 (UART2)
Application notes available: AN914, AN1016 AN1127
ST624X
BLOCK DIAGRAM
SERIAL INTERFACE
ST624X
Consists pins (shared with PB5, SCL: Shift Clock SIN: Serial Data Input SOUT: Serial Data Output Uses dedicated register 8-bit transmit/receive data Protocol largely user Some possible modes include:
Software S-BUS (SIN SOUT tied together) Standard Serial 500kHz
ST624X
USAGE
Initialization
port pins SCL, inputs, SOUT open drain output interrupt falling edge sensitive
Receive
Poll receive start flag any) Write SDSR enable interrupt After received clocks interrupt generated Data then read from SDSR (also disables interrupt) Check stop flags any)
ST624X
USAGE
Transmit
Generate transmit start flags any) Write data SDSR (thus enabling interrupt) Clock must sent SCL: either external clock (slave), generated software (master) After clocks interrupt generated Read SDSR (also disables interrupt) Generate stop flags any)
Fosc/13
ST626X
BLOCK DIAGRAM
CLK-DIVIDER
SPI-DIV REGISTER SPI-DIV REGISTER COUNTER Interrupt
FILTER
CLOCK
FILTER SOUT
SHIFT REGISTER
processor data
SERIAL INTERFACE
ST626X
Similar ST624X SPI, with enhanced features reduce software overhead Consists pins (shared with PC2, SIN: Serial Data Input SOUT: Serial Data Output SCL: Serial Data Clock input: slave mode; output pushpull:
master mode
Clock phase polarity programmed Number bits burst configured
UART
UART
BLOCK DIAGRAM
transmission only
UART
UART
BAUDRATE TABLE
Only available enhanced UART
UART
UART
Integrated clock divider provides common baud rates 38.400 baud with external oscillator) Half-Duplex operating mode Different character options possible:
tart tart tart tart
This peripheral available ST623x ST628XB
STOP (MSB) (LSB) START
UART
UART
Integrated clock divider provides common baud rates 76.800 baud with external oscillator) Half-Duplex operating mode frame option bytes selectable Different character options possible:
Frame
Start Start Start Start Start Start Start Data Data Data Data Data Data Data Parity Even Parity Software Parity Software Parity Parity Parity Software Parity Stop Stop Stop Stop Stop Stop Stop
Frame
This peripheral available ST6218 ST6228
UART
UART
SUMMARY
38400 76800 76800
frame type selectable thanks option bytes mode, allow RS232 communication, external inverter connected between RS232 driver. allow full speed reception, time selected baud rate must added between frames.
UART
UART
RS232 standard frame frame)
Start Stop
Data send: 10100101 push pull high Frame: start, data, stop Terminal config: baud rate, parity, stop.
frame (inverted frame)
Without external inverter
Start Stop
Data send: 101001011 (the ninth used stop bit) push pull inverter between RS232 driver added
With external inverter
Frame: start, data, stop Terminal config: baud rate, parity, stop.
UART
EXAMPLE UART
CONFIGURATION
UART RECEIVE ROUTINE USING STOP
start: ddrd, 00100000b (pc4) input pullup mode ord, 00100000b (pc5) output pushpull drd, 00100000b UARTCR, 00100000b enable receive interrupt loop: wait loop
UART INTERRUPT ROUTINE
it_uart: UARTCR UARTCR, end_it UARTDR end_it: reti stop receive request check data valid =>discard Stock received valid data other actions
SERIAL COMMUNICATIONS
SUMMARY Serial communications easy software:
Routine available Applications Library
ST624X:
Using
ST626X:
Using enhanced
ST623X ST628X:
Using UART
ST6218 ST6228:
Using Enhanced UART
ST62 DRIVERS
Wide range driving capabilities
SEGMENTS (ST624X) DOTS (ST628X)
Software programmable multiplex ratio
1/1, 1/2, 1/3, (ST624X) 1/8, 1/11, 1/16 (ST628X)
Direct connection display
external components required
kept stop mode
Clocked 32KHz oscillator typical consumption (Vdd Vlcd Volt)
Application note available AN678 32KHz oscillator featured particular device
ST628X SIGNALS
1/16 Multiplex, Bias
COM1
VLCD
COMMONS
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16
COM2
COM16
SEG1
SEG2
frame period clocks
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6
SEGMENTS
ST628X DRIVER
ADDRESSING
PAGE
addr addr addr addr addr
SEG3
SEG4
SEG1
PAGES
SEG2
SEG5
SEG6
ST62 DRIVER
ADDRESSING
COM1
COM2
COM3
COM4
display data ST6245 (But used general purpose RAM) display data ST6245/42 (But used general purpose RAM)
ST62 DRIVER
EXAMPLE
COM1 COM2
ADDRESS COM1 COM2
EXAMPLE
CONFIGURATION
DISPLAY ROUTINE
call fill clear LMCR, 10110110b select duty cycle com1, com2 display with fosc%256 (8Mhz) select fLCD 512hz (256hz duty 1/2) m_disp: 0e2h, 11110010b Write character (F2h) 0e8h, 01011101b Write character (5Dh) fill: write: 0f7h (x), 0dfh jrnz write start:
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