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TMS320C5x General Purpose Applications

Digital Signal Processing Solutions

TMS320C5x General Purpose Applications
Digital Signal Processing Solutions
Printed in U.S.A., July 1997 D415015-9761 revision
SPRU164
Literature Number: SPRU164 Manufacturing Part Number: D415015-9761 revision July 1997
Printed on Recycled Paper
Running Title-Attribute Reference
Preface
Read This First
About This Manual
How to Use This Manual
How to Use This Manual / Notational Conventions
If you are looking for information about: Multimedia applications PACK and UNPACK subroutines Part order information Processor initialization subroutine Servo control / disk drive applications Software applications Speech synthesis applications Telecommunications applications XDS510 emulator
Turn to: Chapter 4, Analog Interface Peripherals and Applications Chapter 2, Software Applications Appendix B, Development Support and Part Order Information Chapter 2, Software Applications Chapter 4, Analog Interface Peripherals and Applications Chapter 2, Software Applications Chapter 4, Analog Interface Peripherals and Applications Chapter 4, Analog Interface Peripherals and Applications Appendix A, Design Considerations for Using XDS510 Emulator
Notational Conventions
This document uses the following conventions:
Program listings and program examples are shown in a special typeface. Here is a segment of a program listing:
OUTPUT: LDP BLDD RET #6 #300, 20h data page 6 move data at address 300h to 320h
In syntax descriptions, the instruction is in a bold typeface and parameters are in an italic typeface. Portions of a syntax in bold must be entered as shown portions of a syntax in italics describe the type of information that you specify. Here is an example of an instruction syntax: label BLDD src, dst BLDD is the instruction and has two parameters, src and dst. When you use BLDD, the first parameter must be an actual data memory source address and dst a destination address. A comma and a space (optional) must separate the two addresses.
Notational Conventions / Related Documentation from Texas Instruments
The term OR is used in the assembly language instructions to denote a Boolean operation. The term or is used to indicate selection. Here is an example of an instruction with OR and or: lk OR (src)
This instruction ORs the value of lk with the contents of src. Then, it stores the result in src or dst, depending on the syntax of the instruction.
Related Documentation from Texas Instruments
Read This First
Related Documentation from Texas Instruments
Read This First
Related Documentation from Texas Instruments / Related Documents and Technical Articles
JTAG / MPSD Emulation Technical Reference (literature number SPDU079) provides the design requirements of the XDS510 emulator controller, discusses JTAG designs (based on the IEEE 1149.1 standard), and modular port scan device (MPSD) designs. TMS320 DSP Development Support Reference Guide (literature number SPRU011) describes the TMS320 family of digital signal processors and the tools that support these devices. Included are code-generation tools (compilers, assemblers, linkers, etc.) and system integration and debug tools (simulators, emulators, evaluation modules, etc.). Also covered are available documentation, seminars, the university program, and factory repair and exchange. TMS320 Third-Party Support Reference Guide (literature number SPRU052) alphabetically lists over 100 third parties that provide various products that serve the family of TMS320 digital signal processors. A myriad of products and applications are offered-software and hardware development tools, speech recognition, image processing, noise cancellation, modems, etc.
Related Documents and Technical Articles
If you are an assembly language programmer and would like more information about C or C expressions, you may find this book useful:
The C Programming Language (second edition, 1988), by Brian W. Kernighan and Dennis M. Ritchie, published by Prentice-Hall, Englewood Cliffs, New Jersey.
A wide variety of related documentation is available on DSPs. These references fall into one of the following application categories:
General-purpose DSP Graphics / imagery Speech / voice Control Multimedia Military Telecommunications Automotive Consumer Medical Development support
Related Documents and Technical Articles
In the following list, references appear in alphabetical order according to author. The documents contain beneficial information regarding designs, operations, and applications for signal-processing systems all of the documents provide additional references.
General-Purpose DSP:
1) Antoniou, A., Digital Filters: Analysis and Design, New York, NY: McGrawHill Company, Inc., 1979. 2) Brigham, E.O., The Fast Fourier Transform, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1974. 3) Burrus, C.S., and T.W. Parks, DFT / FFT and Convolution Algorithms, New York, NY: John Wiley and Sons, Inc., 1984. 4) Chassaing, R., Horning, D.W., "Digital Signal Processing with Fixed and Floating-Point Processors." CoED, USA, Volume 1, Number 1, pages 1-4, March 1991. 5) Defatta, David J., Joseph G. Lucas, and William S. Hodgkiss, Digital Signal Processing: A System Design Approach, New York: John Wiley, 1988. 6) Erskine, C., and S. Magar, "Architecture and Applications of a SecondGeneration Digital Signal Processor." Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing, USA, 1985. 7) Essig, D., C. Erskine, E. Caudel, and S. Magar, "A Second-Generation Digital Signal Processor." IEEE Journal of Solid-State Circuits, USA, Volume SC-21, Number 1, pages 86-91, February 1986. 8) Frantz, G., K. Lin, J. Reimer, and J. Bradley, "The Texas Instruments TMS320C25 Digital Signal Microcomputer." IEEE Microelectronics, USA, Volume 6, Number 6, pages 10-28, December 1986. 9) Gass, W., R. Tarrant, T. Richard, B. Pawate, M. Gammel, P. Rajasekaran, R. Wiggins, and C. Covington, "Multiple Digital Signal Processor Environment for Intelligent Signal Processing." Proceedings of the IEEE, USA, Volume 75, Number 9, pages 1246-1259, September 1987. 10) Gold, Bernard, and C.M. Rader, Digital Processing of Signals, New York, NY: McGraw-Hill Company, Inc., 1969. 11) Hamming, R.W., Digital Filters, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1977. 12) IEEE ASSP DSP Committee (Editor), Programs for Digital Signal Processing, New York, NY: IEEE Press, 1979.
Read This First
Related Documents and Technical Articles
13) Jackson, Leland B., Digital Filters and Signal Processing, Hingham, MA: Kluwer Academic Publishers, 1986. 14) Jones, D.L., and T.W. Parks, A Digital Signal Processing Laboratory Using the TMS32010, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1987. 15) Lim, Jae, and Alan V. Oppenheim, Advanced Topics in Signal Processing, Englewood Cliffs, NJ: Prentice- Hall, Inc., 1988. 16) Lin, K., G. Frantz, and R. Simar, Jr., "The TMS320 Family of Digital Signal Processors." Proceedings of the IEEE, USA, Volume 75, Number 9, pages 1143-1159, September 1987. 17) Lovrich, A., Reimer, J., "An Advanced Audio Signal Processor." Digest of Technical Papers for 1991 International Conference on Consumer Electronics, June 1991. 18) Magar, S., D. Essig, E. Caudel, S. Marshall and R. Peters, "An NMOS Digital Signal Processor with Multiprocessing Capability." Digest of IEEE International Solid-State Circuits Conference, USA, February 1985. 19) Morris, Robert L., Digital Signal Processing Software, Ottawa, Canada: Carleton University, 1983. 20) Oppenheim, Alan V. (Editor), Applications of Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1978. 21) Oppenheim, Alan V., and R.W. Schafer, Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1975 and 1988. 22) Oppenheim, A.V., A.N. Willsky, and I.T. Young, Signals and Systems, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1983. 23) Papamichalis, P.E., and C.S. Burrus, "Conversion of Digit-Reversed to Bit-Reversed Order in FFT Algorithms." Proceedings of ICASSP 89, USA, pages 984-987, May 1989. 24) Papamichalis, P., and R. Simar, Jr., "The TMS320C30 Floating-Point Digital Signal Processor." IEEE Micro Magazine, USA, pages 13-29, December 1988. 25) Parks, T.W., and C.S. Burrus, Digital Filter Design, New York, NY: John Wiley and Sons, Inc., 1987. 26) Peterson, C., Zervakis, M., Shehadeh, N., "Adaptive Filter Design and Implementation Using the TMS320C25 Microprocessor." Computers in Education Journal, USA, Volume 3, Number 3, pages 12-16, July- September 1993.
Related Documents and Technical Articles
27) Prado, J., and R. Alcantara, "A Fast Square-Rooting Algorithm Using a Digital Signal Processor." Proceedings of IEEE, USA, Volume 75, Number 2, pages 262-264, February 1987. 28) Rabiner, L.R. and B. Gold, Theory and Applications of Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1975. 29) Simar, Jr., R., and A. Davis, "The Application of High-Level Languages to Single-Chip Digital Signal Processors." Proceedings of ICASSP 88, USA, Volume D, page 1678, April 1988. 30) Simar, Jr., R., T. Leigh, P. Koeppen, J. Leach, J. Potts, and D. Blalock, "A 40 MFLOPS Digital Signal Processor: the First Supercomputer on a Chip." Proceedings of ICASSP 87, USA, Catalog Number 87CH2396 -0, Volume 1, pages 535-538, April 1987. 31) Simar, Jr., R., and J. Reimer, "The TMS320C25: a 100 ns CMOS VLSI Digital Signal Processor." 1986 Workshop on Applications of Signal Processing to Audio and Acoustics, September 1986. 32) Texas Instruments, Digital Signal Processing Applications with the TMS320 Family, 1986 Englewood Cliffs, NJ: Prentice-Hall, Inc., 1987. 33) Treichler, J.R., C.R. Johnson, Jr., and M.G. Larimore, A Practical Guide to Adaptive Filter Design, New York, NY: John Wiley and Sons, Inc., 1987.
Graphics / Imagery:
1) Andrews, H.C., and B.R. Hunt, Digital Image Restoration, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1977. 2) Gonzales, Rafael C., and Paul Wintz, Digital Image Processing, Reading, MA: Addison-Wesley Publishing Company, Inc., 1977. 3) Papamichalis, P.E., "FFT Implementation on the TMS320C30." Proceedings of ICASSP 88, USA, Volume D, page 1399, April 1988. 4) Pratt, William K., Digital Image Processing, New York, NY: John Wiley and Sons, 1978. 5) Reimer, J., and A. Lovrich, "Graphics with the TMS32020." WESCON / 85 Conference Record, USA, 1985.
Speech / Voice:
Read This First
Related Documents and Technical Articles
Control:
Related Documents and Technical Articles
7) Hanselman, H., "LQG-Control of a Highly Resonant Disc Drive Head Positioning Actuator." IEEE Transactions on Industrial Electronics, USA, Volume 35, Number 1, pages 100-104, February 1988. 8) Jacquot, R., Modern Digital Control Systems, New York, NY: Marcel Dekker, Inc., 1981. 9) Katz, P., Digital Control Using Microprocessors, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1981. 10) Kuo, B.C., Digital Control Systems, New York, NY: Holt, Reinholt, and Winston, Inc., 1980. 11) Lovrich, A., G. Troullinos, and R. Chirayil, "An All-Digital Automatic Gain Control." Proceedings of ICASSP 88, USA, Volume D, page 1734, April 1988. 12) Matsui, N. and M. Shigyo, "Brushless DC Motor Control Without Position and Speed Sensors." IEEE Transactions on Industry Applications, USA, Volume 28, Number 1, Part 1, pages 120-127, January-February 1992. 13) Meshkat, S., and I. Ahmed, "Using DSPs in AC Induction Motor Drives." Control Engineering, February 1988. 14) Panahi, I. and R. Restle, "DSPs Redefine Motion Control." Motion Control Magazine, December 1993. 15) Phillips, C., and H. Nagle, Digital Control System Analysis and Design, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1984.
Multimedia:
1) Reimer, J., "DSP-Based Multimedia Solutions Lead Way Enhancing Audio Compression Performance." Dr. Dobbs Journal, December 1993. 2) Reimer, J., G. Benbassat, and W. Bonneau Jr., "Application Processors: Making PC Multimedia Happen." Silicon Valley PC Design Conference, July 1991.
Military:
1) Papamichalis, P., and J. Reimer, "Implementation of the Data Encryption Standard Using the TMS32010." Digital Signal Processing Applications, 1986.
Read This First
Related Documents and Technical Articles
Telecommunications:
Related Documents and Technical Articles
Automotive:
Consumer:
1) Frantz, G.A., J.B. Reimer, and R.A. Wotiz, "Julie, The Application of DSP to a Product." Speech Tech Magazine, USA, September 1988. 2) Reimer, J.B., and G.A. Frantz, "Customization of a DSP Integrated Circuit for a Customer Product." Transactions on Consumer Electronics, USA, August 1988. 3) Reimer, J.B., P.E. Nixon, E.B. Boles, and G.A. Frantz, "Audio Customization of a DSP IC." Digest of Technical Papers for 1988 International Conference on Consumer Electronics, June 8-10 1988.
Medical:
1) Knapp and Townshend, "A Real-Time Digital Signal Processing System for an Auditory Prosthesis." Proceedings of ICASSP 88, USA, Volume A, page 2493, April 1988. 2) Morris, L.R., and P.B. Barszczewski, "Design and Evolution of a PocketSized DSP Speech Processing System for a Cochlear Implant and Other Hearing Prosthesis Applications." Proceedings of ICASSP 88, USA, Volume A, page 2516, April 1988.
Development Support:
1) Mersereau, R., R. Schafer, T. Barnwell, and D. Smith, "A Digital Filter Design Package for PCs and TMS320." MIDCON / 84 Electronic Show and Convention, USA, 1984. 2) Simar, Jr., R., and A. Davis, "The Application of High-Level Languages to Single-Chip Digital Signal Processors." Proceedings of ICASSP 88, USA, Volume 3, pages 1678-1681, April 1988.
Read This First
Trademarks
DuPont Electronics is a registered trademark of E.I. DuPont Corporation. HP-UX is a trademark of Hewlett-Packard Company. IBM, OS / 2, and PC-DOS are trademarks of International Business Machines Corporation. MS and Windows are registered trademarks of Microsoft Corporation. Solaris and SunOS are trademarks of Sun Microsystems, Inc. SPARC is a trademark of SPARC International, Inc., but licensed exclusively to Sun Microsystems, Inc. 320 Hotline On-line, TI, XDS510, XDS510PP, XDS510WS, and XDS511 are trademarks of Texas Instruments Incorporated. VAX and VMS are trademarks of Digital Equipment Corp.
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Read This First
xviii
Running Title-Attribute Reference
Contents
External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Describes the external interface to program memory, local data memory, and I / O space. Also described is the direct memory access (DMA) in a portable computer configuration. 3.1 3.2 3.3 3.4 3.5 External Interface to Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interface to Local Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interface to Global Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interface to I / O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Memory Access (DMA) in a Personal Computer Configuration . . . . . . . . . . . . . . 3-2 3-4 3-6 3-6 3-7
Contents
Running Title-Attribute Reference
Figures
1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 3-1 3-2 3-3 3-4 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 A-1 A-2 A-3 A-4 A-5 A-6 A-7 B-1 B-2
Running Title-Attribute Reference
Tables
Contents
xxiii
Running Title-Attribute Reference
Examples
Chapter 1
Introduction
Device TMS320C50 / LC50 TMS320C51 / LC51 TMS320C52 / LC52 TMS320C53 / LC53 TMS320C53S / LC53S TMS320LC56 TMS320C57S TMS320LC57 On-Chip RAM 10K words 2K words 1K words 4K words 4K words 7K words 7K words 7K words On-Chip ROM 2K words 8K words 4K words 16K words 16K words 32K words 2K words 32K words
Topic
Introduction
TMS320 Family Overview
1.1 TMS320 Family Overview
The TMS320 family consists of two types of single-chip DSPs: 16-bit fixedpoint and 32-bit floating-point. These DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. Combining these two qualities, the TMS320 processors are inexpensive alternatives to custom-fabricated very large scale integration (VLSI) and multichip bit-slice processors. Refer to subsection 1.1.2, TMS320 Typical Applications, for a detailed list of applications of the TMS320 family. The following characteristics make this family the ideal choice for a wide range of processing applications:
Very flexible instruction set Inherent operational flexibility High-speed performance Innovative, parallel architectural design Cost-effectiveness
History, Development, and Advantages of TMS320 DSPs
TMS320 Family Overview
Figure 1-1. Evolution of the TMS320 Family
Introduction
TMS320 Family Overview
TMS320 Typical Applications
The TMS320 family of DSPs offers better, more adaptable approaches to traditional signal-processing problems, such as vocoding, filtering, and error coding. Furthermore, the TMS320 family supports complex applications that often require multiple operations to be performed simultaneously. Figure 1-2 shows many of the typical applications of the TMS320 family.
Figure 1-2. Typical Applications for the TMS320 Family
Automotive Adaptive ride control Antiskid brakes Cellular telephones Digital radios Engine control Global positioning Navigation Vibration analysis Voice commands General-Purpose Adaptive filtering Convolution Correlation Digital filtering Fast Fourier transforms Hilbert transforms Waveform generation Windowing Instrumentation Digital filtering Function generation Pattern matching Phase-locked loops Seismic processing Spectrum analysis Transient analysis Consumer Digital radios / TVs Educational toys Music synthesizers Power tools Radar detectors Solid-state answering machines Control Disk drive control Engine control Laser printer control Motor control Robotics control Servo control
Graphics / Imaging 3-D rotation Animation / digital map Homomorphic processing Pattern recognition Image enhancement Image compression / transmission Robot vision Workstations Medical Diagnostic equipment Fetal monitoring Hearing aids Patient monitoring Prosthetics Ultrasound equipment Telecommunications
Industrial Numeric control Power-line monitoring Robotics Security access
Military Image processing Missile guidance Navigation Radar processing Radio frequency modems Secure communications Sonar processing Voice / Speech Speech enhancement Speech recognition Speech synthesis Speaker verification Speech vocoding Voice mail Text-to-speech
1200- to 19200-bps modems Adaptive equalizers ADPCM transcoders Cellular telephones Channel multiplexing Data encryption Digital PBXs Digital speech interpolation (DSI) Personal digital assistants (PDA)
DTMF encoding / decoding Echo cancellation Fax Line repeaters Speaker phones Spread spectrum communications Video conferencing X.25 Packet Switching Personal communications systems (PCS)
TMS320C5x Overview
1.2 TMS320C5x Overview
Introduction
TMS320C5x Overview
Package Type 132 pin BQFPd 132 pin BQFPd
50 / 35 / 25 / 20 132 pin BQFPd 50 / 35 / 25 / 20 100 pin TQFPk 50 / 35 / 25 50 / 35 / 25 132 pin BQFPd 100 pin TQFPk
50 / 35 / 25 / 20 100 pin QFPh 50 / 35 / 25 / 20 100 pin TQFPk 50 / 35 / 25 50 / 35 / 25 50 / 35 / 25 50 / 35 / 25 50 / 35 / 25 50 / 35 / 25 50 / 35 / 25 50 / 35 / 25 50 / 35 / 25 100 pin QFPh 100 pin TQFPk 132 pin BQFPd 100 pin TQFPk 132 pin BQFPd 100 pin TQFPk 100 pin TQFPk 144 pin TQFPD 128 pinTQFPk
TMS320C5x Key Features
1.3 TMS320C5x Key Features
3.3-V and 5-V static CMOS technology with two power-down modes Power consumption control with IDLE1 and IDLE2 instructions for power-down modes
Introduction
TMS320C5x Key Features
Central processing unit (CPU)
Central arithmetic logic unit (CALU) consisting of the following:
16-bit parallel logic unit (PLU) Dedicated auxiliary register arithmetic unit (ARAU) for indirect addressing Eight auxiliary registers
Program control 8-level hardware stack 4-deep pipelined operation for delayed branch, call, and return instructions Eleven shadow registers for storing strategic CPU-controlled registers during an interrupt service routine (ISR) Extended hold operation for concurrent external direct memory access (DMA) of external memory or on-chip RAM Two indirectly addressed circular buffers for circular addressing
Instruction set Single-cycle multiply / accumulate instructions Single-instruction repeat and block repeat operations Block memory move instructions for better program and data management Memory-mapped register load and store instructions Conditional branch and call instructions Delayed execution of branch and call instructions Fast return from interrupt instructions Index-addressing mode Bit-reversed index-addressing mode for radix-2 fast Fourier transforms (FFTs)
TMS320C5x Key Features
On-chip peripherals
Introduction
Chapter 2
Software Applications
Topic
Software Applications
Processor Initialization
Memory-mapped core processor and peripheral control registers Interrupt structure (IN bit) Mode control (OVM, SXM, PM, AVIS, NDX, TRM bits) Memory control (RAM, OVLY, CNF bits) Auxiliary registers and the auxiliary register pointer (ARP) Data memory page pointer (DP)
Internal single-access RAM configured as program memory Interrupt vector table loaded in internal program memory Interrupt vector table pointer (IPTR) Internal dual-access RAM blocks filled with 0s Interrupts enabled
Processor Initialization
Example 2-1. Initialization of TMS320C5x
Software Applications
Processor Initialization
Example 2-1. Initialization of TMS320C5x (Continued)
Initialize B1 block
Globally enable interrupts Return
Interrupts
Accumulator (ACC) Accumulator buffer (ACCB) Auxiliary register compare register (ARCR) Index register (INDX) Processor mode status register (PMST) Product register (PREG) Status register 0 (ST0) Status register 1 (ST1) Temporary register 0 (TREG0) for multiplier Temporary register 1 (TREG1) for shift count Temporary register 2 (TREG2) for bit test
When the interrupt trap is taken, the contents of all these registers are pushed onto a 1-level stack, with the exception of the the IN bit in ST0 and the XF bit in ST1. On an interrupt, the IN bit is always set to disable interrupts. The values in the registers at the time of the interrupt trap are still available to the ISR but are also protected in the shadow registers. The shadow registers are copied back to the CPU registers when the RETI or RETE instruction is executed. This function allows the CPU to be used for the ISR without requiring the overhead of context save and restore in the ISR.
Software Applications
Interrupts
Example 2-2. Use of INTR Instruction
Temporary storage.
This section will be loaded in program memory address 0h. Skip the next 38 locations to interrupt #20 :Interrupt #20 - begins processing here
Interrupts
Example 2-2. Use of INTR Instruction (Continued)
Software Applications
Software Stack
Example 2-3. Software Stack Operation
Logical and Arithmetic Operations
The following subsections provide examples of logical and arithmetic operations.
Parallel Logic Unit (PLU)
Software Applications
Logical and Arithmetic Operations
Example 2-4. Using PLU to Do Unpacking
Number of packed bits in the word Input word Output buffer. Each word will have one bit in LSB location.
UNPACK
Logical and Arithmetic Operations
Example 2-5. Using PLU to Do Packing
Store the result Return back
Software Applications
Logical and Arithmetic Operations
Multiconditional Instructions
Table 2-1. Conditions for Branch, Call, and Return Instructions
You can combine conditions from four groups (Table 2-2). Up to four conditions can be selected however, each of these conditions must be from different groups. You cannot have two conditions from the same group. For example, you can test EQ and TC at the same time but not NEQ and GEQ. For example:
Logical and Arithmetic Operations
Table 2-2. Groups for Multiconditional Instructions
Group 1 EQ NEQ GT LT GEQ LEQ Group 2 OV NOV Group 3 C NC Group 4 TC NTC BIO
Testing the status of the TC flag is mutually exclusive to testing the BIO pin. The code in Example 2-6 simultaneously tests the carry (C) flag and the sign bit of the accumulator to locate a zero bit (beginning from MSB) in a 64-bit word, consisting of ACC and ACCB with ACC having the higher part. This 64-bit word could be the serial port output where the first 0 indicates the start bit.
Example 2-6. Using Multiple Conditions With BCND Instruction
Software Applications
Logical and Arithmetic Operations
Search Algorithm Using CRGT
Example 2-7 on page 2-15 shows how the CRGT and RPTB instructions find the maximum value and its location by searching through a block of data. Loop overhead is minimized by using the block-repeat function. The accumulator is initialized with the minimum possible value (8000h) before the main search loop is entered. To find the minimum value, CRGT instruction may be replaced by CRLT, and the accumulator is loaded with the maximum possible value (7FFFh) instead of the smallest. The rest of the code remains the same.
Matrix Multiplication Using Nested Loops
Logical and Arithmetic Operations
Example 2-7. Using CRGT and CRLT Instructions
Software Applications
Logical and Arithmetic Operations
Example 2-8. Using Nested Loops
Circular Buffers
Software Applications
Circular Buffers
Example 2-9. Use of Circular Addressing
Circular Buffers
Example 2-10. Modulo-256 Addressing
START .set LDP LACL SAMM . . . MAR APL OPL . . . 04000h #0 #0FFh DBMR Start address of the buffer
0+ AR7 #START, AR7
Increment AR7 by some amount Extract lower 8 bits Add the start address
Software Applications
Single-Instruction Repeat (RPT) Loops
Example 2-11. Memory-to-Memory Block Moves Using RPT with BLDD
Example 2-12. Memory-to-Memory Block Moves Using RPT with BLDP
Example 2-13. Memory-to-Memory Block Moves Using RPT with BLPD
Software Applications
Single-Instruction Repeat (RPT) Loops
Example 2-14. Memory-to-Memory Block Moves Using RPT with TBLR
This routine uses the TBLR instruction to move external program memory to internal data memory. This differs from the BLPD instruction in that the accumulator contains the source program memory address from which to transfer. This allows for a calculated, rather than predetermined, location in program memory to be specified. The calling routine must contain the source program memory address in the accumulator.
TABLER: MAR LAR RPT TBLR RET
, AR3 AR3, #300h #127 +
Example 2-15. Memory-to-Memory Block Moves Using RPT with TBLW
Example 2-16. Memory-to-Memory Block Moves Using RPT with SMMR
Single-Instruction Repeat (RPT) Loops
Example 2-17. Memory-to-Memory Block Moves Using RPT with LMMR
Software Applications
Subroutines
Example 2-18. Square Root Computation Using XC Instruction
Subroutines
Example 2-18. Square Root Computation Using XC Instruction (Continued)
NUMBER .set TEMPR .set GUESS .set .text SQRT MAR LACC LDP SETC SPM SACL LACL SACB SPLK SPLK LACC SUB BCNDD SPLK LACC SACL SACL SPLK LOOP RPTB SQRA LACC SPAC NOP XC LACC SACB LACC SACH ADDB SACH ENDLP LACB RETD LST LST 62h 63h 64h , AR0 #0 SXM 1 NUMBER #0 #11, BRCR #800h, GUESS NUMBER #200h LOOP, LT #800h, TEMPR #4000h GUESS TEMPR #14, BRCR ENDLP-1 TEMPR NUMBER, 16
2, GT TEMPR, 16 GUESS, 15 GUESS TEMPR
#1, ST1 #0, ST0
Restore context
Software Applications
Extended-Precision Arithmetic
Addition
Extended-Precision Arithmetic
Figure 2-1. 32-Bit Addition
Software Applications
Extended-Precision Arithmetic
Example 2-19. 64-Bit Addition
Extended-Precision Arithmetic
Subtraction