User's Guide 1997 Digital Signal Processing Solutions P
|
|
|
Top Searches for this datasheet
TMS320C5x General Purpose Applications
User's Guide
1997
Digital Signal Processing Solutions
Printed U.S.A., July 1997 D415015-9761 revision
SPRU164
TMS320C5x General-Purpose Applications User's Guide
Literature Number: SPRU164 Manufacturing Part Number: D415015-9761 revision July 1997
Printed Recycled Paper
Running Title-Attribute Reference
IMPORTANT NOTICE Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used.
Copyright 1997, Texas Instruments Incorporated
Running Title-Attribute Reference
Preface
Read This First
About This Manual
This user's guide serves reference book developing hardware and/or software applications TMS320C5x digital signal processors (DSPs).
This Manual
following table summarizes 'C5x information contained this user's guide:
looking information about: Application reports Designer's notebook pages features External memory interfacing Extended-precision arithmetic subroutines Fast Fourier transform subroutine Floating-point arithmetic subroutines Hardware applications Infinite impulse response (IIR) filter subroutines Memory-to-memory block move subroutines Modem applications Turn Appendix Application Reports Designer's Notebook Pages Appendix Application Reports Designer's Notebook Pages Chapter Introduction Chapter External Memory interface Chapter Software Applications Chapter Software Applications Chapter Software Applications Chapter Analog Interface Peripherals Applications Chapter Software Applications Chapter Software Applications Chapter Software Applications Chapter Analog Interface Peripherals Applications
This Manual Notational Conventions
looking information about: Multimedia applications PACK UNPACK subroutines Part order information Processor initialization subroutine Servo control/disk drive applications Software applications Speech synthesis applications Telecommunications applications XDS510 emulator
Turn Chapter Analog Interface Peripherals Applications Chapter Software Applications Appendix Development Support Part Order Information Chapter Software Applications Chapter Analog Interface Peripherals Applications Chapter Software Applications Chapter Analog Interface Peripherals Applications Chapter Analog Interface Peripherals Applications Appendix Design Considerations Using XDS510 Emulator
Notational Conventions
This document uses following conventions:
Program listings program examples shown special typeface. Here segment program listing:
OUTPUT: BLDD #300, ;data page ;move data address 300h 320h
syntax descriptions, instruction bold typeface parameters italic typeface. Portions syntax bold must entered shown; portions syntax italics describe type information that specify. Here example instruction syntax: [label] BLDD src, BLDD instruction parameters, dst. When BLDD, first parameter must actual data memory source address destination address. comma space (optional) must separate addresses.
Notational Conventions Related Documentation from Texas Instruments
term used assembly language instructions denote Boolean operation. term used indicate selection. Here example instruction with (src)
dst]
This instruction value with contents src. Then, stores result dst, depending syntax instruction.
Square brackets, identify optional parameter. optional parameter, specify information within brackets; type brackets themselves. example above, instead typing [label], specify name label. When specify more than optional parameter from list, separate them with comma space. Braces, indicate list. Unless list enclosed square brackets, must choose item from list; type braces themselves. Here's example list that provides seven choices: ind: *BRO+ *BRO-}
term 'C5x refers TMS320C5x.
Related Documentation from Texas Instruments
following books describe 'C5x related support tools. obtain copy these documents, call Texas Instruments Literature Response Center (800) 477-8924. When ordering, please identify book title literature number.
TMS320C5x User's Guide (literature number SPRU056) describes 'C5x 16-bit, fixed-point, general-purpose digital signal processors. Covered architecture, internal register structure, instruction set, pipeline, specifications, DMA, ports, on-chip peripherals. TMS320C5x, TMS320LC5x Digital Signal Processors (literature number SPRS030) data sheet contains electrical timing specifications these devices, well signal descriptions pinouts available packages. Calculation TMS320C5x Power Dissipation (literature number SPRA030). This application report describes techniques analyzing system device conditions determine operating current levels. From this analysis, power dissipation device determined. Knowledge power dissipation can, turn, used determine thermal management requirements device.
Read This First
Related Documentation from Texas Instruments
Telecommunications Applications With TMS320C5x DSPs (literature number SPRA033). This application book collection applications related field telecommunications implemented TMS320C5x. Topics covered digital cellular systems, speech synthesis, error-correction coding, baseband modulation demodulation, equalization channel estimation, speech character recognition algorithms, system design considerations. PCMCIA TMS320 MediaCard (literature number SPRA052). This application report describes MediaCard, version 1.0, operates, MediaCard card sound fax/ modem applications, uses TMS320 on-board stereo codec. TMS320C5x Internal Oscillator With External Crystals Ceramic Resonators (literature number SPRA054). This application report provides information about crystal ceramic resonators, their frequency characteristics, general background oscillators, type oscillator circuit used TMS320C5x. Covered design aspects 'C5x oscillator including appropriate configuration external components, measured parameters on-board portion circuitry, oscillator with overtone crystals, general design considerations choosing external components oscillator. This report presents some design solutions common frequencies. Enhanced Control Alternating Current Motor Using Fuzzy Logic TMS320 Digital Signal Processor (literature number SPRA057). This application report describes digital signal processor with specialized fuzzy logic software kernel provides required computing performance control system design while maintaining cost. This report presents fuzzy logic design that enhances system's ability handle abrupt momentum changes motor controller software technology used implement fuzzy logic design. Improving 32-Channel DTMF Decoders Using TMS320C5x (literature number SPRA085). This application report discusses improvements that make multichannel dual-tone multifrequency (DTMF) decoder using TMS320C5x. systems multiple DTMF chips encode decode tones. systems also perform other functions, such voice compression expansion voice mail. using 'C5x, increase performance flexibility systems, while decreasing cost systems.
Related Documentation from Texas Instruments
Digital Signal Processing Applications with TMS320 Family, Volumes (literature numbers SPRA012, SPRA016, SPRA017) Volumes cover applications using 'C10 'C20 families fixed-point processors. Volume documents applications using both fixed-point processors, well 'C30 floating-point processor. TMS320C1x/C2x/C2xx/C5x Code Generation Tools Getting Started Guide (literature number SPRU121) describes install TMS320C1x, TMS320C2x, TMS320C2xx, TMS320C5x assembly language tools compiler 'C1x, 'C2x, 'C2xx, 'C5x devices. installation MS-DOSTM, OS/2TM, SunOSTM, Solarissystems covered. TMS320C1x/C2x/C2xx/C5x Assembly Language Tools User's Guide (literature number SPRU018) describes assembly language tools (assembler, linker, other tools used develop assembly language code), assembler directives, macros, common object file format, symbolic debugging directives 'C1x, 'C2x, 'C2xx, 'C5x generations devices. TMS320C2x/C2xx/C5x Optimizing Compiler User's Guide (literature number SPRU024) describes 'C2x/C2xx/C5x compiler. This compiler accepts ANSI standard source code produces TMS320 assembly language source code 'C2x, 'C2xx, 'C5x generations devices. TMS320C5x Source Debugger User's Guide (literature number SPRU055) tells invoke 'C5x emulator, evaluation module, simulator versions source debugger interface. This book discusses various aspects debugger interface, including window management, command entry, code execution, data management, breakpoints. also includes tutorial that introduces basic debugger functionality. TMS320C5x Evaluation Module Technical Reference (literature number SPRU087) describes 'C5x evaluation module, features, design details external interfaces. TMS320C5x Evaluation Module Getting Started Guide (literature number SPRU126) tells install MS-DOSTM, PC-DOSTM, Windowsversions 'C5x evaluation module. XDS51x Emulator Installation Guide (literature number SPNU070) describes installation XDS510TM, XDS510PPTM, XDS510WSemulator controllers. installation XDS511emulator also described.
Read This First
Related Documentation from Texas Instruments Related Documents Technical Articles
JTAG/MPSD Emulation Technical Reference (literature number SPDU079) provides design requirements XDS510emulator controller, discusses JTAG designs (based IEEE 1149.1 standard), modular port scan device (MPSD) designs. TMS320 Development Support Reference Guide (literature number SPRU011) describes TMS320 family digital signal processors tools that support these devices. Included code-generation tools (compilers, assemblers, linkers, etc.) system integration debug tools (simulators, emulators, evaluation modules, etc.). Also covered available documentation, seminars, university program, factory repair exchange. TMS320 Third-Party Support Reference Guide (literature number SPRU052) alphabetically lists over third parties that provide various products that serve family TMS320 digital signal processors. myriad products applications offered-software hardware development tools, speech recognition, image processing, noise cancellation, modems, etc.
Related Documents Technical Articles
assembly language programmer would like more information about expressions, find this book useful:
Programming Language (second edition, 1988), Brian Kernighan Dennis Ritchie, published Prentice-Hall, Englewood Cliffs, Jersey.
wide variety related documentation available DSPs. These references fall into following application categories:
viii
General-purpose Graphics/imagery Speech/voice Control Multimedia Military Telecommunications Automotive Consumer Medical Development support
Related Documents Technical Articles
following list, references appear alphabetical order according author. documents contain beneficial information regarding designs, operations, applications signal-processing systems; documents provide additional references.
General-Purpose DSP:
Antoniou, Digital Filters: Analysis Design, York, McGrawHill Company, Inc., 1979. Brigham, E.O., Fast Fourier Transform, Englewood Cliffs, Prentice-Hall, Inc., 1974. Burrus, C.S., T.W. Parks, DFT/FFT Convolution Algorithms, York, John Wiley Sons, Inc., 1984. Chassaing, Horning, D.W., "Digital Signal Processing with Fixed Floating-Point Processors." CoED, USA, Volume Number pages 1-4, March 1991. Defatta, David Joseph Lucas, William Hodgkiss, Digital Signal Processing: System Design Approach, York: John Wiley, 1988. Erskine, Magar, "Architecture Applications SecondGeneration Digital Signal Processor." Proceedings IEEE International Conference Acoustics, Speech, Signal Processing, USA, 1985. Essig, Erskine, Caudel, Magar, Second-Generation Digital Signal Processor." IEEE Journal Solid-State Circuits, USA, Volume SC-21, Number pages 86-91, February 1986. Frantz, Lin, Reimer, Bradley, "The Texas Instruments TMS320C25 Digital Signal Microcomputer." IEEE Microelectronics, USA, Volume Number pages 10-28, December 1986. Gass, Tarrant, Richard, Pawate, Gammel, Rajasekaran, Wiggins, Covington, "Multiple Digital Signal Processor Environment Intelligent Signal Processing." Proceedings IEEE, USA, Volume Number pages 1246-1259, September 1987. Gold, Bernard, C.M. Rader, Digital Processing Signals, York, McGraw-Hill Company, Inc., 1969. Hamming, R.W., Digital Filters, Englewood Cliffs, Prentice-Hall, Inc., 1977. IEEE ASSP Committee (Editor), Programs Digital Signal Processing, York, IEEE Press, 1979.
Read This First
Related Documents Technical Articles
Jackson, Leland Digital Filters Signal Processing, Hingham, Kluwer Academic Publishers, 1986. Jones, D.L., T.W. Parks, Digital Signal Processing Laboratory Using TMS32010, Englewood Cliffs, Prentice-Hall, Inc., 1987. Lim, Jae, Alan Oppenheim, Advanced Topics Signal Processing, Englewood Cliffs, Prentice- Hall, Inc., 1988. Lin, Frantz, Simar, Jr., "The TMS320 Family Digital Signal Processors." Proceedings IEEE, USA, Volume Number pages 1143-1159, September 1987. Lovrich, Reimer, Advanced Audio Signal Processor." Digest Technical Papers 1991 International Conference Consumer Electronics, June 1991. Magar, Essig, Caudel, Marshall Peters, NMOS Digital Signal Processor with Multiprocessing Capability." Digest IEEE International Solid-State Circuits Conference, USA, February 1985. Morris, Robert Digital Signal Processing Software, Ottawa, Canada: Carleton University, 1983. Oppenheim, Alan (Editor), Applications Digital Signal Processing, Englewood Cliffs, Prentice-Hall, Inc., 1978. Oppenheim, Alan R.W. Schafer, Digital Signal Processing, Englewood Cliffs, Prentice-Hall, Inc., 1975 1988. Oppenheim, A.V., A.N. Willsky, I.T. Young, Signals Systems, Englewood Cliffs, Prentice-Hall, Inc., 1983. Papamichalis, P.E., C.S. Burrus, "Conversion Digit-Reversed Bit-Reversed Order Algorithms." Proceedings ICASSP USA, pages 984-987, 1989. Papamichalis, Simar, Jr., "The TMS320C30 Floating-Point Digital Signal Processor." IEEE Micro Magazine, USA, pages 13-29, December 1988. Parks, T.W., C.S. Burrus, Digital Filter Design, York, John Wiley Sons, Inc., 1987. Peterson, Zervakis, Shehadeh, "Adaptive Filter Design Implementation Using TMS320C25 Microprocessor." Computers Education Journal, USA, Volume Number pages 12-16, July- September 1993.
Related Documents Technical Articles
Prado, Alcantara, Fast Square-Rooting Algorithm Using Digital Signal Processor." Proceedings IEEE, USA, Volume Number pages 262-264, February 1987. Rabiner, L.R. Gold, Theory Applications Digital Signal Processing, Englewood Cliffs, Prentice-Hall, Inc., 1975. Simar, Jr., Davis, "The Application High-Level Languages Single-Chip Digital Signal Processors." Proceedings ICASSP USA, Volume page 1678, April 1988. Simar, Jr., Leigh, Koeppen, Leach, Potts, Blalock, MFLOPS Digital Signal Processor: First Supercomputer Chip." Proceedings ICASSP USA, Catalog Number 87CH2396 Volume pages 535-538, April 1987. Simar, Jr., Reimer, "The TMS320C25: CMOS VLSI Digital Signal Processor." 1986 Workshop Applications Signal Processing Audio Acoustics, September 1986. Texas Instruments, Digital Signal Processing Applications with TMS320 Family, 1986; Englewood Cliffs, Prentice-Hall, Inc., 1987. Treichler, J.R., C.R. Johnson, Jr., M.G. Larimore, Practical Guide Adaptive Filter Design, York, John Wiley Sons, Inc., 1987.
Graphics/Imagery:
Andrews, H.C., B.R. Hunt, Digital Image Restoration, Englewood Cliffs, Prentice-Hall, Inc., 1977. Gonzales, Rafael Paul Wintz, Digital Image Processing, Reading, Addison-Wesley Publishing Company, Inc., 1977. Papamichalis, P.E., "FFT Implementation TMS320C30." Proceedings ICASSP USA, Volume page 1399, April 1988. Pratt, William Digital Image Processing, York, John Wiley Sons, 1978. Reimer, Lovrich, "Graphics with TMS32020." WESCON/85 Conference Record, USA, 1985.
Speech/Voice:
DellaMorte, Papamichalis, "Full-Duplex Real-Time Implementation FED-STD-1015 LPC-10e Standard V.52 TMS320C25." Proceedings SPEECH TECH pages 218-221, 1989. Frantz, G.A., K.S. Lin, Low-Cost Speech System Using TMS320C17." Proceedings SPEECH TECH '87, pages 25-29, April 1987.
Read This First
Related Documents Technical Articles
Gray, A.H., J.D. Markel, Linear Prediction Speech, York, Springer-Verlag, 1976. Jayant, N.S., Peter Noll, Digital Coding Waveforms, Englewood Cliffs, Prentice-Hall, Inc., 1984. Papamichalis, Panos, Practical Approaches Speech Coding, Englewood Cliffs, Prentice-Hall, Inc., 1987. Papamichalis, Lively, "Implementation Standard LPC-10/52E TMS320C25." Proceedings SPEECH TECH '87, pages 201-204, April 1987. Pawate, B.I., G.R. Doddington, "Implementation Hidden Markov Model-Based Layered Grammar Recognizer." Proceedings ICASSP USA, pages 801- 804, 1989. Rabiner, L.R., R.W. Schafer, Digital Processing Speech Signals, Englewood Cliffs, Prentice-Hall, Inc., 1978. Reimer, J.B. K.S. Lin, "TMS320 Digital Signal Processors Speech Applications." Proceedings SPEECH TECH '88, April 1988. Reimer, J.B., M.L. McMahan, W.W. Anderson, "Speech Recognition Low-Cost System Using DSP." Digest Technical Papers 1987 International Conference Consumer Electronics, June 1987.
Control:
Ahmed, "16-Bit Microcontroller Fits Motion Control System Application." PCIM, October 1988. Ahmed, "Implementation Self Tuning Regulators with TMS320 Family Digital Signal Processors." MOTORCON '88, pages 248-262, September 1988. Ahmed, Lindquist, "Digital Signal Processors: Simplifying HighPerformance Control." Machine Design, September 1987. Ahmed, Meshkat, "Using DSPs Control." Control Engineering, February 1988. Allen, Pillay, "TMS320 Design Vector Current Control Motor Drives." Electronics Letters, Volume Number pages 2188-2190, November 1992. Bose, B.K., P.M. Szczesny, Microcomputer-Based Control Simulation Advanced Synchronous Machine Drive System Electric Vehicle Propulsion." Proceedings IECON '87, Volume pages 454-463, November 1987.
Related Documents Technical Articles
Hanselman, "LQG-Control Highly Resonant Disc Drive Head Positioning Actuator." IEEE Transactions Industrial Electronics, USA, Volume Number pages 100-104, February 1988. Jacquot, Modern Digital Control Systems, York, Marcel Dekker, Inc., 1981. Katz, Digital Control Using Microprocessors, Englewood Cliffs, Prentice-Hall, Inc., 1981. Kuo, B.C., Digital Control Systems, York, Holt, Reinholt, Winston, Inc., 1980. Lovrich, Troullinos, Chirayil, All-Digital Automatic Gain Control." Proceedings ICASSP USA, Volume page 1734, April 1988. Matsui, Shigyo, "Brushless Motor Control Without Position Speed Sensors." IEEE Transactions Industry Applications, USA, Volume Number Part pages 120-127, January-February 1992. Meshkat, Ahmed, "Using DSPs Induction Motor Drives." Control Engineering, February 1988. Panahi, Restle, "DSPs Redefine Motion Control." Motion Control Magazine, December 1993. Phillips, Nagle, Digital Control System Analysis Design, Englewood Cliffs, Prentice-Hall, Inc., 1984.
Multimedia:
Reimer, "DSP-Based Multimedia Solutions Lead Enhancing Audio Compression Performance." Dobbs Journal, December 1993. Reimer, Benbassat, Bonneau Jr., "Application Processors: Making Multimedia Happen." Silicon Valley Design Conference, July 1991.
Military:
Papamichalis, Reimer, "Implementation Data Encryption Standard Using TMS32010." Digital Signal Processing Applications, 1986.
Read This First
xiii
Related Documents Technical Articles
Telecommunications:
Ahmed, Lovrich, "Adaptive Line Enhancer Using TMS320C25." Conference Records Northcon/86, USA, 14/3/1-10, September/October 1986. Casale, Russo, Bellina, "Optimal Architectural Solution Using Processors Implementation ADPCM Transcoder." Proceedings GLOBECOM '89, pages 1267-1273, November 1989. Cole, Haoui, Winship, High-Performance Digital Voice Echo Canceller SINGLE TMS32020." Proceedings ICASSP USA, Catalog Number 86CH2243-4, Volume pages 429-432, April 1986. Cole, Haoui, Winship, High-Performance Digital Voice Echo Canceller Single TMS32020." Proceedings IEEE International Conference Acoustics, Speech Signal Processing, USA, 1986. Lovrich, Reimer, Multi-Rate Transcoder." Transactions Consumer Electronics, USA, November 1989. Lovrich, Reimer, Multi-Rate Transcoder." Digest Technical Papers 1989 International Conference Consumer Electronics, June 7-9, 1989. Hedberg, Fraenkel, "Implementation High-Speed Voiceband Data Modems Using TMS320C25." Proceedings ICASSP USA, Catalog Number 87CH2396-0, Volume pages 1915-1918, April 1987. Mock, "Add DTMF Generation Decoding DSP- Designs." Electronic Design, USA, Volume Number pages 205-213, March 1985. Reimer, McMahan, Arjmand, "ADPCM TMS320 Chip." Proceedings SPEECH TECH pages 246-249, April 1985. Troullinos, Bradley, "Split-Band Modem Implementation Using TMS32010 Digital Signal Processor." Conference Records Electro/86 Mini/Micro Northeast, USA, 14/1/1-21, 1986.
Related Documents Technical Articles
Automotive:
Lin, "Trends Digital Signal Processing Automotive." International Congress Transportation Electronic (CONVERGENCE '88), October 1988.
Consumer:
Frantz, G.A., J.B. Reimer, R.A. Wotiz, "Julie, Application Product." Speech Tech Magazine, USA, September 1988. Reimer, J.B., G.A. Frantz, "Customization Integrated Circuit Customer Product." Transactions Consumer Electronics, USA, August 1988. Reimer, J.B., P.E. Nixon, E.B. Boles, G.A. Frantz, "Audio Customization IC." Digest Technical Papers 1988 International Conference Consumer Electronics, June 8-10 1988.
Medical:
Knapp Townshend, Real-Time Digital Signal Processing System Auditory Prosthesis." Proceedings ICASSP USA, Volume page 2493, April 1988. Morris, L.R., P.B. Barszczewski, "Design Evolution PocketSized Speech Processing System Cochlear Implant Other Hearing Prosthesis Applications." Proceedings ICASSP USA, Volume page 2516, April 1988.
Development Support:
Mersereau, Schafer, Barnwell, Smith, Digital Filter Design Package TMS320." MIDCON/84 Electronic Show Convention, USA, 1984. Simar, Jr., Davis, "The Application High-Level Languages Single-Chip Digital Signal Processors." Proceedings ICASSP USA, Volume pages 1678-1681, April 1988.
Read This First
Trademarks
Trademarks
DuPont Electronics registered trademark E.I. DuPont Corporation. HP-UX trademark Hewlett-Packard Company. IBM, OS/2, PC-DOS trademarks International Business Machines Corporation. Windows registered trademarks Microsoft Corporation. Solaris SunOS trademarks Microsystems, Inc. SPARC trademark SPARC International, Inc., licensed exclusively Microsystems, Inc. Hotline On-line, XDS510, XDS510PP, XDS510WS, XDS511 trademarks Texas Instruments Incorporated. trademarks Digital Equipment Corp.
Need Assistance
Need Assistance
World-Wide Sites
Online Semiconductor Product Information Center (PIC) Solutions Hotline On-line
http://www.ti.com http://www.ti.com/dsps
North America, South America, Central America
Product Information Center (PIC) (972) 644-5580 Literature Response Center U.S.A. (800) 477-8924 Software Registration/Upgrades (214) 638-0333 Fax: (214) 638-7742 U.S.A. Factory Repair/Hardware Upgrades (281) 274-2285 U.S. Technical Training Organization (972) 644-5580 Hotline (281) 274-2320 Fax: (281) 274-2324 Modem (281) 274-2323 Internet anonymous ftp://ftp.ti.com/pub/tms320bbs
Email: dsph@ti.com
Europe, Middle East, Africa
European Product Information Center (EPIC) Hotlines: Multi-Language Support Deutsch 8161 English Francais Italiano EPIC Modem European Factory Repair Europe Customer Training Helpline Fax: Email: epic@ti.com
Fax:
Asia-Pacific
Literature Response Center +852 7288 Fax: +852 2200 Hong Kong Hotline +852 7268 Fax: +852 1002 Korea Hotline 2804 Fax: 2828 Korea Modem 2914 Singapore Hotline Fax: 7179 Taiwan Hotline +886 1450 Fax: +886 2718 Taiwan Modem +886 2592 Taiwan Internet anonymous ftp://dsp.ee.tit.edu.tw/pub/TI/
Japan
Product Information Center +0120-81-0026 Japan) +03-3457-0972 (INTL) 813-3457-0972 Hotline +03-3769-8735 (INTL) 813-3769-8735 Nifty-Serve Type TIASP" Fax: +0120-81-0036 Japan) Fax: +03-3457-1259 (INTL) 813-3457-1259 Fax: +03-3457-7071 (INTL) 813-3457-7071
Documentation
When making suggestions reporting errors documentation, please include following information that title page: full title book, publication date, literature number. Mail: Texas Instruments Incorporated Email: comments@books.sc.ti.com Technical Documentation Services, P.O. 1443 Houston, Texas 77251-1443
Note:
When calling Literature Response Center order documentation, please specify literature number book.
Read This First
xvii
xviii
Running Title-Attribute Reference
Contents
Introduction Summarizes features TMS320 family products presents typical applications. Describes TMS320C5x lists features. TMS320 Family Overview 1.1.1 History, Development, Advantages TMS320 DSPs 1.1.2 TMS320 Typical Applications TMS320C5x Overview TMS320C5x Features
Software Applications Describes TMS320C5x instruction with particular emphasis features special applications. Processor Initialization Interrupts Software Stack Logical Arithmetic Operations 2.4.1 Parallel Logic Unit (PLU) 2.4.2 Multiconditional Instructions 2-12 2.4.3 Search Algorithm Using CRGT 2-14 2.4.4 Matrix Multiplication Using Nested Loops 2-14 Circular Buffers 2-17 Single-Instruction Repeat (RPT) Loops 2-20 Subroutines 2-24 Extended-Precision Arithmetic 2-26 2.8.1 Addition 2-26 2.8.2 Subtraction 2-29 2.8.3 Multiplication 2-30 2.8.4 Division 2-35 Floating-Point Arithmetic 2-39 Application-Oriented Operations 2-46 2.10.1 Modem Application 2-46 2.10.2 Adaptive Filtering 2-49 2.10.3 Infinite Impulse Response (IIR) Filters 2-52 2.10.4 Dynamic Programming 2-55 Fast Fourier Transforms 2-57
2.10
2.11
Contents
External Memory Interface Describes external interface program memory, local data memory, space. Also described direct memory access (DMA) portable computer configuration. External Interface Program Memory External Interface Local Data Memory External Interface Global Data Memory External Interface Space Direct Memory Access (DMA) Personal Computer Configuration
Analog Interface Peripherals Applications Describes TMS320 variety applications. Multimedia Applications 4.1.1 System Design Considerations 4.1.2 Multimedia-Related Devices Telecommunications Applications 4.2.1 System Design Considerations 4.2.2 Telecommunications-Related Devices Dedicated Speech Synthesis Applications 4-10 4.3.1 System Design Considerations 4-10 4.3.2 Speech Synthesis-Related Devices 4-11 Servo Control/Disk Drive Applications 4-12 4.4.1 System Design Considerations 4-12 4.4.2 Servo Control/Disk Drive-Related Devices 4-14 Modem Applications 4-15 Advanced Digital Electronics Applications Consumers 4-18 4.6.1 Advanced Television System Design Considerations 4-18 4.6.2 Advanced Digital Electronics-Related Devices 4-20
Design Considerations Using XDS510 Emulator Describes JTAG emulator cable construct 14-pin connector your target system connect target system emulator. Cable Header Signals Protocol Emulator Cable Emulator Cable Signal Timings Target System Test Clock Configuring Multiple Processors Connections Between Emulator Target System A.7.1 Emulation Signals Buffered A.7.2 Emulation Signals Buffered A-10 Emulation Timing Calculations A-11
Contents
Development Support Part Order Information Provides device part numbers support tool ordering information TMS320C5x development support information available from third-party vendors. Development Support B.1.1 Software Hardware Development Tools B.1.2 Third-Party Support B.1.3 TMS320C5x Design Workshop B.1.4 Assistance Part Order Information B.2.1 Device Development Support Tool Nomenclature B.2.2 Device Nomenclature B.2.3 Development Support Tools Hewlett-Packard E2442A Preprocessor 'C5x Interface B.3.1 Capabilities B.3.2 Logic Analyzers Supported B.3.3 Pods Required B.3.4 Termination Adapters (TAs) B.3.5 Availability
Application Reports Designer's Notebook Pages Lists TMS320C5x application reports TMS320C5x designer's notebook pages (DNP) available you.
Contents
Running Title-Attribute Reference
Figures
4-10 4-11 4-12 4-13 4-14
xxii
Evolution TMS320 Family Typical Applications TMS320 Family 32-Bit Addition 2-27 32-Bit Subtraction 2-29 16-Bit Integer Multiplication Algorithm 2-31 32-Bit Multiplication Algorithm 2-32 16-Bit Integer Division 2-36 Nth-Order, Direct-Form, Type Filter 2-52 Backtracking With Path History 2-56 In-Place With In-Order Outputs Bit-Reversed Inputs 2-57 In-Place With In-Order Inputs Bit-Reversed Outputs 2-58 'C5x Interfacing External EPROM 'C5x Interfacing External Global Memory Interface Direct Memory Access Environment System Block Diagram Multimedia Speech Encoding Modem Communication TMS320C25 TLC32047 Interface Generic Telecom Application General Telecom Applications Typical DSP/Combo Interface DSP/Combo Interface Timing Generic Servo Control Loop 4-12 Disk Drive Control System Block Diagram 4-13 TMS320C14 TLC32071 Interface 4-13 High-Speed V.32bis Multistandard Modem With TLC320AC01 4-17 Applications Performance Requirements 4-18 Video Signal Processing Basic System 4-19 Typical Digital Audio Implementation 4-19 Header Signals Header Dimensions Emulator Cable Interface Emulator Cable Timings Target-System Generated Test Clock Multiprocessor Connections Emulator Connections Without Signal Buffering Buffered Signals A-10 TMS320C5x Device Nomenclature TMS320 Development Tool Nomenclature
Running Title-Attribute Reference
Tables
Characteristics 'C5x DSPs Conditions Branch, Call, Return Instructions 2-12 Groups Multiconditional Instructions 2-13 Bit-Reversal Algorithm 8-Point Radix-2 2-58 Data Converter Switched-Capacitor Filter Telecom Devices-Codec/Filter Telecom Devices-Transient Suppressor Voice Synthesizers 4-10 Speech Memories 4-11 Control Related Devices 4-14 Modem Data Converters 4-15 Audio/Video Analog/Digital Interface Devices 4-20 XDS510 Header Signal Description Emulator Cable Timing Parameters TMS320C5x Development Support Tools Part Numbers TMS320C5x Application Reports TMS320C5x Designer's Notebook Pages
Contents
xxiii
Running Title-Attribute Reference
Examples
2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 2-31 2-32 2-33 2-34 2-35
xxiv
Initialization TMS320C5x INTR Instruction Software Stack Operation Using Unpacking 2-10 Using Packing 2-11 Using Multiple Conditions With BCND Instruction 2-13 Using CRGT CRLT Instructions 2-15 Using Nested Loops 2-16 Circular Addressing 2-18 Modulo-256 Addressing 2-19 Memory-to-Memory Block Moves Using with BLDD 2-21 Memory-to-Memory Block Moves Using with BLDP 2-21 Memory-to-Memory Block Moves Using with BLPD 2-21 Memory-to-Memory Block Moves Using with TBLR 2-22 Memory-to-Memory Block Moves Using with TBLW 2-22 Memory-to-Memory Block Moves Using with SMMR 2-22 Memory-to-Memory Block Moves Using with LMMR 2-23 Square Root Computation Using Instruction 2-24 64-Bit Addition 2-28 64-Bit Subtraction 2-30 32-Bit Integer Multiplication 2-33 32-Bit Fractional Multiplication 2-34 16-Bit Integer Division Using SUBC Instruction 2-37 16-Bit Fractional Division Using SUBC Instruction 2-38 Floating-Point Addition Using SATL SATH Instructions 2-40 Floating-Point Multiplication Using BSAR Instruction 2-44 V.32 Encoder Using Accumulator Buffer 2-47 Adaptive Filter Using RPTB Instructions 2-50 Nth-Order Filter Using MACD Instructions 2-53 Cascaded BiQuad Filter Using MPYA Instructions 2-54 Backtracking Algorithm Using Circular Addressing 2-56 16-Point Radix-2 Complex 2-59 Bit-Reversed Addressing 2-62 Macros 16-Point 2-63 Initialization Routine 2-69
Chapter
Introduction
This user's guide provides applications TMS320C5x generation fixed-point digital signal processors (DSPs) TMS320 family. 'C5x provides improved performance over earlier 'C1x 'C2x generations while maintaining upward compatibility source code between devices. 'C5x central processing unit (CPU) based 'C25 incorporates additional architectural enhancements that allow device twice fast 'C2x devices. Future expansion enhancements expected heighten performance range applications 'C5x DSPs. 'C5x generation static CMOS DSPs consists following devices:
Device TMS320C50/LC50 TMS320C51/LC51 TMS320C52/LC52 TMS320C53/LC53 TMS320C53S/LC53S TMS320LC56 TMS320C57S TMS320LC57 On-Chip words words words words words words words words On-Chip words words words words words words words words
Topic
Page
TMS320 Family Overview TMS320C5x Overview TMS320C5x Features
Introduction
TMS320 Family Overview
TMS320 Family Overview
TMS320 family consists types single-chip DSPs: 16-bit fixedpoint 32-bit floating-point. These DSPs possess operational flexibility high-speed controllers numerical capability array processors. Combining these qualities, TMS320 processors inexpensive alternatives custom-fabricated very large scale integration (VLSI) multichip bit-slice processors. Refer subsection 1.1.2, TMS320 Typical Applications, detailed list applications TMS320 family. following characteristics make this family ideal choice wide range processing applications:
1.1.1
Very flexible instruction Inherent operational flexibility High-speed performance Innovative, parallel architectural design Cost-effectiveness
History, Development, Advantages TMS320 DSPs
1982, Texas Instruments introduced TMS32010 first fixed-point TMS320 family. Before year, Electronic Products magazine awarded TMS32010 title "Product Year". TMS32010 became model future TMS320 generations. Today, TMS320 family consists these generations (Figure 1-1): 'C1x, 'C2x, 'C2xx, 'C5x, 'C54x, 'C6x fixed-point DSPs; 'C3x 'C4x floatingpoint DSPs; 'C8x multiprocessor DSPs. Figure illustrates performance gains that TMS320 family made over time with successive generations. Source code upwardly compatible from fixed-point generation next fixed-point generation (except 'C54x), from floating-point generation next floating-point generation. Upward compatibility preserves software generation your investment, thereby providing convenient cost-efficient means higher-performance, more versatile system. Each generation TMS320 devices variety on-chip memory peripheral configurations developing spin-off devices. These spin-off devices satisfy wide range needs worldwide electronics market. When memory peripherals integrated into processor, overall system cost greatly reduced, circuit board space saved.
TMS320 Family Overview
Figure 1-1. Evolution TMS320 Family
Introduction
TMS320 Family Overview
1.1.2
TMS320 Typical Applications
TMS320 family DSPs offers better, more adaptable approaches traditional signal-processing problems, such vocoding, filtering, error coding. Furthermore, TMS320 family supports complex applications that often require multiple operations performed simultaneously. Figure shows many typical applications TMS320 family.
Figure 1-2. Typical Applications TMS320 Family
Automotive Adaptive ride control Antiskid brakes Cellular telephones Digital radios Engine control Global positioning Navigation Vibration analysis Voice commands General-Purpose Adaptive filtering Convolution Correlation Digital filtering Fast Fourier transforms Hilbert transforms Waveform generation Windowing Instrumentation Digital filtering Function generation Pattern matching Phase-locked loops Seismic processing Spectrum analysis Transient analysis Consumer Digital radios/TVs Educational toys Music synthesizers Power tools Radar detectors Solid-state answering machines Control Disk drive control Engine control Laser printer control Motor control Robotics control Servo control
Graphics/Imaging rotation Animation/digital Homomorphic processing Pattern recognition Image enhancement Image compression/transmission Robot vision Workstations Medical Diagnostic equipment Fetal monitoring Hearing aids Patient monitoring Prosthetics Ultrasound equipment Telecommunications
Industrial Numeric control Power-line monitoring Robotics Security access
Military Image processing Missile guidance Navigation Radar processing Radio frequency modems Secure communications Sonar processing Voice/Speech Speech enhancement Speech recognition Speech synthesis Speaker verification Speech vocoding Voice mail Text-to-speech
1200- 19200-bps modems Adaptive equalizers ADPCM transcoders Cellular telephones Channel multiplexing Data encryption Digital PBXs Digital speech interpolation (DSI) Personal digital assistants (PDA)
DTMF encoding/decoding Echo cancellation Line repeaters Speaker phones Spread spectrum communications Video conferencing X.25 Packet Switching Personal communications systems (PCS)
TMS320C5x Overview
TMS320C5x Overview
'C5x generation consists 'C50, 'C51, 'C52, 'C53, 'C53S, 'C56, 'C57, 'C57S DSPs, which fabricated CMOS integrated-circuit technology. Their architectural design based 'C25. operational flexibility speed 'C5x result combining advanced Harvard architecture (which separate buses program memory data memory), with application-specific hardware logic, on-chip peripherals, on-chip memory, highly specialized instruction set. 'C5x designed execute million instructions second (MIPS). Spin-off devices that combine 'C5x with customized on-chip memory peripheral configurations developed special applications worldwide electronics market. 'C5x devices offer these advantages:
Enhanced TMS320 architectural design increased performance versatility Modular architectural design fast development spin-off devices Advanced integrated-circuit processing technology increased performance power consumption Source code compatibility with 'C1x, 'C2x, 'C2xx DSPs fast easy performance upgrades Enhanced instruction faster algorithms optimized high-level language operation Reduced power consumption increased radiation hardness because static design techniques
Table lists major characteristics 'C5x DSPs. table shows capacity on-chip ROM, number serial parallel input/output (I/O) ports, power supply requirements, execution time machine cycle, package types available with total count. Table guidance choosing best 'C5x your application.
Introduction
TMS320C5x Overview
Table 1-1. Characteristics 'C5x DSPs
On-Chip Memory (16-bit words) DARAM SARAM 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 1056 Ports Serial Parallel 64Kk 64Kk Power Supply Cycle Time (ns) 50/35/25 50/35/25
TMS320 Device 'C50 'LC50 'C51 'C51 'LC51 'LC51 'C52 'C52 'LC52 'LC52 'C53 'C53S 'LC53 'LC53S 'LC56 'C57S 'LC57
Package Type BQFPd BQFPd
50/35/25/20 BQFPd 50/35/25/20 TQFPk 50/35/25 50/35/25 BQFPd TQFPk
50/35/25/20 QFPh 50/35/25/20 TQFPk 50/35/25 50/35/25 50/35/25 50/35/25 50/35/25 50/35/25 50/35/25 50/35/25 50/35/25 QFPh TQFPk BQFPd TQFPk BQFPd TQFPk TQFPk TQFPD pinTQFPk
Dual-access (DARAM) Single-access (SARAM) bootloader available Includes time-division multiplexed (TDM) serial port Includes buffered serial port (BSP) Includes host port interface (HPI) bumpered quad flat-pack (BQFP) package thin quad flat-pack (TQFP) package quad flat-pack (QFP) package thin quad flat-pack (TQFP) package Sixteen parallel ports memory mapped.
TMS320C5x Features
TMS320C5x Features
features 'C5x DSPs listed below. Where feature exclusive particular device, device's name enclosed within parentheses noted after that feature.
Compatibility: Source-code compatible with 'C1x, 'C2x, 'C2xx devices Speed: 20-/25-/35-/50-ns single-cycle fixed-point instruction execution time (50/40/28.6/20 MIPS) Power
3.3-V static CMOS technology with power-down modes Power consumption control with IDLE1 IDLE2 instructions power-down modes
Memory 224K-word 16-bit maximum addressable external memory space (64K-word program, 64K-word data, 64K-word I/O, 32K-word global memory) 1056-word 16-bit dual-access on-chip data 9K-word 16-bit single-access on-chip program/data ('C50) 2K-word 16-bit single-access on-chip boot ('C50, 'C57S) 1K-word 16-bit single-access on-chip program/data ('C51) 8K-word 16-bit single-access on-chip program ('C51) 4K-word 16-bit single-access on-chip program ('C52) 3K-word 16-bit single-access on-chip program/data ('C53, 'C53S) 16K-word 16-bit single-access on-chip program ('C53, 'C53S) 6K-word 16-bit single-access on-chip program/data ('LC56, 'C57S, 'LC57) 32K-word 16-bit single-access on-chip program ('LC56, 'LC57)
Introduction
TMS320C5x Features
Central processing unit (CPU)
Central arithmetic logic unit (CALU) consisting following:
32-bit arithmetic logic unit (ALU), 32-bit accumulator (ACC), 32-bit accumulator buffer (ACCB) 16-bit 16-bit parallel multiplier with 32-bit product capability 16-bit left right data barrel-shifters 64-bit incremental data shifter
16-bit parallel logic unit (PLU) Dedicated auxiliary register arithmetic unit (ARAU) indirect addressing Eight auxiliary registers
Program control 8-level hardware stack 4-deep pipelined operation delayed branch, call, return instructions Eleven shadow registers storing strategic CPU-controlled registers during interrupt service routine (ISR) Extended hold operation concurrent external direct memory access (DMA) external memory on-chip indirectly addressed circular buffers circular addressing
Instruction Single-cycle multiply/accumulate instructions Single-instruction repeat block repeat operations Block memory move instructions better program data management Memory-mapped register load store instructions Conditional branch call instructions Delayed execution branch call instructions Fast return from interrupt instructions Index-addressing mode Bit-reversed index-addressing mode radix-2 fast Fourier transforms (FFTs)
TMS320C5x Features
On-chip peripherals
parallel ports ports memory mapped) Sixteen software-programmable wait-state generators program, data, memory spaces Interval timer with period, control, counter registers software stop, start, reset Phase-locked loop (PLL) clock generator with internal oscillator external clock source Multiple clocking option (x1, depending device) Full-duplex synchronous serial port interface direct communication between 'C5x another serial device Time-division multiplexed (TDM) serial port ('C50, 'C51, 'C53) Buffered serial port (BSP) ('LC56, 'C57S, 'LC57) 8-bit parallel host port interface (HPI) ('C57, 'C57S)
Test/emulation On-chip scan-based emulation logic IEEE JTAG Standard 1149.1 boundary scan logic ('C50, 'C51, 'C53, 'C57S)
Packages 100-pin quad flat-pack (QFP) package ('C52) 100-pin thin quad flat-pack (TQFP) package ('C51, 'C52, 'C53S, 'LC56) 128-pin TQFP package ('LC57) 132-pin bumpered quad flat-pack (BQFP) package ('C50, 'C51, 'C53) 144-pin TQFP package ('C57S)
Introduction
1-10
Chapter
Software Applications
'C5x devices maintain source-code compatibility with 'C1x 'C2x generations have architectural enhancements that improve performance versatility. orthogonal instruction augmented instructions that support additional hardware handle data movement memorymapped registers. Other features include independent parallel logic unit (PLU) performing Boolean operations, 32-bit accumulator buffer (ACCB), registers that provide zero-latency context-switching capabilities interrupt service routines. on-chip dual-access memorymapped register enhanced. This chapter explains 'C5x instruction with particular emphasis features special applications. complete discussion assembler directives used this chapter's examples, consult TMS320C1x/C2x/C2xx/C5x Assembly Language Tools User's Guide.
Topic
Page
Processor Initialization Interrupts Software Stack Logical Arithmetic Operations Circular Buffers 2-17 Single-Instruction Repeat (RPT) Loops 2-20 Subroutines 2-24 Extended-Precision Arithmetic 2-26 Floating-Point Arithmetic 2-39
2.10 Application-Oriented Operations 2-46 2.11 Fast Fourier Transforms 2-57
Software Applications
Processor Initialization
Processor Initialization
Before executing 'C5x algorithm, necessary initialize processor. Generally, initialization takes place anytime processor reset. processor reset applying level input; interrupt vector pointer (IPTR) bits processor mode status register (PMST) cleared, thus mapping vectors page program memory space. This means that reset vector always resides program memory location This location normally contains branch instruction direct program execution system initialization routine. hardware reset clears pending interrupt flags sets interrupt mode (INTM) ST0, thereby disabling interrupts. hardware reset also initializes various status bits peripheral registers. configure processor after reset, following internal functions must initialized:
Memory-mapped core processor peripheral control registers Interrupt structure (INbit) Mode control (OVM, SXM, AVIS, NDX, bits) Memory control (RAM, OVLY, bits) Auxiliary registers auxiliary register pointer (ARP) Data memory page pointer (DP)
(overflow mode), (test/control flag), (interrupt mask register), auxiliary register pointer (ARP), auxiliary register buffer (ARB), data memory page pointer (DP) initialized reset. Example shows coding initializing 'C5x following machine state initialization performed after hardware reset:
Internal single-access configured program memory Interrupt vector table loaded internal program memory Interrupt vector table pointer (IPTR) Internal dual-access blocks filled with Interrupts enabled
Processor Initialization
Example 2-1. Initialization TMS320C5x
.title 'PROCESSOR INITIALIZATION' .mmregs .ref ISR0,ISR1,ISR2,ISR3,ISR4,TIME .ref RCV,XMT,TRX,TXMT,TRP,NMISR Processor initialization TMS320C50. memory mapping program space data space different 'C5x devices. Therefore, memory location pointed address 0800h data space mapped different address program space different 'C5x devices. Hence, IPTR should loaded with corresponding value allocate vector table correct program space. PMST 0081E 0201E 0401E 0801E 0801E V_TBL .sect "vectors" RESET INIT ;This section will loaded program ;memory address INT0 ISR0 ;INT0 begins processing here INT1 ISR1 ;INT1 begins processing here INT2 ISR2 ;INT2 begins processing here INT3 ISR3 ;INT3 begins processing here TINT TIME ;Timer interrupt processing RINT ;Serial port receive interrupt XINT ;Serial port transmit interrupt TRNT ;TDM port receive interrupt TXNT TXMT ;TDM port transmit interrupt INT4 ISR4 ;INT4 begins processing here .space 14*16 words TRAP NMISR .text INIT ;Initialize data pointer #20h,PMST ;Configure data memory AR7,#0800h ;Data space address vector table *,AR7 BLPD #V_TBL,*+ ;Load vector table 0800h SPLK #0081Eh,PMST ;Now configure program space ;and initialize vector table pointer SPLK #01FFh,IMR ;Clear interrupt mask register CLRC ;Disable overflow saturation mode AR7,#60h ;Initialize block RPTZ SACL
Software Applications
Processor Initialization
Example 2-1. Initialization TMS320C5x (Continued)
RPTZ SACL RPTZ SACL CLRC AR7,#100h #511 AR7,#300h #511 INMAIN_PRG ;Initialize block
;Initialize block
;Globally enable interrupts ;Return
Interrupts
Interrupts
'C5x devices have four external, maskable, user interrupts (INT1-INT4) nonmaskable interrupt (NMI) available external devices. Internal interrupts generated serial ports, timer, software interrupt instructions (INTR, TRAP, NMI). interrupt structure described TMS320C5x User's Guide. 'C5x devices capable generating software interrupts using INTR instruction. This allows interrupt service routines (ISRs) executed from your software. first ISRs reserved external interrupts, peripheral interrupts, future implementations. remaining locations interrupt vector table user-definable. INTR instruction invoke interrupts available 'C5x devices. When interrupt executed, certain registers saved automatically. saved 8-deep hardware stack, which also used subroutine calls. Therefore, supports subroutine calls within long 8-level stack exceeded. Also, there 1-deep stack shadow register) each following registers:
Accumulator (ACC) Accumulator buffer (ACCB) Auxiliary register compare register (ARCR) Index register (INDX) Processor mode status register (PMST) Product register (PREG) Status register (ST0) Status register (ST1) Temporary register (TREG0) multiplier Temporary register (TREG1) shift count Temporary register (TREG2) test
When interrupt trap taken, contents these registers pushed onto 1-level stack, with exception INbit ST1. interrupt, INbit always disable interrupts. values registers time interrupt trap still available also protected shadow registers. shadow registers copied back registers when RETI RETE instruction executed. This function allows used without requiring overhead context save restore ISR.
Software Applications
Interrupts
Example illustrates INTR instruction. foreground program sets auxiliary registers invokes user-defined interrupt number Since context saved automatically, free saved registers without destroying calling program's variables. routine shown here uses CRGT instruction find maximum value executions equation points values, points coefficients, points results. return result calling routine, registers restored executing RETI instruction. computed value placed accumulator, standard return executed because stack already popped.
Example 2-2. INTR Instruction
Foreground Program .mmregs TEMP .set .set .set COEFF .set V_TBL .sect "vectors" RESET INIT
;Temporary storage.
.space 38*16 ISR20 .text INIT ;Initialize data pointer AR1,#X ;AR1 points values AR2,#COEFF ;AR2 points coefficients b,a,c that order AR3,#Y ;AR3 points results INTR ;Invoke software interrupt ;Finish program This routine uses block repeat feature 'C5x find maximum value executions equation Y=aX^2+bX+c. values pointed AR1. results pointed AR3. coefficients pointed AR2. completion routine, contains maximum value. AR1, AR2, modified. other registers unaffected. ISR20 ;Use page data memory. LACC #08000h SACB ;Initialize AccB with min. possible value *,AR1 ;ARP Load Block repeat count register with SPLK #0Fh,BRCR IN20
;This section will loaded program ;memory address ;Skip next locations interrupt :Interrupt begins processing here
Interrupts
Example 2-2. INTR Instruction (Continued)
Repeat Block. RPTB END_LOOP-1 SQRA *+,AR2 TEMP TEMP APAC *,0,AR3 SACL *+,0,AR1 CRGT END_LOOP SACL TEMP LACC #RE_ENTER PUSH RETI RE_ENTER LACC TEMP ;For i=0; i<=15; i++. ;ACC PREG ;TREG0 PREG ;Save X^2. ;PREG ;TREG ;PREG a*X^2 ;ACC a*X^2 ;ACC A*X^2 ;Save ;Save maximum ;Save result temporarily ;Push re-entry address onto stack ;Pop registers ;Load with max. value ;Return interrupted code
Software Applications
Software Stack
Software Stack
'C5x internal 8-deep hardware stack that used save restore return addresses subroutines ISRs. Provisions have been made 'C5x extend hardware stack into data memory. PUSH instructions access hardware stack accumulator. additional instructions, PSHD POPD, included instruction that stack directly stored recovered from data memory. software stack implemented using POPD instruction beginning each subroutine save data memory. Then, before returning, PSHD used proper value back onto stack. When stack seven values stored more values stack before other values popped off, subroutine that expands stack needed. routine expand stack shown Example 2-3. this example, main program stores stack, stores starting memory location AR2, indicates subroutine whether push data from memory onto stack data from stack memory. loaded into accumulator before calling subroutine, subroutine pushes data from memory stack. accumulator contains nonzero value, subroutine pops data from stack memory. Because CALL instruction uses stack save program counter, subroutine pops this value into accumulator uses BACC instruction return main program. This prevents program counter from being stored into memory location. subroutine Example uses BCNDD (delayed conditional branch) instruction determine whether save restore operation performed.
Example 2-3. Software Stack Operation
This routine expands stack while letting main program determine where store stack contents, from where restore them. Entry Conditions: (restore stack); (save stack) software stack data memory STACK: BCNDD POP,NEQ ;Delayed branch POPD required *,AR2 ;Use stack pointer ;Get return address ;Repeat times PSHD ;Put memory stack BACC ;Return main program POP: ;Align ;Repeat times POPD ;Put stack memory ;Realign stack pointer BACC ;Return main program
Logical Arithmetic Operations
Logical Arithmetic Operations
following subsections provide examples logical arithmetic operations.
2.4.1
Parallel Logic Unit (PLU)
provides direct logical path data memory values without affecting contents accumulator product register. allows direct manipulation bits location data memory space. source operand either long immediate value dynamic manipulation register (DBMR). long immediate value particularly effective initializing data memory locations, including memory-mapped registers. DBMR source operand allows run-time computation operands. also reduces instruction execution time cycle, which important time-critical routines. Example page 2-10 Example page 2-11 illustrate initialization logical operation. UNPACK subroutine (Example 2-4) extracts individual bits from single word stores them separately array. PACK subroutine (Example 2-5) does opposite UNPACK getting bits from different locations packing them single word. Example 2-5, notice that instruction inserted repeatblock loop. repeat-block loop must least three words long 'C5x devices.
Software Applications
Logical Arithmetic Operations
Example 2-4. Using Unpacking
.title 'Routine extract bits from single word' PCKD ---------------- ------ ----------------
UNPCKD ---------------- |Bn| ---------------- 0|Bn-1| ---------------- ---------------- 0|B0| ---------------- .mmregs NO_BITS .set PCKD .set UNPCKD .set
;Number packed bits word ;Input word ;Output buffer. Each word will have ;one location.
UNPACK
LOOP
.text ;DP=0 *,AR0 AR0,#UNPCKD+NO_BITS-1 ;End table address SPLK #NO_BITS-1,BRCR ;Initialize count register SPLK #1,DBMR ;Load mask DBMR register LACC PCKD ;Packed bits RPTB LOOP-1 ;Begin looping SACL ;Save remaining packed bits ;Keep only ;Shift right eliminate unpacked ;Return back
2-10
Logical Arithmetic Operations
Example 2-5. Using Packing
.title 'Routine pack input bits single word' PCKD ---------------- ------ ----------------
UNPCKD ---------------- |Bn| ---------------- 0|Bn-1| ---------------- ---------------- 0|B0| ---------------- .data NO_BITS .set PCKD .set UNPCKD .set .text PACK AR0,#UNPCKD *,AR0 SPLK #NO_BITS-2,BRCR LACC RPTB LOOP-1 LOOP SACL PCKD
;Number bits packed ;Packed word ;Array unpacked bits ;AR0 points start UNPACKED array ;DP=0 ;Loop NO_BITS-1 times ;Get ;Begin looping ;Make space next ;Put next
;Store result ;Return back
Software Applications
2-11
Logical Arithmetic Operations
2.4.2
Multiconditional Instructions
'C5x includes instructions that test multiple conditions before passing control another section program. These instructions are: BCND, BCNDD, CCD, RETC, RETCD, These instructions test conditions listed Table individually combination with other conditions.
Table 2-1. Conditions Branch, Call, Return Instructions
Mnemonic Condition none Description Accumulator equal Accumulator equal Accumulator less than Accumulator less than equal Accumulator greater than Accumulator greater than equal Carry cleared Carry accumulator overflow detected Accumulator overflow detected signal Test/control flag cleared Test/control flag Unconditional operation
combine conditions from four groups (Table 2-2). four conditions selected; however, each these conditions must from different groups. cannot have conditions from same group. example, test same time GEQ. example:
BCND BRANCH,LT,NOV,TC overflow set.
this example, (ACC conditions must branch taken.
2-12
Logical Arithmetic Operations
Table 2-2. Groups Multiconditional Instructions
Group Group Group Group
Testing status flag mutually exclusive testing pin. code Example simultaneously tests carry flag sign accumulator locate zero (beginning from MSB) 64-bit word, consisting ACCB with having higher part. This 64-bit word could serial port output where first indicates start bit.
Example 2-6. Using Multiple Conditions With BCND Instruction
SPLK RPTB SFLB BCND ENDLOOP: ENDLOOP,NC,LT #0FFFEh,PMST #63,BRCR ;No. iterations ;Code 64-bit input word ;load ACCB AR0,#0 ENDLOOP-1 ;Initialize counter ;For I=0,I<=63,I++ ;Shift left ACC+ACCB, shifted ;out Carry flag ;Increment counter ;Exit carry=0 current MSB=1 ;ACC+ACCB contains aligned data ;Clear BRAF flag
Software Applications
2-13
Logical Arithmetic Operations
2.4.3
Search Algorithm Using CRGT
Example page 2-15 shows CRGT RPTB instructions find maximum value location searching through block data. Loop overhead minimized using block-repeat function. accumulator initialized with minimum possible value (8000h) before main search loop entered. find minimum value, CRGT instruction replaced CRLT, accumulator loaded with maximum possible value (7FFFh) instead smallest. rest code remains same.
2.4.4
Matrix Multiplication Using Nested Loops
'C5x provides three different types instructions implement code loops. (single-instruction repeat) instruction allows following instruction executed times. RPTB (repeat block) instruction repeatedly executes block instructions with loop count determined block repeat counter register (BRCR). BANZ (branch instruction another implementing for-next loops with count specified auxiliary register. Three-level-deep nested loops efficiently implemented these three instructions with each instruction controlling loop. Example page 2-16 shows this nested code structure N-by-N matrix multiplication. Note BANZD (delayed BANZ) instruction avoid flushing instruction pipeline. Also, note MADS (multiply-accumulate using BMAR) instruction dynamically switch between rows matrix compute elements product matrix
2-14
Logical Arithmetic Operations
Example 2-7. Using CRGT CRLT Instructions
This routine searches through block data data memory store maximum value address that value memory locations MAXVAL MAXADR, respectively. data block could size defined Block Repeat Counter Register (BRCR). 'C5X instructions: RPTB Repeat block code defined repeat counter BRCR. CRGT Compare ACCB. Store larger value both ACCB, CARRY value larger than previously larger value found. Execute conditionally words) CARRY set. MAXADR .set MAXVAL .set .mmregs .text ;Point data page AR0,#0300h ;AR= data memory addr SETC ;Set sign extension mode LACC #08000h ;Load minimum value #07FFFh (largest possible) check minimum value SACB ;Store into ACCB SPLK #9,BRCR ;Rpt cont data values RPTB endb ;Repeat block from here endb-1 startb: LACC ;Load data from <(AR0)> into CRGT ;Set carry previous largest value CRLT find minimum value SACL MAXVAL ;Save largest which ACCB #1,C ;Save addr current value previous largest AR0,MAXADR endb: routine, following registers contain: 32050 ACCB 32050 (MAXVAL) 32050 (MAXADR) 0307h .data ;Data expected data .word 5000 ;Start address 0300h .word 10000 .word .word 3200 .word -5600 .word -2105 .word 2100 .word 32050 .word 1000 .word .end
Software Applications
2-15
Logical Arithmetic Operations
Example 2-8. Using Nested Loops
.title "NxN Matrix Multiply Routine" .mmregs This routine performs multiplication matrices. where A,B, size. Entry Conditions: element (0,0) program space) element (0,0) data space) element (0,0) data space) Storage matrix elements memory (beginning from memory): SPLK #3Eh,PMST SPLK #2000h,AR1 SPLK #0810h,AR2 SPLK #0820h,AR3 *,AR2 MTRX_MPY: AR0,#(N-1) ;Set loop count SPLK #N,INDX ;Row size AR2,AR4 ;Save addr ;For i=0,i<N,++i LOOP1: SMMR AR1,BMAR ;BMAR A(i,0) SPLK #(N-1),BRCR ;Setup loop2 count AR4,AR5 ;AR5 B(0,0) LOOP2: RPTB ELOOP2 ;For j=0,j<N,++j AR5,AR2 ;AR2 B(0,j) LOOP3: RPTZ #(N-1) ;For k=0,k<N,++k ELOOP3: MADS ;Acc=A(i,k)xB(k,j) APAC ;Final accumulation *,AR5 ;ARp *+,AR3 ;AR5 B(0,j+1) ELOOP2: SACL *+,0,AR2 ;Save C(i,j) *,AR0 ;Loop back BANZD LOOP1,*-,AR1 ;Count ADRK ;AR1 A(i+1,0) ELOOP1: *,AR2 ;ARp
2-16
Circular Buffers
Circular Buffers
Circular addressing important feature 'C5x instruction set. Algorithms like convolution, correlation, finite impulse response (FIR) filters make circular buffers memory. 'C5x supports concurrent buffers operating auxiliary registers. Five memory-mapped registers control circular buffer operation: CBSR1, CBSR2, CBER1, CBER2, CBCR. start addresses must loaded corresponding buffer registers (CBSRx CBERx) before circular buffer enabled. Also, auxiliary register that acts pointer buffer must initialized with proper value. Example page 2-18 shows circular buffer generate digital sine wave. 256-word sine-wave table loaded DARAM block internal data memory from external program memory. Accessing internal DARAM requires only machine cycle. block move address register (BMAR) loaded with address table. block-move instruction moves samples sine wave internal data memory, which then circular buffer. start addresses this circular buffer loaded into corresponding registers (CBSR1 CBER1). auxiliary register also initialized beginning sine-wave table. Note SAMM instruction update because auxiliary registers memory-mapped data page Finally, circular buffer enabled mapped that buffer. other circular buffer disabled. Whenever next sample pulled from table, postincrement indirect addressing used with pointer. This ensures that pointer wraps around beginning table previous sample last table.
Software Applications
2-17
Circular Buffers
Example 2-9. Circular Addressing
.title 'Digital Sine-Wave Generator' .mmregs This routine illustrates circular addressing capability devices. digital sine-wave generator implemented circular buffer with pointer. XSINTBL location external program memory where this table stored. moved internal data memory block where setup circular buffer. XSINTBL .set 03000h ;Program space address sine table .text SINTBL AR0,#0300h ;Address block *,AR0 LACC #XSINTBL ;Get sine table address ;external program memory SAMM BMAR ;Load source register #255 ;Move 256-word BLPD BMAR,*+ ;Load table from external program ;memory internal data memory SAMM CBSR1 ;Start address buffer=300h SAMM ;AR7 points start buffer #255 SAMM CBER1 ;End address buffer=3FFh SPLK #0Fh,CBCR ;Enable CB#1, disable CB#2 ;pointer CB#1 NXTSMP *,AR7 LACC ;Get next sample from table ;AR7 updated next valid sample DISBLE #0FFF7h,CBCR ;Disable CB#1
2-18
Circular Buffers
step size must greater than check update auxiliary register generates address outside range circular buffer. This happen same sine table used generate sine waves different frequencies changing step size. Modulo addressing avoid such problems. simple perform modulo addressing 'C5x devices instructions. example, implement modulo-256 counter, first load dynamic manipulation register (DBMR) with (the maximum value allowed); when auxiliary register updated amount), ANDed with DBMR ORed with start address buffer. start address modulo-2k buffer must have LSBs. Hence, modulo-256 addressing, first eight LSBs start register must (see Example 2-10).
Example 2-10. Modulo-256 Addressing
START .set LACL SAMM 04000h #0FFh DBMR ;Start address buffer
;Max value
#START,AR7
;Increment some amount ;Extract lower bits ;Add start address
Software Applications
2-19
Single-Instruction Repeat (RPT) Loops
Single-Instruction Repeat (RPT) Loops
'C5x provides different types repeat instructions. repeat block (RPTB) instruction implements code loops that words size. These loops require additional cycles jump from end-ofblock start-of-block address each iteration. addition, these zero-overhead loops interruptible that they used background processing without affecting latency time-critical tasks. other hand, single-instruction repeat (RPT) pipelines execution next instruction provide high-speed repeat mode. 16-bit repeat counter register (RPTC) allows execution single instruction times. When this repeat feature used, instruction being repeated fetched only once. result, many multicycle instructions, such MAC/MACD, BLDD/ BLDP, TBLR/TBLW, become single-cycle when repeated. Some 'C5x instructions behave differently single-instruction repeat mode efficiently 'C5x multiple-bus architecture. following instructions fall this category: BLDD, BLDP, BLPD, OUT, MAC, MACD, MADS, MADD, TBLR, TBLW, LMMR, SMMR Because instruction fetched internally latched when singleinstruction repeat mode, program used these instructions read write second operand parallel operations being done using data bus. With instruction latched repeated execution, program counter loaded with second operand address (which data, program, space) incremented succeeding executions read/write successive memory locations. example, instruction fetches multiplicand from program memory program bus. Simultaneously with program fetch, second multiplicand fetched from data memory data bus. addition these data fetches, preparation made accesses following cycle incrementing program counter indexing auxiliary register. instruction another example instruction that benefits from simultaneous transfers data both program data buses. this case, data values from successive locations space read transferred data memory. complete details above-listed instructions behave repeat mode, individual description each instruction TMS320C5x User's Guide. Example 2-11 through Example 2-17 demonstrate implementation memory-to-memory block moves 'C5x using single-instruction repeat (RPT) loops. There single instruction move data from memory memory.
2-20
Single-Instruction Repeat (RPT) Loops
Example 2-11. Memory-to-Memory Block Moves Using with BLDD
This routine uses BLDD instruction move external data memory internal data memory. MOVEDD: LACC #4000h SAMM BMAR ;BMAR source data memory. AR7,#100h ;AR7 destination data memory *,AR7 ;LARP AR7. #1023 ;Move 1024 value blocks BLDD BMAR,*+
Example 2-12. Memory-to-Memory Block Moves Using with BLDP
This routine uses BLDP instruction move external data memory internal program memory. This instruction could used boot load program on-chip program memory from external data memory. MOVEDP: LACC #800h SAMM BMAR ;BMAR destination program memory ('C50) AR7,#0E000h ;AR7 source data memory. #8191 ;Move program memory space. BLDP
Example 2-13. Memory-to-Memory Block Moves Using with BLPD
This routine uses BLPD instruction move external program memory internal data memory. This routine useful loading coefficient table stored external program memory data memory when external data memory available. MOVEPD: AR7,#100h ;AR7 destination data memory. #127 ;Move values from external program BLPD #3800h,*+ internal data memory
Software Applications
2-21
Single-Instruction Repeat (RPT) Loops
Example 2-14. Memory-to-Memory Block Moves Using with TBLR
This routine uses TBLR instruction move external program memory internal data memory. This differs from BLPD instruction that accumulator contains source program memory address from which transfer. This allows calculated, rather than predetermined, location program memory specified. calling routine must contain source program memory address accumulator.
TABLER: TBLR
*,AR3 AR3,#300h #127
;AR3 destination data memory. ;Move items data memory block
Example 2-15. Memory-to-Memory Block Moves Using with TBLW
This routine uses TBLW instruction move data memory program memory. This differs from BLDP instruction that accumulator contains destination program memory address which transfer. This allows calculated, rather than predetermined, location program memory specified. calling routine must contain destination program memory address accumulator. TABLEW: *,AR4 ;ARP AR4. AR4,#380h ;AR4 source address data memory. #127 ;Move items from data memory TBLW ;program memory.
Example 2-16. Memory-to-Memory Block Moves Using with SMMR
This routine uses SMMR instruction move data from memory-mapped port local data memory. Note that ports mapped data page 'C5x memory map. INPUT: #511 ;Input values from port table beginning SMMR 51h,800h 800h data memory. 2-22
Single-Instruction Repeat (RPT) Loops
Example 2-17. Memory-to-Memory Block Moves Using with LMMR
This routine uses LMMR instruction move data from local data memory memory-mapped port. Note that ports mapped data page 'C5x memory map. OUTPUT: ;data page ;Output values from table beginning 800h LMMR 50h,800h data memory port 50h.
Software Applications
2-23
Subroutines
Subroutines
Example 2-18 shows subroutine determine square root 16-bit number. main routine executes point where square root number needed. this point, delayed call (CALLD) made subroutine, transferring control that section program memory execution then returning calling routine delayed return (RETD) instruction when execution completed. Example 2-18 shows several features 'C5x instruction set. particular, note delayed call (CALLD), delayed return (RETD), conditional execute (XC) instructions. four-level-deep pipeline 'C5x devices, normal branch instructions require four cycles execute. Using delayed branches, only cycles required execution. instruction useful where only instructions executed conditionally. this example, notice used avoid extra cycle branch instruction. instruction also helps keeping execution time routine constant, regardless input conditions. This because executes NOPs place instructions conditions met. Note that restore done with instruction prevent from being overwritten. indirect addressing used, order reversed.
Example 2-18. Square Root Computation Using Instruction
Autocorrelation This routine performs correlation vectors then calls Square Root subroutine that will determine amplitude waveform. AUTOC CALLD SQRT ;Call square root subroutine after #0,ST0 ;executing next instructions #1,ST1 ;Get value passed SQRT subroutine Square Root Computation This routine computes square root number that located higher half accumulator. number format. BRCR .set ;DP=0 .set ;Internal block .set 2-24
Subroutines
Example 2-18. Square Root Computation Using Instruction (Continued)
NUMBER .set TEMPR .set GUESS .set .text SQRT LACC SETC SACL LACL SACB SPLK SPLK LACC BCNDD SPLK LACC SACL SACL SPLK LOOP RPTB SQRA LACC SPAC LACC SACB LACC SACH ADDB SACH ENDLP LACB RETD *,AR0 NUMBER #11,BRCR #800h,GUESS NUMBER #200h LOOP,LT #800h,TEMPR #4000h GUESS TEMPR #14,BRCR ENDLP-1 TEMPR NUMBER,16
;Set SXM=1 ;Set mode fractional arithmetic ;Save number ;Clear accumulator buffer ;Initialize iterations ;Set initial guess
NUMBER<200h then begin looping ;Otherwise initial guess ;and temporary root 4000h ;and increase iterations ;Repeat block ;Square temporary root ;Acc=NUMBER-TEMPR**2 ;Dead cycle NUMBER>TEMPR**2 skip next instr. ;Otherwise ROOT TEMPR
2,GT TEMPR,16 GUESS,15 GUESS TEMPR
;GUESS GUESS/2 ;TEMPR GUESS+ROOT ;High contains square root NUMBER
#1,ST1 #0,ST0
;Restore context
Software Applications
2-25
Extended-Precision Arithmetic
Extended-Precision Arithmetic
Numerical analysis, floating-point computations, other operations require arithmetic executed with more than bits precision. Since 'C5x devices 16/32-bit fixed-point processors, software required extended precision arithmetic operations. Subroutines that perform extended-precision arithmetic functions 'C5x provided examples this section. technique consists performing arithmetic parts, similar which longhand arithmetic done. 'C5x several features that help make extended-precision calculations more efficient. features carry bit. carry affected arithmetic operations accumulator, including addition subtraction with accumulator buffer. This allows 32-bit-long arithmetic operations using accumulator buffer second operand. carry also affected rotate shift accumulator instructions. also explicitly modified load status register set/reset control instructions. proper operation, overflow mode should reset (OVM that accumulator result loaded with saturation value.
2.8.1
Addition
carry whenever input scaling shifter, product register (PREG), accumulator buffer value added accumulator contents generates carry from Otherwise, carry reset because carry from exception this case addition accumulator with shift instruction (ADD dma,16), which only carry bit. This allows generate proper single carry when addition either lower upper half accumulator actually causes carry. Figure demonstrates significance carry additions. Example 2-19 page 2-28 shows implementation 64-bit numbers added each other obtain 64-bit result.
2-26
Extended-Precision Arithmetic
Figure 2-1. 32-Bit Addition
(ACC) (ACC)
(ACC)
(ACC)
(ACC)
(ACC)
(ACC) (ADDC)
(ACC) (ADDC)
(ACC) (ADD dma,16)
(ACC) (ADD dma,16)
Software Applications
2-27
Extended-Precision Arithmetic
Example 2-19. 64-Bit Addition
64-bit numbers added each other producing 64-bit result. number (X3, (Y3, added resulting (W3, W0). result required 64-bit ACC/ACCB pair, replace instructions indicated comments below. ----------- -OR- ACCB* ADD64 LACC X1,16 ;ACC ADDS ;ACC ADDS ;ACC Y1,16 ;ACC SACL ;THESE INSTR REPLACED SACH ;"SACB" RESULT DESIRED (ACC ACCB) LACC X3,16 ;ACC ADDC ;ACC ADDS ;ACC Y3,16 ;ACC SACL ;THESE INSTR REQUIRED SACH ;THE RESULT DESIRED (ACC ACCB)
2-28
Extended-Precision Arithmetic
2.8.2
Subtraction
carry reset whenever input scaling shifter, PREG, accumulator buffer value subtracted from accumulator contents generates borrow into Otherwise, carry because borrow into required. exception this case dma,16 instruction, which only reset carry bit. This allows generate proper single carry when subtraction either from lower upper half accumulator actually causes borrow. Figure demonstrates significance carry subtraction. Example 2-20 page 2-30 shows implementation 64-bit numbers subtracted from each other. borrow generated within accumulator each 16-bit parts subtraction operation.
Figure 2-2. 32-Bit Subtraction
(ACC) (ACC)
(ACC)
(ACC)
(ACC)
(ACC)
(ACC) (SUBB)
(ACC) (SUBB)
(ACC) (SUB dma,16)
(ACC) (SUB dma,16)
Software Applications
2-29
Extended-Precision Arithmetic
Example 2-20. 64-Bit Subtraction
64-bit numbers subtracted, producing 64-bit result. number (Y3, subtracted from (X3, resulting (W3, W0). result required 64-bit ACC/ACCB pair, replace instructions indicated comments below. ----------- -OR- ACCB SUB64 LACC X1,16 ADDS SUBS Y1,16 SACL THESE INSTR REPLACED SACH "SACB" RESULT DESIRED (ACC ACCB) LACL SUBB X3,16 Y3,16 SACL THESE INSTR REQUIRED SACH RESULT DESIRED (ACC ACCB)
2.8.3
Multiplication
Another important feature that aids extended-precision calculations MPYU (unsigned multiply) instruction. MPYU instruction allows unsigned 16-bit numbers multiplied 32-bit result placed PREG single cycle. Efficiency gained generating partial products from 16-bit portions 32-bit larger value, instead having split value into 15-bit smaller parts. Further efficiency gained using accumulator buffer hold partial results, instead using temporary location data memory. ability 'C5x devices barrel shift accumulator bits only cycle also useful scaling justifying operands. 16-bit integer multiplication, which operand 2s-complement signed integer other unsigned integer, algorithm shown Figure used.
2-30
Extended-Precision Arithmetic
Figure 2-3. 16-Bit Integer Multiplication Algorithm
Signed integer
Unsigned integer Signed multiplication Final 32-bit result
Steps required: Multiply operands they signed integers. unsigned integer upper half 32-bit signed product. correction factor must added signed multiplication result because weight 16-bit unsigned integer 215. Consider following representation signed integer unsigned integer -215x15 214x14 213x13 21x1 20x0 215y15 214y14 213y13 21y1 20y0 Multiplication yields: (215y15 214y14 213y13 21y1 20y0) 215y15X 214y14X 213y13X 21y1X 20y0X
However, considered signed integers, their multiplication yields: (-215y15 214y14 213y13 21y1 20y0) -215y15X 214y14X 213y13X 21y1X 20y0X
Software Applications
2-31
Extended-Precision Arithmetic
difference between equations first term righthand side equations. Hence, correction term, 216y15X, equation (2), result would identical that equation correct result. This method multiplying signed integer with unsigned integer used implement extended-precision multiplication 'C5x. Figure shows 32-bit multiplication algorithm based this method. Example 2-21 page 2-33 implements this algorithm. product 64-bit integer number. Note BSAR instructions. Example 2-22 page 2-34 performs fractional multiplication. operands format, while product format.
Figure 2-4. 32-Bit Multiplication Algorithm
Unsigned multiplication Signed multiplication Signed multiplication
Signed multiplication
Final 64-bit result
2-32
Extended-Precision Arithmetic
Example 2-21. 32-Bit Integer Multiplication
.title "32-bit Optimized Integer Multiplication" .def MPY32 This routine multiplies 32-bit signed integers resulting 64-bit product. operands fetched from data memory result written back data memory. Data Storage: X1,X0 32-bit operand Y1,Y0 32-bit operand W3,W2,W1,W0 64-bit product Entry Conditions: .set 300h ;DP=6 .set 301h ;DP=6 .set 302h ;DP=6 .set 303h ;DP=6 .set 304h ;DP=6 .set 305h ;DP=6 .set 306h ;DP=6 .set 307h ;DP=6 .text MPY32: X0,0 bit#15 MPYU X0Y0 ;Save ;Save partial X0Y1 ;ACC X0Y1, X1Y0 MPYA ;ACC X0Y1+X1Y0, P=X1Y1 ADDS ;ACC X0Y1+X1Y0+X0Y02^-16 SACL ;Save final BSAR ;Shift right 1,TC ;Add Y0,0 bit#15 APAC ;ACC X1Y1 (X0Y1+X1Y0)2^-16 1,TC ;Add SACL ;Save SACH ;Save
Software Applications
2-33
Extended-Precision Arithmetic
Example 2-22. 32-Bit Fractional Multiplication
.title "32-bit Fractional Multiplication" This routine multiplies signed integers resulting product. operands fetched from data memory result written back data memory. Data Storage: X1,X0 operand Y1,Y0 operand W1,W0 product Entry Conditions: .set 300h ;DP=6 .set 301h ;DP=6 .set 302h ;DP=6 .set 303h ;DP=6 .set 304h ;DP=6 .set 305h ;DP=6 .text X0,0 bit#15 ;TREG0 X0*Y0 ;ACC X0*Y0 X1*Y0 MPYA ;ACC X0*Y0 X1*Y0 BSAR ;Throw away bits 1,TC ;then Y0,0 bit#15 APAC ;ACC X1*Y1 1,TC ;then SACL ;Save lower product SACH ;Save upper product
2-34
Extended-Precision Arithmetic
2.8.4
Division
Integer fractional division implemented 'C5x repeated subtractions executed with SUBC, special conditional subtract instruction. Given 16-bit positive dividend divisor, repetition SUBC command times produces 16-bit quotient accumulator 16-bit remainder high accumulator. SUBC implements binary division same manner long division done (Figure 2-5). dividend shifted until subtracting divisor longer produces negative result. each subtract that does produce negative answer, quotient then shifted. shifting remainder quotient after each subtract produces separation quotient remainder high halves accumulator, respectively. Both dividend divisor must positive when using SUBC command. Thus, sign quotient must determined quotient computed using absolute value dividend divisor. Integer division implemented with SUBC instruction, shown Example 2-23 page 2-37. integer division, absolute value numerator must greater than absolute value denominator. Fractional division also implemented with SUBC instruction shown Example 2-24 page 2-38. When implementing division algorithm, important know quotient represented fraction degree accuracy which quotient computed. fractional division, absolute value numerator must less than absolute value denominator. Note that dividend loaded into high accumulator that only iterations required N-bit fraction.
Software Applications
2-35
Extended-Precision Arithmetic
Figure 2-5. 16-Bit Integer Division
LONG DIVISION: 0000 0000 0110 0000 0000 0000 0101 0000 0010 0001 -101 SUBC METHOD: HIGH COMMENT Dividend loaded into ACC. divisor left-shifted subtracted from ACC. result negative, discard result, shift left bit, replace with REMAINDER QUOTIENT
0000 0000 0000 0000
0000 0000 0010 0001 1000 0000 0000 0000 0111 1111 1101 1111
0000 0000 0000 0000
0000 0000 0100 0010 1000 0000 0000 0000 0111 1111 1011 1110
Second SUBC command. result negative, discard result, shift (dividend) left bit, replace with
0000 0000 0000 0100 0000 0000 0000 0001 0010 0000 0000 0000 1000 0000 0000 0000 1010 0000 0000 0000
(14) 14th SUBC command. result positive. Shift result left replace with
0000 0000 0000 0011 0000 0000 0000 0000
0100 0000 0000 0001 1000 0000 0000 0000 1100 0000 0000 0001
(15) 15th SUBC command. result again positive. Shift result left replace with
0000 0000 0000 0001
1000 0000 0000 0011 1000 0000 0000 0000 -1111 1111 1111 1101
(16) 16th SUBC command. result negative, discard result, shift left bit, replace with
0000 0000 0000 0011 REMAINDER
0000 0000 0000 0110 QUOTIENT
Answer reached after SUBC commands stored ACC.
2-36
Extended-Precision Arithmetic
Example 2-23. 16-Bit Integer Division Using SUBC Instruction
This routine implements integer division with SUBC instruction. this integer division routine, absolute value numerator must greater than absolute value denominator. addition, calling routine must check verify that divisor does equal 16-bit dividend placed accumulator, high accumulator zeroed. divisor data memory. completion last SUBC, quotient division lower-order 16-bits accumulator. remainder higher-order 16-bits. Instruction: RETCD return conditions true after executing next 2-word instruction single-word instructions DENOM .set NUMERA .set QUOT .set .set TEMSGN .set INTDIV NUMERA ;Determine sign quotient. DENOM TEMSGN ;Save sign LACL DENOM ;Make denominator numerator positive. SACL DENOM ;Save absolute value denominator LACL NUMERA divisor dividend aligned, division start here. cycle division. accumulator contains SUBC DENOM ;the quotient high accumulator contains ;the remainder loop. TEMSGN,0 ;Test sign quotient. RETCD ;Return sign positive, else continue. SACL QUOT ;Store quotient remainder during delayed SACH ;return. LACL sign negative, negate quotient return RETD QUOT SACL QUOT
Software Applications
2-37
Extended-Precision Arithmetic
Example 2-24. 16-Bit Fractional Division Using SUBC Instruction
This routine implements fractional division with SUBC instruction. this division routine, absolute value denominator must greater than absolute value numerator. addition, calling routine must check verify that divisor does equal 16-bit dividend placed high accumulator, accumulator zeroed. divisor data memory. DENOM .set NUMERA .set QUOT .set .set TEMSGN .set FRACDIV NUMERA ;Determine sign quotient. DENOM TEMSGN LACL DENOM ;Make denominator numerator positive. SACL DENOM LACC NUMERA,16 ;Load high accumulator, zero accumulator. divisor dividend aligned, division start here. ;15-cycle division. accumulator contains SUBC DENOM ;the quotient high accumulator contains ;remainder loop. TEMSGN,0 ;Test sign quotient. RETCD ;Return sign positive, else continue. SACL QUOT ;Store quotient remainder during delayed SACH ;return.* LACL sign negative, negate quotient return RETD QUOT SACL QUOT
2-38
Floating-Point Arithmetic
Floating-Point Arithmetic
implement floating-point arithmetic 'C5x, operands must converted fixed point arithmetic operations then converted back floating point. Conversion floating-point notation performed normalizing input data. multiply floating-point numbers, mantissas multiplied exponents added. resulting mantissa must renormalized. Floatingpoint addition subtraction requires shifting mantissa that exponents operands match. difference between exponents used left shift lower power operand before adding. Then, output must renormalized. 'C5x instructions used floating-point operations NORM, SATL, SATH, NORM used convert fixed-point numbers floatingpoint numbers. SATL combination with SATH provides 2-cycle through 31-bit right shift. helps avoid extra cycles caused branch instructions. Example 2-25 page 2-40 Example 2-26 page 2-44 show implement floating-point arithmetic 'C5x. Floating-point numbers generally represented mantissa exponent values. Single-precision IEEE floating-point numbers represented 24-bit mantissa, 8-bit exponent, sign bit. order simplify routines, format slightly different from IEEE format used. Four words occupied each floating-point number. sign word, word exponent, words mantissa reserved memory shown examples.
Software Applications
2-39
Floating-Point Arithmetic
Example 2-25. Floating-Point Addition Using SATL SATH Instructions
.title 'Floating Point Addition Algorithm' .def FL_ADD THIS SUBROUTINE ADDS FLOATING-POINT NUMBERS PRODUCING NORMALIZED FLOATING-POINT PRODUCT. FORMAT FLOATING-POINT NUMBERS SPECIFIED BELOW. INPUT OUTPUT FORMAT ===================== ---------------- SIGN WORD ---------------- ---------------- BITS EXPONENT ---------------- ---------------- BITS HIGH PART MANTISSA ---------------- ---------------- BITS PART MANTISSA ---------------- Instructions: SAMM save accumulator contents memory-mapped register LACB accumulator loaded with contents accumulator buffer SACB contents accumulator copied accumulator buffer SATL accumulator barrel-shifted right value specified LSBs TREG1 SATH accumulator barrel-shifted right bits TREG1 one. SPLK store immediate long constant data memory compare long immediate value DBMR) with data memory TC=1 values same TC=0 otherwise TREG1 .set ASIGN .set ;Sign, exponent, high part mantissa AEXP .set input number .set .set BSIGN .set ;Sign, exponent, high part mantissa BEXP .set input number .set .set
2-40
Floating-Point Arithmetic
Example 2-25. Floating-Point Addition Using SATL SATH Instructions (Continued)
CSIGN CEXP DIFFEXP FL_ADD .set .set .set .set .set .text SETC LACL SACB LACC SACL BCND BCND LACC SAMM BCND LACB SATL SATH SACB LACC SACL LACC SACL LACC CLRC SETC BCNDD LACL BCND SPLK SPLK SACH SACL *,AR0 AR0,#0 BHI,16 AEXP BEXP DIFFEXP AEQB,EQ ALTB,LT DIFFEXP TREG1 AGRT32,GEQ ;Sign, exponent, high part mantissa resulting floating point number
CMPEXP
;Initialization ;Set sign extension mode ;ARP ;AR0 used NORM instruction ;Load with ;Add high ;AccB BHIBLO ;Acc AEXP=BEXP ;Save difference ;Load TREG1 with right shifts reqd. difference ;Acc BHIBLO ;Right justify BHIBLO ;Store result back AccB ;Copy sign exponent values (i.e. result)
AGTB
AEQB
CHKSGN
;Acc AHIALO ;Acc=A-B 1,TC ;then Acc=B-A CZERO,EQ 2,LT #0FFFFh,CSIGN ;then CSIGN=-1 2,GT #0,CSIGN ;then CSIGN=0 1,LT A-B<0 ;then Acc=|A-B| NORMAL ;delayed branch ;Save result
ASIGN CSIGN AEXP CEXP ASIGN BSIGN 1,LT ADNOW,EQ AHI,16
;Acc=ASIGN-BSIGN ;Clear flag ;Set flag both have same sign
Software Applications
2-41
Floating-Point Arithmetic
Example 2-25. Floating-Point Addition Using SATL SATH Instructions (Continued)
CZERO LACL SACL SACL RETD SACL SACL ADDB BCNDD SACH SACL BCND LACC LACC ADDS CLRC SBRK SETC NORM SACH SACL LACC RETD SACL CLRC SACH SACL LACC SACL LACC SACL LACC SACL LACC SAMM BCND LACL CEXP CSIGN OVFLOW,OV CZERO,EQ #0,CHI 2,TC CLO,16 AR0,#16 2,NTC CHI,16 2,LT CEXP AR0,CEXP CEXP CEXP CEXP CEXP BSIGN CSIGN BEXP CEXP DIFFEXP TREG1 BGRT32,GEQ AHI,16 ;then result zero ;Make sign positive ;Return delayed ;Clear CHICLO signs same ;then numbers ;Save CHICLO CHICLO zero, goto CZERO ;Compare with ;Dead cycle ;then normalize only part ;AR0 exponent value ;Acc=CHICLO ;Disable sign extension mode ;then shift right once ;and decrement exponent. ;Enable sign extension mode ;Repeat times ;Normalize ;Store high part ;Store part result ;Save exponent ;Return delayed ;CEXP=CEXP-AR0 ;Disable sign extension mode ;Shift right ;Save result ;Increment exponent ;Save ;Copy sign ;Copy exponent
ADNOW
NORMAL
OUTPUT
OVFLOW
ALTB
;since here ;No. shifts reqd. right-justification ;difference exponent ;Acc=AHIALO
2-42
Floating-Point Arithmetic
Example 2-25. Floating-Point Addition Using SATL SATH Instructions (Continued)
SATL SATH SACL SACH LACC SACL RETD LACC SACL LACC SACL LACC SACL LACC SACL RETD LACC SACL ;Right-justify ALOAHI ;Jump back after next instructions ;Save normalized value exponent ;then ;Return after ;saving exponent ;then ;Copy ;Copy ASIGN CSIGN ;Return after ;copying AEXP CEXP
BGRT32
CHKSGN ASIGN CSIGN AEXP CEXP
AGRT32
Software Applications
2-43
Floating-Point Arithmetic
Example 2-26. Floating-Point Multiplication Using BSAR Instruction
.title 'Floating Point Multiplication Routine' THIS SUBROUTINE MULTIPLIES FLOATING-POINT NUMBERS PRODUCING NORMALIZED FLOATING-POINT PRODUCT. FORMAT FLOATING- POINT NUMBERS SPECIFIED BELOW. INPUT OUTPUT FORMAT ===================== ---------------- SIGN WORD ---------------- ---------------- BITS EXPONENT ---------------- ---------------- BITS HIGH PART MANTISSA ---------------- ---------------- BITS PART MANTISSA ---------------- NOTE THAT EVEN PRODUCT ZERO, SIGN PRODUCT EITHER POSITIVE NEGATIVE DEPENDING INPUTS. Instructions: BSAR 1-16 right barrel arithmetic shift cycle CLRC reset control SETC control branch after executing next one-word instructions two-word instruction ASIGN .set ;Sign, exponent, high parts mantissa AEXP .set input number .set .set BSIGN .set ;Sign, exponent, high parts mantissa BEXP .set input number .set .set CSIGN .set ;Sign, exponent, high parts mantissa CEXP .set resulting floating point number .set .set 2-44
Floating-Point Arithmetic
Example 2-26. Floating-Point Multiplication Using BSAR Instruction (Continued)
MULT .text *,AR0 AR0,#0 LACC AEXP BEXP SACL CEXP CLRC MPYU MPYU MPYA BSAR APAC BCND NZERO,NEQ SACH SIGN SACL SACL CEXP NORM SACH SACL SETC LACC CEXP AR0,CEXP CEXP SACL CEXP LACL ASIGN RETD BSIGN SACL CSIGN
;ARP ;Reset exponent counter left shift register
;CEXP AEXP BEXP ;for barrel shift, disable sign extension ALO*BHI ;Acc=ALO*BHI, T=AHI ;P=AHI*BLO ;Acc=ALO*BHI AHI*BLO, P=AHI*BHI ;Retain upper bits plus additional ;bit zero MSBs product zero product zero ;then clear CHI,CLO CEXP ;and jump SIGN ;Discard additional sign (Q63) ;Remove leading zero ;Save product ;Enable sign extension mode ;CEXP<-AR0 ;CEXP=CEXP-AR0 signs same then product ;Return after next instructions ;otherwise -ve.
NZERO
SIGN
Software Applications
2-45
Application-Oriented Operations
2.10 Application-Oriented Operations
following subsections provide application-oriented operations for:
modem applications adaptive filtering infinite impulse response (IIR) filters dynamic programming
2.10.1 Modem Application
Digital signal processors especially appropriate modem applications. 'C5x devices with their enhanced instruction reduced instruction cycle time particularly effective implementing encoding decoding algorithms. Features like circular addressing, repeat block, single-cycle barrel shift reduce execution time such routines. Example 2-27 page 2-47 shows differential convolutional encoder 9600-bit/second V.32 modem. This encoder uses trellis coding with carrier states. data stream transmitted divided into groups four consecutive data bits. first bits time each group differentially encoded into according following equations: Y1n-1 (Q1n Y1n-1) Y2n-1 This done subroutine called DIFF. differentially encoded bits used inputs convolutional encoder subroutine ENCODE, which generates redundant Y0n. These five bits packed into single word PACK subroutine.
2-46
Application-Oriented Operations
Example 2-27. V.32 Encoder Using Accumulator Buffer
.title 'Convolutional Encoding V.32 Modem' .mmregs STATMEM INPUT YPAST OUTPUT LOCATE PCKD_IP PCKD_OP COUNT INIT .set .set .set .set .set .set 1000h .set 2000h .set .text AR1,#PCKD_IP AR2,#PCKD_OP AR3,#COUNT-1 *,AR1 LACC *+,0,AR0 SACL LOCATE AR0,#INPUT+3 LACL SAMM BRCR LACL SAMM DBMR LACC LOCATE RPTB LOOP1-1 SACL CALL CALL LACL SAMM LACC RPTB SACL BANZ DIFF ENCODE AR0,#INPUT BRCR LOOP2-1 ;(60h 62h) Delay States S1,S2,S3 ;(64h 67h) Four input bits ;(68h 69h) Past values ;Y0, redundant ;Temporary storage current input word ;Input buffer bits packed word) ;Output buffer bits packed word) input data words
;COUNT contains input words
START
;Temporary storage current input word ;Loop times
UNPACK
;Load DBMR with mask ;Acc packed input bits ;for I=0,I<=3,I++ ;Save ;Mask bits except ;Shift right next ;Call differential encoder ;Call convolutional encoder ;Loop times only ;Get first (MSB) ;for I=0,I<=2,I++ ;make space left-shifting once ;Pack next left-shifting other
LOOP1
PACK
LOOP2 *,AR2 *+,0,AR3 START ;ARP ;Save packed form ;Loop COUNT zero ;Return
Software Applications
2-47
Application-Oriented Operations
Example 2-27. V.32 Encoder Using Accumulator Buffer (Continued)
This subroutine differentially encodes (INPUT buffer) according previous output values Y1n-1 Y2n-1 (YPAST buffer). resulting values overwrite previous Q2n. DIFF LACC YPAST ;Acc=Y1n-1 INPUT ;Q1n Y1n-1 INPUT+1 ;(Q1n Y1n-1) YPAST+1 ;(Q1n Y1n-1) Y2n-1 SACL INPUT+1 SACL YPAST+1 ;Save LACC YPAST INPUT ;Q1n Y1n-1 RETD ;Delayed return SACL INPUT ;Save SACL YPAST ;save Y1n-1 This subroutine generates redundant convolutional encoding, taking input. Three delay states located STATMEM buffer. ENCODE LACC STATMEM SACL OUTPUT LACC INPUT+1 STATMEM+1 SACB ;Save AccB LACC OUTPUT INPUT XORB ;(Y0 SACL STATMEM ;Save LACC OUTPUT ANDB SACB LACC INPUT INPUT+1 STATMEM+2 ;(Y1 XORB ;((Y1 S2)) SACL STATMEM+1 ;Update RETD ;Delayed return LACC OUTPUT SACL STATMEM+2 ;Update
2-48
Application-Oriented Operations
2.10.2 Adaptive Filtering
There many practical applications adaptive filtering; example adapting updating coefficients. This become computationally expensive time-consuming. MPYA, ZALR, RPTB instructions 'C5x reduce execution time. means adapting coefficients 'C5x least-mean-square algorithm given following equation:
2Be(i)x(i-k)
where x(i) y(i) y(i)
kx(i-k)
Quantization errors updated coefficients minimized result obtained rounding rather than truncating. each coefficient filter given point time, factor 2Be(i) constant. This factor then computed once stored TREG0 each updates. MPYA ZALR instructions help reducing number instructions main adaptation loop. Furthermore, RPTB (repeat block) instruction allows block instructions repeated without penalty looping. Example 2-28 page 2-50 shows routine that implements 128-tap finite impulse response (FIR) filter adaptation coefficients. SARAM 'C5x mapped both program data spaces same time setting OVLY control flags This feature used locate coefficient table SARAM that table accessed MACD instructions without modifying configuration. Note that MACD instruction requires operands program space. address coefficient table determined runtime, load BMAR (block move address register) with address computed dynamically replace instruction MACD COEFFP,*- with MADD
Software Applications
2-49
Application-Oriented Operations
Example 2-28. Adaptive Filter Using RPTB Instructions
.title 'Adaptive Filter' .def ADPFIR .def .mmregs This 128-tap adaptive filter uses on-chip memory block coefficients block data samples. newest input should memory location when called. output will memory location when returned. OVLY when this routine called. COEFFP .set 02000h ;Program memory address coeff. COEFFD .set 02000h ;Data memory address coeff. 'C51,'C53,'C56,'C57, COEFFD 0800h instead 02000h .set ;Constant one. (DP=0). BETA .set ;Adaptation constant. (DP=0). .set ;Signal error. (DP=0). ERRF .set ;Error function. (DP=0). .set ;Filter output. (DP=0). .set 037Fh ;Newest data sample. FRSTAP .set 0380h ;Next newest data sample. LASTAP .set 03FFh ;Oldest data sample. Finite impulse response (FIR) filter. ADPFIR ;Clear register. LACC #1,14 ;Load output rounding bit. *,AR3 AR3,#LASTAP ;Point oldest sample. #127 MACD COEFFP,*- ;128-tap filter. APAC SACH ;Store filter output. ;Acc -y(n) AR3,#X *,15 ;Add newest input sample. SACH ERR,1 ;err(n) x(n) y(n) DMOV ;Include newest sample Adaption Filter Coefficients. BETA beta*err(i) ;errf(i) beta err(i) ONE,14 ;Round results. SACH ERRF,1 ;Save errf(i) LACC #126 SAMM BRCR ;127 coefficients update loop. AR2,#COEFFD ;Point coefficients. AR3,#LASTAP+1 ;Point data samples. 2-50
Application-Oriented Operations
Example 2-28. Adaptive Filter Using RPTB Instructions (Continued)
ADAPT SACH LOOP ZALR RETD APAC SACH *,AR3 RPTB ZALR MPYA LOOP-1 *,AR3 *-,AR2 ;For I=0,I<=126,I++ ;Load ACCH with ak(i). 2*beta*err(i)*x(i-k-1) ak(i) 2*beta*err(i)*x(i-k) ;Store ak(i+1) ;Finally update last coeff. a0(i) ;Delayed return ;Acc a0(i) 2*beta*err(i)*x(i) ;Save a0(i+1) ERRF *-,AR2 2*beta*err(i)*x(i-255)
Software Applications
2-51
Application-Oriented Operations
2.10.3 Infinite Impulse Response (IIR) Filters
Infinite impulse response (IIR) filters widely used digital signal processing applications. transfer function filter given H(z)
Y(z) X(z)
Figure shows block diagram Nth-order, direct-form, type filter. time domain, Nth-order filter represented following difference equations: time interval x(n) current input sample y(n) output filter d(n) x(n) 1)a1 1)aN y(n) d(n)b0 1)b1 1)bN equations above easily implemented 'C5x using multiply-accumulate instructions (MAC, MACD, MADS, MADD). Note that second equation also requires data-move operation update state variable sequence d(n). Example 2-29 page 2-53 implements Nth-order filter using single-instruction repeat (RPT) multiply-accumulate (MAC, MACD) instructions.
Figure 2-6. Nth-Order, Direct-Form, Type Filter
d(n) x(n)
y(n)
-aN-1
bN-1
2-52
Application-Oriented Operations
Example 2-29. Nth-Order Filter Using MACD Instructions
.title "Nth Order Type Filter" .mmregs This routine implements N-th order type filter. d(n) x(n) d(n-1)a1 d(n-2)a2 d(n-N+1)aN-1 y(n) d(n)b0 (dn-1)b1 d(n-N+1)bN-1 Memory Requirement: State variables (low high data memory): d(n) d(n-1) d(n-N+1) Coefficient (low high program memory): -a(N-1) -a(N-2) -a(1) b(N-1) b(N-2) b(1) b(0) Entry Conditions: Input d(n-N+1) Output COEFFA -a(N-1) COEFFB b(N-1) IIR_N: ;Clear register LACC *,15,AR1 ;Get input #(N-2) ;For i=1,i<=N-1,++i COEFFA,*- ;Acc+=-a(N-i))*d(n-N+i) APAC ;Final accumulation SACH ;Save d(n) ADRK ;AR1 d(n-N+1) LAMM BMAR ;Acc a(N-1) #N-1 ;Acc b(N-1) SAMM BMAR ;BMAR b(N-1) RPTZ #(N-1) ;For i=1,i<=N,++i MACD COEFFB,*- ;Acc+=b(N-i)*d(n-N+i) *,AR2 ;Final accumulation SACH ;Save
recursive nature filter, quantization filter coefficients cause significant variation from desired frequency response. avoid this problem, desired filter transfer function broken into lower order sections that cascaded with each other. Example 2-30 page 2-54 shows implementation cascaded second-order sections (also called biquad sections). filter coefficients state variables stored data memory. Note MPYA instructions perform multiply-accumulate data-move operations.
Software Applications
2-53
Application-Oriented Operations
Example 2-30. Cascaded BiQuad Filter Using MPYA Instructions
.title Cascaded BiQuad Filters" .mmregs This routine implements cascaded blocks biquad canonic type filters. Each biquad requires data memory locations d(n),d(n-1),d(n-2), coefficients -a1,-a2,b0,b1,b2. each block: d(n) x(n)-d(n-1)a1-d(n-2)a2 y(n) d(n)b0+d(n-1)b1+d(n-2)b2 Coefficients Storage (low high data memory): -a2,-a1,b2,b1,b0, ,-a2,-a1,b2,b1,b0 biquad biquad State Variables (low high data memory): d(n),d(n-1),d(n-2), ,d(n),d(n-1),d(n-2) biquad biquad Entry Conditions: d(n-2) biquad biquad input sample (Q15 number) output sample (Q15 number) BIQUAD: ;Setup variables ;Clear register LACC *,15,AR1 ;Get input SPLK #2,INDX ;Setup index register SPLK #N-1,BRCR ;Setup count ;Begin computation; RPTB ELOOP-1 ;Repeat biquads LOOP: *-,AR2 d(n-2) MPYA *+,AR1 ;Acc x(n), -d(n-2)a2 *-,AR2 ;Acc -d(n-2)a2, d(n-1) -d(n-1)a1 *+,AR1 ;Acc -d(n-1)a1, SACH *0+,1 ;Save d(n) d(n-2)b2 LACL ;Acc *-,AR2 d(n-1), d(n-2) d(n-1) *+,AR1 ;Acc d(n-2)b2, d(n-1)b1 *-,AR2 d(n), d(n-1) d(n) *+,AR1 ;Acc d(n-1)b1, d(n)b0 ELOOP: *,AR4 ;Final accumulation SACH ;Save output format 2-54
Application-Oriented Operations
2.10.4 Dynamic Programming
Dynamic programming techniques widely used optimal search algorithms. Applications such speech recognition, telecommunications, robotics dynamic programming algorithms. 'C5x devices have enhanced instruction efficient implementation dynamic programming methods. Most real-time search algorithms basic dynamic programming principle that final optimal path from start state goal state always passes through optimal path from start state intermediate state. Identifying intermediate paths reduces long, time-consuming search final goal. integral part optimal search scheme based dynamic programming principle backtracking operation. backtracking necessary retrace optimal path when goal state reached. Example 2-31 page 2-56 shows implementation backtracking algorithm which path history consists four independent path traces time periods. This path history stored circular buffer. After each backtracking operation, path history updated search algorithm (not shown) next time period. path history buffer shown Figure equal Each group four consecutive memory locations buffer corresponds expansion four paths node time period). Each element group corresponds four states that time period. addition, each element group points element previous time period that belongs that path. Using path history buffer shown Figure 2-7, element corresponding state current time period contains This points second element previous time period that contains this way, beginning from current time period using pointers step back time, this path traced back 1-0-2-1. Note that this simplified backtracking approach taken here illustrate 'C5x programming techniques. Most real applications would require more complex backtracking algorithms.
Software Applications
2-55
Application-Oriented Operations
Example 2-31. Backtracking Algorithm Using Circular Addressing
Backtracking Example This program back-tracks optimal path expanded dynamic programming algorithm. path history consists four paths expanded times. circular buffer length N*4. Note that decrement type circular buffer used. start address circular buffer initialized this because reasons: avoid skipping end-address circ buffer ensure that wrap-around complete before next iteration.
AR0,#BUFFER ;Get buffer address LMMR INDX,PATH ;Get selected path [0.3] SPLK #N-1,BRCR ;Trace back time periods init. pointer circular buffer#1; length=N*4 words SPLK #BUFFER+(N-1)*4,CBSR1 SPLK #BUFFER-3,CBER1 SPLK #08h,CBCR RPTB TLOOP-1 ;For i=0,i<N,i++ ;Offset state# LACC ;Get next pointer reset state#0 SAMM INDX ;Save next state# SBRK ;Decrement avoid skipping CBER1 SBRK ;Now correctly positioned time TLOOP: ;period back (circular addressing)
Figure 2-7. Backtracking With Path History
State Current time period
Path trace five periods Buffer
Buffer
Current time period Path history circular buffer
2-56
Fast Fourier Transforms
2.11 Fast Fourier Transforms
Fourier transforms important tool often used digital signal processing systems. purpose transform convert information from time domain frequency domain. inverse Fourier transform converts information back time domain from frequency domain. Computationally efficient implementations Fourier transforms known fast Fourier transforms (FFT). 'C5x reduces execution time FFTs virtue 50-ns instruction cycle time. Also, bit-reversed addressing mode helps reduce execution time radix-2 FFTs. demonstrated Figure Figure 2-9, inputs outputs sequential order. This scrambling data locations direct result radix-2 derivation. Observation figures relationship input output addressing reveal that address indexing bit-reversed order, shown Table 2-3. result, either input data sequence output data sequence must scrambled association with execution FFT. Example 2-32 page 2-59, input data scrambled before execution algorithm that output order.
Figure 2-8. In-Place With In-Order Outputs Bit-Reversed Inputs
Stage x(0) x(4) x(2) x(6) x(1) x(5) x(3) x(7) x(7) x(6) Stage Stage x(0) x(1) x(2) x(3) x(4) x(5)
Legend twiddle factor
Software Applications
2-57
Fast Fourier Transforms
Figure 2-9. In-Place With In-Order Inputs Bit-Reversed Outputs
Stage x(0) x(4) x(2) x(6) x(1) x(5) x(3) x(7) x(6) x(7) Stage Stage x(0) x(1) x(2) x(3) x(4) x(5)
Legend twiddle factor
Table 2-3. Bit-Reversal Algorithm 8-Point Radix-2
Index Pattern Bit-Reversed Pattern Bit-Reversed Index
2-58
Fast Fourier Transforms
Example 2-32. 16-Point Radix-2 Complex
.file .title .width .set .mmregs .set "c5cx0016.asm" "0016 point Radix-2, Complex FFT" ;NUMBER POINTS
pmstmask 0110b ;ndx=trm=1 POINT COMPLEX, RADIX-2 WITH TMS320C5x LOOPED CODE PROGRAM BASED BOOK 'DIGITAL SIGNAL PROCESSING APPLICATIONS' FROM TEXAS INSTRUMENTS OPTIMIZED TMS320C5x INCLUDING REVERSAL ADDRESSING MODE. USED REGISTERS: PMST, BRCR Stacklevel, Block temp variables PROGRAM MEMORY: WORDS ('END' 'FFT') WITHOUT INITIALIZATION COEFFICIENTS BITS (Q15 Format) SCALING: 1/2^4 PROGRAM SEQUENCE:0. INITIALIZATION FFT/COEFF ADD: 240H 20BH INPUT DATA INTO 'INPUT' ADD: 220H 23FH CALL SUBROUTINE ADD: 600H 6A3H 2.1. BITREVERSAL FROM INPUT DATA ADD: 200H 21FH 2.2. WITH WORK SPACE DATA ADD: 200H 21FH OUTPUT RESULTS FROM DATA ADD: 200H 21FH INPUT DATA ADDRESS 0220h-023fh: DATA STORED 'INPUT' SEQUENCE: X(0),X(1),.,X(15) Y(0),Y(1),.,Y(15) OUTPUT DATA ADDRESS 0200h-021fh: DATA STORED 'DATA' SEQUENCE: X(0),Y(0),X(1),Y(1),. ,X(15),Y(15) THIS PROGRAM INCLUDES FOLLOWING FILE: FILE 'TWIDDLES.Q15' CONSISTS TWIDDLE FACTORS FORMAT FILE 'C5CXRAD2.MAC' macro files FILE 'INIT-FFT.ASM' initialization
Software Applications
2-59
Fast Fourier Transforms
Example 2-32. 16-Point Radix-2 Complex (Continued)
.include .def .def .def .sect "twiddles" table twiddle factors TWIDSTRT .set .include twiddles.q15 TWIDEND .set TWIDLEN .set TWIDEND-TWIDSTRT INPUT .usect "input",N*2 ;input data array DATA .usect "data",N*2 ;working data array TWID .usect "twid",N*2 ;reserve space twiddles .include init-fft.asm .sect "fftprogram" CODE WITH BIT-REVERSED INPUT SAMPLES ARP=AR3 FFT: AR3,DATAADD ;TRANSFER WORDS FROM 'input' 'data' LACC SAMM INDX ;indexregister=7 TIMES BLDD #INPUT,*BR0+ CODE STAGES STAGE1: SPLK #7,INDX ;index register AR1,DATAADD ;pointer DATA r1,i1 AR2,#DATA+2 ;pointer DATA r2,i2 AR3,#DATA+4 ;pointer DATA r3,i3 AR4,#DATA+6
Other recent searches
SDB1204 - SDB1204 SDB1204 Datasheet
MPBG041 - MPBG041 MPBG041 Datasheet
GMS99C58 - GMS99C58 GMS99C58 Datasheet
CRO2570A-LF - CRO2570A-LF CRO2570A-LF Datasheet
CLV0872A-LF - CLV0872A-LF CLV0872A-LF Datasheet
AN7734 - AN7734 AN7734 Datasheet
2N6486 - 2N6486 2N6486 Datasheet
2N6487 - 2N6487 2N6487 Datasheet
2N6488 - 2N6488 2N6488 Datasheet
2N6489 - 2N6489 2N6489 Datasheet
2N6490 - 2N6490 2N6490 Datasheet
2N6491 - 2N6491 2N6491 Datasheet
2N3906 - 2N3906 2N3906 Datasheet
MAX6640 - MAX6640 MAX6640 Datasheet
MAX6640EVCMOD2 - MAX6640EVCMOD2 MAX6640EVCMOD2 Datasheet
MAX6640EVKIT - MAX6640EVKIT MAX6640EVKIT Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
