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TMS320C54x Reference
Volume Peripherals
Literature Number: SPRU131C Manufacturing Part Number: D425004-9761 revision October 1996
IMPORTANT NOTICE Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used.
Copyright 1996, Texas Instruments Incorporated
Preface
Read This First
About This Manual
TMS320C54x fixed-point digital signal processor (DSP) TMS320 family. This book first volume 4-volume serves reference TMS320C54x provides information developing hardware software applications using '54x. Unless otherwise specified, references '54x apply TMS320C54x, well TMS320LC54x TMS320VC54x.
This Manual
following table summarizes '54x information contained this book:
looking information about: Addressing modes Turn these chapters: Chapter Data Addressing Chapter Program Memory Addressing Boot loader Buffered serial port structure Clock generator Chapter Memory Chapter Serial Ports Chapter Architectural Overview Chapter Architectural Overview Chapter On-Chip Peripherals architecture Chapter Architectural Overview Chapter Central Processing Unit External Hold mode Host port interface Interrupts Chapter External Operation Chapter External Operation Chapter On-Chip Peripherals Chapter Program Memory Addressing
This Manual
looking information about: Memory
Turn these chapters: Chapter Architectural Overview Chapter Memory
On-chip peripherals Overview '54x Parallel Ports
Chapter On-Chip Peripherals Chapter Introduction Chapter Architectural Overview Chapter On-Chip Peripherals
Power-down modes Program control Pipeline latencies
Chapter Program Memory Addressing Chapter Program Memory Addressing Chapter Architectural Overview Chapter Pipeline
Reset code submission Serial ports Status registers
Chapter Program Memory Addressing Appendix Submitting Codes Chapter Serial Ports Chapter Central Processing Unit Appendix Peripheral Registers
serial port Timer
Chapter Serial Ports Chapter Architectural Overview Chapter On-Chip Peripherals
Wait-state generator
Chapter Architectural Overview Chapter On-Chip Peripherals
Notational Conventions Information About Cautions
Notational Conventions
This book uses following conventions.
TMS320C54x either forms instruction set:
mnemonic form algebraic form. This book uses mnemonic form instruction set. information about mnemonic form instruction set, TMS320C54x Reference Set, Volume Mnemonic Instruction Set. information about algebraic form instruction set, TMS320C54x Reference Set, Volume Algebraic Instruction Set.
Program listings program examples shown special
typeface. Here segment program listing:
RSBX A,*AR1+ INMAIN_PG ;Int_RAM(I)=0 ;Globally enable interrupts ;Return foreground program
Square brackets, identify optional parameter.
optional parameter, specify information within brackets; type brackets themselves.
Information About Cautions
This book contains cautions.
This example caution statement. caution statement describes situation that could potentially damage your software equipment.
information caution provided your protection. Please read each caution carefully.
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Related Documentation From Texas Instruments
Related Documentation from Texas Instruments
following books describe '54x related support tools. obtain copy these documents, call Texas Instruments Literature Response Center (800) 477-8924. When ordering, please identify book title literature number. TMS320C54x Reference (literature number SPRU210) composed four volumes information, each with literature number individual ordering.
TMS320C54x Reference Set, Volume Peripherals (literature number SPRU131) describes TMS320C54x 16-bit, fixed-point, general-purpose digital signal processors. Covered architecture, internal register structure, data program addressing, instruction pipeline, DMA, on-chip peripherals. Also includes development support information, parts lists, design considerations using XDS510 emulator. TMS320C54x Reference Set, Volume Mnemonic Instruction (literature number SPRU172) describes TMS320C54x digital signal processor mnemonic instructions individually. Also includes summary instruction classes cycles. TMS320C54x Reference Set, Volume Algebraic Instruction (literature number SPRU179) describes TMS320C54x digital signal processor algebraic instructions individually. Also includes summary instruction classes cycles. TMS320C54x Reference Set, Volume Applications Guide (literature number SPRU173) describes software hardware applications TMS320C54x digital signal processor. Also includes development support information, parts lists, design considerations using XDS510 emulator. TMS320C54x, TMS320LC54x, TMS320VC54x Fixed-Point Digital Signal Processors (literature number SPRS039) data sheet contains electrical timing specifications these devices, well signal descriptions pinouts available packages. TMS320C54x DSKplus User's Guide (literature number SPRU191) describes TMS320C54x digital signal processor starter (DSK), which allows execute custom 'C54x code real time debug line line. Covered installation procedures, description debugger assembler, customized applications, initialization routines.
Related Documentation From Texas Instruments
TMS320C54x Assembly Language Tools User Guide (literature number SPRU102) describes assembly language tools (assembler, linker, other tools used develop assembly language code), assembler directives, macros, common object file format, symbolic debugging directives 'C54x generation devices.
TMS320C5xx Source Debugger User's Guide (literature number SPRU099) tells invoke 'C54x emulator, EVM, simulator versions source debugger interface. This book discusses various aspects debugger interface, including window management, command entry, code execution, data management, breakpoints. also includes tutorial that introduces basic debugger functionality. TMS320C54x Code Generation Tools Getting Started Guide (literature number SPRU147) describes install TMS320C54x assembly language tools compiler 'C54x devices. installation MS-DOSTM, OS/2TM, SunOSTM, SolarisTM, HP-UX9.0x systems covered. TMS320C54x Evaluation Module Technical Reference (literature number SPRU135) describes 'C54x EVM, features, design details external interfaces. TMS320C54x Optimizing Compiler User's Guide (literature number SPRU103) describes 'C54x compiler. This compiler accepts ANSI standard source code produces TMS320 assembly language source code 'C54x generation devices. TMS320C54x Simulator Getting Started (literature number SPRU137) describes install TMS320C54x simulator source debugger 'C54x. installation MS-DOSTM, PC-DOSTM, SunOSTM, SolarisTM, HP-UXsystems covered. TMS320 Third-Party Support Reference Guide (literature number SPRU052) alphabetically lists over third parties that provide various products that serve family '320 digital signal processors. myriad products applications offered-software hardware development tools, speech recognition, image processing, noise cancellation, modems, etc. TMS320 Development Support Reference Guide (literature number SPRU011) describes TMS320 family digital signal processors tools that support these devices. Included code-generation tools (compilers, assemblers, linkers, etc.) system integration debug tools (simulators, emulators, evaluation modules, etc.). Also covered available documentation, seminars, university program, factory repair exchange.
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Technical Articles
Technical Articles
wide variety related documentation available digital signal processing. These references fall into following application categories:
General-Purpose Graphics/Imagery Speech/Voice Control Multimedia Military Telecommunications Automotive Consumer Medical Development Support
following list, references appear alphabetical order according author. documents contain beneficial information regarding designs, operations, applications signal-processing systems; documents provide additional references. Texas Instruments strongly suggests that refer these publications.
General-Purpose DSP:
Chassaing, Horning, D.W., "Digital Signal Processing with Fixed Floating-Point Processors" CoED, USA, Volume Number pages 1-4, March 1991. Defatta, David Joseph Lucas, William Hodgkiss, Digital Signal Processing: System Design Approach, York: John Wiley, 1988. Erskine, Magar, "Architecture Applications Second-Generation Digital Signal Processor," Proceedings IEEE International Conference Acoustics, Speech, Signal Processing, USA, 1985. Essig, Erskine, Caudel, Magar, Second-Generation Digital Signal Processor," IEEE Journal Solid-State Circuits, USA, Volume SC-21, Number pages 86-91, February 1986. Frantz, Lin, Reimer, Bradley, "The Texas Instruments TMS320C25 Digital Signal Microcomputer," IEEE Microelectronics, USA, Volume Number pages 10-28, December 1986.
viii
Technical Articles
Gass, Tarrant, Richard, Pawate, Gammel, Rajasekaran, Wiggins, Covington, "Multiple Digital Signal Processor Environment Intelligent Signal Processing," Proceedings IEEE, USA, Volume Number pages 1246-1259, September 1987. Jackson, Leland Digital Filters Signal Processing, Hingham, Kluwer Academic Publishers, 1986. Jones, D.L., T.W. Parks, Digital Signal Processing Laboratory Using TMS32010, Englewood Cliffs, Prentice-Hall, Inc., 1987. Lim, Jae, Alan Oppenheim, Advanced Topics Signal Processing, Englewood Cliffs, Prentice- Hall, Inc., 1988. Lin, Frantz, Simar, Jr., "The TMS320 Family Digital Signal Processors," Proceedings IEEE, USA, Volume Number pages 1143-1159, September 1987. Lovrich, Reimer, Advanced Audio Signal Processor" Digest Technical Papers 1991 International Conference Consumer Electronics, June 1991. Magar, Essig, Caudel, Marshall Peters, NMOS Digital Signal Processor with Multiprocessing Capability," Digest IEEE International Solid-State Circuits Conference, USA, February 1985. Oppenheim, Alan R.W. Schafer, Digital Signal Processing, Englewood Cliffs, Prentice-Hall, Inc., 1975 1988. Papamichalis, P.E., C.S. Burrus, "Conversion Digit-Reversed Bit-Reversed Order Algorithms," Proceedings ICASSP USA, pages 984-987, 1989. Papamichalis, Simar, Jr., "The TMS320C30 Floating-Point Digital Signal Processor," IEEE Micro Magazine, USA, pages 13-29, December 1988. Papamichalis, P.E., "FFT Implementation TMS320C30," Proceedings ICASSP USA, Volume page 1399, April 1988. Parks, T.W., C.S. Burrus, Digital Filter Design, York, John Wiley Sons, Inc., 1987. Peterson, Zervakis, Shehadeh, "Adaptive Filter Design Implementation Using TMS320C25 Microprocessor" Computers Education Journal, USA, Volume Number pages 12-16, July-September 1993.
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Technical Articles
Prado, Alcantara, Fast Square-Rooting Algorithm Using Digital Signal Processor," Proceedings IEEE, USA, Volume Number pages 262-264, February 1987. Rabiner, L.R. Gold, Theory Applications Digital Signal Processing, Englewood Cliffs, Prentice-Hall, Inc., 1975. Simar, Jr., Davis, "The Application High-Level Languages Single-Chip Digital Signal Processors," Proceedings ICASSP USA, Volume page 1678, April 1988. Simar, Jr., Leigh, Koeppen, Leach, Potts, Blalock, MFLOPS Digital Signal Processor: First Supercomputer Chip," Proceedings ICASSP USA, Catalog Number 87CH2396-0, Volume pages 535-538, April 1987. Simar, Jr., Reimer, "The TMS320C25: CMOS VLSI Digital Signal Processor," 1986 Workshop Applications Signal Processing Audio Acoustics, September 1986. Texas Instruments, Digital Signal Processing Applications with TMS320 Family, 1986; Englewood Cliffs, Prentice-Hall, Inc., 1987. Treichler, J.R., C.R. Johnson, Jr., M.G. Larimore, Practical Guide Adaptive Filter Design, York, John Wiley Sons, Inc., 1987.
Graphics/Imagery:
Reimer, Lovrich, "Graphics with TMS32020," WESCON/85 Conference Record, USA, 1985.
Speech/Voice:
DellaMorte, Papamichalis, "Full-Duplex Real-Time Implementation FED-STD-1015 LPC-10e Standard V.52 TMS320C25," Proceedings SPEECH TECH pages 218-221, 1989. Gray, A.H., J.D. Markel, Linear Prediction Speech, York, Springer-Verlag, 1976. Frantz, G.A., K.S. Lin, Low-Cost Speech System Using TMS320C17," Proceedings SPEECH TECH '87, pages 25-29, April 1987. Papamichalis, Lively, "Implementation Standard LPC-10/52E TMS320C25," Proceedings SPEECH TECH '87, pages 201-204, April 1987.
Technical Articles
Papamichalis, Panos, Practical Approaches Speech Coding, Englewood Cliffs, Prentice-Hall, Inc., 1987. Pawate, B.I., G.R. Doddington, "Implementation Hidden Markov Model-Based Layered Grammar Recognizer," Proceedings ICASSP USA, pages 801-804, 1989. Rabiner, L.R., R.W. Schafer, Digital Processing Speech Signals, Englewood Cliffs, Prentice-Hall, Inc., 1978. Reimer, J.B. K.S. Lin, "TMS320 Digital Signal Processors Speech Applications," Proceedings SPEECH TECH '88, April 1988. Reimer, J.B., M.L. McMahan, W.W. Anderson, "Speech Recognition Low-Cost System Using DSP," Digest Technical Papers 1987 International Conference Consumer Electronics, June 1987.
Control:
Ahmed, "16-Bit Microcontroller Fits Motion Control System Application," PCIM, October 1988. Ahmed, "Implementation Self Tuning Regulators with TMS320 Family Digital Signal Processors," MOTORCON '88, pages 248-262, September 1988. Allen, Pillay, "TMS320 Design Vector Current Control Motor Drives" Electronics Letters, Volume Number pages 2188-2190, November 1992. Panahi, Restle, "DSPs Redefine Motion Control" Motion Control Magazine, December 1993. Lovrich, Troullinos, Chirayil, All-Digital Automatic Gain Control," Proceedings ICASSP USA, Volume page 1734, April 1988. Ahmed, Meshkat, "Using DSPs Control," Control Engineering, February 1988. Meshkat, Ahmed, "Using DSPs Induction Motor Drives," Control Engineering, February 1988. Matsui, Shigyo, "Brushless Motor Control Without Position Speed Sensors" IEEE Transactions Industry Applications, USA, Volume Number Part pages 120-127, January-February 1992. Hanselman, "LQG-Control Highly Resonant Disc Drive Head Positioning Actuator," IEEE Transactions Industrial Electronics, USA, Volume Number pages 100-104, February 1988.
Read This First
Technical Articles
Bose, B.K., P.M. Szczesny, Microcomputer-Based Control Simulation Advanced Synchronous Machine Drive System Electric Vehicle Propulsion," Proceedings IECON '87, Volume pages 454-463, November 1987. Ahmed, Lindquist, "Digital Signal Processors: Simplifying High-Performance Control," Machine Design, September 1987.
Multimedia:
Reimer, "DSP-Based Multimedia Solutions Lead Enhancing Audio Compression Performance" Dobbs Journal, December 1993. Reimer, Benbassat, Bonneau Jr., "Application Processors: Making Multimedia Happen" Silicon Valley Design Conference, July 1991.
Military:
Papamichalis, Reimer, "Implementation Data Encryption Standard Using TMS32010," Digital Signal Processing Applications, 1986.
Telecommunications:
Ahmed, Lovrich, "Adaptive Line Enhancer Using TMS320C25," Conference Records Northcon/86, USA, 14/3/1-10, September/October 1986. Casale, Russo, Bellina, "Optimal Architectural Solution Using Processors Implementation ADPCM Transcoder," Proceedings GLOBECOM '89, pages 1267-1273, November 1989. Cole, Haoui, Winship, High-Performance Digital Voice Echo Canceller SINGLE TMS32020," Proceedings ICASSP USA, Catalog Number 86CH2243-4, Volume pages 429-432, April 1986. Cole, Haoui, Winship, High-Performance Digital Voice Echo Canceller Single TMS32020," Proceedings IEEE International Conference Acoustics, Speech Signal Processing, USA, 1986. Lovrich, Reimer, Multi-Rate Transcoder," Transactions Consumer Electronics, USA, November 1989. Lovrich, Reimer, Multi-Rate Transcoder" Digest Technical Papers 1989 International Conference Consumer Electronics, June 7-9, 1989.
Technical Articles
Hedberg, Fraenkel, "Implementation High-Speed Voiceband Data Modems Using TMS320C25," Proceedings ICASSP USA, Catalog Number 87CH2396-0, Volume pages 1915-1918, April 1987. Mock, "Add DTMF Generation Decoding DSP- Designs," Electronic Design, USA, Volume Number pages 205-213, March 1985. Reimer, McMahan, Arjmand, "ADPCM TMS320 Chip," Proceedings SPEECH TECH pages 246-249, April 1985. Troullinos, Bradley, "Split-Band Modem Implementation Using TMS32010 Digital Signal Processor," Conference Records Electro/86 Mini/Micro Northeast, USA, 14/1/1-21, 1986.
Automotive:
Lin, "Trends Digital Signal Processing Automotive," International Congress Transportation Electronic (CONVERGENCE '88), October 1988.
Consumer:
Frantz, G.A., J.B. Reimer, R.A. Wotiz, "Julie, Application Product," Speech Tech Magazine, USA, September 1988. Reimer, J.B., G.A. Frantz, "Customization Integrated Circuit Customer Product," Transactions Consumer Electronics, USA, August 1988. Reimer, J.B., P.E. Nixon, E.B. Boles, G.A. Frantz, "Audio Customization IC," Digest Technical Papers 1988 International Conference Consumer Electronics, June 8-10 1988.
Medical:
Knapp Townshend, Real-Time Digital Signal Processing System Auditory Prosthesis," Proceedings ICASSP USA, Volume page 2493, April 1988. Morris, L.R., P.B. Barszczewski, "Design Evolution Pocket-Sized Speech Processing System Cochlear Implant Other Hearing Prosthesis Applications," Proceedings ICASSP USA, Volume page 2516, April 1988.
Read This First
xiii
Technical Articles Trademarks
Development Support:
Mersereau, Schafer, Barnwell, Smith, Digital Filter Design Package TMS320," MIDCON/84 Electronic Show Convention, USA, 1984. Simar, Jr., Davis, "The Application High-Level Languages Single-Chip Digital Signal Processors," Proceedings ICASSP USA, Volume pages 1678-1681, April 1988.
Trademarks
HP-UX trademark Hewlett-Packard Company. MS-DOS registered trademark Microsoft Corporation. OS/2 PC-DOS trademarks International Business Machines Corporation. PAL® registered trademark Advanced Micro Devices, Inc. Solaris SunOS trademarks Microsystems, Inc. SPARC trademark SPARC International, Inc., licensed exclusively Microsystems, Inc. Windows registered trademark Microsoft Corporation. Hotline Online, XDS510, XDS510WS trademarks Texas Instruments Incorporated.
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Contents
Contents
Introduction Summarizes features TMS320 family products presents typical applications. Describes TMS320C54x lists features. TMS320 Family Overview 1.1.1 History, Development, Advantages TMS320 DSPs 1.1.2 Typical Applications TMS320 Family TMS320C54x Overview TMS320C54x Features
Architectural Overview Summarizes TMS320C54x architecture. Provides general information about CPU, structures, internal memory organization, on-chip peripherals, scanning logic. Structure Internal Memory Organization 2.2.1 On-Chip 2.2.2 On-Chip Dual-Access (DARAM) 2.2.3 On-Chip Single-Access (SARAM) 2.2.4 On-Chip Memory Security 2.2.5 Memory-Mapped Registers Central Processing Unit (CPU) 2.3.1 Arithmetic Logic Unit (ALU) 2.3.2 Accumulators 2.3.3 Barrel Shifter 2.3.4 Multiplier/Adder Unit 2.3.5 Compare, Select, Store Unit (CSSU) Data Addressing 2-10 Program Memory Addressing 2-11 Pipeline Operation 2-11 On-Chip Peripherals 2-12 2.7.1 General-Purpose Pins 2-12 2.7.2 Software-Programmable Wait-State Generator 2-12 2.7.3 Programmable Bank-Switching Logic 2-13 2.7.4 Host Port Interface 2-13 2.7.5 Hardware Timer 2-13 2.7.6 Clock Generator 2-13
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Contents
2.10
Serial Ports 2.8.1 Synchronous Serial Ports 2.8.2 Buffered Serial Ports 2.8.3 Serial Ports External Interface IEEE Standard 1149.1 Scanning Logic
2-14 2-14 2-14 2-14 2-15 2-15
Memory Describes TMS320C54x memory configuration operation. Includes memory maps descriptions program memory, data memory, space. Also includes descriptions memory-mapped registers. Memory Space 3.1.1 Extended Program Memory (Available TMS320C548) Program Memory 3.2.1 Program Memory Configurability 3.2.2 On-Chip Organization 3-10 3.2.3 Program Memory Address On-Chip Contents 3-11 3.2.4 On-Chip Code Contents Mapping 3-11 Data Memory 3-13 3.3.1 Data Memory Configurability 3-13 3.3.2 On-Chip Organization 3-14 3.3.3 Memory-Mapped Registers 3-17 3.3.4 Memory-Mapped Registers 3-17 Memory 3-21 Program Data Security 3-21
Central Processing Unit Describes TMS320C54x operations. Includes information about arithmetic logic unit, accumulators, shifter, multiplier/adder unit, compare select store unit, exponent encoder. Status Control Registers 4.1.1 Status Registers (ST0 ST1) 4.1.2 Processor Mode Status Register (PMST) Arithmetic Logic Unit (ALU) 4.2.1 Input 4.2.2 Overflow Handling 4-11 4.2.3 Carry 4-11 4.2.4 Dual 16-Bit Mode 4-12 Accumulators 4-13 4.3.1 Storing Accumulator Contents 4-13 4.3.2 Accumulator Shift Rotate Operations 4-14 4.3.3 Saturation Upon Accumulator Store (Available Devices) 4-15 4.3.4 Application-Specific Instructions 4-15
xviii
Contents
Barrel Shifter Multiplier/Adder Unit 4.5.1 Multiplier Input Sources 4.5.2 Multiply/Accumulate (MAC) Instructions 4.5.3 Saturation Upon Multiplication (Available Devices) Compare, Select, Store Unit (CSSU) Exponent Encoder
4-17 4-19 4-20 4-22 4-23 4-24 4-27
Data Addressing Describes seven basic addressing modes TMS320C54x. Immediate Addressing Absolute Addressing 5.2.1 dmad Addressing 5.2.2 pmad Addressing 5.2.3 Addressing 5.2.4 *(lk) Addressing Accumulator Addressing Direct Addressing 5.4.1 DP-Referenced Direct Addressing 5.4.2 SP-Referenced Direct Addressing Indirect Addressing 5-10 5.5.1 Single-Operand Addressing 5-10 5.5.2 ARAU Address-Generation Operation 5-11 5.5.3 Single-Operand Address Modifications 5-13 5.5.4 Dual-Operand Address Modifications 5-19 5.5.5 TMS320C2x/C2xx/C5x Compatibility (ARP) Mode 5-23 Memory-Mapped Register Addressing 5-25 Stack Addressing 5-27 Data Types 5-28
Program Memory Addressing Describes TMS320C54x program control mechanisms. Includes information about address generation, program counter, hardware stack, reset, interrupts, power-down modes. Program-Memory Address Generation Program Counter (PC) 6.2.1 Program Counter Extension Register (XPC, Available TMS320C548) Branches 6.3.1 Unconditional Branches 6.3.2 Conditional Branches 6.3.3 Branches (Available TMS320C548) Calls 6.4.1 Unconditional Calls 6.4.2 Conditional Calls 6-10 6.4.3 Calls (Available TMS320C548) 6-11
Contents
Contents
6.10
6.11
Returns 6.5.1 Unconditional Returns 6.5.2 Conditional Returns 6.5.3 Returns (Available TMS320C548) Conditional Operations 6.6.1 Using Multiple Conditions 6.6.2 Conditional Execute (XC) Instruction 6.6.3 Conditional Store Instructions Repeating Single Instruction Repeating Block Instructions Reset Operation Interrupts 6.10.1 Interrupt Flag Register (IFR) 6.10.2 Interrupt Mask Register (IMR) 6.10.3 Phase Receive Interrupt Request 6.10.4 Phase Acknowledge Interrupt 6.10.5 Phase Execute Interrupt Service Routine (ISR) 6.10.6 Interrupt Context Save 6.10.7 Interrupt Latency 6.10.8 Interrupt Operation: Quick Summary 6.10.9 Remapping Interrupt-Vector Addresses 6.10.10 Interrupt Tables Power-Down Modes 6.11.1 IDLE1 Mode 6.11.2 IDLE2 Mode 6.11.3 IDLE3 Mode 6.11.4 Hold Mode 6.11.5 Other Power-Down Capabilities
6-12 6-12 6-13 6-14 6-16 6-17 6-17 6-18 6-20 6-23 6-25 6-26 6-27 6-29 6-30 6-31 6-32 6-33 6-33 6-34 6-35 6-37 6-43 6-43 6-44 6-44 6-45 6-45
Pipeline Describes TMS320C54x pipeline operation lists pipeline latency cycles these types latencies. Pipeline Operation 7.1.1 Branch Instructions Pipeline 7.1.2 Call Instructions Pipeline 7.1.3 Return Instructions Pipeline 7-12 7.1.4 Conditional Execute Instructions Pipeline 7-19 7.1.5 Conditional-Call Conditional-Branch Instructions Pipeline 7-20 Interrupts Pipeline 7-26 Dual-Access Memory Pipeline 7-28 7.3.1 Resolved Conflict Between Instruction Fetch Operand Read 7-30 7.3.2 Resolved Conflict Between Operand Write Dual-Operand Read 7-32 7.3.3 Resolved Conflict Among Operand Write, Operand Write, Dual-Operand Read 7-34
Contents
Single-Access Memory Pipeline Pipeline Latencies 7.5.1 Recommended Instructions Accessing Memory-Mapped Registers 7.5.2 Updating ARx, SP-A Resolved Conflict 7.5.3 Rules Determine DAGEN Register Access Conflicts 7.5.4 Latencies 7.5.5 Latencies Stack Pointer 7.5.6 Latencies Temporary Register 7.5.7 Latencies Accessing Status Registers 7.5.8 Latencies Repeat-Block Loops 7.5.9 Latencies PMST Register 7.5.10 Latencies Memory-Mapped Accesses Accumulators
7-36 7-38 7-38 7-41 7-47 7-47 7-53 7-60 7-63 7-75 7-78 7-82
On-Chip Peripherals Describes TMS320C54x peripherals control them. Includes information about general-purpose pins, timers, clock, host port interface. Peripheral Memory-Mapped Registers General-Purpose 8-10 8.2.1 Branch Control Input (BIO) 8-10 8.2.2 External Flag Output (XF) 8-11 Timer 8-12 8.3.1 Timer Registers 8-12 8.3.2 Timer Operation 8-14 Clock Generator 8-16 8.4.1 Hardware-Configurable (Available Non-LP Devices) 8-16 8.4.2 Software-Programmable (Available TMS320C545LP/546LP/548) 8-17 Host Port Interface 8-22 8.5.1 Basic Host Port Interface Functional Description 8-23 8.5.2 Details Host Port Interface Operation 8-26 8.5.3 Host Read/Write Access 8-32 8.5.4 DSPINT HINT Function Operation 8-36 8.5.5 Considerations Changing Memory Access Mode (SAM/HOM) IDLE2/3 8-37 8.5.6 Access Memory During Reset 8-39 Serial Ports Describes TMS320C54x serial ports. Includes information about standard serial port interface, buffered serial port interface, time-division multiplexed serial port interface. Introduction Serial Ports Serial Port Interface 9.2.1 Serial Port Interface Registers 9.2.2 Serial Port Interface Operation 9.2.3 Configuring Serial Port Interface 9.2.4 Burst Mode Transmit Receive Operations 9-17 9.2.5 Continuous Mode Transmit Receive Operations 9-24 9.2.6 Serial Port Interface Exception Conditions 9-26 9.2.7 Example Serial Port Interface Operation 9-30
Contents
Contents
Buffered Serial Port (BSP) Interface 9.3.1 Operation Standard Mode 9.3.2 Autobuffering Unit (ABU) Operation 9.3.3 System Considerations Operation 9.3.4 Operation Power-Down Mode Time-Division Multiplexed (TDM) Serial Port Interface 9.4.1 Basic Time-Division Multiplexed Operation 9.4.2 Serial Port Interface Registers 9.4.3 Serial Port Interface Operation 9.4.4 Mode Transmit Receive Operations 9.4.5 Serial Port Interface Exception Conditions 9.4.6 Examples Serial Port Interface Operation
9-32 9-34 9-39 9-48 9-53 9-54 9-54 9-54 9-56 9-60 9-62 9-62
External Operation 10-1 Discusses external interface timing events involved memory accesses. Describes hold mode wake-up sequence from IDLE3 mode. 10.1 10.2 10.3 External Interface 10-2 External Priority 10-4 External Control 10-5 10.3.1 Wait-State Generator 10-5 10.3.2 Bank-Switching Logic 10-7 External Interface Timing 10-12 10.4.1 Memory Access Timing 10-12 10.4.2 Access Timing 10-16 10.4.3 Memory Access Timing 10-17 Start-Up Access Sequences 10-22 10.5.1 Reset 10-22 10.5.2 IDLE3 10-24 Hold Mode 10-26 10.6.1 Interrupts During Hold 10-27 10.6.2 Hold Reset 10-27
10.4
10.5
10.6
Peripheral Registers Peripheral RegistersShows fields TMS320C54x peripheral registers. Design Considerations Using XDS510 Emulator Describes JTAG emulator cable construct 14-pin connector your target system connect target system emulator. Designing Your Target System's Emulator Connector (14-Pin Header) Protocol Emulator Cable Emulator Cable Signal Timing Emulation Timing Calculations
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Contents
Connections Between Emulator Target System B.6.1 Buffering Signals B.6.2 Using Target-System Clock B.6.3 Configuring Multiple Processors Physical Dimensions 14-Pin Emulator Connector Emulation Design Considerations B.8.1 Using Scan Path Linkers B.8.2 Emulation Timing Calculations Scan Path Linker (SPL) B.8.3 Using Emulation Pins B.8.4 Performing Diagnostic Applications
B-10 B-10 B-12 B-13 B-14 B-16 B-16 B-18 B-20 B-24
Development Support Part Order Information Provides device part numbers support tool ordering information TMS320C54x development support information available from third-party vendors. Development Support C.1.1 Development Tools C.1.2 Third-Party Support C.1.3 Technical Training Organization (TTO) TMS320 Workshops C.1.4 Assistance Part Order Information C.2.1 Device Development Support Tool Nomenclature Prefixes C.2.2 Device Nomenclature C.2.3 Development Support Tools
Submitting Codes Provides information submitting codes Texas Instruments. Glossary Defines terms abbreviations used throughout this book.
Contents
xxiii
Figures
Figures
3-10 4-10 4-11 5-10 5-11 5-12
xxiv
Evolution TMS320 Family Block Diagram TMS320C54x Internal Hardware Memory Maps TMS320C541 Memory Maps TMS320C542 TMS320C543 Memory Maps TMS320C545 TMS320C546 Memory Maps TMS320C548 Extended Program Memory With On-Chip Mapped Program Space (OVLY Extended Program Memory With On-Chip Mapped Program Space Data Space (OVLY On-Chip Block Organization 3-10 On-Chip Program Memory (High Addresses) 3-12 On-Chip Block Organization 3-15 Addresses On-Chip Data Memory 3-16 Status Register (ST0) Diagram Status Register (ST1) Diagram Processor Mode Status Register (PMST) Diagram Functional Diagram Accumulator 4-13 Accumulator 4-13 Barrel Shifter Functional Diagram 4-18 Multiplier/Adder Functional Diagram 4-20 Compare, Select, Store Unit (CSSU) 4-24 Viterbi Operator 4-25 Exponent Encoder 4-27 Instruction With Short-Immediate Addressing Instruction With 16-Bit-Immediate Addressing Direct-Addressing Instruction Format Direct Addressing Block Diagram DP-Referenced Direct Address SP-Referenced Direct Address Indirect-Addressing Instruction Format Single Data-Memory Operand 5-10 Indirect Addressing Block Diagram Single Data-Memory Operand 5-12 Circular Addressing Block Diagram 5-17 Circular Buffer Implementation 5-17 Indirect-Addressing Instruction Format Dual Data-Memory Operands 5-20 Indirect Addressing Block Diagram Dual Data-Memory Operands 5-21
Figures
5-13 5-14 5-15 5-16 5-17 8-10 8-11 8-12 8-13 8-14 8-15 9-10 9-11 9-12 9-13 9-14
Indexes Auxiliary Registers 5-23 Indirect-Addressing Instruction Format Compatibility Mode 5-24 Memory-Mapped Register Addressing Block Diagram 5-25 Stack Stack Pointer Before After Push Operation 5-27 Word Order Memory 5-29 Program-Address Generation Logic (PAGEN) Registers Interrupt Flag Register (IFR) Diagram 6-28 Interrupt Mask Register (IMR) Diagram 6-29 Interrupt-Vector Address Generation 6-35 Flow Diagram Interrupt Operation 6-36 Pipeline Stages Pipelined Memory Accesses Half-Cycle Accesses Dual-Access Memory 7-29 TMS320C54x Peripheral Memory-Mapped Registers Timing Diagram 8-10 External Flag Timing Diagram 8-11 Timer Control Register (TCR) Diagram 8-13 Timer Block Diagram 8-14 Clock Mode Register (CLKMD) Diagram 8-18 Worst-Case Lockup Time Versus CLKOUT Frequency 8-21 Host Port Interface Block Diagram 8-22 Generic System Block Diagram 8-24 Select Input Logic 8-28 HPIC Diagram Host Reads from HPIC 8-31 HPIC Diagram Host Writes HPIC 8-31 HPIC Diagram TMS320C54x Reads From HPIC 8-31 HPIC Diagram TMS320C54x Writes HPIC 8-31 Timing Diagram 8-33 One-Way Serial Port Transfer Serial Port Interface Block Diagram Serial Port Control Register (SPC) Diagram Receiver Signal Multiplexers 9-12 Burst Mode Serial Port Transmit Operation 9-18 Serial Port Transmit With Long Pulse 9-19 Burst Mode Serial Port Transmit Operation With Delayed Frame Sync External Frame Sync Mode (SP) 9-20 Burst Mode Serial Port Transmit Operation With Delayed Frame Sync External Frame Sync Mode (BSP) 9-20 Burst Mode Serial Port Receive Operation 9-21 Burst Mode Serial Port Receive Overrun 9-21 Serial Port Receive With Long Pulse 9-22 Burst Mode Serial Port Transmit Maximum Packet Frequency 9-23 Burst Mode Serial Port Receive Maximum Packet Frequency 9-23 Continuous Mode Serial Port Transmit 9-25
Contents
Figures
9-15 9-16 9-17 9-18 9-19 9-20 9-21 9-22 9-23 9-24 9-25 9-26 9-27 9-28 9-29 9-30 9-31 9-32 9-33 9-34 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-23
xxvi
Continuous Mode Serial Port Receive 9-26 Receiver Functional Operation (Burst Mode) 9-27 Receiver Functional Operation (Burst Mode) 9-27 SP/BSP Transmitter Functional Operation (Burst Mode) 9-28 SP/BSP Receiver Functional Operation (Continuous Mode) 9-29 SP/BSP Transmitter Functional Operation (Continuous Mode) 9-30 Block Diagram 9-33 Control Extension Register (BSPCE) Diagram Serial Port Control Bits 9-36 Transmit Continuous Mode with External Frame (Format Bits) 9-39 Block Diagram 9-41 Control Extension Register (BSPCE) Diagram Control Bits 9-42 Circular Addressing Registers 9-46 Transmit Buffer Receive Buffer Mapping Example 9-47 Standard Mode Initialization Timing 9-49 Autobuffering Mode Initialization Timing 9-50 Time-Division Multiplexing 9-54 4-Wire 9-56 Serial Port Registers Diagram 9-58 Serial Port Timing (TDM Mode) 9-60 Example Configuration Diagram 9-63 External Interface Priority 10-4 Software Wait-State Register (SWWSR) Diagram 10-5 Software Wait-State Generator Block Diagram 10-7 Bank-Switching Control Register (BSCR) Diagram 10-8 Bank Switching Between Memory Reads 10-10 Bank Switching Between Program Space Data Space 10-11 Memory Interface Operation Read-Read-Write 10-13 Memory Interface Operation Write-Write-Read 10-14 Memory Interface Operation Read-Read-Write (Program-Space Wait States) 10-15 Parallel Interface Operation Read-Write-Read 10-16 Parallel Operation Read-Write-Read (I/O-Space Wait States) 10-17 Memory Read Write 10-18 Memory Read Read 10-18 Memory Write Write 10-19 Memory Write Read 10-19 Write Memory Write 10-20 Write Memory Read 10-20 Read Memory Write 10-21 Read Memory Read 10-21 External Reset Sequence 10-23 IDLE3 Wake-Up Sequence 10-25 HOLD HOLDA Minimum Timing 10-28 HOLD Interaction 10-29 Bank-Switching Control Register (BSCR) Diagram
Figures
A-10 A-11 A-12 A-13 A-14 A-15 A-16 B-10 B-11 B-12 B-13 B-14 B-15
Control Extension Register (BSPCE) Diagram Clock Mode Register (CLKMD) Diagram devices only) Control Register (HPIC) Diagram Interrupt Flag Register (IFR) Diagram Interrupt Mask Register (IMR) Diagram Processor Mode Status Register (PMST) Diagram Serial Port Control Register (SPC) Diagram Software Wait-State Register (SWWSR) Diagram Status Register (ST0) Diagram Status Register (ST1) Diagram Channel Select Register (TCSR) Diagram Receive Address Register (TRAD) Diagram Receive/Transmit Address Register (TRTA) Diagram Serial Port Control Register (TSPC) Diagram Timer Control Register (TCR) Diagram 14-Pin Header Signals Header Dimensions Emulator Cable Interface Emulator Cable Timings Emulator Connections Without Signal Buffering B-10 Emulator Connections With Signal Buffering B-11 Target-System-Generated Test Clock B-12 Multiprocessor Connections B-13 Pod/Connector Dimensions B-14 14-Pin Connector Dimensions B-15 Connecting Secondary JTAG Scan Path Scan Path Linker B-17 EMU0/1 Configuration Meet Timing Requirements Less Than B-21 Suggested Timings EMU0 EMU1 Signals B-22 EMU0/1 Configuration With Additional Gate Meet Timing Requirements Greater Than B-23 EMU0/1 Configuration Without Global Stop B-24 Emulation Connections JTAG Scan Paths B-25 TMS320C54x Device Nomenclature TMS320 Code Submittal Flowchart
Contents
xxvii
Tables
Tables
5-10 5-11 6-10
xxviii
Typical Applications TMS320 DSPs Usage Read Write Accesses Program Data Memory TMS320C54x Devices Host Port Interfaces TMS320C54x Devices 2-13 Serial Port Interfaces TMS320C54x Devices 2-14 On-Chip Program Memory Available TMS320C54x Devices On-Chip Data Memory Available TMS320C54x Devices 3-13 Memory-Mapped Registers 3-18 Data Security 3-21 Status Register (ST0) Summary Status Register (ST1) Summary Processor Mode Status Register (PMST) Summary Input Selection Instructions 4-10 Multiplier Input Selection Several Instructions 4-21 Operations Dual 16-Bit Mode 4-25 Instructions That Allow Immediate Addressing Direct-Addressing Instruction Summary Indirect-Addressing Instruction Summary Single Data-Memory Operand 5-10 Indirect Addressing Types With Single Data-Memory Operand 5-13 Bit-Reversed Addresses 5-19 Indirect-Addressing Instruction Summary Dual Data-Memory Operands 5-20 Auxiliary Registers Selected Field Instruction 5-20 Indirect Addressing Types With Dual Data-Memory Operands 5-21 Assembler Syntax Comparison TMS320C2x/C2xx/C5x '54x 5-23 Indirect-Addressing Instruction Summary Compatibility Mode 5-24 Instructions With 32-Bit Word Operands 5-28 Loading Addresses Into Loading Addresses into Unconditional Branch Instructions Conditional Branch Instructions Branch Instructions Unconditional Call Instructions 6-10 Conditional Call Instruction 6-11 Call Instructions 6-11 Unconditional Return Instructions 6-13 Conditional Return Instruction 6-14
Tables
6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28
Return Instructions 6-15 Conditions Conditional Instructions 6-16 Grouping Conditions Multiconditional Instructions 6-17 Conditional Store Instructions 6-18 Conditions Conditional Store Instructions 6-19 Multicycle Instructions That Become Single-Cycle Instructions When Repeated 6-20 Nonrepeatable Instructions 6-21 TMS320C541 Interrupt Locations Priorities 6-37 TMS320C542 Interrupt Locations Priorities 6-38 TMS320C543 Interrupt Locations Priorities 6-39 TMS320C545 Interrupt Locations Priorities 6-40 TMS320C546 Interrupt Locations Priorities 6-41 TMS320C548 Interrupt Locations Priorities 6-42 Operation During Four Power-Down Modes 6-43 DARAM Blocks 7-28 Accessing DARAM Blocks 7-28 Recommended Instructions Accessing Memory-Mapped Registers 7-39 Instructions That Access DAGEN Registers Read Stage 7-41 Store-Type Instructions 7-42 Pipeline-Protected Instructions Updating 7-48 Latencies Accessing 7-49 Latencies Accessing 7-50 Latencies Compiler Mode (CPL 7-54 Pipeline-Protected Instructions Update Noncompiler Mode (CPL 7-57 Latencies Noncompiler Mode (CPL 7-58 Pipeline-Protected Instructions Updating 7-60 Latencies Register Based Second-Instruction Category 7-61 Recommended Instructions Writing 7-63 Pipeline-Protected Instruction Update Compatibility Mode (CMPT 7-64 Latencies Compatibility Mode (CMPT CMPT 7-65 Recommended Instructions Update Noncompiler Mode (CPL 7-66 Latencies Noncompiler Mode (CPL 7-67 Latencies 7-69 Latencies 7-71 Pipeline-Protected Instructions Writing 7-72 Latencies Field 7-73 Recommended Instructions Writing Before RPTB Loop 7-75 Latencies Updating Before RPTB Loop 7-75 Latencies Updating From Within RPTB Loop 7-77 Latencies OVLY, IPTR, MP/MC Bits 7-79 Latencies DROM 7-81 Latencies Accumulators When Used Memory-Mapped Registers 7-84 TMS320C541 Peripheral Memory-Mapped Registers TMS320C542 Peripheral Memory-Mapped Registers
Contents
xxix
Tables
8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 8-20 8-21 8-22 8-23 9-10 9-11 9-12 9-13 9-14 9-15 10-1 10-2 10-3 10-4 10-5 10-6 10-7
TMS320C543 Peripheral Memory-Mapped Registers TMS320C545 Peripheral Memory-Mapped Registers TMS320C546 Peripheral Memory-Mapped Registers TMS320C548 Peripheral Memory-Mapped Registers Timer Registers 8-12 Timer Control Register (TCR) Summary 8-13 Clock Modes 8-17 Clock Mode Settings Reset 8-18 Clock Mode Register (CLKMD) Summary 8-18 Multiplier Related PLLNDIV, PLLDIV, PLLMUL 8-20 Registers Description 8-25 Signal Names Functions 8-26 Input Control Signals Function Selection Descriptions 8-29 Control Register (HPIC) Descriptions 8-30 HPIC Host/TMS320C54x Read/Write Characteristics 8-31 Wait-State Generation Conditions 8-34 Initialization HPIA 8-35 Read Access With Autoincrement 8-35 Write Access With Autoincrement 8-36 Sequence Entering Exiting IDLE2 IDLE3 8-38 Operation During RESET 8-39 Serial Ports TMS320C54x Devices Sections that Cover Serial Ports Serial Port Registers Serial Port Pins Serial Port Control Register (SPC) Summary Serial Port Clock Configuration 9-17 Buffered Serial Port Registers 9-34 Differences Between Serial Port Operation Standard Mode 9-35 Control Extension Register (BSPCE) Summary Serial Port Control Bits 9-37 Buffered Serial Port Word Length Configuration 9-38 Autobuffering Unit Registers 9-40 Control Extension Register (BSPCE) Summary Control Bits 9-43 Serial Port Registers 9-55 Interprocessor Communications Scenario 9-63 Register Contents 9-64 External Interface Signals 10-2 Software Wait-State Register (SWWSR) Summary 10-6 TMS320C548 Software Wait-State Register (SWWSR) Summary 10-6 Bank-Switching Control Register (BSCR) Summary 10-8 BNKCMP Bank Size 10-9 State Signals When EXIO 10-11 Counter Down-Time With Multiplication Factors Operation 10-24 14-Pin Header Signal Descriptions Emulator Cable Timing Parameters Development Support Tools Part Numbers
Examples
Examples
7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 7-30 7-31 7-32 Accumulator Store With Shift 4-14 CMPS Instruction Operation 4-26 Normalization Accumulator 4-27 Sequence Auxiliary Registers Modifications Bit-Reversed Addressing 5-18 Sample Pipeline Diagram Branch Instruction Pipeline Delayed-Branch Instruction Pipeline Call Instruction Pipeline Delayed-Call Instruction Pipeline 7-10 INTR Instruction Pipeline 7-11 Return Instruction Pipeline 7-12 Delayed-Return Instruction Pipeline 7-14 Return-With-Interrupt-Enable Instruction Pipeline 7-15 Delayed Return-With-Interrupt-Enable Instruction Pipeline 7-16 Return-Fast Instruction Pipeline 7-17 Delayed Return-Fast Instruction Pipeline 7-18 Instruction Pipeline 7-19 Instruction Pipeline 7-21 Instruction Pipeline 7-22 Instruction Pipeline 7-24 Instruction Pipeline 7-25 Interrupt Response Pipeline 7-27 Instruction Fetch Operand Read 7-31 Operand Write Dual-Operand Read Conflict 7-33 Operand Write Operand Read Conflict 7-35 Resolving Conflict When Updating Multiple ARxs 7-43 Resolving Conflict When Updating 7-45 Resolving Conflict When Updating 7-46 Updated With Latency 7-51 Updated With 1-Cycle Latency 7-51 Updated With Without 1-Cycle Latency 7-52 Updated With Without 2-Cycle Latency 7-52 Updated With 2-Cycle Latency 7-52 Updated With 1-Cycle Latency 7-53 Load With Latency Compiler Mode (CPL 7-55 Load With 1-Cycle Latency Compiler Mode (CPL 7-55
Contents
xxxi
Examples
7-33 7-34 7-35 7-36 7-37 7-38 7-39 7-40 7-41 7-42 7-43 7-44 7-45 7-46 7-47 7-48 7-49 7-50 7-51 7-52 7-53 7-54 7-55 7-56 7-57 7-58 7-59 7-60 7-61 7-62 7-63 7-64 7-65 7-66 7-67 7-68 7-69
xxxii
Load With Without 2-Cycle Latency Load With 2-Cycle Latency Compiler Mode (CPL Load With 3-Cycle Latency Compiler Mode (CPL Load With Latency Noncompiler Mode (CPL Load With Without 1-Cycle Latency Noncompiler Mode (CPL Load With 1-Cycle Latency Noncompiler Mode (CPL Load With Latency Load With 1-Cycle Latency Load With Latency Compatibility Mode (CMPT Load With 2-Cycle Latency Compatibility Mode (CMPT Load With 3-Cycle Latency Compatibility Mode (CMPT Load With Latency Noncompiler Mode (CPL Load With 2-Cycle Latency Noncompiler Mode (CPL Load With 3-Cycle Latency Noncompiler Mode (CPL Update With 1-Cycle Latency Update With 2-Cycle Latency Update With 3-Cycle Latency Update With Latency Update With 1-Cycle Latency Update With Latency Update With 1-Cycle Latency Loading Before Executing Repeat-Block Loop SRCCD Instruction With Latency SRCCD Instruction With 3-Cycle Latency Modifying From Within RPTB Loop BRAF Deactivation OVLY Setup Followed Unconditional Branch OVLY Setup Followed Conditional Branch OVLY Setup Followed Return MP/MC Setup Followed Unconditional Delayed Call IPTR Setup Followed Software Trap DROM Setup Followed Read Access DROM Setup Followed Dual-Read Access Accumulator Access With 1-Cycle Latency Accumulator Access With Conflict Updating Accumulator With 1-Cycle Latency Updating Accumulator With Latency Serial Port Initialization Routine Serial Port Interrupt Service Routine Transmit Initialization Routine Receive Initialization Routine Serial Port Transmit Initialization Routine Serial Port Transmit Interrupt Service Routine Serial Port Receive Initialization Routine
7-56 7-56 7-56 7-59 7-59 7-59 7-62 7-62 7-66 7-66 7-66 7-68 7-68 7-68 7-70 7-70 7-70 7-71 7-71 7-74 7-74 7-76 7-76 7-77 7-77 7-78 7-79 7-79 7-80 7-80 7-80 7-81 7-81 7-82 7-83 7-84 7-85 9-31 9-31 9-52 9-52 9-65 9-65 9-66
Examples
Serial Port Receive Interrupt Service Routine 9-66 Timing Single-Processor System Without Buffers Timing Single- Multiple-Processor System With Buffered Input Output Timing Single-Processor System Without Buffering (SPL) B-19 Timing Single- Multiprocessor-System With Buffered Input Output (SPL) B-19
Contents
xxxiii
Chapter
Introduction
TMS320C54x devices fixed-point digital signal processors (DSPs) TMS320 family. '54x meets specific needs real-time embedded applications, such telecommunications. '54x central processing unit (CPU), with modified Harvard architecture, features minimized power consumption high degree parallelism. Also, versatile addressing modes instruction improve overall system performance.
Topic
Page
TMS320 Family Overview TMS320C54x Overview TMS320C54x Features
TMS320 Family Overview
TMS320 Family Overview
TMS320 family consists fixed-point, floating-point, multiprocessor digital signal processors (DSPs). TMS320 architecture designed specifically real-time signal processing. following characteristics make this family ideal choice wide range processing applications:
Very flexible instruction Inherent operational flexibility High-speed performance Innovative parallel architecture Cost-effectiveness C-friendly architecture
1.1.1
History, Development, Advantages TMS320 DSPs
1982, Texas Instruments introduced TMS32010-the first fixed-point TMS320 family. Before year, Electronic Products magazine awarded TMS32010 title "Product Year". Today, TMS320 family consists eight generations: 'C1x, 'C2x, 'C2xx, 'C5x, 'C54x fixed-point DSPs; 'C3x 'C4x floating-point DSPs; 'C8x multiprocessor DSPs. Devices within generation TMS320 family have same structure different on-chip memory peripheral configurations. Spinoff devices combinations on-chip memory peripherals satisfy wide range needs worldwide electronics market. integrating memory peripherals onto single chip, TMS320 devices reduce system costs save circuit board space. Figure illustrates performance gains that TMS320 family made.
TMS320 Family Overview
Figure 1-1. Evolution TMS320 Family
Performance
Introduction
TMS320 Family Overview
1.1.2
Typical Applications TMS320 Family
Table lists some typical applications TMS320 family DSPs. TMS320 DSPs offer more adaptable approaches traditional signal-processing problems such vocoding filtering than standard microprocessor/ microcomputer devices. They also support complex applications that often require multiple operations performed simultaneously.
Table 1-1. Typical Applications TMS320 DSPs
Automotive Adaptive ride control Antiskid brakes Cellular telephones Digital radios Engine control Navigation global positioning Vibration analysis Voice commands Anticollision radar General-Purpose Adaptive filtering Convolution Correlation Digital filtering Fast Fourier transforms Hilbert transforms Waveform generation Windowing Instrumentation Digital filtering Function generation Pattern matching Phase-locked loops Seismic processing Spectrum analysis Transient analysis Consumer Digital radios/TVs Educational toys Music synthesizers Pagers Power tools Radar detectors Solid-state answering machines Control Disk drive control Engine control Laser printer control Motor control Robotics control Servo control
Graphics/Imaging rotation Animation/digital maps Homomorphic processing Image compression/transmission Image enhancement Pattern recognition Robot vision Workstations Medical Diagnostic equipment Fetal monitoring Hearing aids Patient monitoring Prosthetics Ultrasound equipment Telecommunications
Industrial Numeric control Power-line monitoring Robotics Security access
Military Image processing Missile guidance Navigation Radar processing Radio frequency modems Secure communications Sonar processing Voice/Speech Speaker verification Speech enhancement Speech recognition Speech synthesis Speech vocoding Text-to-speech Voice mail
1200- 600-bps modems Adaptive equalizers ADPCM transcoders Cellular telephones Channel multiplexing Data encryption Digital PBXs Digital speech interpolation (DSI) DTMF encoding/decoding Echo cancellation
Faxing Line repeaters Personal communications systems (PCS) Personal digital assistants (PDA) Speaker phones Spread spectrum communications Video conferencing X.25 packet switching
TMS320C54x Overview
TMS320C54x Overview
'54x high degree operational flexibility speed. combines advanced modified Harvard architecture (with program memory bus, three data memory buses, four address buses), with applicationspecific hardware logic, on-chip memory, on-chip peripherals, highly specialized instruction set. Spinoff devices that combine '54x with customized on-chip memory peripheral configurations have been, continue developed specialized areas electronics market. '54x devices offer these advantages:
Enhanced Harvard architecture built around program bus, three data
buses, four address buses increased performance versatility
Advanced design with high degree parallelism application-
specific hardware logic increased performance
highly specialized instruction faster algorithms optimized
high-level language operation
Modular architecture design fast development spinoff devices Advanced processing technology increased performance
power consumption
power consumption increased radiation hardness because
static design techniques
Introduction
TMS320C54x Features
TMS320C54x Features
This section lists features '54x DSPs.
Advanced multibus architecture with program bus, three data buses, four address buses 40-bit arithmetic logic unit (ALU), including 40-bit barrel shifter independent 40-bit accumulators 17-bit 17-bit parallel multiplier coupled 40-bit dedicated adder nonpipelined single-cycle multiply/accumulate (MAC) operation Compare, select, store unit (CSSU) add/compare selection Viterbi operator Exponent encoder compute exponent 40-bit accumulator value single cycle address generators, including eight auxiliary registers auxiliary register arithmetic units
Memory
192K words 16-bit addressable memory space (64K-words program, 64K-words data, 64K-words I/O), with extended program memory words) '548. On-chip configurations follows words):
Program Program/Data DARAM SARAM
Device '541 '542 '543 '545 '546 '548
Dual-access Single-access
TMS320C54x Features
Instruction
Single-instruction repeat block repeat operations Block memory move instructions better program data management Instructions with 32-bit long operand Instructions with 3-operand simultaneous reads Arithmetic instructions with parallel store parallel load Conditional-store instructions Fast return from interrupt
On-chip peripherals
Software-programmable wait-state generator Programmable bank switching On-chip phase-locked loop (PLL) clock generator with internal oscillator external clock source. With external clock source, there several multiplier values available from following device options:
Option Option Option Software-programmable
'545LP, '546LP, '548 designated LP-type devices. These devices have software-programmable additional saturation modes. softwareprogrammable described subsection 8.4.2, Software-Programmable PLL, page 8-17. saturation modes described subsection 4.1.2, Processor Mode Status Register (PMST), page 4-6.
Each device offers selection clock modes from option list only.
External bus-off control disable external data bus, address bus, control signals Data with holder feature Programmable timer
Introduction
TMS320C54x Features
Ports:
Serial Ports Device '541 '542 '543 '545 '546 '548 Host Port Interface Synchronous Buffered Time-Division Multiplexed
Power
Power consumption control with IDLE IDLE IDLE instructions power-down modes Control disable CLKOUT signal
Emulation: IEEE Standard 1149.1 boundary scan logic interfaced
on-chip scan-based emulation logic
Speed: 25/20/15/12.5/10-ns execution time single-cycle, fixed-point instruction MIPS/50 MIPS/66 MIPS/80 MIPS/100 MIPS): Device '541 Power Supply '542 '543 '545 '546 '548 Speed ns/20 ns/20 ns/20 ns/20 ns/20 ns/15 12.5 ns/10 Package 100-pin TQFP 100-pin TQFP 144-pin TQFP 128-pin/144-pin TQFP 100-pin TQFP 128-pin TQFP 100-pin TQFP 144-pin TQFP
12.5 MIPS) (100 MIPS) available 'LC548 only.
Chapter
Architectural Overview
This chapter provides overview architectural structure '54x, which comprises central processing unit (CPU), memory, on-chip peripherals. '54x DSPs advanced modified Harvard architecture that maximizes processing power with eight buses. Separate program data spaces allow simultaneous access program instructions data, providing high degree parallelism. example, three reads write performed single cycle. Instructions with parallel store application-specific instructions fully utilize this architecture. addition, data transferred between data program spaces. Such parallelism supports powerful arithmetic, logic, bit-manipulation operations that performed single machine cycle. Also, '54x includes control mechanisms manage interrupts, repeated operations, function calling. Figure '54x functional block diagram, which includes principal blocks structure.
Topic
Page
Structure Internal Memory Organization Central Processing Unit (CPU) Data Addressing 2-10 Program Memory Addressing 2-11 Pipeline Operation 2-11 On-Chip Peripherals 2-12 Serial Ports 2-14 External Interface 2-15
2.10 IEEE Standard 1149.1 Scanning Logic 2-15
Block Diagram
Figure 2-1. Block Diagram TMS320C54x Internal Hardware
System control interface Program address generation logic (PAGEN) IPTR, BRC, RSA, Data address generation logic (DAGEN) ARAU0, ARAU1 AR0-AR7 ARP,
encoder
register
Sign
Sign A(40) B(40)
Sign
Sign
Multiplier Fractional
Legend: Accumulator Accumulator data data unit program Barrel shifter register ALU(40)
COMP MSW/LSW select
Adder(40)
ZERO
ROUND
Memory external interface
Peripheral interface
Sign
Barrel shifter
Structure
Structure
'54x architecture built around eight major 16-bit buses (four program/ data buses four address buses):
program (PB) carries instruction code immediate
operands from program memory.
Three data buses (CB, interconnect various elements,
such CPU, data address generation logic, program address generation logic, on-chip peripherals, data memory.
carry operands that read from data memory. carries data written memory.
Four address buses (PAB, CAB, DAB, EAB) carry addresses
needed instruction execution. '54x generate data-memory addresses cycle using auxiliary register arithmetic units (ARAU0 ARAU1). carry data operands stored program space (for instance, coefficient table) multiplier adder multiply/accumulate operations destination data space data move instructions (MVPD READA). This capability, conjunction with feature dual-operand read, supports execution single-cycle, 3-operand instructions such FIRS instruction. '54x also on-chip bidirectional accessing on-chip peripherals; this connected through exchanger interface. Accesses that this require more cycles reads writes, depending peripheral's structure. Table summarizes buses used various types accesses.
Architectural Overview
Structure
Legend:
Peripheral write Peripheral read Data dual read Program write Program read Access Type Dual read/coefficient read Data read/data write Data single write Data long (32-bit) read Data single read
Table 2-1. Usage Read Write Accesses
high 16-bit word 16-bit word
(hw)
Address
(lw)
(hw)
Data
(lw)
Internal Memory Organization
Internal Memory Organization
'54x memory organized into three individually selectable spaces: program, data, space. '54x devices contain both random-access memory (RAM) read-only memory (ROM). Among devices, types represented: dual-access (DARAM) single-access (SARAM). Table shows much ROM, DARAM, SARAM available different '54x devices. '54x also registers plus peripheral registers that mapped data-memory space. '54x memory types features introduced subsections following this paragraph. details about configuring using various memory blocks, Chapter Memory.
Table 2-2. Program Data Memory TMS320C54x Devices
Memory Type ROM: Program Program/data DARAM SARAM '541 '542 '543 '545 '546 '548
configure dual-access (DARAM) single-access (SARAM) data memory program/data memory.
2.2.1
On-Chip
on-chip part program memory space and, some cases, part data memory space. amount on-chip available each device varies, shown Table 2-2. devices with small amount words), contains boot loader, which useful booting faster on-chip external RAM. details boot loading, TMS320C54x Reference Set, Volume Applications Guide. devices with larger amounts ROM, portion mapped into both data program space. larger ROMs also custom ROMs: provide code data programmed into object file format, Texas Instruments generates appropriate process mask program ROM. Appendix Submitting Codes details submitting codes Texas Instruments.
Architectural Overview
Internal Memory Organization
2.2.2
On-Chip Dual-Access (DARAM)
DARAM composed several blocks. Because each DARAM block accessed twice machine cycle, central processing unit (CPU) read from write single block DARAM same cycle. DARAM always mapped data space primarily intended store data values. also mapped into program space used store program code.
2.2.3
On-Chip Single-Access (SARAM)
SARAM composed several blocks. Each block accessible once machine cycle either read write. SARAM always mapped data space primarily intended store data values. also mapped into program space used store program code.
2.2.4
On-Chip Memory Security
'54x maskable memory security option protects contents on-chip memories. When designate this option, externally originating instruction access on-chip memory spaces.
2.2.5
Memory-Mapped Registers
data memory space contains memory-mapped registers on-chip peripherals. These registers located data page simplifying access them. memory-mapped access provides convenient save restore registers context switches transfer information between accumulators other registers.
Central Processing Unit (CPU)
Central Processing Unit (CPU)
'54x common '54x devices. '54x contains:
40-bit arithmetic logic unit (ALU) 40-bit accumulators Barrel shifter 17-bit multiplier 40-bit adder Compare, select, store unit (CSSU) Data address generation unit Program address generation unit
2.3.1
Arithmetic Logic Unit (ALU)
'54x performs 2s-complement arithmetic with 40-bit arithmetic logic unit (ALU) 40-bit accumulators (accumulators also perform Boolean operations. uses these inputs:
16-bit immediate value 16-bit word from data memory 16-bit value temporary register, 16-bit words from data memory 32-bit word from data memory 40-bit word from either accumulator
also function 16-bit ALUs perform 16-bit operations simultaneously. Section 4.2, Arithmetic Logic Unit (ALU), page 4-9, more details about operation.
2.3.2
Accumulators
Accumulators (see Figure page 2-2) store output from multiplier/adder block. They also provide second input ALU; accumulator input multiplier/adder. Each accumulator divided into three parts:
Guard bits (bits 39-32) High-order word (bits 31-16) Low-order word (bits 15-0)
Instructions provided storing guard bits, storing high- low-order accumulator words data memory, transferring 32-bit accumulator words data memory. Also, either accumulators used temporary storage other. Section 4.3, Accumulators page 4-13, more details about features these accumulators.
Architectural Overview
Central Processing Unit (CPU)
2.3.3
Barrel Shifter
'54x barrel shifter 40-bit input connected accumulators data memory (using DB), 40-bit output connected data memory (using EB). barrel shifter produce left shift bits right shift bits input data. shift requirements defined shift count field instruction, shift count field (ASM) status register ST1, temporary register (when designated shift count register). barrel shifter exponent encoder normalize values accumulator single cycle. LSBs output filled with MSBs either zero filled sign extended, depending state sign-extension mode (SXM) ST1. Additional shift capabilities enable processor perform numerical scaling, extraction, extended arithmetic, overflow prevention operations. Section 4.4, Barrel Shifter, page 4-17, more details about function shifter. Section 4.7, Exponent Encoder, page 4-27, more information about encoder's accumulator-normalizing function.
2.3.4
Multiplier/Adder Unit
multiplier/adder unit performs 17-bit 2s-complement multiplication with 40-bit addition single instruction cycle. multiplier/adder block consists several elements: multiplier, adder, signed/unsigned input control logic, fractional control logic, zero detector, rounder complement), overflow/saturation logic, 16-bit temporary storage register (T). multiplier inputs: input selected from data-memory operand, accumulator other selected from program memory, data memory, accumulator immediate value. fast, on-chip multiplier allows '54x perform operations efficiently such convolution, correlation, filtering. addition, multiplier together execute multiply/accumulate (MAC) computations operations parallel single instruction cycle. This function used determining Euclidian distance implementing symmetrical filters, which required complex algorithms. Section 4.5, Multiplier/Adder Unit, page 4-19, more details about multiplier/adder unit.
Central Processing Unit (CPU)
2.3.5
Compare, Select, Store Unit (CSSU)
compare, select, store unit (CSSU) performs maximum comparisons between accumulator's high word, allows both test/control flag (TC) status register transition register (TRN) keep their transition histories, selects larger word accumulator store into data memory. CSSU also accelerates Viterbi-type butterfly computations with optimized on-chip hardware. Section 4.6, Compare, Select, Store Unit (CSSU), page 4-24, more details about this unit.
Architectural Overview
Data Addressing Unit (CPU) Data Addressing Central Processing
Data Addressing
'54x offers seven basic data addressing modes:
Immediate addressing uses instruction encode fixed value. Absolute addressing uses instruction encode fixed address. Accumulator addressing uses accumulator access location
program memory data.
Direct addressing uses seven bits instruction encode lower
seven bits address. seven bits used with data page pointer (DP) stack pointer (SP) determine actual memory address.
Indirect addressing uses auxiliary registers access memory. Memory-mapped register addressing uses memory-mapped registers
without modifying either current value current value.
Stack addressing manages adding removing items from system
stack. During execution instructions using direct, indirect, memory-mapped register addressing, data-address generation logic (DAGEN) computes addresses data-memory operands. detailed discussion data addressing modes, Chapter Data Addressing.
2-10
Program Pipeline Operation Program Memory Addressing Memory Addressing
Program Memory Addressing
Program memory usually addressed '54x device with program counter (PC). With some instructions, however, absolute addressing used access data items that have been stored program memory. (Absolute addressing described Chapter Data Addressing.) which used fetch individual instructions, loaded program-address generation logic (PAGEN). Typically, PAGEN increments sequential instructions fetched. However, PAGEN load with non-sequential value result some instructions other operations. Operations that cause discontinuity include branches, calls, returns, conditional operations, single-instruction repeats, multipleinstruction repeats, reset, interrupts. calls interrupts, current saved onto stack, which referenced stack pointer (SP). When called function interrupt service routine finished, value that saved restored from stack return instruction. detailed discussion hardware software factors program address generation, Chapter Program Memory Addressing.
Pipeline Operation
instruction pipeline consists sequence operations that occur during execution instruction. '54x pipeline levels: prefetch, fetch, decode, access, read, execute. each levels, independent operation occurs. Because these operations independent, from instructions active given cycle, each instruction different stage completion. Typically, pipeline full with sequential instructions, each stages. When discontinuity occurs, such during branch, call, return, more stages pipeline temporarily unused. more details about pipeline operation, Chapter Pipeline.
Architectural Overview
2-11
On-Chip Peripherals
On-Chip Peripherals
'54x devices have same CPU, different on-chip peripherals connected their CPUs. '54x devices have these on-chip peripheral options:
General-purpose pins (BIO Software-programmable wait-state generator Programmable bank-switching logic Host port interface (HPI) Hardware timer Clock generator Serial ports Synchronous serial ports Buffered serial ports Time-division multiplexed (TDM) serial ports
more information about these peripherals, Chapter On-Chip Peripherals, Chapter Serial Ports, Chapter External Operation.
2.7.1
General-Purpose Pins
Each '54x device general-purpose pins: input that used monitor status external devices. software-controlled output that allows signal external devices. Section 8.2, General-Purpose Pins, page 8-10, more details about
2.7.2
Software-Programmable Wait-State Generator
software-programmable wait-state generator extends external cycles seven machine cycles interface with slower off-chip memory devices. software wait-state generator incorporated without external hardware. off-chip memory accesses, from zero seven wait states specified within software wait-state register (SWWSR) each 32K-word block program data memory, 64K-word block space. subsection 10.3.1, Wait-State Generator, page 10-5, more details.
2-12
On-Chip Peripherals
2.7.3
Programmable Bank-Switching Logic
programmable bank-switching logic automatically insert cycle when access crosses memory bank boundaries inside program memory data memory. cycle also inserted when access crosses from program memory data memory. This extra cycle prevents contention allowing memory devices release before other devices start driving bus. size memory bank bank switching defined bank switching control register (BSCR). subsection 10.3.2, Bank-Switching Logic, page 10-7, more details.
2.7.4
Host Port Interface
host port interface (HPI) 8-bit parallel port that provides interface host processor. Information exchanged between '54x host processor through '54x on-chip memory that accessible both host processor '54x. Table identifies HPI-equipped '54x devices. Section 8.5, Host Port Interface, page 8-22, more details about operation.
Table 2-3. Host Port Interfaces TMS320C54x Devices
On-Chip Peripheral Host port interface '541 '542 '543 '545 '546 '548
2.7.5
Hardware Timer
'54x features 16-bit timing circuit with 4-bit prescaler. timer counter decremented every CLKOUT cycle. Each time counter decrements timer interrupt generated. timer stopped, restarted, reset, disabled specific status bits. Section 8.3, Timer, page 8-12, more details.
2.7.6
Clock Generator
clock generator consists internal oscillator phase-locked loop (PLL) circuit. clock generator driven internally crystal resonator circuit externally clock source. circuit generate internal clock multiplying clock source specific factor; thus, should clock source with lower frequency than that CPU. more details about generator, Section 8.4, Clock Generator, page 8-16.
Architectural Overview
2-13
Serial Ports
Serial Ports
serial ports '54x vary device, three types serial ports represented: synchronous, buffered, time-division multiplexed (TDM). Table number each type various '54x devices. subsections following this paragraph provide introduction three types serial ports. more details about these ports, turn Chapter Serial Ports.
Table 2-4. Serial Port Interfaces TMS320C54x Devices
Serial Ports Synchronous Buffered '541 '542 '543 '545 '546 '548
2.8.1
Synchronous Serial Ports
synchronous serial ports high-speed, full-duplexed serial ports that provide direct communication with serial devices such codecs, analog-todigital (A/D) converters, other serial systems. When more than synchronous serial port resides '54x, these ports identical independent. Each synchronous serial port operate one-fourth machine cycle rate (CLKOUT). synchronous serial port transmitter receiver double buffered individually controlled maskable external interrupt signals. Data framed either bytes words.
2.8.2
Buffered Serial Ports
buffered serial port (BSP) synchronous serial port that enhanced with autobuffering unit clocked full CLKOUT rate. full-duplexed double-buffered offer flexible data stream length. autobuffering unit supports high-speed transfers reduces overhead servicing interrupts.
2.8.3
Serial Ports
time-division multiplexed (TDM) serial port synchronous serial port that enhanced allow time-division multiplexing data. configured either synchronous operations operations commonly used multiprocessor applications.
2-14
External Interface External Interface IEEE Standard 1149.1 Scanning Logic
External Interface
'54x address words data memory, words program memory words '548), words 16-bit parallel ports. Accesses either external memory ports take place through external interface. Individual space-select signals, allow selection physically separate spaces. interface's external ready input signal software-generated wait states allow processor interface with memory devices many different speeds. interface's hold modes allow external device take control '54x buses; this way, external device access resources program, data, spaces. External memory accessed most '54x instructions. However, accessing ports requires special instructions: PORTR PORTW. Chapter External Operation, more details about interfacing '54x external devices.
2.10 IEEE Standard 1149.1 Scanning Logic
IEEE Standard 1149.1 scanning-logic circuitry used emulation testing purposes only. This logic provides boundary scan from interfacing devices. Also, used test pin-to-pin continuity well perform operational tests devices peripheral '54x. IEEE Standard 1149.1 scanning logic interfaced internal scanning-logic circuitry that access on-chip resources. Thus, '54x perform onboard emulation using IEEE Standard 1149.1 serial scan pins emulation-dedicated pins. Appendix Design Considerations Using XDS510 Emulator, more information.
Architectural Overview
2-15
Chapter
Memory
This chapter describes '54x memory configuration operation. general, '54x devices have total memory space 192K 16-bit words. This space divided into three specific memory segments: words program, words data, words I/O. some cases, such '548, memory structure been modified through overlay paging schemes. parallel nature '54x architecture dual-access capability on-chip allow '54x perform four concurrent memory operations given machine cycle: instruction fetch, two-operand reads, operand write. There several advantages operating from on-chip memory:
Higher performance because wait states required Lower cost than external memory Lower power than external memory
main advantage operating from off-chip memory ability access larger memory space.
Topic
Page
Memory Space Program Memory Data Memory 3-13 Memory 3-21 Program Data Security 3-21
Memory Space
Memory Space
'54x's memory organized into three individually selectable spaces: program, data, I/O. Within these spaces, RAM, ROM, EPROM, EEPROM, memory-mapped peripherals reside either off-chip. Together, these three spaces provide total address range 192K words (except '548). program memory space contains instructions execute, well tables used execution. data-memory space stores data used instructions. memory space interfaces external memory-mapped peripherals also serve extra data storage space. Depending chip version, several on-chip memory types available '54x: dual-access (DARAM), single-access (SARAM), ROM. RAMs always mapped into data space, also mapped into program space. activated mapped into program space; also mapped, part, into data space. Three features '54x allow flexibility enabling disabling on-chip memories program data spaces:
MP/MC bit. this on-chip mapped into program
space. this on-chip mapped into program space.
OVLY bit. this on-chip RAMs mapped into program
data space. this on-chip RAMs mapped only into data space.
DROM bit. this part on-chip mapped into
data space. this on-chip mapped into data space. DROM independent state MP/MC. MP/MC, OVLY, DROM bits located processor mode status register (PMST). more details, Section 4.1, Status Control Registers, page 4-2. Figure through Figure show '54x device's data program memory maps maps affected MP/MC, OVLY, DROM bits.
Memory Space
Figure 3-1. Memory Maps TMS320C541
'541 Program Memory
0000h OVLY OVLY 0000h-13FFh External 0000h-007Fh Reserved 0080h-13FFh On-chip DARAM 0000h
'541 Data Memory
0000h-005Fh 0060h-007Fh 0080h-13FFh Memory-mapped registers Scratch-pad DARAM On-chip DARAM
2000h
2000h
4000h 1400h-8FFFh External
4000h
6000h
6000h
1400h-DFFFh External 8000h 8000h
A000h
A000h
MP/MC 9000h-FF7Fh On-chip C000h FF80h-FFFFh Interrupt vectors (internal) MP/MC 9000h-FF7Fh External FF80h-FFFFh Interrupt vectors (external) E000h E000h DROM E000h-FFFFh External DROM E000h-FEFFh On-chip FF00h-FFFFh Reserved FFFFh FFFFh C000h
Memory
Memory Space
Figure 3-2. Memory Maps TMS320C542 TMS320C543
'542/'543 Program Memory '542/'543 Data Memory
0000h
0000h
OVLY OVLY 2000h
0000h-27FFh External 0000h-007Fh Reserved 0080h-27FFh On-chip DARAM
0000h-005Fh Memory-mapped registers 0060h-007Fh Scratch-pad DARAM 2000h 0080h-27FFh On-chip DARAM
4000h
4000h
6000h
6000h
8000h 2800h-EFFFh External
8000h
2800h-FFFFh External A000h A000h
C000h
C000h
E000h
MP/MC F000h-F7FFh Reserved F800h-FF7Fh On-chip FF80h-FFFFh Interrupt vectors MP/MC F000h-FF7Fh External FF80h-FFFFh Interrupt vectors
E000h
FFFFh
FFFFh
Memory Space
Figure 3-3. Memory Maps TMS320C545 TMS320C546
'545/'546 Program Memory
0000h OVLY OVLY 0000h-17FFh External 0000h-007Fh Reserved 0080h-17FFh On-chip DARAM 0000h
'545/'546 Data Memory
0000h-005Fh 0060h-007Fh 0080h-17FFh Memory-mapped registers Scratch-pad DARAM On-chip DARAM
2000h 1800h-3FFFh External
2000h
4000h
4000h
6000h
6000h 1800h-BFFFh External
8000h MP/MC 4000h-FF7Fh On-chip FF80h-FFFFh Interrupts (internal) A000h MP/MC 4000h-FF7Fh External FF80h-FFFFh Interrupts (external)
8000h
A000h
C000h
C000h
DROM C000h-FFFFh External E000h E000h DROM C000h-FEFFh On-chip FF00h-FFFFh Reserved
FFFFh
FFFFh
Memory
Memory Space
Figure 3-4. Memory Maps TMS320C548
'548 Program Memory
OVLY OVLY 2000h 0000h-1FFFh External (paged) 0000h-007Fh Reserved 0080h-1FFFh On-chip DARAM 2000h
0000h
0000h
'548 Data Memory
0000h-005Fh 0060h-007Fh 0080h-1FFFh Memory-mapped registers Scratch-pad DARAM On-chip DARAM
4000h
4000h
OVLY OVLY 6000h
2000h-7FFFh External (paged) 2000h-7FFFh On-chip SARAM 6000h
2000h-7FFFh On-chip SARAM
8000h
8000h
A000h
A000h
8000h-EFFFh External (Paged) C000h C000h 8000h-FFFFh External
E000h
MP/MC F000h-F7FFh Reserved F800h-FF7Fh On-chip FF80h-FFFFh Interrupt vectors MP/MC F000h-FF7Fh External (paged) FF80h-FFFFh Interrupt vectors
E000h
FFFFh
FFFFh
Memory Space
3.1.1
Extended Program Memory (Available TMS320C548)
'548 uses paged extended memory scheme program space allow access 8192K program memory. order implement this scheme, '548 includes several additional features:
address lines, instead extra memory-mapped register, program counter extension regis-
(XPC)
extra instructions addressing extended program space
Program memory '548 organized into pages that each length, shown Figure 3-5.
Figure 3-5. Extended Program Memory With On-Chip Mapped Program Space (OVLY
0000
0000
0000
0000
Page words
Page words
Page words
Page words
FFFF FFFF FFFF FFFF
XPC=127
When on-chip enabled program space, each page program memory made parts: common block words unique block words. common block shared pages each unique block accessible only through assigned page. Figure shows common unique blocks. on-chip enabled (MP/MC enabled only page mapped other page program memory. value register defines page selection. This register memory-mapped into data space address 001Eh. hardware reset, initialized
Memory
Memory Space
Figure 3-6. Extended Program Memory With On-Chip Mapped Program Space Data Space (OVLY
0000
Page words
7FFF
8000
8000
8000
8000
Page words
FFFF FFFF
Page words
FFFF
Page words
FFFF
Page words
Note:
XPC=127
When on-chip enabled program space, accesses region 0000 7FFF, regardless page number, mapped on-chip 0000 7FFF. Figure more information about this on-chip memory region.
facilitate page switching through software, '548 special instructions that affect XPC:
FB[D] branch FBACC[D] branch location specified value accumula-
accumulator
FCALA[D] call location specified value accumulator
accumulator
FCALL[D] call FRET[D] return FRETE[D] return with interrupts enabled
addition these instructions, '54x instructions extended bits '548:
READA Read program memory addressed accumulator store
data memory
WRITA Write data program memory addressed accumulator
other instructions modify access only memory within current page.
Program Memory
Program Memory
external program memory '54x devices (except '548) addresses 16-bit words. '54x devices have on-chip ROM, dual-access (DARAM), single-access (SARAM) that mapped software into program space. When cells mapped into program space, device automatically accesses them when addresses fall within their bounds. When program address generation unit (PAGEN) generates address outside bounds on-chip memory, device automatically generates external access. (For more information about program address generation, Chapter Program Memory Addressing.) Table shows on-chip program memory available various '54x devices.
Table 3-1. On-Chip Program Memory Available TMS320C54x Devices
3.2.1
Program Memory Configurability
Device `541 `542 `543 `545 `546 `548 (MP/MC DARAM (OVLY SARAM (OVLY
MP/MC OVLY bits determine which on-chip memories enabled program space. reset, logic level present MP/MC transferred MP/MC PMST register (see Section 4.1, Status Control Registers, page 4-2). MP/MC determines whether enable on-chip ROM. MP/MC device configured microprocessor, on-chip enabled. MP/MC device configured microcomputer, on-chip enabled. MP/MC sampled only reset; however, disable enable on-chip through software setting clearing MP/MC PMST register. reset, RAM-DARAM SARAM present)-is addressable program space. make addressable program space setting OVLY PMST register. OVLY then mapped only data space. OVLY then mapped into both program space data space.
Memory
Figure 3-7. On-Chip Block Organization
organized blocks versions these devices.
3-10
Program Memory
3.2.2
D000h
C000h
E000h
B000h
A000h
F000h
9000h
8000h
7000h
6000h
5000h
4000h
On-Chip Organization
D000-DFFF
C000-CFFF
E000-EFFF
B000-BFFF
A000-AFFF
F000-FFFF 9800-9FFF 9000-97FF
'541
on-chip subdivided organized blocks enhance performance. example, block organization enables fetch instruction from block without sacrificing data accesses that come from different block ROM. Figure shows organized blocks each '54x device. gray lines figure indicate block boundaries.
Figure through Figure (pages through 3-6) show program memory configurations individual '54x devices.
F7FF-FFFF
'542/'543
D000-DFFF
C000-CFFF
E000-EFFF
B000-BFFF
A000-AFFF
F000-FFFF
'545/'546
9000-9FFF
8000-8FFF
7000-7FFF
6000-6FFF
5000-5FFF
4000-4FFF
F7FF-FFFF
'548
Program Memory
3.2.3
Program Memory Address On-Chip Contents
device reset, reset, interrupt, trap vectors mapped address FF80h program space. However, these vectors remapped beginning 128-word page program space after device reset. This feature facilitates moving vector table boot then removing from memory map. details remapping vectors, subsection 6.10.9, Remapping Interrupt-Vector Addresses, page 6-35. Note: on-chip ROM, words reserved device-testing purposes. Application code written implemented on-chip must reserve these words addresses FF00h-FF7Fh program space.
3.2.4
On-Chip Code Contents Mapping
'54x devices have either large (24K, 28K, words) on-chip words on-chip ROM. large on-chip ROMs programmed with your code, while content 2K-word on-chip ROMs defined Texas Instruments. '54x devices with words ROM, these words F800h FFFFh) contain:
bootloader program that boots from serial ports, external memory,
port, host port interface present)
256-word µ-law expansion table 256-word A-law expansion table 256-word sine look-up table interrupt vector table
Figure shows which these items particular '54x device shows addresses each items. address range code, F800h-FFFFh, mapped on-chip MP/MC Note: submit code Texas Instruments object file format program into '54x on-chip ROM. Appendix Submitting Codes details submit code Texas Instruments.
Memory
3-11
Program Memory
3-12
Figure 3-8. On-Chip Program Memory (High Addresses)
FD00h
FC00h
FE00h
FB00h
FF80h FF00h FA00h
F900h
F800h
Built-in self-test (BIST) code User-specified code '541/'545/'546
Interrupt vector table
Built-in self-test (BIST) code A-law expansion table µ-law expansion table Sine look-up table Bootloader code '542/'543/'548
Interrupt vector table
Data Memory
Data Memory
data memory '54x contains 16-bit words. number '54x devices have on-chip that mapped software into data space addition dual- single-access (DARAM SARAM). Table shows on-chip data memory available various '54x devices.
Table 3-2. On-Chip Data Memory Available TMS320C54x Devices
Device '541 '542 '543 '545 '546 '548 Program/Data (DROM DARAM SARAM
Accesses data (when enabled) made when addresses fall within bounds corresponding on-chip memories. When data-address generation logic (DAGEN) generates address outside bounds on-chip memory, device automatically generates external access. (For more information about generation data addresses, Chapter Data Addressing.)
3.3.1
Data Memory Configurability
Data memory reside both off-chip. on-chip DARAM mapped into data memory space. some '54x devices, portion on-chip (the amount shown Table 3-2) into data space setting DROM located PMST register (see Section 4.1, Status Control Registers, page 4-2). This portion on-chip enabled both data space (DROM bit) program space (MP/MC bit), allowing instruction area data residing data space. reset, processor clears DROM
Memory
3-13
Data Memory
data accessed single cycle instruction using single datamemory operand addressing, including instruction with 32-bit long word operand. dual-memory operand addressing, access requires cycles both operands reside same block; operands reside different blocks, access requires single cycle. address boundaries blocks, subsection 3.2.2, On-Chip Organization, page 3-10. Figure through Figure (pages through 3-6) show data memory configurations individual '54x devices.
3.3.2
On-Chip Organization
On-chip subdivided organized blocks enhance performance. example, block organization enables fetch operands from block DARAM write another block DARAM same cycle. Figure page 3-15 shows block organization each '54x device. gray lines figure indicate block boundaries. Figure 3-10 page 3-16 shows organization first DARAM '54x devices. This portion data memory includes memory-mapped peripheral registers, words scratch-pad DARAM, words DARAM. gray lines figure indicate memory-page boundaries used with direct memory addressing (see Section 5.4, Direct Addressing, page 5-7), refers data page pointer (see Section 4.1, Status Control Registers, page 4-2).
3-14
Figure 3-9. On-Chip Block Organization
7000h 6000h 5000h 4000h 3000h 2000h 1000h 0000h
0B00-0FFF 0800-0AFF 1000-13FF 0400-07FF 0000-03FF
Dual-access
'541
1800-1FFF
0800-0FFF
2000-27FF
1000-17FF
0000-07FF
'542/'543
Single-access
0800-0FFF
1000-17FF
0000-07FF
'545/'546
Memory
6000-7FFF 6000 7FFF 4000-5FFF 4000 5FFF 2000-3FFF 2000 3FFF 1800-1FFF 0800-0FFF 1000-17FF 0000-07FF
'548
Data Memory
3-15
Data Memory
Figure 3-10. Addresses On-Chip Data Memory
0380h 0300h 0280h 0200h 0180h 0100h 0080h 0060h 0040h 0020h 0000h Memory-mapped Memory mapped peripheral registers Memory-mapped registers Scratch-pad DARAM DARAM DARAM DARAM DARAM DARAM DARAM DARAM
3-16
Data Memory
3.3.3
Memory-Mapped Registers
words data memory space include device's memory-mapped registers, which reside data page (data addresses 0000h-007Fh, shown Figure 3-10 page 3-16). Data page consists following:
registers total) accessible with wait states;
Table page 3-18.
peripheral registers used control data registers peripher-
circuits. These registers reside within addresses 0020h-005F reside dedicated peripheral structure called TIBUS. They require least cycles when accessed. number cycles required depends peripherals built into '54x devices. list peripherals particular '54x device, Section 8.1, Peripheral MemoryMapped Registers, page 8-2.
scratch-pad block (60h-7Fh data memory) includes words
DARAM variable storage that helps avoid fragmenting large block.
3.3.4
Memory-Mapped Registers
Table lists memory-mapped registers. This subsection gives brief summary more registers.
3.3.4.1
Interrupt Registers (IMR, IFR)
interrupt mask register (IMR) individually masks specific interrupts required times. interrupt flag register (IFR) indicates current status interrupts. Interrupts described detail Section 6.10, Interrupts, page 6-26.
3.3.4.2
Status Registers (ST0, ST1)
status registers contain status various conditions modes '54x devices. contains flags (OVA, OVB, produced arithmetic operations manipulations, addition fields. reflects status modes instructions executed processor. Section 4.1, Status Control Registers, page detailed information.
Memory
3-17
Data Memory
3-18
Table 3-3. Memory-Mapped Registers
Address
1E-1F
PMST
Name
Reserved
Program counter extension register ('548) Processor mode status register Block-repeat address Block-repeat counter Stack pointer Auxiliary register Auxiliary register Auxiliary register Auxiliary register Auxiliary register Auxiliary register Auxiliary register Auxiliary register Transition register Temporary register Status register Status register Reserved testing Description Interrupt flag register Interrupt mask register Block-repeat start address Circular-buffer size register Accumulator guard bits (bits 39-32) Accumulator high word (bits 31-16) Accumulator word (bits 15-0) Accumulator word (bits 15-0) Accumulator high word (bits 31-16) Accumulator guard bits (bits 39-32)
Data Memory
3.3.4.3
Accumulators
'54x devices have 40-bit accumulators: accumulator accumulator Each accumulator memory-mapped partitioned into accumulator word (AL, BL), accumulator high word (AH, BH), accumulator guard bits (AG, BG). Section 4.3, Accumulators page 4-13 more details about these accumulator features.
3.3.4.4
Temporary Register
temporary register many uses. example, hold:
multiplicands multiply multiply/accumulate instructions
(For more details about register processes multiplication, Section 4.5, Multiplier/Adder Unit, page 4-19.)
dynamic (execution-time programmable) shift count instructions with
shift operation such ADD, instructions
dynamic address BITT instruction Branch metrics used DADST DSADT instructions
operation Viterbi decoding addition, instruction stores exponent value computed into register, then NORM instruction uses register value normalize number.
3.3.4.5
Transition Register (TRN)
16-bit transition (TRN) register holds transition decision path metrics perform Viterbi algorithm. CMPS (compare select store) instruction updates contents register basis comparison between accumulator high word accumulator word.
3.3.4.6
Auxiliary Registers (AR0-AR7)
eight 16-bit auxiliary registers (AR0-AR7) accessed modified auxiliary register arithmetic units (ARAUs). primary function auxiliary registers generate 16-bit addresses data space. However, these registers also general-purpose registers counters. information about role auxiliary registers play datamemory addressing, Section 5.5, Indirect Addressing, page 5-10.
Memory
3-19
Data Memory
3.3.4.7
Stack-Pointer Register (SP)
16-bit stack-pointer register (SP) contains address system stack. always points last element pushed onto stack. stack manipulated interrupts, traps, calls, returns, PSHD, PSHM, POPD, POPM instructions. Pushes pops stack predecrement postincrement, respectively, 16-bit value stack pointer.
3.3.4.8
Circular-Buffer Size Register (BK)
ARAUs use16-bit circular-buffer size register (BK) circular addressing specify data block size. information circular addressing, subsection 5.5.3.4, Circular Address Modifications, page 5-15.
3.3.4.9
Block-Repeat Registers (BRC, RSA, REA)
16-bit block-repeat counter (BRC) register specifies number times block code repeat when block repeat performed. 16-bit blockrepeat start address (RSA) register contains starting address block program memory repeated. 16-bit block-repeat address (REA) register contains ending address block program memory repeated. more information about repeating multiple instructions BRC, RSA, REA, Section 6.8, Repeating Block Instructions, page 6-23.
3.3.4.10 Processor Mode Status Register (PMST)
processor mode status register (PMST) controls memory configurations '54x devices. PMST described detail Section 4.1, Status Control Registers, page 4-2.
3.3.4.11 Program Counter Extension Register (XPC, Available '548)
program counter extension register (XPC) contains upper bits current program memory address. subsection 3.1.1, Extended Program Memory page 3-7, more information about extended memory.
3-20
Memory Memory Program Data Security
Memory
'54x devices offer memory space addition program- data-memory spaces. memory space 64K-word address space (0000h-FFFFh) exists only external device. instructions, PORTR PORTW, used access this space. Read timings vary from those program- data-memory spaces facilitate access individual I/O-mapped devices rather than memories. details external operation control accesses, Chapter External Operation.
Program Data Security
'54x staged security options: on-chip security ROM/ security. Table summary security feature.
Table 3-4. Data Security
Affect On-Chip Memory Accesses Security Affected both program data accesses. Instructions fetched from on-chip read on-chip program data accesses. Instructions fetched from on-chip external memory will prohibited from accessing on-chip will read invalid data (0FFFFh) program data accesses. ROM/RAM Affected both program data accesses. Instructions fetched from on-chip on-chip read on-chip program data accesses. Instructions fetched from external memory will prohibited from accessing on-chip will read invalid data (0FFFFh) program data accesses. Affected both program data accesses. Instructions fetched from on-chip on-chip read on-chip program data accesses. Instructions fetched from external memory will prohibited from accessing on-chip will read invalid data (0FFFFh) program data accesses. Unaffected this security option.
Memory
3-21
Chapter
Central Processing Unit
This chapter describes '54x central processing unit (CPU) operations. perform high-speed arithmetic operations within instruction cycle because parallel architectural design. following functional components discussed this chapter:
40-bit arithmetic logic unit (ALU) 40-bit accumulator registers Barrel shifter supporting shift range Multiply/accumulate block 16-bit temporary register 16-bit transition register (TRN) Compare, select, store unit (CSSU) Exponent encoder
registers memory-mapped, enabling quick saves restores.
Topic
Page
Status Control Registers Arithmetic LogIc Unit (ALU) Accumulators 4-13 Barrel Shifter 4-17 Multiplier/Adder Unit 4-19 Compare, Select, Store Unit (CSSU) 4-24 Exponent Encoder 4-27
Status Control Registers
Status Control Registers
'54x three status control registers:
Status register (ST0) Status register (ST1) Processor mode status register (PMST)
contain status various conditions modes; PMST contains memory-setup status control information. Because these registers memory-mapped, they stored into loaded from data memory; status processor saved restored subroutines interrupt service routines (ISRs).
4.1.1
Status Registers (ST0 ST1)
individual bits registers cleared with SSBX RSBX instructions. example, sign-extension mode with SSBX SXM, reset with RSBX SXM. ARP, fields loaded using instruction with short-immediate operand. fields also loaded with data-memory values using instruction. bits shown Figure described Table 4-1. bits shown Figure described Table page 4-4.
Figure 4-1. Status Register (ST0) Diagram
15-13
Table 4-1. Status Register (ST0) Summary
Name Reset Value Function Auxiliary register pointer. This 3-bit field selects auxiliary register compatibility mode indirect single-operand addressing (see section 5.5, Indirect Addressing, page 5-10). must always zero when standard mode (CMPT
Status Control Registers
Table 4-1. Status Register (ST0) Summary (Continued)
Name Reset Value Function Test/control flag. stores results arithmetic logic unit (ALU) test operations. affected BIT, BITF, BITT, CMPM, CMPR, CMPS, SFTC instructions. status (set cleared) determines conditional branch, call, execute, return instructions execute.
following conditions true:
tested BITT compare condition tested CMPM, CMPR, CMPS exists between datamemory value immediate operand, another auxiliary register, accumulator high word accumulator word. accumulator tested SFTC have different values from each other.
Carry result addition generates carry; cleared result subtraction generates borrow. Otherwise, reset after addition after subtraction, except with 16-bit shift. these cases, only only reset carry bit, they cannot affect otherwise. Carry borrow defined 32nd position operated level only. shift rotate instructions (ROR, ROL, SFTA, SFTL), MIN, MAX, ABS, instructions also affect this bit. Overflow flag accumulator when overflow occurs either multiplier's adder destination result accumulator Once overflow occurs, remains until either reset, BC[D], CC[D], RC[D], instruction executed using ANOV conditions. RSBX instruction also clear this bit. Overflow flag accumulator when overflow occurs either multiplier's adder destination result accumulator Once overflow occurs, remains until either reset, BC[D], CC[D], RC[D], instruction executed using BNOV conditions, when expression that writes does overflow. This RSBX instruction also clear this bit. Data-memory page pointer. This 9-bit field concatenated with seven LSBs instruction word form direct-memory address bits single datamemory operand addressing. This operation done compiler mode (CPL) field loaded instruction with short-immediate operand from data memory.
Central Processing Unit
Status Control Registers
Figure 4-2. Status Register (ST1) Diagram
BRAF IN10 FRCT CMPT
Table 4-2. Status Register (ST1) Summary
Name BRAF Reset Value Function Block-repeat active flag. BRAF indicates whether block repeat currently active. BRAF BRAF block repeat deactivated. BRAF cleared when block-repeat counter (BRC) decrements below block repeat active. BRAF automatically when RPTB instruction executed.
Compiler mode. indicates which pointer used relative direct addressing: relative direct-addressing mode using data page pointer (DP) selected. relative direct-addressing mode using stack pointer (SP) selected.
status. indicates status external flag (XF) pin, which generalpurpose output pin. SSBX instruction RSBX instruction reset Hold mode. indicates whether processor continues internal execution when acknowledging active HOLD signal: processor continues execution from internal program memory places external interface high-impedance state. processor halts internal execution.
IN
Interrupt mode. INglobally masks enables interrupts. unmasked interrupts enabled. maskable interrupts disabled.
SSBX instruction sets INand RSBX instruction resets INTM. INis reset when maskable interrupt trap taken (INTR external interrupts). INis cleared when RETE RETF instruction (return from interrupt) executed. INdoes affect nonmaskable interrupts NMI). INcannot memory-write operations. Always read
Status Control Registers
Table 4-2. Status Register (ST1) Summary
Name Reset Value Function Overflow mode. determines what loaded into destination accumulator when overflow occurs: overflowed result from either multiplier's adder overflows normally destination accumulator. destination accumulator either most positive value 7FFF FFFFh) most negative value 8000 0000h) upon encountering overflow.
SSBX RSBX instructions reset OVM, respectively. Sign-extension mode. determines whether sign extension performed: Sign extension suppressed. Data sign extended before being used ALU.
does affect definitions certain instructions: ADDS, LDU, SUBS instructions suppress sign extension regardless value. SSBX RSBX instructions reset SXM, respectively. Dual 16-Bit/double-precision arithmetic mode. determines arithmetic mode ALU's operation: FRCT CMPT operates double-precision arithmetic mode. operates dual 16-bit arithmetic mode.
Fractional mode. When FRCT multiplier output left-shifted compensate extra sign bit. Compatibility mode. CMPT determines compatibility mode ARP: CMPT updated indirect addressing mode with single datamemory operand. must always when this mode. updated indirect addressing mode with single datamemory operand, except when instruction selecting auxiliary register (AR0).
CMPT
Accumulator shift mode. 5-bit field specifies shift value within through range coded 2s-complement value. Instructions with parallel store, well STH, STL, ADD, SUB, this shift capability. loaded from data memory instruction using short-immediate operand.
Central Processing Unit
Status Control Registers
4.1.2
Processor Mode Status Register (PMST)
PMST register loaded with memory-mapped register instructions such STM. PMST bits shown Figure described Table 4-3.
Figure 4-3. Processor Mode Status Register (PMST) Diagram
15-7 IPTR MP/MC OVLY AVIS DROM CLKOFF SMUL
Only devices; reserved bits other devices
Table 4-3. Processor Mode Status Register (PMST) Summary
Name IPTR Reset Value 1FFh Function Interrupt vector pointer. 9-bit IPTR field points 128-word program page where interrupt vectors reside. remap interrupt vectors boot-loaded operations. reset, these bits reset vector always resides address FF80h program-memory space. RESET instruction does affect this field.
MP/MC
MP/MC Microprocessor/microcomputer mode. MP/MC enables/disables on-chip addressable program memory space. MP/MC MP/MC on-chip enabled addressable. on-chip available.
MP/MC value corresponding logic level MP/MC when sampled reset. This sampled again until next reset. RESET instruction does affect this bit. This also cleared software. OVLY overlay. OVLY enables on-chip dual-access data blocks mapped into program space. values OVLY are: OVLY OVLY on-chip addressable data space program space. on-chip mapped into program space data space. Data page (addresses 7Fh), however, mapped into program space.
Only devices; reserved bits other devices
Status Control Registers
Table 4-3. Processor Mode Status Register (PMST) Summary (Continued)
Name AVIS Reset Value Function Address visibility mode. AVIS enables/disables internal program address visible address pins. AVIS external address lines change with internal program address. Control data lines affected address driven with last address bus. This mode allows internal program address appear pins '54x that internal program address traced. Also, allows interrupt vector decoded conjunction with IACK when interrupt vectors reside on-chip memory.
AVIS
DROM
Data ROM. DROM enables on-chip mapped into data space. values DROM are: DROM DROM on-chip mapped into data space. portion on-chip mapped into data space. Chapter Memory, details.
CLKOFF SMUL
CLOCKOUT off. When CLKOFF output CLKOUT disabled remains high level. Saturation multiplication. When SMUL saturation multiplication result occurs before performing accumulation instruction. SMUL applies only when FRCT SMUL allows operations consistent with basic operation defined ETSI specifications (GSM specs 6.06, 6.10, 6.53). effect that result 8000h 8000h saturated FFFFh fractional mode, before performing subsequent addition/subtraction required instruction. this mode, instruction equivalent when OVM=1. mode result multiplication saturated before performing addition/ subtraction, only results instructions saturated.
Only devices; reserved bits other devices
Central Processing Unit
Status Control Registers
Table 4-3. Processor Mode Status Register (PMST) Summary (Continued)
Name Reset Value Function Saturation store. When saturation data from accumulator enabled before storing memory. saturation performed after shift operation. Saturation store takes place with following instructions: STH, STL, STLM, DST, ST||ADD, ST||LD, ST||MACR[R], ST||MAS[R], ST||MPY, ST||SUB. following steps performed when using saturate store: 40-bit data value shifted (right left) depending instruction. shift same described SFTA instruction depends bit. 40-bit data value saturated 32-bit value; saturation depends (the number always assumed positive). following 32-bit value generated: 7FFF FFFFh value greater than 7FFF FFFFh
following 32-bit value generated: 7FFF FFFFh value greater than 7FFF FFFFh 8000 0000h value less than 8000 0000h
data stored memory depending upon instruction. accumulator contents remain unchanged during operation.
Only devices; reserved bits other devices
Arithmetic Logic Unit (ALU)
Arithmetic Logic Unit (ALU)
40-bit ALU, shown Figure 4-4, implements wide range arithmetic logical functions, most which execute single clock cycle. After operation performed ALU, result usually transferred destination accumulator (accumulator Instructions that perform memory-tomemory operations (ADDM, ANDM, ORM, XORM) exceptions.
Figure 4-4. Functional Diagram
CB15 DB15
Sign
Shifter output (40)
Sign
output
OVA/OVB ZA/ZB
Legend: Accumulator Accumulator data data unit Barrel shifter register
4.2.1
Input
input takes several forms from several sources. input source either values:
shifter output 32-bit 16-bit data-memory operand shifted
accumulator value)
Central Processing Unit
Arithmetic Logic Unit (ALU)
data-memory operand from data
input source three values:
value accumulators data-memory operand from data value register
When 16-bit data-memory operand through data 40-bit input constructed ways:
bits through contain data-memory operand, bits thr
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