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55°C 125°C Operating Temperature Range, Processing Processed MIL-PRF-3


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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
55°C 125°C Operating Temperature Range, Processing Processed MIL-PRF-38535 (QML) 1K-Word 32-Bit Single-Cycle Dual-Access On-Chip Blocks Validated Compiler 64-Word 32-Bit Instruction Cache 32-Bit Instruction Data Words, 24-Bit Addresses 32-Bit Floating-Point Integer Multiplier Arithmetic Logic Unit (ALU) Parallel Multiplier Execution Single Cycle On-Chip Direct Memory Access (DMA) Controller Concurrent Operation Integer, Floating-Point, Logical Operations
Address Generators With Eight Auxiliary Registers Auxiliary Register Arithmetic Units (ARAUs) Zero-Overhead Loops With Single-Cycle Branches Interlocked Instructions Multiprocessing Support 32-Bit Barrel Shifter Eight Extended-Precision Registers (Accumulators) Two- Three-Operand Instructions Conditional Calls Returns Block Repeat Capability Fabricated Using Enhanced Performance Implanted CMOS (EPICTM) Texas Instruments (TITM) 32-Bit Timers
SMJ320C30 Features
Performance SMJ320C30-33 (60-ns Cycle) MFLOPS 16.7 MIPS SMJ320C30-40 (50-ns Cycle) MFLOPS MIPS 4K-Word 32-Bit Single-Cycle Dual-Access On-Chip Block 32-Bit External Ports (24- 13-Bit Address) Serial Ports With Support 32-Bit Transfers Packaging 181-Pin Grid Array Ceramic Package Suffix) 196-Pin Ceramic Quad Flatpack With Nonconductive Tie-Bar (HFG Suffix) 244-Pad JEDEC Standard Frame Approval 40-MHz Versions
SMJ320C31 Features
Performance SMJ320C31-33 (60-ns Cycle) 33.3 MFLOPS 16.7 MIPS SMJ320C31-40 (50-ns Cycle) MFLOPS MIPS SMJ320C31-50 (40-ns Cycle) MFLOPS MIPS Flexible Boot-Program Loader Serial Port Support 2-Bit Transfers 32-Bit Data (24-Bit Address) Packaging 132-Pin Ceramic Quad Flatpack With Nonconductive Tie-Bar (HFG Suffix) 141-Pin Staggered Grid Array Ceramic Package (GFA Suffix) 244-Pad JEDEC-Standard Frame Approval 33-, 40-, 50-MHz Versions
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. EPIC trademarks Texas Instruments Incorporated.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1996, Texas Instruments Incorporated
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
SMJ320C30 181-Pin Grid Array Package BOTTOM VIEW
SMJ320C31 141-Pin Staggered Grid Array Package BOTTOM VIEW
SMJ320C30 196-Pin Quad Flatpack VIEW
SMJ320C31 132-Pin Quad Flatpack VIEW
DVDD DVSS
DVSS
DVDD
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
SMJ320C30 PACKAGE VIEW
SMJ320C31 PACKAGE VIEW
Leads
Leads
Face
Face
SMJ320C30 PACKAGE VIEW
SMJ320C31 PACKAGE VIEW
Leads
Leads
Face
Face
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
description
SMJ320C3x's internal busing special digital signal processing (DSP) instruction have speed flexibility execute MFLOPS (million floating-point operations second). SMJ320C3x devices optimize speed implementing functions hardware that other processors implement through software microcode. This hardware-intensive approach provides performance previously unavailable single chip. emphasis total system cost resulted less expensive processor that designed into systems currently using costly bit-slice processors. Also, appropriate selection based cost performance enhanced different processors SMJ320C3x line:
SMJ320C30-33: SMJ320C30-40: SMJ320C31-33: SMJ320C31-40: SMJ320C31-50:
60-ns single-cycle execution time, supply 50-ns single-cycle execution time, supply cost, reduced overall size, 60-ns single-cycle execution time, supply cost, reduced overall size, 50-ns single-cycle execution time, supply cost, reduced overall size, 40-ns single-cycle execution time, supply
SMJ320C30 SMJ320C31 perform parallel multiply operations integer floating-point data single cycle. Each processor also possesses general-purpose register file, program cache, dedicated ARAUs, internal dual-access memories, channel supporting concurrent short machine-cycle time. High performance ease results these features. General-purpose applications enhanced greatly large address space, multiprocessor interface, internally externally generated wait states, external interface ports (two SMJ320C30, SMJ320C31), timers, serial ports (two SMJ320C30, SMJ320C31), multiple interrupt structure. SMJ320C3x supports wide variety system applications from host processor dedicated coprocessor. High-level language support implemented easily through register-based architecture, large address space, powerful addressing modes, flexible instruction set, well-supported floating-point arithmetic.
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
functional block diagram SMJ320C30
Cache Block Block
PDATA PADDR HOLD HOLDA STRB D31- DDATA DADDR1 DADDR2 DMADATA DMAADDR
Controller Serial Port Global-Control Register Serial-Port-Control Register Receive/Transmit (R/X) Timer Register Data-Transmit Register Data-Receive Register Serial Port FSX0 CLKX0 FSR0 CLKR0
RESET INT(3 IACK XF(1,0) IODVDD ADVDD PDVDD DDVDD MDVDD DVSS CVSS IVSS VBBP VSUBS CLKIN EMU(6 RSV(10 CPU1 CPU2 REG1 REG2 CPU1 REG1 REG2 Multiplier 32-Bit Barrel Shifter ExtendedPrecision Registers (R7-R0) Source-Address Register DestinationAddress Register TransferCounter Register Peripheral Address
Peripheral Data
Serial-Port-Control Register
Controller
Receive/Transmit (R/X) Timer Register Data-Transmit Register Data-Receive Register Timer
DISP0, IR0,
Global-Control Register Timer-Period Register Timer-Counter Register Timer Global-Control Register Timer-Period Register Timer-Counter Register Port Control
ARAU0
ARAU1
Other Registers (12) Auxiliary Registers (AR0 AR7)
Primary-Control Register Expansion-Control Register
Available SMJ320C30
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FSX1 CLKX1 FSR1 CLKR1 TCLK0 TCLK1
Block
XRDY MSTRB IOSTRB XD31-XD0 XA12 -XA0
SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
functional block diagram SMJ320C31
Cache Block Block
PDATA PADDR HOLD HOLDA STRB D31- DDATA DADDR1 DADDR2 DMADATA DMAADDR
Controller Serial Port Global-Control Register Serial-Port-Control Register Receive/Transmit Timer Register Data-Transmit Register Data-Receive Register FSX0 CLKX0 FSR0 CLKR0
RESET INT(3 IACK MCBL XF(1,0) CPU1 CPU2 REG1 REG2 Controller CPU1 REG1 REG2 Multiplier 32-Bit Barrel Shifter ExtendedPrecision Registers (R7-R0) Source-Address Register DestinationAddress Register TransferCounter Register Peripheral Address
Peripheral Data
CLKIN EMU(3
DISP0, IR0, Global-Control Register ARAU0 ARAU1 Timer-Period Register Auxiliary Registers (AR0 AR7) Port Control Other Registers (12) STRB-Control Register Timer-Counter Register TCLK1
includes AVDD, VDDL, DVDD, CVDD, PVDD. includes DVSS, CVSS, VSSL, IVSS.
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Boot Loader Timer Global-Control Register Timer-Period Register Timer-Counter Register Timer TCLK0
SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
memory
Figure depicts memory SMJ320C30 SMJ320C31. Refer TMS320C3x User's Guide (literature number SPRU031) detailed description this memory mapping.
Reset, Interrupt, Trap Vectors, Reserved Locations (64) (External STRB Active) 03Fh 040h External STRB Active Words Words) 7FFFFFh 800000h 801FFFh 802000h 803FFFh 804000h 805FFFh 806000h 807FFFh 808000h Peripheral-Bus Memory-Mapped Registers Words Internal) 8097FFh 809800h 809BFFh 809C00h 809FFFh 80A000h Block Word Internal) Block Word Internal) 8097FFh 809800h 809BFFh 809C00h 809FFFh 80A000h Reset, Interrupt, Trap Vectors, Reserved Locations (192) 0BFh 0C0h 0FFFh 1000h External STRB Active Words Words) 7FFFFFh 800000h 801FFFh 802000h 803FFFh 804000h 805FFFh 806000h 807FFFh 808000h Peripheral-Bus Memory-Mapped Registers Words Internal) Block Word Internal) Block Word Internal) (Internal)
Expansion-Bus MSTRB Active Words) Reserved Words) Expansion-Bus IOSTRB Active Words) Reserved Words)
Expansion-Bus MSTRB Active Words) Reserved Words) Expansion-Bus IOSTRB Active Words) Reserved Words)
External STRB Active Words Words)
External STRB Active Words Words)
0FFFFFFh Microprocessor Mode
0FFFFFFh Microcomputer Mode
Figure SMJ320C30 SMJ320C31 Memory
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
functions
This section gives signal descriptions SMJ320C3x devices microprocessor mode. following tables list each signal, number pins, type operating mode(s) (that input, output, high-impedance state indicated respectively), brief function description. pins labeled have special functions should connected user. line over signal name (for example, RESET) indicates that signal active (true logic-0 level). signals grouped according functions. SMJ320C30 Functions
NAME TYPE DESCRIPTION PRIMARY INTERFACE STRB I/O/Z 32-bit data port primary interface 24-bit address port primary interface Read write primary interface. high when read performed when write performed over parallel interface. External access strobe primary interface Ready. indicates that external device prepared primary interface transaction complete. Hold primary interface. When HOLD logic low, ongoing transaction completed. STRB, high-impedance state transactions over primary interface held until HOLD becomes logic high NOHOLD primary control register set. Hold acknowledge primary interface. HOLDA generated response logic HOLD. HOLDA indicates that STRB, high-impedance state that transactions over held. HOLDA high response logic high HOLD when NOHOLD primary control register set. EXPANSION INTERFACE XD31 XA12 MSTRB IOSTRB XRDY I/O/Z 32-bit data port expansion interface 13-bit address port expansion interface Read write signal expansion interface. When read performed, held high; when write performed, low. External memory access strobe expansion interface External access strobe expansion interface Ready signal. XRDY indicates that external device prepared expansion interface transaction complete. CONTROL SIGNALS RESET INT3 INT0 IACK XF1, I/O/Z Reset. When RESET logic low, device reset condition. When RESET becomes logic high, execution begins from location specified reset vector. External interrupts Interrupt acknowledge. IACK logic high IACK instruction. IACK used indicate beginning interrupt-service routine. Microcomputer microprocessor mode External flags. used general-purpose support interlocked processor instructions. CONDITIONS WHEN SIGNAL
HOLD
HOLDA
input, output, high-impedance state package active, HOLD active, RESET active
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
SMJ320C30 Functions (Continued)
NAME TYPE DESCRIPTION SERIAL PORT SIGNALS CLKX0 FSX0 CLKR0 FSR0 I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z Serial port transmit clock. CLKX0 serial-shift clock serial port transmitter. Data transmit output. Serial port transmits serial data DX0. Frame synchronization pulse transmit. FSX0 pulse initiates transmit-data process over DX0. Serial port receive clock. CLKR0 serial-shift clock serial port receiver. Data receive. Serial port receives serial data DR0. Frame synchronization pulse receive. FSR0 pulse initiates receive-data process over DR0. SERIAL PORT SIGNALS CLKX1 FSX1 CLKR1 FSR1 I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z Serial port transmit clock. CLKX1 serial-shift clock serial port transmitter. Data transmit output. Serial port transmits serial data DX1. Frame synchronization pulse transmit. FSX1 pulse initiates transmit-data process over DX1. Serial port receive clock. CLKR1 serial-shift clock serial port receiver. Data receive. Serial port receives serial data DR1. Frame synchronization pulse receive. FSR1 pulse initiates receive-data process over DR1. TIMER SIGNALS TCLK0 I/O/Z Timer clock input, TCLK0 used timer count external pulses. output, TCLK0 outputs pulses generated timer TIMER SIGNALS TCLK1 I/O/Z Timer clock input, TCLK1 used timer count external pulses. output, TCLK1 outputs pulses generated timer SUPPLY OSCILLATOR SIGNALS (see Note Ground Ground CONDITIONS WHEN SIGNAL
IODVDD ADVDD PDVDD DDVDD MDVDD DVSS
CVSS Ground input, output, high-impedance state package active, HOLD active, RESET active Recommended decoupling capacitor NOTE CVSS, VSS, IVSS same plane.
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
SMJ320C30 Functions (Continued)
NAME TYPE DESCRIPTION SUPPLY OSCILLATOR SIGNALS (CONTINUED) (see Note IVSS VBBP VSUBS CLKIN EMU0 EMU2 EMU3 Ground pump oscillator output Substrate pin. ground Output from internal oscillator crystal. crystal used, should left unconnected. Input internal oscillator from crystal clock External clock. period equal twice CLKIN. External clock. period equal twice CLKIN. Reserved. pullup resistors Reserved Shutdown high impedance. When active, EMU4 shuts down SMJ320C30 places pins high-impedance state. EMU4 used board-level testing ensure that dual drive conditions occur. CAUTION: corrupts SMJ320C30 memory register contents. Reset device with high restore known operating condition. Reserved Reserved. pins directly Reserved. pullups each CONDITIONS WHEN SIGNAL
EMU4
EMU5, EMU6 RSV0 RSV4 RSV5 RSV10
Locator Reserved input, output, high-impedance state, Connect package active, HOLD active, RESET active Follow connections specified reserved pins. 18-k 22-k pullup resistors best results. supply pins must connected common supply plane, ground pins must connected common ground plane. NOTE CVSS, VSS, IVSS same plane.
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
SMJ320C31 Functions
NAME TYPE DESCRIPTION PRIMARY INTERFACE STRB I/O/Z 32-bit data port primary interface 24-bit address port primary interface Read write. high when read performed when write performed over parallel interface. External access strobe primary interface Ready. indicates that external device prepared transaction completion. Hold. When HOLD logic low, ongoing transaction completed. STRB, high-impedance state, transactions over primary interface held until HOLD becomes logic high NOHOLD primary control register set. Hold acknowledge. HOLDA generated response logic HOLD. HOLDA indicates that STRB, high-impedance state that transactions over held. HOLDA high response logic high HOLD NOHOLD primary control register being set. CONTROL SIGNALS RESET INT3 INT0 IACK MCBL Reset. When RESET logic low, device reset condition. When RESET becomes logic high, execution begins from location specified reset vector. External interrupts Interrupt acknowledge. IACK logic high IACK instruction. IACK used indicate beginning interrupt-service routine. Microcomputer boot loader microprocessor mode select Shutdown high impedance. When active, shuts down SMJ320C31 places pins high-impedance state. used board-level testing ensure that dual drive conditions occur. CAUTION: corrupts SMJ320C31 memory register contents. Reset device with high restore known operating condition. External flags. used general-purpose support interlocked processor instruction. SERIAL PORT SIGNALS CLKR0 CLKX0 FSR0 FSX0 I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z Serial port receive clock. CLKR0 serial-shift clock serial port receiver. Serial port transmit clock. CLKX0 serial-shift clock serial port transmitter. Data receive. Serial port receives serial data DR0. Data transmit output. Serial port transmits serial data DX0. Frame synchronization pulse receive. FSR0 pulse initiates receive-data process over DR0. Frame synchronization pulse transmit. FSX0 pulse initiates transmit-data process over DX0. CONDITIONS WHEN SIGNAL
HOLD
HOLDA
XF1,
I/O/Z
input, output, high-impedance state package. connected. active, HOLD active, RESET active
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
SMJ320C31 Functions (Continued)
NAME TYPE DESCRIPTION TIMER SIGNALS TCLK0 TCLK1 I/O/Z I/O/Z Timer clock input, TCLK0 used timer count external pulses. output, TCLK0 outputs pulses generated timer Timer clock input, TCLK1 used timer count external pulses. output, TCLK1 outputs pulses generated timer SUPPLY OSCILLATOR SIGNALS VSS|| VSUBS CLKIN EMU2 EMU0 External clock. period equal twice CLKIN. External clock. period equal twice CLKIN. supply. must connected common supply plane.# Ground. grounds must connected common ground plane. Substrate pin. ground Output from internal crystal oscillator. crystal used, should left unconnected. Internal oscillator input from crystal clock RESERVEDk Reserved. pullup resistors EMU3 Reserved input, output, high-impedance state package. connected. active, HOLD active, RESET active includes AVDD, VDDL, DVDD, CVDD, PVDD. Recommended decoupling capacitor value includes DVSS, CVSS, VSSL, IVSS. Follow connections specified reserved pins. 22-k pullup resistors best results. supply pins must connected common supply plane, ground pins must connected common ground plane. CONDITIONS WHEN SIGNAL
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
SMJ320C30 Assignments
NUMBER LOCATOR/NC IACK INT0 INT1 INT2 INT3 MSTRB RESET STRB IOSTRB NAME NUMBER NUMBER NUMBER NUMBER
NAME HOLD HOLDA XRDY FSR0 FSX0 CLKR0 CLKX0 FSR1 FSX1 CLKR1 CLKX1
NAME
NAME RSV6 RSV7 RSV8 RSV9 RSV10 ADVDD{ ADVDD{ DDVDD DDVDD{
NAME XD11 XD12 XD13 XD14 XD15 XD16 XD17 XD18 XD19 XD20 XD21 XD22 XD23 XD24 XD25 XD26 XD27 XD28 XD29 XD30 XD31 DVDD DVDD DVSSW DVSSW DVSSW DVSSW IVSSw IVSSw
EMU0 EMU1 EMU2 EMU3 EMU4 EMU5 EMU6 CLKIN TCLK0 TCLK1 VBBP VSUBS VDD} VDD} VDD} VDD} VSSw XA10 XA11 XA12 RSV0 RSV1 RSV2 RSV3 RSV4 RSV5
IODVDD{ IODVDD{ IODVDD{ MDVDD{ MDVDD{ PDVDD{ CVSSw CVSSw VDD} VDD} VDD} VDD} VSSw VSSw
VSUBS XD10
ADVDD, DDVDD, IODVDD, MDVDD, PDVDD common plane internal device. common plane internal device. VSS, CVSS, IVSS common plane internal device. DVSS common plane internal device.
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
SMJ320C31 Assignments
NUMBER CLKR0 CLKX0 NAME NUMBER NAME EMU0 EMU1 EMU2 EMU3 FSR0 FSX0 HOLD HOLDA IACK INT0 NUMBER NAME INT1 INT2 INT3 MCBL RESET STRB TCLK0 TCLK1 AVDD} AVDD AVDD VDDL VDDL DVDD DVDD DVDD VDDL VDDL DVDD} DVDD} CVDD CVDD VDDL VDDL PVDD} PVDD} VDDL VDDL VSSL{ DVSS DVSS CVSS{ CVSS{
NUMBER
NAME VSSL{ VSSL{ DVSS DVSS IVSS{ CVSS{ IVSS{ DVSS
VSSL{ VSSL{ DVSS CVSS{ IVSS{ DVSS
VSSL{ IVSS{ DVSS
CVSS{ VSUBSw CVSS{ CLKIN Connect DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS
CVSS, VSSL, IVSS same plane. AVDD, DVDD, CVDD, PVDD same plane. VSUBS connects metallization. this clean ground.
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, (see Note Input voltage range, Output voltage range, Continuous power dissipation (see Note 3.15 Operating free-air temperature range, 55°C 125°C Storage temperature range, Tstg 65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: voltage values with respect VSS. Actual operating power less. This value obtained under specially produced worst-case test conditions, which sustained during normal device operation. These conditions consist continuous parallel writes checkerboard pattern both primary extension buses maximum rate possible. normal (ICC) current specification electrical characteristics table also read Calculation TMS320C30 Power Dissipation Application Report (literature number SPRA020).
recommended operating conditions (see Note
'320C30-40 '320C31-40 '320C31-50 '320C30 '320C31 Supply voltage (CVSS, etc.) High-level input voltage High-level input voltage CLKIN Low-level input voltage High-level output current Low-level output current 4.75 5.25 UNIT
Supply voltage (AVDD, etc.)
Operating free-air temperature nominal values 25°C. These values derived from characterization tested. NOTE input output voltage levels compatible.
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
electrical characteristics over recommended ranges supply voltage (unless otherwise noted) (see Note
PARAMETER High-level output voltage Low-level output voltage High-impedance current Input current Input current Input current CLKIN) XA12 others TEST CONDITIONS MIN, MIN, MIN, Inputs with internal pullups (see Note '320C30 '320C31 Supply current pply MAX, 25°C 25°C, tc(CI) MIN, Note '320C30 '320C31 '320C31 Supply current, standby; IDLE2, clock shut Input capacitance Output capacitance 25°C UNIT
CLKIN capacitance conditions shown MAX, appropriate value specified recommended operating conditions. typical values 25°C. These values derived from characterization tested. These values derived design tested. NOTES: input output voltage levels compatible. Pins with internal pullup devices: INT0 INT3, RSV0 RSV10. Although RSV0 RSV10 have internal pullup devices, external pullups should used each identified Functions tables. Actual operating current less than this maximum value. This value obtained under specially produced worst-case test conditions, which sustained during normal device operation. These conditions consist continuous parallel writes checkerboard pattern both primary expansion buses maximum rate possible. Calculation TMS320C30 Power Dissipation Application Report (literature number SPRA020).
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
PARAMETER MEASUREMENT INFORMATION
Tester Electronics
VLOAD
Output Under Test
Where: VLOAD (all outputs) (all outputs) Selected emulate termination (typical value 1.54 80-pF typical load-circuit capacitance
Figure Test Load Circuit
signal transition levels
TTL-level outputs driven minimum logic-high level maximum logic-low level Output transition times specified follows:
high-to-low transition TTL-compatible output signal, level which output said longer high level which output said low-to-high transition, level which output said longer level which output said high
Figure TTL-Level Outputs Transition times TTL-compatible inputs specified follows:
high-to-low transition input signal, level which input said longer high level which input said low-to-high transition input signal, level which input said longer level which input said high
Figure TTL-Level Inputs
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
PARAMETER MEASUREMENT INFORMATION SMJ320C30, SMJ320C31 timing parameter symbology
Timing parameter symbols used herein were created accordance with JEDEC Standard 100-A. order shorten symbols, some terminal names other related terminology have been abbreviated follows, unless otherwise noted:
ASYNCH Asynchronous reset signals, include XF0, XF1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, CLKX1, DX1, FSX1, CLKR1, DR1, FSR1, TCLK0, TCLK1 CLKX, includes CLKX0 CLKX1 CLKIN Control signals, include STRB, MSTRB, IOSTRB Includes DR0, Includes DX0, FSX/R, includes FSX0, FSX1, FSR0, FSR1 Includes FSR0, FSR1 Includes FSX0, FSX1 General-purpose input/output; peripheral pins include CLKX0/1, CLKR0/1, DX0/1, DR0/1, FSX0/1, FSR0/1, TCLK0/1 Includes HOLD HOLDA IACK (M)S RESET TCLK (X)A (X)D (X)RDY (X)RW IACK INT3- INT0 IOSTRB (M)STRB, includes MSTRB STRB RESET STRB CLKX/R, includes CLKX0, CLKX1, CLKR0, CLKR1 TCLK0, TCLK1 Includes XA12 Includes XD31 XFx, includes Includes XRDY (X)R/W, includes XR/W
CONTROL GPIO
HOLD HOLDA
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
timing parameters X2/CLKIN, (see Note Figure Figure Figure Figure
tf(CI) tw(CIL) tw(CIH) tr(CI) tc(CI) tf(H) tw(HL) tw(HH) tr(H) td(HL-HH) Fall time, CLKIN Pulse duration, CLKIN low, tc(CI) (see Note Pulse duration, CLKIN high, tc(CI) (see Note Rise time, CLKIN Cycle time, CLKIN Fall time, Pulse duration, (see Note Pulse duration, high (see Note Rise time, Delay time, from high from high 10.5 10.5 '320C30-33 '320C31-33 '320C30-40 '320C31-40 '320C31- UNIT
tc(H) Cycle time, These values derived design tested. These values derived from characterization tested. NOTES: input output voltage levels compatible. Rise fall times, assuming duty cycle, incorporated within this specification (see TAG). tc(CI) CLKIN (1.5
Figure CLKIN Timing
Figure Timings
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
timing parameters X2/CLKIN, (see Note Figure Figure Figure Figure (continued)
CLKIN 55°C
SMJ320C30
25°C Temperature
125°C
Figure CLKIN Function Temperature (Typical Guaranteed)
CLKIN
SMJ320C31
55°C 25°C Temperature 125°C
Figure CLKIN Function Temperature (Typical Guaranteed)
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
memory-read-cycle memory-write-cycle timing [(M)STRB (see Figure Figure
Delay time, (M)STRB Delay time, (M)STRB high Delay time, high Delay time, high (X)R Delay time, valid Delay time, (X)A valid Setup time, valid before (read) Setup time, (X)D before (read) Hold time, (X)D after (read) Setup time, before high Setup time, (X)RDY before high Hold time, (X)RDY after high Delay time, high (X)R high (write) Valid time, (X)D after (write) Hold time, (X)D after high (write) Delay time, high valid back-to-back write cycles (write) Delay time, high (X)A valid back-to-back write cycles (write) '320C30-33 '320C31-33 13.1 13.2 14.1 14.2 15.1 15.2 17.1 17.2 22.1 td[H1L-(M)SL] td[H1L-(M)SH] td(H1H-RWL) td[H1H-(X)RWL] td(H1L-A) td[H1L-(X)A] tsu(D-H1L)R tsu[(X)DR-H1L]R th[H1L-(X)D]R tsu(RDY-H1H) tsu[(X)RDY-H1H] th[H1H-(X)RDY] td[H1H-(X)RWH]W tv[H1L(X)D]W th[H1H-(X)D]W td(H1H-A) td[H1H-(X)A] '320C30-40 '320C31- '320C31- UNIT
td[A-(X)RDY] Delay time, (X)RDY from valid These values derived design tested. These values derived from characterization tested. This value frequency-dependent calculated (delay, high) (parameter 14.x) (parameter 17.x)
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
memory-read-cycle memory-write-cycle timing [(M)STRB (see Figure Figure (continued)
(M)STRB
(X)R
14.1 14.2 13.1
(X)A 15.1 15.2 (X)D 17.1 17.2
(X)RDY
Figure Memory-Read-Cycle Timing [(M)STRB
(M)STRB
13.1 13.2 (X)R 14.1 14.2 22.1 22.2 (X)A (X)D 17.1 17.2 (X)RDY
Figure Memory-Write-Cycle Timing [(M)STRB
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
memory-read-cycle timing (IOSTRB SMJ320C30 only) (see Figure
td(H1H-IOSL) td(H1H-IOSH) td[H1L-(X)RWH] td[H1L-(X)A] tsu[(X)D-H1H]R th[H1H-(X)D]R tsu[(X)RDY-H1H] th[H1H-(X)RDY] Delay time, high IOSTRB Delay time, high IOSTRB high Delay time, (X)R high Delay time, (X)A valid Setup time, (X)D before high Hold time, (X)D after high Setup time, (X)RDY before high Hold time, (X)RDY after high '320C30-33 '320C30-40 UNIT
These values derived design tested. These values derived from characterization tested.
IOSTRB (X)R (X)A (X)D (X)RDY
Figure SMJ320C30 Memory-Read-Cycle Timing (IOSTRB
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
memory-write-cycle timing (IOSTRB SMJ320C30 only) (see Figure
td(H1H-IOSL) td(H1H-IOSH) td[H1L-(X)RWH] td[H1L-(X)A] tsu[(X)RDY-H1H] th[H1H-(X)RDY] td(H1L-XRWL) tv[H1H(X)D]W Delay time, high IOSTRB Delay time, high IOSTRB high Delay time, (X)R high Delay time, (X)A valid Setup time, (X)RDY before high Hold time, (X)RDY after high Delay time, Valid time, (X)D after high '320C30-33 '320C30-40 UNIT
th[H1L-(X)D]W Hold time, (X)D after These values derived design tested.
IOSTRB (X)R (X)A (X)D (X)RDY
Figure SMJ320C30 Memory-Write-Cycle Timing (IOSTRB
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
timing when executing LDFI LDII (see Figure
td(H3H-XF0L) tsu(XF1-H1L) th(H1L-XF1) Delay time, high Setup time, valid before Hold time, after '320C30-33 '320C31-33 '320C30-40 '320C31-40 '320C31- UNIT
Fetch LDFI LDII
Decode
Read
Execute
(M)STRB
(X)R
(X)A
(X)D
(X)RDY
Figure Timing When Executing LDFI
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
timing when executing STFI STII (see Figure
td(H3H-XF0H) Delay time, high high '320C30 '320C31 '320C30 '320C31 '320C31 UNIT
Fetch STFI STII
Decode
Read
Execute
(M)STRB
(X)R/W
(X)A
(X)D
(X)RDY
Figure Timing When Executing STFI STII
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
timing when executing SIGI (see Figure
41.1 td(H3H-XF0L) td(H3H-XF0H) tsu(XF1-H1L) th(H1L-XF1) Delay time, high Delay time, high high Setup time, valid before Hold time, after Fetch SIGI '320C30 '320C31 '320C30 '320C31 '320C31 UNIT
Decode
Read
Execute
41.1
Figure Timing When Executing SIGI
timing loading register when configured output (see Figure
tv(H3H-XF) Valid time, high valid '320C30 '320C31 '320C30 '320C31 '320C31 UNIT
Fetch Load Instruction
Decode
Read
Execute
OUTXF
Figure Timing Loading Register When Configured Output
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
change from output input mode (see Figure
td(H3H-XFx) tsu(XFx-H1L) Delay time, after high Setup time, before '320C30 '320C31 '320C30 '320C31 '320C31 UNIT
th(H1L-XFx) Hold time, after These values derived from characterization tested.
Execute Load
Buffers From Output Input
Synchronizer Delay
Value Terminal Seen
I/OXFx (see Note Output
INXFx (see Note
Data Sampled
Data Seen
NOTE OXFx represents either register, INXFx represents either register depending whether XF1, respectively, being affected.
Figure Change From Output Input Mode
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
change from input output mode (see Figure
Delay time, high switching from input output '320C30 '320C31 td(H3H-XFIO) '320C30 '320C31 '320C31 UNIT
Execution Load
I/OXFx (see Note (see Note NOTE OXFx represents either register, INXFx represents either register depending whether XF1, respectively, being affected.
Figure Change From Input Output Mode
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
reset timing
RESET asynchronous input that asserted time during clock cycle. specified timings met, exact sequence shown Figure occurs; otherwise, additional delay clock cycle occur. high-impedance state during reset provided with resistive pullup, nominally prevent spurious writes from occurring. asynchronous reset signals include XF0/1, CLKX0/1, DX0/1, FSX0/1, CLKR0/1, DR0/1, FSR0/1, TCLK0/1. HOLD asynchronous input asserted during reset. Resetting device initializes primary- expansion-bus control registers seven software wait states and, therefore, results slow external accesses until these registers initialized.
reset timing tc(CI)] (see Figure
tsu(RESET) td(CLKINH-H1H) td(CLKINH-H1L) tsu(RESETH-H1L) td(CLKINH-H3L) td(CLKINH-H3H) tdis(H1H-XD) tdis(H3H-XA) td(H3H-CONTROLH) td(H1H-IACKH) tdis(RESETL-ASYNCH) Setup time, RESET before CLKIN Delay time, CLKIN high Delay time, CLKIN high Setup time, RESET high before after clock cycles Delay time, CLKIN high Delay time, CLKIN high Disable time, high (X)D high-impedance state Disable time, high (X)A high-impedance state Delay time, high control signals high Delay time, high IACK high Disable time, RESET asynchronous reset signals high-impedance state '320C30 '320C31 '320C30 '320C31 '320C31 UNIT
These values derived from characterization tested. These values derived design tested. Figure Figure temperature dependence 40-MHz SMJ320C30 SMJ320C31.
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
reset timing (continued)
CLKIN RESET Clock Cycles (X)D (see Note (X)A (see Note Control Signals (see Note IACK Asynchronous Reset Signals (see Note NOTES:
this diagram X(D) includes XD31 XD0. this diagram, (X)A includes XA12 XA0. Control signals include STRB, MSTRB, IOSTRB. Asynchronous reset signals include XF1, XF0, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, CLKX1, DX1, FSX1, CLKR1, DR1, FSR1, TCLK0, TCLK1. microprocessor mode, reset vector fetched twice, with seven software wait states each time. micromputer mode, reset vector fetched twice, with software wait states.
Figure Reset Timing tc(Cl)]
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
INT3-INT0 response timing tc(H)] (see Figure
tsu(INT) tw(INT) Setup time, INT3 INT0 before Pulse duration, INT3 INT0, assure only interrupt seen (see Notes '320C30 '320C31 '320C30 '320C31 '320C31 UNIT
These values derived from characterization tested. NOTES: Interrupt pulse duration must least wide ensure seen. must less than wide ensure responded only once. INT3 INT0 asynchronous inputs asserted point during clock cycle. SMJ320C3x interrupts level-sensitive, edge-sensitive. Interrupts detected falling edge processor recognize only interrupt given input, interrupt pulse must held minimum falling edge more than falling edges. SMJ320C3x accept interrupt from same source every clock cycles. specified timings met, exact sequence shown occurs; otherwise, additional delay clock cycle occur. Reset Interrupt Vector Read
Fetch First Instruction Service Routine
INT3 INT0 Pins INT3 INT0 Flag Vector Address Addr First Instruction Address
Data
Figure INT3 INT0 Response Timing tc(H)]
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
interrupt-acknowledge (IACK) timing (see Figure
td(H1H-IACKL) td(H1H-IACKH) Delay time, high IACK Delay time, high IACK high '320C30 '320C31 '320C30 '320C31 '320C31 UNIT
Fetch IACK Instruction
IACK Data Read
IACK
Address
Data
Figure Interrupt-Acknowledge (IACK) Timing
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
serial-port timing (see Figure Figure
td(H1-SCK) tc(SCK) tw(SCK) tr(SCK) tf(SCK) td(DX) tsu(DR) th(DR) td(FSX) tsu(FSR) th(FS) tsu(FSX) td(CH DX)V d(CH-DX)V td(FSX-DX)V tdDXZ Delay time, high internal CLKX Cycle time, CLKX time Pulse duration CLKX high duration, Rise time, CLKX Fall time, CLKX Delay time CLKX valid time, Setup time before CLKR time, Hold time from CLKR time, Delay time CLKX internal high time, Setup time, before CLKR time Hold time input from CLKX time, Setup time external before CLKX time, Delay time, CLKX first bit, precedes CLKX high Delay time, first bit, CLKX precedes Delay time, CLKX high high impedance following last data CLKX CLKX CLKR CLKR CLKR CLKR CLKX CLKX CLKR CLKR CLKX CLKX CLKX CLKX CLKX CLKX [tc(H) [tc(H) -21] [tc(SCK) tc(SCK) [tc(H) [tc(H) [tc(SCK) tc(SCK) CLKX CLKX CLKX CLKX tc(H)+12 [tc(SCK) [tc(SCK) 2]+5 CLOCK SOURCE '320C30 '320C31 tc(H)+12 [tc(SCK) [tc(SCK) 2]+5 '320C30 '320C31 UNIT
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Template Release Date: 7-11-94
These values derived from characterization tested. These values derived design tested.
serial-port timing (see Figure Figure (continued)
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CLOCK SOURCE td(H1-SCK) tc(SCK) tw(SCK) tr(SCK) tf(SCK) td(DX) tsu(DR) th(DR) td(FSX) tsu(FSR) th(FS) tsu(FSX) td(CH DX)V d(CH-DX)V td(FSX-DX)V tdDXZ Delay time, high internal CLKX Cycle time, CLKX time Pulse duration CLKX high duration, Rise time, CLKX Fall time, CLKX Delay time CLKX valid time, Setup time before CLKR time, Hold time from CLKR time, Delay time CLKX internal high time, Setup time, before CLKR time Hold time input from CLKX time, Setup time external before CLKX time, Delay time, CLKX first bit, precedes CLKX high Delay time, first bit, CLKX precedes CLKX CLKX CLKR CLKR CLKR CLKR CLKX CLKX CLKR CLKR CLKX CLKX CLKX CLKX CLKX CLKX CLKX CLKX CLKX CLKX
'320C31 tc(H)+10 [tc(SCK) [tc(SCK) 2]+5 [tc(H) [tc(H) [tc(SCK) tc(SCK)
UNIT
SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
Delay time, CLKX high high impedance following last data These values derived from characterization tested. These values derived design tested.
SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
serial-port timing (continued)
CLKX/ (int) (ext) NOTES: Timing diagrams show operations with serial port global-control register bits CLKXP CLKRP FSXP FSRP These timings valid serial-port modes, including handshake, except where otherwise indicated. functional description serial port operation, refer TMS320C3x User's Guide (literature number SPRU031D). Timing diagrams depend upon length serial-port word, where bits, respectively.
Figure Serial-Port Timing, Fixed-Data-Rate Mode
CLKX (int) (ext) NOTES:
Timing diagrams show operations with serial port global-control register bits CLKXP CLKRP FSXP FSRP These timings valid serial-port modes, including handshake, except where otherwise indicated. Timings expressly specified variable-data-rate mode same those fixed-data-rate mode. Timing diagrams depend upon length serial-port word, where bits, respectively.
Figure Serial-Port Timing, Variable-Data-Rate Mode
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
HOLD/HOLDA timing (see Note Figure
tsu(HOLD) tv(HOLDA) tw(HOLD) tw(HOLDA) td(H1L-SH)H tdis(H1L-S) ten(H1L-S) tdis(H1L-RW) ten(H1L-RW) tdis(H1L-A) ten(H1L-A) tdis(H1H-D) Setup time, HOLD before Valid time, HOLDA after Pulse duration, HOLD Pulse duration, HOLDA Delay time, STRB high HOLD Disable time, STRB high impedance Enable time, STRB active Disable time, high impedance Enable time, active Disable time, address high impedance Enable time, address valid Disable time, high data high impedance '320C30 '320C31 2tc(H) tc(H) '320C30 '320C31 2tc(H) tc(H) '320C31 2tc(H) UNIT
These values derived design tested. These values derived from characterization tested. NOTE HOLD asynchronous input asserted point during clock cycle. specified timings met, exact sequence shown Figure occurs; otherwise, additional delay clock cycle occur. NOHOLD primary-bus-control register (refer TMS320C3x User's Guide, literature number SPRU031D) overrides HOLD signal. When this set, device comes hold prevents future hold cycles from occurring.
HOLD HOLDA (see Note STRB Write Data
NOTE HOLDA goes response HOLD going continues remain through cycle after HOLD returns high.
Figure HOLD HOLDA Timing
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
peripheral-pin general-purpose timing (see Note Figure
tsu(GPIOH1L) th(GPIOH1L) Setup time, general-purpose input before Hold time, general-purpose input after '320C30 '320C31 '320C30 '320C31 '320C31 UNIT
td(GPIOH1H) Delay time, general-purpose output after high NOTE Peripheral pins include CLKX0 CLKR0 FSX0 FSR0 TCLK0 modes these pins defined contents internal control registers associated with each peripheral.
Peripheral
Figure Peripheral-Pin General-Purpose Timing
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
change peripheral from general-purpose output input mode (see Figure
th(H1H) tsu(GPIOH1L) th(GPIOH1L) Hold time after high Setup time, peripheral before Hold time, peripheral after '320C30 '320C31 '320C30 '320C31 '320C31 UNIT
Execute Store Peripheral Control Register
Buffers From Output Input
Synchronizer Delay
Value Terminal Seen Peripheral Control Register
Control Peripheral Output
Data Data Sampled Data Seen
Figure Change Peripheral From General-Purpose Output Input Mode
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
change peripheral from general-purpose input output mode (see Figure
Delay time, high peripheral switching from input output '320C30 '320C31 td(GPIOH1H) '320C30 '320C31 '320C31 UNIT
Execution Store Peripheral Control Register
Control Peripheral
Figure Change Peripheral From General-Purpose Input Output Mode
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
timing parameters timer (see Figure
tsu(TCLK-H1L) th(TCLK-H1L) td(TCLK-H1H) tc(TCLK) tw(TCLK) Setup time, TCLK before Hold time, TCLK after Delay time, high TCLK valid Cycle time TCLK time, Pulse duration TCLK high duration, TCLK TCLK TCLK TCLK TCLK TCLK TCLK tc(H) tc(H) tc(H) [tc(TCLK) tc(H) [tc(TCLK) 2]+5 '320C30 '320C31 UNIT
tsu(TCLK-H1L) th(TCLK-H1L) td(TCLK-H1H) tc(TCLK) tw(TCLK) Setup time, TCLK before Hold time, TCLK after Delay time, high TCLK valid Cycle time TCLK time, Pulse duration TCLK high duration, TCLK TCLK TCLK TCLK TCLK TCLK TCLK
'320C30 '320C31 tc(H) tc(H) tc(H) [tc(TCLK) tc(H) [tc(TCLK) 2]+5
UNIT
tsu(TCLK-H1L) th(TCLK-H1L) td(TCLK-H1H) tc(TCLK) tw(TCLK) Setup time, TCLK before Hold time, TCLK after Delay time, high TCLK valid Cycle time TCLK time, Pulse duration TCLK high duration, TCLK TCLK TCLK TCLK TCLK TCLK TCLK
'320C31 tc(H) tc(H) tc(H) tc(H)
UNIT
[tc(TCLK) [tc(TCLK) 2]+5 Timing parameters applicable synchronous input clock. Timing parameters applicable asynchronous input clock. Assured design tested
Timer NOTE Period polarity valid logic level specified contents internal control registers.
Figure Timer-Pin Timing
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
timing parameters tc(CI)] (see Figure
'320C30 '320C31 '320C30 '320C31 tdis(SHZ) ten(SHZ) Disable time, high impedance Enable time, high active '320C31-50
UNIT
These values derived from characterization tested.
(see Note
NOTE Enabling destroys SMJ320C3x register memory contents. Assert reset SMJ320C3x restore known condition.
Figure Timing
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
SMJ320C30 part order information
DEVICE SMJ320C30GBM33 SM320C30GBM33 5962-9052603MXA SMJ320C30HFGM33 SM320C30HFGM33 5962-9052603MUA SMJ320C30GBM40 SM320C30GBM40 SMJ320C30TAM33 SM320C30TAM33 SMJ320C30TBM33 SM320C30TBM33 SMJ320C30HFGM40 SM320C30HFGM40 5962-9052604MUA 5962-9052604MXA TECHNOLOGY 0.8-µm CMOS 0.8-µm CMOS 0.8-µm CMOS 0.8-µm CMOS 0.8-µm CMOS 0.8-µm CMOS 0.8-µm CMOS 0.8-µm CMOS 0.8-µm CMOS 0.8-µm CMOS 0.8-µm CMOS 0.8-µm CMOS 0.8-µm CMOS 0.8-µm CMOS 0.8-µm CMOS 0.8-µm CMOS POWER SUPPLY OPERATING FREQUENCY PACKAGE TYPE Ceramic 181-pin Ceramic 181-pin Ceramic 181-pin Ceramic 196-pin quad flatpack with nonconductive Ceramic 196-pin quad flatpack with nonconductive Ceramic 196-pin quad flatpack with nonconductive Ceramic 181-pin Ceramic 181-pin 203-lead frame with polyimide encapsulant 203-lead frame with polyimide encapsulant 203-lead frame bare-die option 203-lead frame with bare-die option Ceramic 196-pin quad flatpack with nonconductive Ceramic 196-pin quad flatpack with nonconductive Ceramic 196-pin quad flatpack with nonconductive Ceramic 181-pin PROCESSING LEVEL Standard DESC Standard DESC Standard Standard Standard Standard DESC DESC
PREFIX
MIL-STD-38535 (QML) Standard Processing
SPEED RANGE TEMPERATURE RANGE 55°C 125°C 70°C PACKAGE TYPE 181-Pin Grid Array (PGA) Ceramic Package 196-Pin Ceramic Quad Flatpack with nonconductive 203-lead frame with polyimide encapsulant 203-lead frame, bare-die option Known Good
DEVICE FAMILY SMJ320 Family
TECHNOLOGY CMOS
DEVICE '320C30
Figure SMJ320C30 Device Nomenclature
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
SMJ320C31 part order information
DEVICE SMJ320C31GFAM33 SM320C31GFAM33 SMJ320C31GFAM40 SM320C31GFAM40 SMJ320C31HFGM33 SM320C31HFGM33 SMJ320C31HFGM40 SM320C31HFGM40 SMJ320C31TAM33 SM320C31TAM33 SMJ320C31TBM33 SM320C31TBM33 SMJ320C31GFAM50 SM320C31GFAM50 SMJ320C31HFGM50 SM320C31HFGM50 5962-9205802MXA 5962-9205802MYA 5962-9205803MXA 5962-9205803MYA 5962-9205804MXA 5962-9205804MYA TECHNOLOGY 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS POWER SUPPLY OPERATING FREQUENCY PACKAGE TYPE Ceramic 141-pin staggered Ceramic 141-pin staggered Ceramic 141-pin staggered Ceramic 141-pin staggered Ceramic 132-pin quad flatpack with nonconductive Ceramic 132-pin quad flatpack with nonconductive Ceramic 132-pin quad flatpack with nonconductive Ceramic 132-pin quad flatpack with nonconductive 132-lead frame with polyimide encapsulant 132-lead frame with polyimide encapsulant 132-lead frame bare-die option 132-lead frame with bare-die option Ceramic 141-pin staggered Ceramic 141-pin staggered Ceramic 132-pin quad flatpack with nonconductive Ceramic 132-pin quad flatpack with nonconductive 141-pin CPGA 132-pin CQFP 141-pin CPGA 132-pin CQFP Ceramic 141-pin staggered Ceramic 132-pin quad flatpack with nonconductive bar. PROCESSING LEVEL Standard Standard Standard Standard DESC DESC DESC DESC DESC DESC
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
SMJ320C31 part order information (continued)
PREFIX
MIL-PRF-38535 (QML) Standard Processing
SPEED RANGE
DEVICE FAMILY SMJ320 Family
TEMPERATURE RANGE 55°C 125°C 70°C PACKAGE TYPE 141-Pin Staggered Grid Array Ceramic Package 132-Pin Ceramic Quad Flatpack with nonconductive 132-lead frame with polyimide encapsulant 132-lead frame, bare-die option Known Good
TECHNOLOGY CMOS
DEVICE '320C31
Figure SMJ320C31 Device Nomenclature
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
SMJ320C30 (Rev. Inner Lead Bond (ILB) Information Number Side Number Designator
Side Number
Side Number
Zero-Zero (Origin)
Side Number
Figure SMJ320C30 Numbering Format (Refer Table inner lead bond (ILB) pitch leadframe same bond pitch. Table provides reference following: lead numbers. lead numbers same bond numbers. 'C30 signal identities relation numbers Signal functions that more than test location. (There bond locations, leads, test locations.) 'C30 X-,Y-coordinates, where bond serves origin, (0,0) pitch leadframe
addition, following notes significant: coordinate data microns. Coordinate origin (0,0) (center bond 51). Average pitch (7.32 mils). Smallest pitch value 156,8 (6.17 mils). active silicon dimensions 10224,00 11032,00 (402.52 mils 434.33 mils). size approximately 10541,00 11353,8 (415.00 mils 447.00 mils). Distance from diced silicon polyimide support ring 1016,0 mils). Bond dimensions 115,00 115,00 (4.53 mils 4.53 mils). Center bond edge ranges from (7.1 mils mils). range (1.57 mils) exists since dicing process will result some tolerance. consistency precision bond locations reference each other, center bond chosen origin.
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
Table SMJ320C30 Lead Information Rev. (0,8
SIDE BOND LOCATIONS DIE/TAB BOND IDENTITY PDVDD PDVDD FSR0 CLKR0 CLKX0 FSX0 TCLK0 TCLK1 EMU6 IODVDD IODVDD XD10 XD11 XD12 XD13 XD14 XD15 XD16 XD17 XD18 XD19 XD20 XD21 XD22 XD23 XD24 XD25 XD26 XD27 XD28 XD29 XD30 IODVDD IODVDD TEST LOCATIONS X-COORDINATE BOND Y-COORDINATE BOND 9563.00 9367.80 9199.20 9007.20 8823.20 8631.20 8447.20 8255.20 8071.20 7879.20 7695.20 7503.20 7319.20 7127.20 6947.00 6751.80 6853.20 6399.20 6207.20 6023.20 5831.20 5647.20 5455.20 5271.20 5083.00 4887.80 4731.00 4535.80 4367.20 4183.20 3991.20 3807.20 3615.20 3431.20 3239.20 3055.20 2863.20 2679.20 2487.20 2303.20 2111.20 1927.20 1735.20 1551.20 1359.20 1175.20 983.20 799.20 619.00 423.80 PITCH LEAD REFERENCE WHICH BOND PADS 195.20 (1,2) 168.60 (2,3) 192.00 (3,4) 184.00 (4,5) 192.00 (5,6) 184.00 (6,7) 192.00 (7,8) 184.00 (8,9) 192.00 (9,10) 184.00 (10,11) 192.00 (11,12) 184.00 (12,13) 192.00 (13,14) 180.20 (14,15) 195.20 (15,16) 168.60 (16,17) 184.00 (17,18) 192.00 (18,19) 184.00 (19,20) 192.00 (20,21) 184.00 (21,22) 192.00 (22,23) 184.00 (23,24) 188.20 (24,25) 195.20 (25,26) 156.80 (26,27) 195.20 (27,28) 168.60 (28,29) 184.00 (29,30) 192.00 (30,31) 184.00 (31,32) 192.00 (32,33) 184.00 (33,34) 192.00 (34,35) 184.00 (35,36) 192.00 (36,37) 184.00 (37,38) 192.00 (38,39) 184.00 (39,40) 192.00 (40,41) 184.00 (41,42) 192.00 (42,43) 184.00 (43,44) 192.00 (44,45) 184.00 (45,46) 192.00 (46,47) 184.00 (47,48) 180.20 (48,49) 195.20 (49,50)
423.80
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
Table SMJ320C30 Lead Information Rev. (0,8 (Continued)
SIDE BOND LOCATIONS DIE/TAB BOND IDENTITY DVSS DVSS CVSS CVSS XD31 ADVDD ADVDD EMU0 EMU1 EMU2 EMU3 EMU4/SHZ MC/MP XA12 XA11 XA10 IVSS IVSS DVSS DVSS TEST LOCATIONS 117, 120, X-COORDINATE BOND 0.00 195.2 374.80 570.00 746.60 938.60 1138.60 1338.60 1530.60 1730.60 1922.60 2122.60 2322.60 2514.36 2902.80 2714.60 2902.80 3098.00 3274.60 3474.60 3666.60 3866.60 4258.60 4458.60 4650.60 4846.80 5042.00 5214.80 2410.00 5578.60 5778.60 5970.60 6170.60 6370.60 6562.60 6774.80 6990.80 7198.80 7402.60 7606.80 7822.80 8026.60 8218.60 8418.60 8610.60 8810.60 9010.60 9202.60 9398.80 9594.00 9758.80 9954.00 Y-COORDINATE BOND PITCH LEAD REFERENCE WHICH BOND PADS 195.20 (51, 179.60 (52, 195.20 (53, 176.60 (54, 192.00 (55, 200.00 (56, 200.00 (57, 192.00 (58, 200.00 (59, 192.00 (60, 200.00 (61, 200.00 (62, 192.00 (63, 200.00 (64, 188.20 (65, 195.20 (66, 176.60 (67, 200.00 (68, 192.00 (69, 200.00 (70, 200.00 (71, 192.00 (72, 200.00 (73, 192.00 (74, 196.20 (75, 195.20 (76, 172.80 (77, 195.20 (78, 168.60 (79, 200.00 (80, 192.00 (81, 200.00 (82, 200.00 (83, 192.00 (84, 212.20 (85, 216.00 (86, 208.00 (87, 203.80 (88, 204.20 (89, 216.00 (90, 203.80 (91, 192.00 (92, 200.00 (93, 192.00 (94, 200.00 (95, 200.00 (96, 192.00 (97, 196.20 (98, 195.20 (99, 100) 164.80 (100, 101) 195.20 (101, 102)
0.00
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
Table SMJ320C30 Lead Information Rev. (0,8 (Continued)
SIDE BOND LOCATIONS DIE/TAB BOND IDENTITY ADVDD ADVDD DDVDD DDVDD DDVDD DDVDD TEST LOCATIONS 123, 125, 139, 141, 151, 153, 154, 156, 158, 180, 182, X-COORDINATE BOND Y-COORDINATE BOND 430.60 625.80 764.40 986.40 1170.40 1362.40 1546.40 1738.40 1922.40 2114.40 2298.40 2490.40 2674.40 2866.40 3046.60 3241.80 3410.40 3594.40 3786.40 3970.40 4162.40 4346.40 4538.40 4722.40 4910.60 5105.80 5262.60 5457.80 5626.40 5810.40 6002.40 6186.40 6378.40 6562.40 6754.40 6938.40 7130.40 7314.40 7506.40 7690.40 7882.40 8066.40 8258.40 8442.40 8634.40 8818.40 9010.40 9194.40 9374.60 9569.80 PITCH LEAD REFERENCE WHICH BOND PADS 195.20 (103,104) 168.60 (104,105) 192.00 (105,106) 184.00 (106,107) 192.00 (107,108) 184.00 (108,109) 192.00 (109,110) 184.00 (110,111) 192.00 (111,112) 184.00 (112,113) 192.00 (113,114) 184.00 (114,115) 192.00 (115,116) 180.20 (116,117) 195.20 (117,118) 168.60 (118,119) 184.00 (119,120) 192.00 (120,121) 184.00 (121,122) 192.00 (122,123) 184.00 (123,124) 192.00 (124,125) 184.00 (125,126) 188.20 (126,127) 195.20 (127,128) 156.80 (128,129) 195.20 (129,130) 168.60 (130,131) 184.00 (131,132) 192.00 (132,133) 184.00 (133,134) 192.00 (134,135) 184.00 (135,136) 192.00 (136,137) 184.00 (137,138) 192.00 (138,139) 184.00 (139,140) 192.00 (140,141) 184.00 (141,142) 192.00 (142,143) 184.00 (143,144) 192.00 (144,145) 184.00 (145,146) 192.00 (146,147) 184.00 (147,148) 192.00 (148,149) 184.00 (149,150) 180.20 (150,151) 195.20 (151,152)
10377.80
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
Table SMJ320C30 Lead Information Rev. (0,8 (Continued)
SIDE BOND LOCATIONS DIE/TAB BOND IDENTITY DVSS DVSS CVSS CVSS X2/CLKIN VSUBS VBBP EMU5 XRDY MSTRB IOSTRB XR/W HOLDA HOLD MDVDD MDVDD STRB RESET IACK INT0 INT1 INT2 INT3 RSV0 RSV1 RSV2 RSV3 RSV4 RSV5 RSV6 RSV7 RSV8 RSV9 RSV10 FSR1 CLKR1 CLKX1 FSX1 DVSS DVSS TEST LOCATIONS 185, 188, 192, 203, 213, 215, 217, 219, 241, 243, X-COORDINATE BOND 9947.20 9752.00 9587.20 9392.00 9217.00 9043.80 8696.00 8535.40 7935.40 7739.40 7551.40 7359.40 7175.40 6991.40 6795.20 6611.20 6416.00 6243.20 6055.40 5863.40 5667.20 5479.40 5295.40 5111.40 4915.20 4731.20 4536.00 4371.20 4176.00 4003.20 3803.20 3603.20 3403.20 3203.20 3003.20 2795.20 2595.20 2407.40 2223.40 2039.40 1855.40 1671.40 1479.40 1295.40 1111.40 927.40 743.40 559.40 375.40 195.20 0.00 Y-COORDINATE BOND PITCH LEAD REFERENCE WHICH BOND PADS 195.20 (153,154) 164.80 (154,155) 195.20 (155,156) 175.00 (156,157) 173.20 (157,158) 347.80 (158,159) 160.60 (159,160) 600.00 (160,161) 196.00 (161,162) 188.00 (162,163) 192.00 (163,164) 184.00 (164,165) 184.00 (165,166) 196.20 (166,167) 184.00 (167,168) 195.20 (168,169) 172.80 (169,170) 187.80 (170,171) 192.00 (171,172) 196.20 (172,173) 187.80 (173,174) 184.00 (174,175) 184.00 (175,176) 196.20 (176,177) 184.00 (177,178) 195.20 (178,179) 164.80 (179,180) 195.20 (180,181) 172.80 (181,182) 200.00 (182,183) 200.00 (183,184) 200.00 (184,185) 200.00 (185,186) 200.00 (186,187) 208.00 (187,188) 200.00 (188,189) 187.80 (189,190) 184.00 (190,191) 184.00 (191,192) 184.00 (192,193) 184.00 (193,194) 192.00 (194,195) 184.00 (195,196) 184.00 (196,197) 184.00 (197,198) 184.00 (198,199) 184.00 (199,200) 184.00 (200,201) 180.20 (201,202) 195.20 (202,203)
9986.80 9986.80
9993.60
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
MECHANICAL DATA
WITH PROTECTIVE FILM) SMJ320C30 244-PIN FRAME (PG5) SOCKET, OLB/ILB 0,25-mm PITCH
0,26 0,24
12,52 12,48
Leads 0,26 12,27 0,24 12,23
Face
2,25 Places)
0,26 0,24
12,77 12,73
4081546/A 11/95
16,00 Places)
NOTES:
linear dimensions millimeters. This drawing subject change without notice. lead width 0,1016 0,02 lead width 0,0832 0,015 Tape width encapsulated with polyimide overcoat.
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0,26 12,27 0,24 12,23
SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
MECHANICAL DATA
WITHOUT PROTECTIVE FILM) SMJ320C30 244-PIN FRAME (PG5) SOCKET, OLB/ILB 0,25-mm PITCH
0,26 0,24
12,52 12,48
Leads 0,26 12,27 0,24 12,23
Face
2,25 Places)
0,26 0,24
12,77 12,73
4081547/A 11/95
16,00 Places)
NOTES:
linear dimensions millimeters. This drawing subject change without notice. lead width 0,1016 0,02 lead width 0,0832 0,015 Tape width bare die.
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0,26 12,27 0,24 12,23
SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
SMJ320C31 (Rev. Inner Lead Bond Information Number (Origin) Side Number
XXXX
Designator
Side Number
Side Number
Side Number
Figure SMJ320C31 Numbering Format (Refer Table inner lead bond (ILB) pitch leadframe same bond pitch. Table provides reference following: lead numbers. lead numbers same bond numbers. 'C31 signal identities relation numbers Signal functions that more than test location. (There bond locations, leads, test locations.) 'C31 X-,Y-coordinates, where bond serves origin, (0,0) pitch leadframe
addition, following notes significant: X-,Y-coordinate data microns. Coordinate origin (0,0) (center bond Average pitch (9.17 mils). Smallest pitch value 179,6 (7.07 mils). active silicon dimensions 10215,20 10324,00 (402.17 mils 406.46 mils). size approximately 10541 10642,60 (415.00 mils 419.00 mils). Distance from diced silicon polyimide support ring 635.00 mils).
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
Table SMJ320C31 Lead Information Rev. (0,8
SIDE BOND LOCATIONS BOND IDENTITY DVSS AVDD CVSS VDDL VDDL VSSL VSSL DVSS DVDD IVSS DVDD TEST LOCATIONS X-COORDINATE CENTER BOND Y-COORDINATE CENTER BOND 0.00 -300.00 -569.20 -843.80 -1137.00 -1415.60 -1710.80 -1974.00 -2251.40 -2536.40 -2809.80 -3108.20 -3406.00 -3662.80 -3983.60 -4164.00 -4457.80 -4821.40 -5001.40 -5316.80 -5594.80 -5873.20 -6193.40 -6543.20 -6796.40 -7102.20 -7374.40 -7659.60 -7947.40 -8237.80 -8496.60 -8788.20 -9012.40 PITCH LEAD REFERENCE WHICH BOND PADS 300.00 (1,2) 269.20 (2,3) 274.60 (3,4) 293.20 (4,5) 278.60 (5,6) 295.20 (6,7) 263.20 (7,8) 277.40 (8,9) 285.00 (9,10) 273.40 (10,11) 298.40 (11,12) 297.80 (12,13) 256.80 (13,14) 320.80 (14,15) 180.40 (15,16) 293.80 (16,17) 363.60 (17,18) 180.00 (18,19) 315.40 (19,20) 278.00 (20,21) 278.40 (21,22) 320.20 (22,23) 349.80 (23,24) 253.20 (24,25) 305.80 (25,26) 272.20 (26,27) 285.20 (27,28) 287.80 (28,29) 290.40 (29,30) 258.80 (30,31) 291.60 (31,32) 224.20 (32,33)
0.00
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
Table SMJ320C31 Lead Information Rev. (0,8 (Continued)
SIDE BOND LOCATIONS BOND IDENTITY DVSS CVSS DVDD IVSS VDDL VDDL DVSS VSSL VSSL DVDD DVDD TEST LOCATIONS 101, 102, 106, 107, 117, 118, 120, 121, X-COORDINATE CENTER BOND 508.60 861.20 1142.00 1414.00 1682.80 1926.00 2301.60 2514.00 2828.00 3035.60 3436.20 3650.80 3919.60 4213.20 4556.60 4736.20 5051.60 5333.20 5618.40 5958.40 6138.80 6428.40 6714.80 7012.60 7279.60 7560.40 7842.80 8127.60 8403.60 8689.20 8979.60 9254.00 9631.20 Y-COORDINATE CENTER BOND PITCH LEAD REFERENCE WHICH BOND PADS
-9480.40
352.60 (34, 280.80 (35, 272.00 (36, 268.80 (37, 243.20 (38, 375.60 (39, 212.40 (40, 314.00 (41, 207.60 (42, 400.60 (43, 214.60 (44, 268.80 (45, 293.60 (46, 343.40 (47, 179.60 (48, 315.40 (49, 281.60 (50, 285.20 (51, 340.00 (52, 180.40 (53, 289.60 (54, 286.40 (55, 297.80 (56, 267.00 (57, 280.80 (58, 282.40 (59, 284.80 (60, 276.00 (61, 285.60 (62, 290.40 (63, 274.40 (64, 377.20 (65,
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
Table SMJ320C31 Lead Information Rev. (0,8 (Continued)
SIDE BOND LOCATIONS BOND IDENTITY DVSS CVSS IVSS CLKIN HOLDA HOLD CVDD STRB RESET CVDD IACK INT0 DVSS VSSL INT1 VDDL VDDL INT2 INT3 CVSS FSR0 CLKR0 CLKX0 IVSS FSX0 PVDD TEST LOCATIONS 123, 125, 126, 128, 129, 131, 132, 138, 139, 146, 147, 152, 153, 155, 156, 159, 160, 162, 163, 168, 169, 174, 175, 178, 179, 182, X-COORDINATE CENTER BOND Y-COORDINATE CENTER BOND -9032.60 -8822.20 -8542.20 -8240.40 -8054.20 -7742.80 -7460.00 -7167.00 -6736.00 -6459.20 -6191.20 -5896.00 -5617.60 -5351.00 -5060.00 -4784.80 -4504.00 -4279.20 -3998.80 -3672.00 -3330.60 -3150.20 -2826.40 -2546.60 -2280.20 -1970.20 -1699.40 -1423.80 -1143.20 -862.80 -601.40 -288.60 5.60 PITCH LEAD REFERENCE WHICH BOND PADS
10074.00
210.40 (67, 280.00 (68, 301.80 (69, 186.20 (70, 311.40 (71, 282.80 (72,73) 293.00 (73, 431.00 (74, 276.80 (75, 268.00 (76, 295.20 (77, 278.40 (78, 266.60 (79, 291.00 (80, 275.20 (81, 280.80 (82, 224.80 (83, 280.40 (84, 326.80 (85, 341.40 (86, 180.40 (87, 323.80 (88, 279.80 (89, 266.40 (90, 310.00 (91, 270.80 (92, 275.60 (93, 280.60 (94, 280.40 (95, 261.40 (96, 312.80 (97, 294.20 (98,
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
Table SMJ320C31 Lead Information Rev. (0,8 (Continued)
SIDE BOND LOCATIONS BOND IDENTITY VSUBS DVSS TCLK0 PVDD TCLK1 EMU3 EMU0 EMU1 EMU2 MCBL CVSS VDDL VDDL VSSL DVSS AVDD AVDD CVSS TEST LOCATIONS 184, 185, 187, 188, 191, 192, 193, 195, 196, 204, 205, 209, 210, 212, 213, 217, 218, 220, 221, 224, 225, 235, 236, 237, 239, 240, 242, 243, X-COORDINATE CENTER BOND 9649.40 9335.20 9055.60 8776.80 8506.80 8223.20 7851.00 7580.60 7277.40 6976.60 6736.60 6394.00 6191.00 5895.40 5564.60 5384.20 4986.80 4704.80 4366.80 4186.40 3863.80 3586.40 3290.80 3014.60 2724.40 2457.40 2172.60 1826.00 1550.00 1271.80 989.00 715.20 441.00 Y-COORDINATE CENTER BOND PITCH LEAD REFERENCE WHICH BOND PADS 314.20 (100, 101) 279.60 (101, 102) 278.80 (102, 103) 270.00 (103, 104) 283.60 (104, 105) 372.20 (105, 106) 270.40 (106, 107) 303.20 (107, 108) 300.80 (108, 109) 240.00 (109, 110) 342.60 (110, 111) 203.00 (111, 112) 295.60 (112, 113) 330.80 (113, 114) 180.40 (114, 115) 397.40 (115, 116) 282.00 (116, 117) 338.00 (117, 118) 180.40 (118, 119) 322.60 (119, 120) 277.40 (120, 121) 295.60 (121, 122) 276.20 (122, 123) 290.20 (123, 124) 267.00 (124, 125) 284.80 (125, 126) 346.60 (126, 127) 276.00 (127, 128) 278.20 (128, 129) 282.80 (129, 130) 273.80 (130, 131) 274.20 (131, 132)
484.80
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
MECHANICAL DATA
WITH PROTECTIVE FILM) SMJ320C31 244-PIN FRAME (PG2) SOCKET, OLB/ILB 0,30-mm PITCH
0,31 9,62 0,29 9,58
Leads 0,31 9,62 0,29 9,58
Face
2,25 Places)
0,31 9,62 0,29 9,58 14,00 Places)
4081548/A 11/95
NOTES:
linear dimensions millimeters. This drawing subject change without notice. lead width 0,120 0,03 lead width 0,0832 0,015 tape width encapsulated with polyimide overcoat.
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0,31 9,62 0,29 9,58
SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
MECHANICAL DATA
WITHOUT PROTECTIVE FILM) SMJ320C31 244-PIN FRAME (PG2) SOCKET, OLB/ILB 0,30-mm PITCH
0,31 9,62 0,29 9,58
Leads 0,31 9,62 0,29 9,58
Face
2,25 Places)
0,31 9,62 0,29 9,58 14,00 Places) 4081549/A 11/95
NOTES:
linear dimensions millimeters. This drawing subject change without notice. lead width 0,120 0,03 lead width 0,0832 0,015 tape width bare die.
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0,31 9,62 0,29 9,58
SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
MECHANICAL DATA
(S-CQFP-F132) CERAMIC QUAD FLATPACK WITH TIE-BAR
0.960 (24,38) 0.945 (24,00) 0.800 (20,32) 0.225 (5,72) Width 0.175 (4,45)
1.210 (30,73) 2.015 (51,18) 1.990 (50,55)
2.025 (51,44)
0.061 (1,55) 0.059 (1,50)
0.013 (0,33) 0.006 (0,15)
Braze 0.014 (0,36) 0.002 (0,05)
0.040 (1,02) 0.030 (0,76) 0.025 (0,64) DETAIL 0.020 (0,51) DETAIL
0.010 (0,25) 0.005 (0,12)
0.116 (2,95) DETAIL 4040231-8 04/96
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. Ceramic quad flatpack with flat leads brazed non-conductive carrier. This package hermetically sealed with metal lid. terminals will gold plated. Thermal Resistance Characteristics PARAMETER °C/W 44.3
above data applies SMJ320C31 132-pin QFP.
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
MECHANICAL DATA
(S-CQFP-F196)
1.365 (34,67) 1.325 (33,66) 1.200 (30,48) 0.600 (15,20) 0.225 (5,72) Width 0.175 (4,45)
CERAMIC QUAD FLATPACK WITH
Thermal Resistance Characteristics PARAMETER °C/W 28.9
2.505 (63,63) 2.485 (63,12)
1.710 (43,43) 1.690 (42,93)
1.150 (29,21) Places 0.061 (1,55) Places 0.059 (1,50)
0.105 (2,67) 0.018 (0,46)
0.010 (0,25) 0.006 (0,15) Braze 0.014 (0,36) 0.002 (0,05)
0.040 (1,02) 0.030 (0,76) 0.025 (0,64) DETAIL 0.020 (0,51) DETAIL
0.008 (0,20) 0.004 (0,10)
0.130 (3,30) DETAIL 4040231-6 04/96
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. Ceramic quad flatpack with flat leads brazed nonconductive tie-bar carrier This package hermetically sealed with metal lid. terminals will gold plated. Falls within JEDEC -113
above data applies SMJ320C30 196-pin QFP.
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
MECHANICAL DATA
GA-GB (S-CPGA-P15
CERAMIC GRID ARRAY PACKAGE
1.400 (35,56)
0.050 (1,27) Places 0.022 (0,55) 0.016 (0,41) 0.140 (3,56) 0.120 (3,05) 0.100 (2,54)
1.540 (39,12) 1.480 (37,59) 0.110 (2,79) 0.095 (2,41) 0.040 (1,02) 0.025 (0,63)
1.590 (40,38) 1.535 (38,99) 0.205 (5,21) 0.205 (5,21) 0.060 (1,52) 0.060 (1,52)
Notes Large Outline Small Outline Cavity Cavity Down Cavity Cavity Down
MAXIMUM PINS WITHIN MATRIX
4040114-8 04/96 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Index mark appear bottom depending package vendor. Pins located within 0.010 (0,25) diameter true position relative each other maximum material condition within 0.030 (0,76) diameter relative edges ceramic. This package hermetically sealed with metal lids with ceramic lids using glass frit. pins gold plated solder dipped. Falls within MIL-STD-1835 CMGA7-PN CMGA19-PN JEDEC MO-067AG MO-066AG, respectively Thermal Resistance Characteristics PARAMETER °C/W 26.6
above data applies SMJ320C30 181-pin PGA.
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SMJ320C30, SMJ320C31 DIGITAL SIGNAL PROCESSORS
MECHANICAL DATA
(S-CPGA-P141)
1.080 (27,43) 1.040 (26,42)
CERAMIC GRID ARRAY PACKAGE
0.900 (22,86) 0.100 (2,54) 0.050 (1,27)
0.026 (0,66) 0.006 (0,15) 0.145 (3,68) 0.105 (2,67)
0.034 (0,86) 0.022 (0,56) 0.016 (0,41) 0.048 (1,22) Places 4040133/D 04/96 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MO-128 Thermal Resistance Characteristics PARAMETER °C/W 39.0 0.140 (3,56) 0.120 (3,05)
above data applies SMJ320C31 141-pin PGA.
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IMPORTANT NOTICE Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used.
Copyright 1996, Texas Instruments Incorporated

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