STVD7: WINDOWS DEBUGGER MCUs Dedicated Board External clock
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INTRODUCTION CORE ADRESSING MODES PERIPHERALS SOFTWARE TOOLS HARDWARE TOOLS STVD7
STVD7: WINDOWS DEBUGGER MCUs
Dedicated Board
External clock
Triggers
Emulator
Development
Simulator
Flat Cable
Visual Debug Overview
Hardware Development System Graphical Interface (32-bit) User Friendly Source Level Debugging Compatible with:
Macro-Assembler Tool Chain Hiware Compiler Tool Chain COSMIC Compiler Tool Chain
Complete Family Support Real Time Trace Breakpoints, Logic Analyser, Hardware Events.
Visual Debug Project settings
Visual Debug Micro Configuration
Visual Debug Debugging Features
Running application
Chip Reset Restart Application Continue Stop Step into Step over Step Step over Step Cursor
Visual Debug Debugging Features
Common Debug Features
Disassembly Memory Dump Instruction Breakpoints Data Breakpoints Watch Call Stack Local Variables Registers Window Symbol browser Peripheral registers window
Visual Debug Debugging Features
Peripheral registers window:
visualise/ change peripheral's values Accessing some status register allowed
Visual Debug Emulator-Specific functions
Hardware Test:
check that emulator still working online
Visual Debug Emulator-Specific functions
Logical Analyser
Advanced breaks:
conditional breakpoints execution application.
Visual Debug Emulator-Specific functions
Trace filtering:
conditionally filter cycle events trace buffer that wish view
TRIGGER OUTPUT
Hardware Events mode
Trigger output signal Trace filtering
TRIGIN mode
Break external input signal (rising edge)
Trace overflow break mode
Break when trace full (256 bytes)
Visual Debug Debugging Features
Console Information window:
This window displays output Permits entry commands Permits load binary file without debug information
STVD7
SIMULATOR OVERVIEW
Scope
Instruction level simulation Peripheral simulation: Port, Watchdog, Timer, ADC, SPI, I2C, E2PROM level simulation (Grapher.exe) interrupt processing simulation
Time management
Display time break time
Breakpoints management
Read write access Stack Overflow/Underflow Invalid memory access detection
trace logic analyser features
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