John Pritiskutch Brett Hanson ABSTRACT This paper focuses structu

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UNDERSTANDING LDMOS DEVICE FUNDAMENTALS
John Pritiskutch Brett Hanson
ABSTRACT This paper focuses structural aspects basic types power MOSFETS: DMOS LDMOS. comparison DMOS LDMOS structures reveals basic fundamentals MOSFET device technology challenges that exist improve their performance reliability. date, MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) research predominately focused VLSI technology, which been driven computer market pressures. VLSI devices employ physical structures similar power MOSFETs, VLSI devices utilize much smaller physical dimensions. salient differences between MOSFETs VLSI devices larger channel lengths, greater junction depths thicker gate oxides, employed former, required obtain high power needed most applications. Todays power applications need higher gain more power without complicated peripheral circuitry. market being driven need higher reliability, gain, linearity output power requirements that will constrained application's power supply limitations. Most high power applications using supply voltages ranging from volts. MOSFETs. There major structural categories MOSFETs today. These structures, DMOS (double-diffused Metal-Oxide-Semiconductor) LDMOS (laterally diffused Metal-Oxide-Semiconductor), have unique behaviors: semiconductor process geometry dependent. These acronyms confusing, especially since acronym LDMOS concatenation acronyms that have been used designate various aspects lateral device often stands lateral current double-diffused (DMOS). These devices created common types, PMOS (p-type MOSFET) NMOS (n-type MOSFET), this paper will focus NMOS only. Figures depict physical structures DMOS LDMOS, respectively. From these figures, apparent LDMOS predominately lateral, surface-effect device, while DMOS geometry incorporates large vertical lateral structures forcing time current density spatial dependent vector contain significant vertical lateral component. Both these MOSFETs composed three terminal devices (assuming substrate shorted source), commonly identified source, gate drain, where voltage gate controls current flowing from drain source. most common circuit configuration these devices common source (CS) configuration, which comparable some respects) common emitter configuration bipolar transistor. Considering this, frequency-dependent source ground connection will introduce negative feedback. Other configurations used under configuration drain connected high voltage while source grounded. gate used induce field-enhanced depletion region between source drain, thereby creating "channel". acronym NMOS derived from fact that p-type channel been inverted,
July 2000
AN1226 APPLICATION NOTE creating effective n-type material depletion holes p-type channel. high concentration electrons left with energy near conduction band barrier lowering caused gate field, electrons then accelerate field produced drain source biasing. details above mentioned gate-induced channel critical operation. LDMOS channel predominately defined physical size gate structure (ignoring secondary effects diffusion vagaries) that overlies graded p-type threshold adjust, implantation diffusion area. source drain regions laterally opposing sides gate area, diffusion process produce undercut region below gate single-step lateral diffusion process that defines source drain regions. source drain regions under bias create depletion regions that connected gate induced depletion region p-body, this connection defines "effective channel length" which measure distance between source drain depletion edges. NMOS, depletion region region where high electric field lowers energy barrier electron conduction band. Once barrier lowered sufficiently, current easily flows between source drain. LDMOS channel current controlled vertical electric field induced gate lateral field that exists between source drain. Figure Basic DMOS Structure
Gate terminal Polysilicon Gate Oxide Source terminal source
Body
Drain-Source depletion width
substrate Drain terminal
depletion region between source drain dependent junction doping profiles. general, depletion region will reach farther into lower doped region than higher doped region. depletion region will extend into channel region reducing actual channel length formed diffusion effective channel length. This creates possibility undesired behavior form carrier injection high electric fields, drain induced barrier lowering (DIBL) short channel effects (SCE). carefully designed, lightly doped drain, threshold adjust p-body (that graded appropriately) will mitigate undesired behavior. contrast LDMOS, DMOS structure consists n-type substrate which grown nepitaxial layer that forms large drain region. gate region formed surface that overlies graded p-type body implantation diffusion area. source regions implanted diffused either side gate form separate transistors with common drain region. depletion regions
AN1226 APPLICATION NOTE will form around source p-body these depletion regions connected field induced depletion region formed gate. depletion region connecting drain source defines channel dimensions determined source body doping. Another fundamental difference between DMOS LDMOS characteristic source connection outside world. source DMOS located surface die, while drain formed substrate region therefore wire bonds must used connect source external circuitry. These wire bonds form dependant frequency element reducing gain high frequencies negative feedback. addition, common surface connection dictates that insulating material (BeO) used isolate drain. This insulating material thermal impedance that must considered power dissipation. source LDMOS also surface, however common connection formed diffusing highly doped p-type region, which acts like ohmic connection from source surface substrate, eliminating need parasitic wire bonds. This method also eliminates ceramic interface (that exists DMOS) improves junction case thermal resistance, therefore, relieves some associated power dissipation issues. summary, LDMOS channel determined gate length, source diffusion drain diffusion. Figure Basic LDMOS Structure
Gateterminal Polysilicon
Gate Oxide Source-Sinkershort source Drain Drainterminal Drain
Thresholdadjust
Drain-Sourcedepletion width
Sinker
substrate Sourceterminal
DMOS channel determined lateral source diffusion edge p-body diffusion edge. differences electrical field distributions influence each MOSFET's behaviors fact that DMOS significant lateral vertical components, whereas LDMOS predominately lateral field device. differences source connections significant terms high frequency behavior, that DMOS will have greater negative feedback. These inherent differences establish appropriate domain applications each these MOSFET structures. salient parameters that distinguish differences circuit-level performance used SPICE) DMOS LDMOS VDS(on), CISS, CRSS (see Figures VDS(on) inverse RDS(on). contrast DMOS, LDMOS contains additional p-type sinker element which graded doping concentration subsequent diffusion. This portion DS(on) optimization this element critical reducing RDS(on). shallow junctions LDMOS subsequent reduction gate overlap, reduce input capacitance (CISS). most significant differences between LDMOS DMOS terms circuit performance pertains feedback capacitance (CRSS). CRSS
AN1226 APPLICATION NOTE LDMOS structure primarily composed gate drain overlap which minimal compared DMOS. DMOS CRSS larger because entire Drain contributes CRSS. other significant parameters that important circuit behavior critically dependent DMOS LDMOS specific structures. example, transconductance directly proportional channel width/length ratio, voltage threshold always determined doping channel, gate oxide thickness., etc. CONCLUSION This brief description fundamental structure LDMOS DMOS invites comparison critical parameters which determine unique behavior these different MOSFET devices. From this comparison speculate qualitative aspect LDMOS DMOS. example, contemplating which structure most susceptible drain source punch-through, would consider depletion regions. LDMOS channel length doping must prevent drain source depletion edges from meeting. geometry doping profiles keys understanding many other issues well. following paper this series (AN1228 Related LDMOS Device Parameters Performance) investigates root causes various failure mechanisms that endemic DMOS LDMOS. This investigation will require understanding microscopic aspects semiconductor physics processing will therefore enlighten reader some esoteric phenomena that exist with MOSFETs.
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