REAL TIME EMULATION DEVELOPMENT TOOLS FAMILY HARDWARE FEATURES Su

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REAL TIME EMULATION DEVELOPMENT TOOLS FAMILY HARDWARE FEATURES Su

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ST626x-EMU2
REAL TIME EMULATION DEVELOPMENT TOOLS FAMILY
HARDWARE FEATURES Supports ST62 ST63 family Real time emulation KBytes emulation memory Breakpoint single address address area Break events defined Program Space, Data space mixed with external signals full programmable output synchronisation Read/Write registers (without wait state) Selective trace Range Start/Stop Break Stack Overflow real trace memory Tracing bits including external signals
SOFTWARE FEATURES Symbolic debugger source level On-line assembler/disassembler files capable storing displayed screen Command files able execute debugger commands
February 1998
This advance information from SGS-THOMSON. Details subject change without notice.
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Table Contents
ST626x-EMU2
DELIVERY CHECK HDS2 MAINFRAME EMULATOR MAIN BOARD HDS2 MAIN BOARD 2.2.1 External output: OUT1 OUT2 2.2.2 Data acquisition signals 2.2.3 LEDs RUN, STOP, WAIT INSTALLING PROBE:
INSTALLING EMU2 DEVELOPMENT TOOL INSTALLING ST626X-DBE DEDICATION BOARD HDS2 COMPONENTS LAYOUT MAIN BOARD (MB097) COMPONENTS LAYOUT MAIN BOARD (MB174) MAINFRAME EMULATOR (FIRST GENERATION) MOTHER BOARD (CLZ80) REAL TIME BOARD (GPFM/3) INTERFACE BOARD ST626X-EMU DEVELOPMENT TOOL INSTALLING ST626X-DBE DEDICATION BOARD INSTALLING PROBE DEDICATION BOARD (DBE) VOLTAGE FUNCTIONING RANGE JUMPER DESCRIPTION DEDICATION BOARD 4.2.1 Choosing emulated device: 4.2.1.1 Emulating ST621X/2X family: 4.2.1.2 Emulating ST626X ST629X family: 4.2.2 Mask option Port ST626X ST629X 4.2.3 Hardware WATCHDOG selection: 4.2.4 MIXT option: Wake STOP mode 4.2.5 Clock Source Selection: 4.2.6 Reset delay duration: EMULATED PERIPHERALS 4.3.1 Oscillator 4.3.2 Mapping 4.3.3 Timer Timer Watchdog 4.3.4 Analog Digital Converter 4.3.5 Serial Peripheral Interface (SPI) 4.3.6 Port 4.3.7 Port 4.3.8 Port 4.3.9 Voltage Inhibit, (LVI) 4.3.10 NMI/CKOUT
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Table Contents
TROUBLESHOOTING POWER DURING EMULATION DISCREPANCIES BETWEEN EMULATOR EPROM DEVICE AVOID MOST FREQUENT PROBLEMS WHEN PROGRAMMING MICROS! 5.4.1 Execution Interrupt 5.4.2 Execution WAIT STOP instructions ANNEX COMPONENTS LAYOUT
ST626X-DBE SCHEMATICS PROBE
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ST626x-EMU2 DELIVERY CHECK
DELIVERY CHECK
This development tool able emulate components belonging ST620X/1X/2X, ST625X/ ST629X family. dedication board common emulating three families.Tthe choice emulated Device made properly setting configuration dedication board, connecting appropriate PROBE appropriate connectors. development tool delivered with: mainframe emulator HDS2 emulator Volts power supply added with HDS2 emulator flat cables connecting probes dedication board emulate ST626X/9X families: emulation probe ST625X/6X ST629X (Ref. DB051 with DIL28 footprint). emulation probe ST625X/6X ST629X (Ref. DB051 with DIL20 footprint). emulate ST620X/1X families: emulation probe ST620X/1X/2X (Ref. DB210 with DIL28 footprint). emulation probe ST620/1X/2X (Ref. DB210 with DIL20 footprint). emulation probe ST620X/1X/2X (Ref. DB210 with DIL16 footprint). Finally, footprint footprint adapter also included package: DB090: adapter DB093/20: adapter DB093/1: adapter Instructions Warning This development tool conforms with EN55022 emissions standard ITE, with generic 50082-1 immunity standards. Then, complies with 89/336/EEC directive. product Class apparatus. residential environment this device cause radioelectrical disturbance which require that user adopts appropriate precautions.
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ST626x-EMU2 HDS2 MAINFRAME EMULATO
HDS2 MAINFRAME EMULATOThe HDS2 mainframe been designed replace one. main modifications are: communication transfer rate: much faster thanks parallel port. dimension weight: boards, basic part system, have been redesigned board. cost overall system been well reduced second version HDS2, (metal with MB174 main Board) modified conformity, features have been introduced: Read/Write registers during execution program without wait state. Selective record logical analyseur Range Start/Stop mode. Output OUT1 OUT2 synchronisation external equipment, programmable same Selective trace, Range Start/ Stop mode. Stack overflow: break automatically generated default) case stack overflow. Break execution: this version, program stops before execution fetch. These mainframes consist basic part, common devices, ST62 ST63 family dedicated board depending specific device emulate. This emulator fully compatible with existing dedicated boards, excepting ST638X ST631XX which have been designed boards. Only dedicated board (DBE) changed emulate device within ST62/ ST63 families. parallel port allows very fast communication transfer rate. symbolic debugger, software part real time emulation tool, common ST62 ST63 devices. debugger uses windowed menu driven interface, enables user configuration emulator.
Figure Hardware Development System Emulator
HARDWARE DEVELOPMENT SYSTEM EMULATOR (HDS2)
Parallel Port connection
Dedication Board
OUT-1 Power Triggers OUT-2 Stop Wait
HDS2 EMULATOR (.EMU2)
probe
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ST626x-EMU2 HDS2 MAINFRAME EMULATO
MAIN BOARD Main board controls emulator thanks central processing unit which performs commands coming from host computer through parallel line. board contains, emulation resources, core ST6, Program emulation, break point, trace memory, automaton necessary logic real time emulation. connectors, used exchange signals with interface board. amount program memory main board factory 32k, fact size memory depends dedication board, which contains Program Pagination Register (PRPR) exists PRPR memory size lower than 4k). configuration jumpers required. HDS2 MAIN BOARD rear panel there power plug connect power: Volts min. (The delivered power volts volts input output). power switch. parallel connector PC(TM) compatible. front panel: "POWER signal. signals which used synchronizing external equipment. leds indicating when core "STOP", "WAIT" "RUN" mode. connector data acquisition signals. explanation these signals done debugger manual.
2.2.1 External output: OUT1 OUT2 debugging hardware very useful have synchronization signals. goal outputs offer this feature user. They programmed differently whether debugger used debugger ST6NDB Source Level Debugger WGDB6, explained following paragraph. They full programmable with WGDB6. Ouptput OUT1 OUT2 under ST6NDB When using Version debugger ST6NDB: This feature programmable thanks Hardware Breakpoint Menu. breakpoint MENU allows define breaking events. These events will generate actual breakpoint only break enable When break off, these events existing development tool. HDS2 emulator version 4.3, signals OUT1 OUT2 connected these internal breaking events. Therefore these signals used synchronize external device while running (breakpoint off). Ouptput OUT1 OUT2 under WGDB6 When using WGDB6 Version debugger source level under Windows: This feature full programmable thanks Hardware Events/Trigger Menu. Output OUT1 OUT2 programmed ways: Events synchronisation: allows user preset pulses synchronisation external equipment. events defined addresses range addresses. Events Timing Measure: allows user measure time elapsed during subroutine example. this case, output OUT2 user defined address, RESET other one, OUT1 clock cycle gated OUT2. These functioning modes clearly displayed screen.
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ST626x-EMU2 HDS2 MAINFRAME EMULATO
2.2.2 Data acquisition signals same recorded Buses, Flags, Bank registers trace memory, HDS2 offers user possibility record external signals. These signals must connected Analyser probe connector front panel HDS2, shown below. These inputs CMOS compatible Volts. 2.2.3 LEDs RUN, STOP, WAIT Three leds have been added indicate user state core development tool during emulation. When user's program running real time), When core WAIT mode, WAIT
Caution:
When core STOP mode, both leds STOP WAIT
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ST626x-EMU2 HDS2 MAINFRAME EMULATO
INSTALLING PROBE: Before installing probe, user must choose device emulated: ST620x/1x/2x ST625x/6x ST629x Then, Connect flat cables appropriate connectors, board inside main frame, unscrew screws each side dedication board, press outward release buttons extract board. connectors ST625X/6X ST629X family (printed board). connectors ST620X/1X/2X family (printed board). prevent mistakes, bump connectors impose them right. Furthermore, verify that each connector, which clearly printed both boards, same side line flat cables. Then connect chosen probe opposite side flat cables, with respect each connector. Schematics these probes shown annex. ST620X/1X/2X probes emulate oscillator function jumper probe crystal. OSCIN, clock must given OSCIN input. this clock issued from probe, dedication board must external clock.
INSTALLING EMU2 DEVELOPMENT TOOL When receiving whole development tool, dedication board delivered inside mainframe. user just connect power supply mains(100 volts). connect output (5Volts) power supply connector rear panel connect parallel cable between parallel connector host computer. INSTALLING ST626X-DBE DEDICATION BOARD HDS2 there already dedication board development tool, user simply unscrew screws each side dedication board, press outward release buttons extract board. Then insert dedication board guide rods push hardly backplane, and: screw screws each side dedication board.
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ST626x-EMU2 HDS2 MAINFRAME EMULATO
COMPONENTS LAYOUT MAIN BOARD (MB097)
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ST626x-EMU2 HDS2 MAINFRAME EMULATO
COMPONENTS LAYOUT MAIN BOARD (MB174)
VR02091U
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ST626x-EMU2 MAINFRAME EMULATOR (FIRST GENERATION)
MAINFRAME EMULATOR (FIRST GENERATION)
mainframe emulator contains positions boards: Mother board (CLZ80) must inserted first (bottom) position Real time board (GPFM/3) must second position interface (DB014) must inserted third position dedication board ST620X/1X/2X/5X/6X/9X-DBE (MB064) inserted position rear panel there main-power selector select volts volts. power plug power switch front panel: RS232 connector link emulator with EXT-SIG connector that allows choose between groups signals memorize trace memory. These signals independent from probe data acquisition signals. explanation these signals done debugger manual Mother board reset push button push-button MOTHER BOARD (CLZ80) mother board (CLZ80) controls mainframe emulator linked through RS232 line. this board only connectors used: connected front panel RS232 connector connected front panel mother board reset push-button REAL TIME BOARD (GPFM/3) Real time board (GPFM/3) contains emulation resources: Program emulation, break point, trace memory. connectors, used exchange signals with interface board. When emulating ST62XX ST63XX, interface board N-WELL interface board. connectors used. emulating components other families, interface board P-WELL interface board: this case only connector used, jumpers must plugged. JUMPERS SETTING ST62XX ST63XX emulation: jumpers must removed. jumper only must link CONNECTORS: Used link this board with N-WELL interface board. Used connect data acquisition probe.
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ST626x-EMU2 MAINFRAME EMULATOR (FIRST GENERATION)
INTERFACE BOARD interface board emulates CPU-core. JUMPERS SETTINGS: used emulation mode allows definition type EPROM (27256/27128) used stand-alone (without CLZ80 GPFM/3 boards) mode size emulation program position reference names depend version board. they identified board.
Size normal setting supported Comment
ST626X-EMU DEVELOPMENT TOOL When receiving whole development tool, dedication board delivered inside mainframe, plugged position backplane. First all, mandatory verify mainframe: remove screws rear panel main frame lift side rear panel pull from rear panel, dissociates from front panel remove lid, attention wire ground connection Verify that boards correctly inserted backplane mainframe right order: CLZ80 board must inserted first (bottom) position GPFM/3 board must second position Interface (DB014) must inserted third position positions intended receive couple dedication boards order emulate family component: this case, only ST626X-DBE board must positions.
purpose this jumper allow emulator check amount emulation program that used. TEST/NO TEST: must TEST position CONNECTORS: link this board GPFM/3 board. receives signals from J1-EXT SIG. connector situated front panel emulator. connected ST6-RESET, ST6-INT pushbuttons, STOP-LED WAIT-LED situated front panel emulator.
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ST626x-EMU2 MAINFRAME EMULATOR (FIRST GENERATION)
INSTALLING ST626X-DBE DEDICATION BOARD When receiving only dedication board, user must install dedication board described below. Open main frame removing lid: remove screws rear panel main frame lift side rear panel pull from rear panel, dissociates from front panel remove lid, attention wire ground connection Then remove dedication board dedication board which plugged position backplane, which emulating other family SGS-THOMSON devices. After that, plug dedication board positions backplane.
INSTALLING PROBE Before installing probe, user must choose device emulated, please refer 4.2.1 chapter. Then, Connect flat cables appropriate connectors. connectors ST625X/6X ST629X family (printed board). connectors ST620X/1X/2X family (printed board). prevent mistakes, bump connectors impose them right. Furthermore, verify that each connector, which clearly printed both boards, same side line flat cables. Then, remove screws which holding small metal cover bottom development tool. Stick flat cables through this opening. Then connect chosen probe opposite side flat cables, with respect each connector.
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ST626x-EMU2 DEDICATION BOARD (DBE)
DEDICATION BOARD (DBE)
This board contains specific functions ST620X/1X/2X, ST625X/6X ST629X emulation Oscillator EEPROM (Byte mode parallel mode) Timer Timer Watchdog Analog Digital Converter Serial Peripheral Interface Analog Digital Converter Port Bits Port Bits Port Bits (one part ST625X/6X, ST629X, other ST620X/1X/2X) Voltage Inhibit Pagination Registers white indicates position jumpers components board. Note pin: When input power connected, this input used reference voltage emulator.(please refer chapter) power given taken this emulator. Notes write-only registers: Several Data Space registers emulated device write-only, however, offer more flexibility user, they readable when commands such "watching register" used. VOLTAGE FUNCTIONING RANGE This board been designed emulate device range Volts. When input power connected, this input used reference voltage emulator. This reference voltage buffered thanks operational amplifier emitter follower powering output buffers, giving high reference voltage ADC. Then outputs peripherals fully compatible CMOS level with application which powered range from Volts. When this input connected, buffers powered with volts. power given taken this emulator.
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ST626x-EMU2 DEDICATION BOARD (DBE)
JUMPER DESCRIPTION DEDICATION BOARD Jumpers board used select amount MEMORY, emulated PERIPHERALS, metal MASK OPTION device. This chapter explains select these features. Note ST620X/1X/2X: difference between ST620X/1X ST622X only about size presence. Development Tool offers maximum ROM, choice will always device ST622X family. 4.2.1 Choosing emulated device: This board been designed emulate families components: ST621X/2X, ST626X ST629X. choices different whether used, respectively CKOUT, with amount DATA space memory. select this choice, only jumper must front name name device, clearly printed board. When peripheral used, example ST6292, registers this peripheral zero value, they cannot written.
Emulated Device Jumper NMI/CKOUT
4.2.1.1 Emulating ST621X/2X family: emulate device ST621X/2X family, ST621X/2X probe must connected through flat cables. There probe emulating pins devices (DB031), probe emulating pins devices(DB030). dedication board must connected probe. dedication board must connected probe. number pins clearly printed both boards, line flat cables must same side connectors. 4.2.1.2 Emulating ST626X ST629X family: emulate device ST629X ST626X family, corresponding probe must connected from dedication board respectively probe, through flat cables. pins probe emulate pins devices, pins probe emulate pins devices. following table shows difference between emulating ST626X emulating ST629X.
ADC/SIO Data Space Memory Bank (0->3F) EEPROM BANK (0->3F) EEPROM (0->2F) Bank (0->3F) EEPROM BANK (0->3F) Bank (0->3F) EEPROM BANK (0->3F) Bank (0->3F) EEPROM BANK
ST6293/94
ST6293/94
CKOUT
ST6291/92
ST6291/92
CKOUT
ST6260/65
ST6260/65
ST6263*
ST620/65
ST6253*
ST6260/65
careful emulate ST6253/63 also EEPROM ST6253 those peripherals don't exist these devices
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ST626x-EMU2 DEDICATION BOARD (DBE)
4.2.2 Mask option Port ST626X ST629X There option bits state port PB0, PB1, PB2, during RESET. This state input with pull-up high impedance. option byte both PB1, other, option Byte PB3. OPT4: Option Byte When jumper between option Pull-up during reset PB1. When jumper between option high impedance during reset PB1. OPT5: Option Byte When jumper between option Pull-up during reset PB3. When jumper between option high impedance during reset PB3. factory setting these jumpers Pull-up during reset. When emulating ST621X ST622X these jumpers ignored.
4.2.3 Hardware WATCHDOG selection: jumper permits emulate "hardware WATCHDOG" metal mask option device. watchdog activated ways device: software Watchdog activated setting, software, watchdog register. other "watchdog HARD", means watchdog automatically armed after RESET (generated watchdog not). Jumper setting: Watchdog automatically activated HARDWARE 2-3: Watchdog only activated SOFTWARE jumper setting clearly printed board shown following figure Note: When activating watchdog, STOP instructions automatically executed WAIT instructions processor, following chapter special STOP mode. 4.2.4 MIXT option: Wake STOP mode special option effectively execute STOP mode when encountered, wake from this STOP mode using pin. This feature only available when ST6223/24, ST626X when MIXT option selected. When this feature selected, even watchdog been activated (Hard soft), STOP instructions effectively executed, when HIGH. goes low, before executing STOP, STOP instructions converted WAIT instructions. Jumper setting ways: Select ST6223/24 clearly printed board jumper between select ST6260/65 clearly printed board. 1-2:
VR02091P
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ST626x-EMU2 DEDICATION BOARD (DBE)
4.2.5 Clock Source Selection: system CLOCK chosen between internal board oscillator OSCIN XTAL) input probe. This jumper setting clearly printed board, with INTERNAL clock EXTERNAL clock. Jumper setting: this case external clock selected: means Clock issued from probe selected. internal clock selected. this case internal clock made thanks oscillator with quartz, this quartz XT1, exchanged desired user.
delay 4096, 8192 16384 jumper must front respectively clearly printed board.
VR02091Q
VR02091Q
4.2.6 Reset delay duration: long reset kept level, processor remains reset state. After reset been released, counter provides delay between detection reset high level release reset: jumper permits select duration this delay. standard delay 2048 oscillator cycles: jumper must front
Note CLOCK "issued from probe": user uses probe made SGS-THOMSON, this probe able send clock dedication board ways thanks jumper: clock made board oscillator probe. clock directly issued from application. this case signal OSCIN must CMOS level. When oscillator used, mandatory disable oscillator putting jumper "oscillator disable" (factory setting). WARNING probe board oscillator: Probe: "open" schematic this probe permits user reconstruct probe, same oscillator application. probe able support cristal resonator pins with without capacitor, course used also with PROBE: Installing ferrite coil compatibility conform directive, particularly emission, delivered ferrite coil must placed follow: Place each part each side flat cables Place metal clip them together
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ST626x-EMU2 DEDICATION BOARD (DBE)
EMULATED PERIPHERALS 4.3.1 Oscillator ST621X/2X standard oscillator described data sheet device. ST626X ST629X, four bits oscillator control write only register 0DCH emulated, including oscillator frequency control Bit2=1 then Fosc approximately divided 100), XTAL EXTAL respectively input output clock emulator, according selector. These XTAL EXTAL emulate actual oscillator, which connected crystal 4.3.2 Mapping Program memory size always valid Bytes (0FFFH) Data space memory size depends emulated device. mapping data space different ways: there bank memory range 03FH not. Memory Banks: case ST6291, ST6292. this case, there always EEPROM from 02FH, nothing from Memory Bank Register (0E8H), value, possible write Memory Banks exist: case ST6293, ST6294, ST626X. this case range from 03FH fully used through content Memory Bank Register located 0E8H (write only). meaning each these bits selects first EEPROM bank selects second EEPROM bank selects bank. others used existing. Care must taken that only these three must time, more details Data Sheet corresponding device. 4.3.3 Timer Timer Watchdog Clock these devices voluntarily validated only during emulation, provides evolving values them. Therefore attention that NEXT mode values counters slightly different real time session because setting emulation. using these peripherals, please, refer data sheet corresponding DEVICE. 4.3.4 Analog Digital Converter This peripheral available only when component ST620X/1X/2X, ST629X ST625X/6X family, which contains ADC, been selected with jumper. Except these devices, registers zero value able written. input connected inputs, port port properly programming registers these ports (one time). more than input selected, they will short circuited each other's. analog Digital Converter converts input value about 50µS Xtal clock. Clock conversion always present, means that data conversion always accomplished after writing start conversion even made NEXT mode emulation. allows user convert analog input step step. Note voltage reference: high voltage reference applied voltage internally buffered board. voltage reference GROUND. Then have conversion result 0FFH, voltage analog input must equal voltage pin. 4.3.5 Serial Peripheral Interface (SPI) This peripheral available only when ST6293, ST6294 ST626X been selected with other devices, registers zero value able written. Serial Peripheral Interface, when validated, always active: means clock data depend whether system step step mode not. using this peripheral, please, refer Data Sheet corresponding device. Note: this peripheral, forget register.
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ST626x-EMU2 DEDICATION BOARD (DBE)
4.3.6 Port This port always selected whatever emulated device, permitted (see 3.3.4 chapter), each input this port input (one time). functioning mode each input selected properly programming three associated registers: Data Register (DRA), Data Direction Register (DDRA), Option Register (ORA) follow.
Mode Input without pullup, interrupt disabled Input with pullup, interrupt enabled Input with pullup, interrupt disabled Analog Input
more details about this peripheral, please, refer Data Sheet corresponding Device. 4.3.7 Port This port always selected, functioning mode input selected properly programming three associated registers: Data Register (DRB), Data Direction Register (DDRB), Option Register (ORB) follow.
Mode Input without pullup, interrupt disabled Input with pullup, interrupt enabled Input with pullup, interrupt disabled Push Pull Output Open Drain NMOS output
Push Pull Output Open Drain NMOS output
Beware mixing input output modes same port, this case, instructions Data Registers: When port input mode, data read state device probe); when port output mode data read data register, when using read/modify/ write instruction, port mode changed from input mode analog input mode unintentionally!
Beware mixing input output modes same port, this case instructions Data Registers: When port input mode, data read state device probe); when port output mode data read data register, when using read/modify/ write instruction, port mode changed from input mode analog input mode unintentionally!. more details about this peripheral, please, refer Data Sheet corresponding Device.
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ST626x-EMU2 DEDICATION BOARD (DBE)
4.3.8 Port This port always selected, permitted (see 3.3.4 chapter), each input this port input (one time). functioning mode each input selected properly programming three associated registers: Data Register (DRC), Data Direction Register (DDRC), Option Register (ORC) follow. used ST626X/9X, used ST621X emulation.
Mode Input without pullup, interrupt disabled Input with pullup, interrupt enabled Input with pullup, interrupt disabled Analog Input Push Pull Output Open Drain NMOS output
from input mode analog input mode unintentionally! more details about this peripheral, please, refer Data Sheet corresponding Device. 4.3.9 Voltage Inhibit, (LVI) probe input system, furnish power application. Voltage inhibit system permanently watches probe. generates RESET when goes under Volts threshold releases when goes over Volts, same time register (0DDH) one. more details about this peripheral, please, refer Data Sheet corresponding Device. 4.3.10 NMI/CKOUT NMI/CKOUT PIN, package, package, either entry CKOUT output depending selected device (see 3.3.1 chapter). input ST626X family, CKOUT ST629X. When selected, Maskable interrupt input When CKOUT selected, output clock whose frequency clock XTAL divided CKOUT output controlled Oscillator Control Register (0DCH): set: CKOUT reset: CKOUT Fosc/2 more details about this peripheral, please, refer Data Sheet Device.
Beware mixing input output modes same port, this case, instructions Data Registers: When port input mode, data read state device probe); when port output mode data read data register, when using read/modify/ write instruction, port mode changed
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ST626x-EMU2 TROUBLESHOOTING
TROUBLESHOOTING
POWER beginning emulation session, screen must appear debugger message, with "WAIT" during software connection establishment. "TIMEOUT" message encountered, there connection problem, which come from these reasons: when using ST6HDS2 development Tool power parallel line well connected when using main frame: verify that delivered cable actually connected directly Main Frame. necessary there another cable which either "wire wire" connection adaptor. serial line connected right port computer. DURING EMULATION During emulation: Problem with program Counter case "Check Hardware Jumpering" wrongly executing code step mode: Most time, this problem occurs with HDS1 emulator with HDS2 plastic version, coming from that development tool RESET state, caused application where probe connected powered then schmitt trigger Reset active causes RESET Reset emulated device level probe connected, powered either application voltage input. properly emulating RESET please refer following chapter. During emulation: Reset emulation With ST6HDS2 metal box, possible begin emulation session even application off, required particularly MONITOR applications. With HDS1 emulator, with HDS2 plastic Version, application requires that software must executed just after power mandatory proceed follow: connect, remove probe from application. power emulator. begin emulation session: load program. then start execution program Real Time. plug probe application (which off), this time emulator reset state, because Reset pins level. Power application, then execution software will start. DISCREPANCIES BETWEEN EMULATOR EPROM DEVICE When some differences behaviour appearing between emulator device, most cases, comes from using read/modify/ write instructions registers which only writable. registers which some bits writable, some bits readable. these registers, trouble caused, because when reading, random value read CPU, after calculating mask, this random value written register, changing unintentionally! same problem occur with registers, where some bits have different function during writing during reading. Example Ports: When reading port input mode, read value level pin. When reading port output, read value value corresponding Data Register. user check each used register correctly accessed. principle registers, with which care must taken, listed below: EEPROM control registers control registers SPIs Data registers Ports Analog Digital Converter Control Register Interrupt Option Register Program Pagination Registers Data RAM/EEPROM Banking Register Data window Register
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ST626x-EMU2 TROUBLESHOOTING
AVOID MOST FREQUENT PROBLEMS WHEN PROGRAMMING MICROS! 5.4.1 Execution Interrupt interrupt executed, most cases, comes from: core normal mode: after RESET core mode, enter normal mode which execute interrupt, core must execute RETI instruction. global enable interrupt been SET, been unintentionally cleared, then register must checked. default value enable Interrupts 010H. enable interrupt desired peripheral been SET, been unintentionally cleared. Interrupt Option Register write only, been wrongly written read/modify/write instruction, only permitted. 5.4.2 Execution WAIT STOP instructions WAIT mode, WAIT STOP mode WAIT STOP front panel emulator). STOP WAIT instructions exited, comes from: core normal mode: after RESET core mode, enter normal mode which execute interrupt exit from these states, core must execute RETI instruction.
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ST626x-EMU2 ANNEX
ANNEX
COMPONENTS LAYOUT
VR02091O
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ST626x-EMU2 ANNEX
ST626X-DBE SCHEMATICS Figure Main sheet
-12V VME64 47uF 47uF 470uF-EA 47uF 47uF TP18 A[0.7] CYC01 CYC05 INTFLL PRUN0 INT0 INT2 INT4 INTRES WEA12 EXTINT CYC0I BDIO RESSO STOP INTFLL WRITE PRUN0 INT0 INT2 INT4 INTRES CLOCK CYCOI READ READ WRITE ROMADR CLOCK WEA12 INTRES PRUN EXTINT BDIO RESSO STOP WAIT STOP CLKSYST CK/12 VDDI VDDI CK/12
-12V +12V
INTFR WAIT CYC01 INT1 INT3 EXTRES
INTFR WAIT +12V CYC01 CYC03 INT1 INT3 EXTRES
CYC05 PININT0
A[0.7]
ROMADRTP6 TP10 TP11 TP12 TP13 TP14 TP15 TP16
TP17
RBB[0.3]
RBB[0.3] RBB[0.3]
RBB0 RBB2
EXWR EXWR DRBB0 DRBB2 DRBB4 CLKSYST DRBB6 DRBB8 RAMPB0 RAMPB2 RAMPB4 RAMPB6
VME64
RBB1 RBB3 RESTO BIT4
RESTO
BIT4 ROMADR ROMADR DRBB1 DRBB[0.7] DRBB3 DRBB5
DRBB7 RAMPB1 RAMPB3 RAMPB5 RAMPB7
DD[0.7]
DD[0.7]
INTRES
RAMPB[0.7]
RAMPB[0.7] DRBB[0.7]
VR02091M
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ST626x-EMU2 ANNEX
Figure Main sheet (Cont'd)
PORTA, Timer
File PATIM1.SCH PLD1A[0.4] DD[0.7] WRITE READ CLOCK NRESETI PRUN PULS PULS PLD1A[0.4] D[0.7] WRITE READ CLOCK NRESETI PRUN PULS TIM1IN TOUT TIMOUT NITTIM1 LATCH0 LATCH1 EXT[0.10] PA[0.7] PACAD[0.7] File PORTB1.SCH PLD1A[0.4] DD[0.7] WRITE READ TY9B CLOCK EOCADC NRESETI PRUN LATCH0 LATCH1 PLD1A[0.4] D[0.7] WRITE READ TY9B CLOCK EOCADC NRESETI PRUN LATCH0 LATCH1 TIM1IN TOUT TIMOUT NITTIM1 LATCH0 LATCH1 EXT[0.10] PA[0.7] PACAD[0.7] EXT5 VDDI PRUN READ WRITE EXT1
PORTB, TIM2, RTC, IOR, control
NITPB ITRTC NITTIM2 NADCRRR NITADC NSTARTADC PB[0.7] PBCAD[0.7] EXT[0.10] BIT4 INTFR INTFLL ADCCLOCK TEST NITPB ITRTC NITTIM2 NADCRRR NITADC NSTARTADC PB[0.7] PBCAD[0.7] EXT[0.10] BIT4 INTFR INTFLL ADCCLOCK TEST
PORTC, SI4,
PLD1A[0.4] PLD1A[0.4] DD[0.7] WRITE READ CLOCK LATCH0 LATCH1 NRESETI PRUN PLD1A[0.4] D[0.7] WRITE READ CLOCK LATCH0 LATCH1 NRESETI PRUN File PCSI4.SCH TIMOUT TOUT ITSI4 TIM1IN TIMOUT TOUT ITSI4 TIM1IN PC[0.7] PCCAD[0.7]
MW2X30C
EXT4 CLOCK
EXT6 EXT2 EXT3 EXT8 EXT7 EXT10 EXT9
EXT0
LATCH0 LATCH1
PC[0.7] PCCAD[0.7] EXT[0.10] RBB[0.3]
PROBE Connection EXT[0.10] RBB[0.3] PA[0.7] PB[0.7] PC[0.7]
CONTROL, ADRESS DECODING, INTERFACE POWEFile CONTROL.SCH INT[0.4] CLOCK RESSO RESTO A[0.7] NITPB PRUN BDIO EXWR TY9B VCKOUT ITSI4 NITTIM1 NITADC NITTIM2 ITRTC INT[0.4] CLOCK RESSO RESTO A[0.7] NITPB PRUN BDIO EXWR TY9B VCKOUT ITSI4 NITTIM1 NITADC NITTIM2 ITRTC NRESETI RSTINT PLD1A[0.4] NRESETAP EXTRES VCCAPP READ WRITE EXTRES NRESETI RSTINT PLD1A[0.4]
EXTAL XTAL
EXTAL XTAL NRES CKNMI VSREF VCCAPP
CKNMI VSREF
READ WRITE
VCKOUT CKNMI OPTSE
VCKOUT CKNMI OPTSE
BANK, Clock Generation, Reset, WATCHDOG, Pag. Register
DD[0.7] WRITE READ NRESETI STOP WAIT PULS A[0.7] INTRES OPTSER RSTINT D[0.7] WRITE READ NRESETI STOP WAIT PULS A[0.7] INTRES OPTSER RSTINT File EEPRBNK.SCH CLOCK CLKSYST PRUN PRUN0 EXTINT CKNMI VCKOUT EXT[0.10] TY2B TY9B RAMPB[0.7] DRBB[0.7] ROMADR OSCIN OSCOUT CLOCK CLKSYST PRUN PRUN0 EXTINT CKNMI VCKOUT EXT[0.10] TY2B TY9B RAMPB[0.7] DRBB[0.7] ROMADR XTAL EXTAL
CKNMI VCKOUT EXT[0.8]
Analog Digital Converter
DD[0.7] FILE: CAD.SCH D[0.7] PA[0.7] PACAD[0.7] PB[0.7] PBCAD[0.7] ADCCLOCK NADCRRR NSTARTADC PC[0.7] PCCAD[0.7] EOCADC VSREF PA[0.7] PACAD[0.7] PB[0.7] PBCAD[0.7] PC[0.7] PCCAD[0.7] EOCADC VSREF VR02091N
ADCCLOCK
NADCRRR NSTARTADC
NADCRRR NSTARTADC
25/38
File PA07.SCH PUPPA[0.7] PUPPA[0.7] OUTPA[0.7] VOUTPA[0.7] INPA[0.7] PA[0.7] PA[0.7] PA[0.7] OUTPA[0.7] VOUTPA[0.7] INPA[0.7] 10K-S10 TOUT TIMOUT TOUT TIMOUT PORT VOUTPA7 VOUTPA6 VOUTPA5 VOUTPA4 VOUTPA0 VOUTPA3 VOUTPA2 VOUTPA1
26/38
IC10 470K EXT0 EXT1 EXT[0.8] PORTA OPTION EXT[0.8] PLD1A4 LATCH0 INPA7 VOUTPA7 OUTPA7 PAUP/CAD7
RP13
PAUP/CAD0 PAUP/CAD7 PAUP/CAD1 PAUP/CAD2 PAUP/CAD6 PAUP/CAD5 PAUP/CAD3 PAUP/CAD4 LATCH0
LATCH1 OUTPA0 OUTPA1 OUTPA2 OUTPA3 OUTPA4 OUTPA5 OUTPA6 OUTPA7
10K-S10
10K-S10
PLD1A[0.4]
PLD1A[0.4]
ST626x-EMU2 ANNEX
WRITE READ NRESETI CLOCK
NRESETI
Figure Port Timer
D[0.7]
D[0.7]
PAUP/CAD0 OUTPA0 VOUTPA0 INPA0
Input Input Input Input Input Input Input Input/CLK
LATCH1
INPA5 VOUTPA5 OUTPA5 PAUP/CAD5 INPA6 VOUTPA6 OUTPA6 PAUP/CAD6 RS5A RS4B 1K-4R8P RS5B RS4A 1K-4R8P
PAUP/CAD1 OUTPA1 VOUTPA1 INPA1
RS5C RS4C
PAUP/CAD2 OUTPA2 VOUTPA2 INPA2 EPM5128 10K-S10 RP18
RS5D RS4D
MW2X8C
OUTPA0 OUTPA1 OUTPA2 OUTPA3 OUTPA4 OUTPA5 OUTPA6 OUTPA7
PPTA CK/12 PPTA
NITTIM1 PULS
PRUN
PRUN
LATCH0
IC49 374E
PUPPA0 PUPPA1 PUPPA2 PUPPA3 PUPPA4 PUPPA5 PUPPA6 PUPPA7
PACAD[0.7]
LATCH0 LATCH1 PACAD[0.7]
TIM1IN
PAUP/CAD0 PAUP/CAD1 PAUP/CAD2 PAUP/CAD3 PAUP/CAD4 PAUP/CAD5 PAUP/CAD6 PAUP/CAD7 LATCH1
IC54 374E
PACAD0 PACAD1 PACAD2 PACAD3 PACAD4 PACAD5 PACAD6 PACAD7
VR02091J
PUPPA[0.7] VOUTPA[0.7] PA[0.7] PA[0.7]
PUPPA[0.7]
VOUTPA[0.7] OUTPA[0.7] INPA[0.7] PUPPA4 RS8A 100K-4R8P IC41A 74HC126E 74HC14E IC32A IC53A 74HC126E VOUTPA4 IC48A 74HC126E IC33A 74HC14E 74HC4049I RS7A 100K-4R8P
OUTPA[0.7] INPA[0.7]
PUPPA0
VOUTPA0
Figure Port buffers
OUTPA4 IC24A INPA4
OUTPA0 IC25A INPA0
IC42A 74HC126E
74HC4049I
PUPPA1 IC48D 74HC126E OUTPA5 INPA5 74HC4049I PUPPA6 IC24F IC32F IC41D 74HC126E IC33F 74HC14E IC48B 74HC126E IC33B 74HC14E INPA6 RS8C 100K-4R8P OUTPA6 IC24B 74HC4049I PUPPA7 IC48C 74HC126E IC33E 74HC14E RS8D 100K-4R8P VOUTPA7 OUTPA7 INPA7 IC24E 74HC4049I VOUTPA6 IC41B 74HC126E IC32B RS8B 100K-4R8P VOUTPA5
PUPPA5
VOUTPA1
IC53D 74HC126E
RS7B 100K-4R8P 74HC14E IC53B 74HC126E
OUTPA1
IC25F
INPA1
IC42D 74HC126E
74HC4049I PUPPA2
VOUTPA2
RS7C 100K-4R8P 74HC14E
OUTPA2
IC25B
INPA2
IC42B 74HC126E
74HC4049I
PUPPA3
VOUTPA3
IC53C 74HC126E IC32E IC41C 74HC126E 74HC14E
RS7D 100K-4R8P
OUTPA3
IC25E
INPA3
IC42C 74HC126E
74HC4049I
VR02091K
ST626x-EMU2 ANNEX
27/38
10K-S10 10K-S10 10K-S10 PULLUP EPLD HIGH LEVEL Impedence RP16 OUTPB0 PBUPCAD7 OUTPB7 PBUPCAD6 PBUPCAD5 OUTPB1 PBUPCAD4 OUTPB2 PBUPCAD3 OUTPB6 OUTPB5 PBUPCAD2 OUTPB3 PBUPCAD1 OUTPB4 PBUPCAD0 74HC4060 470K PBUPCAD[0.7] PBUPCAD[0.7] PBUPCAD[0.7] PORT File PB07.SCH EXT2 PUPPB[0.7] PUPPB[0.7] OUTPB[0.7] VOUTPB[0.7] INPB[0.7] PB[0.7] PB[0.7] PB[0.7] OUTPB[0.7] TS[0.7] INPB[0.7] PBCAD[0.7] 374E 374E PBCAD[0.7] 32.768 100K PBUPCAD0 PBUPCAD1 PBUPCAD2 PBUPCAD3 PBUPCAD4 PBUPCAD5 PBUPCAD6 PBUPCAD7 PUPPB0 PUPPB1 PUPPB2 PUPPB3 PUPPB4 PUPPB5 PUPPB6 PUPPB7 PBUPCAD0 PBUPCAD1 PBUPCAD2 PBUPCAD3 PBUPCAD4 PBUPCAD5 PBUPCAD6 PBUPCAD7 IC39 IC22 PBCAD0 PBCAD1 PBCAD2 PBCAD3 PBCAD4 PBCAD5 PBCAD6 PBCAD7 IC13
28/38
7777 9876 OOOOOO ADCCLOCK ITRTC INTEFR OUTPB6 PBUPCAD6 EXT3 PRUN ITRTC NNNN PPPP UUUU TTTT RS12A 1K-4R8P RS12B RS11A RS11B INPB7 INPB6 INPB5 INPB4 RS12C RP17 10K-S10 OOOOOOOO 4555 9012 TTTUT4 T354PP EPM5192 TEST NITTIM2 BIT4 INTFR INTFLL EXT[0.8] EXT[0.8] RS11C RS12D RS11D 1K-4R8P NNNN PPPP UUUU TTTT PPPP DDDD AAAA INPB3 INPB2 OUTPB5 PBUPCAD5 PORTB OPTION OPEN OPEN DRAIN OPTION CLOSED PUSH-PULL OPTION MW2X8C 6789 OUTPB0 OUTPB1 OUTPB2 OUTPB3 OUTPB4 OUTPB5 OUTPB6 OUTPB7 NADCRRR NITADC NSTARTADC NITPB VR02091F
LATCH0 LATCH1
PRUN READ WRITE
D[0.7]
D[0.7]
CLOCK NRESETI
RP13 10K-S10
OPT4
23456 7891
ST626x-EMU2 ANNEX
Figure Port Timer
PULLUP
MW1X3C
PULLUP
MW1X3C OPT5
23456 7890
RP14 10K-S10
09876
PLD1A[0.4]
OOOOO
OUTPB1 PBUPCAD1 INTEFLL NITADC
EOCADC
NSTARTADC STARTRTC NITPB EOCADC
PLD1A4 CLOCK2Hz OUTPB2 PBUPCAD2
OOOO
33333 45678
UBEYAX
PLD1A[0.4]
TY9B
MW1X2C
PUPPB[0.7] PB[0.7] PUPPB4 INPB[0.7] 74HC4049I 74HC14E PUPPB5 RS17B 100K-4R8P VOUTPB5 IC46D 74HC126E IC38D 74HC14E OUTPB5 IC29D INPB5 74HC4049I PUPPB6 RS17C 100K-4R8P VOUTPB6 OUTPB6 IC16C INPB6 74HC4049I PUPPB7 IC40C 74HC126E IC32D 74HC14E RS17D 100K-4R8P VOUTPB7 OUTPB7 IC16D INPB7 74HC4049I IC46C 74HC126E IC21D 74HC14E VR02091B IC45C 74HC126E RS18A 100K-4R8P IC46B 74HC126E IC21C 74HC14E IC45B 74HC126E IC45D 74HC126E RS18C 100K-4R8P 74HC14E IC46A 74HC126E IC38C RS17A 100K-4R8P INPB4 OUTPB4 IC29C IC45A 74HC126E VOUTPB4 RS18D 100K-4R8P PB[0.7] VOUTPB[0.7] OUTPB[0.7] INPB[0.7] PUPPB[0.7] VOUTPB[0.7] OUTPB[0.7]
PUPPB0
VOUTPB0
IC33C
OUTPB0
IC40A 74HC126E
IC25C
INPB0
IC23A 74HC126E
74HC4049I PUPPB1
Figure Port Timer buffer
VOUTPB1
IC33D 74HC14E
OUTPB1
IC40D 74HC126E
IC25D
INPB1
IC23D 74HC126E
PUPPB2
74HC4049I
VOUTPB2
IC32C 74HC14E
OUTPB2
IC40B 74HC126E
RS18B 100K-4R8P
IC24C
INPB2
IC23B 74HC126E
74HC4049I
PUPPB3
VOUTPB3
OUTPB3
IC24D
INPB3
IC23C 74HC126E
74HC4049I
ST626x-EMU2 ANNEX
29/38
File PC07.SCH RP11 RP14 PC[0.7] PC[0.7] PC[0.7] PUPPC0 PUPPC7 PUPPC1 PUPPC2 PUPPC6 PUPPC5 PUPPC3 PUPPC4 10K-S10 10K-S10 10K-S10 OUTPC7 OUTPC6 OUTPC5 OUTPC4 OUTPC0 OUTPC3 OUTPC2 OUTPC1 TSPC7 TSPC6 TSPC5 TSPC4 TSPC0 TSPC2 TSPC1 TSPC3
30/38
IC27 IC19 PUPCAD7 PUPCAD6 PUPCAD5 PUPCAD4 PUPCAD3 PUPCAD2 PUPCAD1 PUPCAD0 374E GND18 PUPPC7 PUPPC6 PUPPC5 PUPPC4 PUPPC3 PUPPC2 PUPPC1 PUPPC0 INPC5 TSPC5 OUTPC5 PUPCAD5 EXT7 EXT8 EPM5128 INPC6 TSPC6 OUTPC6 PUPCAD6 PUPCAD7 PUPCAD6 PUPCAD5 PUPCAD4 PUPCAD3 PUPCAD2 PUPCAD1 PUPCAD0 374E GND18 RBB2 RBB1 RBB0 INPC7 TSPC7 OUTPC7 PUPCAD7 PCCAD7 PCCAD6 PCCAD5 PCCAD4 PCCAD3 PCCAD2 PCCAD1 PCCAD0 PCCAD[0.7] PCCAD[0.7] EXT[0.9] EXT[0.9] 33444444 89012345 PLD1A4 MW2X8C RP15 10K-S10 ITSI4 TIM1IN RBB[0.3] RBB[0.3] RS9A 1K-4R8P RS9B RS10A RS10B 234567890 RS9C RS10C RS9D RS10D 1K-4R8P OUTPC0 OUTPC1 OUTPC2 OUTPC3 OUTPC4 OUTPC5 OUTPC6 OUTPC7 VR02091H
PORT
PUPPC[0.7]
PUPPC[0.7]
OUTPC[0.7] TSPC[0.7]
OUTPC[0.7]
TSPC[0.7]
INPC[0.7]
INPC[0.7]
LATCH0 LATCH1 PLD1A[0.4]
PLD1A[0.4]
Figure Port
WRITE READ
NRESETI
ST626x-EMU2 ANNEX
D[0.7]
D[0.7]
CLOCK
333366 12245668
PUPCAD0 OUTPC0 TSPC0 INPC0
PRUN
ITSI4
PPPPPPPP TTTTTTTT
PUPCAD1 OUTPC1 TSPC1 INPC1
PUPCAD2 OUTPC2 TSPC2 INPC2
2222233 5678901
UUSN
TIMOUT
TOUT
IC12A
100K
74HC14
PUPPC[0.7] PC[0.7] PUPPC4 OUTPC4 74HC126E 74HC14E IC21A IC28A IC43A 74HC126E TSPC4 IC51A 74HC126E IC38A 74HC14E IC16A INPC4 74HC4049I RS1B 100K-4R8P PC[0.7]
TSPC[0.7]
PUPPC[0.7] TSPC[0.7] OUTPC[0.7]
OUTPC[0.7]
INPC[0.7]
INPC[0.7]
PUPPC0
TSPC0
OUTPC0
RS1A 100K-4R8P
INPC0
IC29A
IC20A 74HC126E
Figure Port buffers
74HC4049I
PUPPC1 IC51D 74HC126E OUTPC5 IC28D 74HC126E IC16F INPC5 74HC4049I PUPPC6 TSPC6 OUTPC6 IC38F 74HC14E IC51B 74HC126E IC38B 74HC14E RS1D 100K-4R8P RS1C 100K-4R8P TSPC5
PUPPC5
TSPC1
OUTPC1
IC43D 74HC126E IC21F 74HC14E
IC29F INPC1 74HC4049I PUPPC2
IC20D 74HC126E
RS2B 100K-4R8P
TSPC2
OUTPC2
IC43B 74HC126E
INPC2
IC29B
IC20B 74HC126E
RS2C 100K-4R8P IC21B IC28B 74HC126E 74HC14E
74HC4049I
IC16B INPC6 74HC4049I PUPPC7
PUPPC3 TSPC7 RS2D IC28C 74HC126E 74HC4049I IC21E 74HC14E 100K-4R8P VR02091I IC43C 74HC126E OUTPC7 IC16E INPC7
TSPC3 IC51C 74HC126E IC38E 74HC14E
OUTPC3
RS2A 100K-4R8P
INPC3
IC29E
IC20C 74HC126E
74HC4049I
ST626x-EMU2 ANNEX
31/38
PRUN 74HC244 OSCOUT IC52A 74HC126E IC35A 100K 10987654 2143 877777 098765 PRUN ROMADR TY2B TY9B CLKSYST INTRES CLOCK MW1X3C CLOCK CEXT 10NF REXT/CEXT 74HC123 TTTT RDRBB6 RAMD6 CLKSYSTNB RAMADD7 RAMADD3 44445555 67890123 EPM5192 IC52B 74HC126E EXT[0.10] RDRBB[0.7] RDRBB[0.7] RAMADD6 MW2X4C IC18 HC4040 VCKOUT CKNMI EXT[0.10] RAMPB[0.7] DRBB[0.7] 333333 345678 4444 1234 0123 NNNN PPPP UUUU TTTT RAMADD2 CKBUILDUP RDRBB5 RAMD5 RP25 RP26 RAMADD0 RAMADD1 RAMADD2 RAMADD3 RAMADD4 RAMADD5 RAMADD6 RAMADD7 BNK0 BNK1 BNK2 BNK3 RAMD0 RAMD1 RAMD2 RAMD3 RAMD4 RAMD5 RAMD6 RAMD7
32/38
NCERAM RWRAM 10K-S10 10K-S10 IC14 CY7C185 VR02091L HARD SOFT MW1X3C WATCHDOG
PRUN0
IC15A
OSCIN
4049I
ST626x-EMU2 ANNEX
NRESETI EXTINT PULS
D[0.7]
D[0.7]
A[0.7]
A[0.7]
READ
READ
WRITE
WRITE
RDRBB1 RAMD1 NCERAM RAMADD4
OPTSE
RAMADD0 OPTSER RAMADD5
8MHZ IC11A
IC11D
RAMADD1 PRUN RDRBB2 RAMD2 TY2B RDRBB3
74HC04
74HC04
22PF
22PF
IC35B CEXT
REXT/CEXT
Figure RAM, EEPROM, Bank reg., Data windowing, watchdog, Reset
74HC123
RSTINT STOP WAIT
CLOCK PLD1A[0.4] PLD1A[0.4] PLD1A0 PLD1A1 PLD1A2 PLD1A3 PLD1A4 10K-S10 198765432 INT[0.4] INT[0.4] INT0 INT1 INT2 INT3 INT4 NRESETI SH/LD 74HC165 MW2X8C IC17
CLOCK
A[0.7]
A[0.7]
TY9B
20V8
RESTO RESSO NITPB NITTIM1 ITSI4 NITTIM1 NITADC NITTIM2 ITRTC PRUN VCKOUT 100K IC26B 098765432 10uH 10uF 1N4004 100NF 10uF 100NF 100K IC57A LM324
ITSI4 NITTIM1 NITADC NITTIM2 ITRTC
IC15C
20V8
Figure Control interface power
CKNMI
RP27 10K-S10
74HC14E READ WRITE RSTINT
4049I
IC34 SH/LD 74HC165
MW2X8C
OPTSE
100K
IC26A
IC15B
NRESETAP
1N4148
4049I
74HC14E EXTRES BDIO EXWR
20V8
1N4148
VDDI
+VIN +VIN
+VOUT +VOUT
100nF 470uF-EA
-VIN -VIN VSRC
-VOUT -VOUT
BD233
100nF
56uH IC56 470pF VR02091E COMP MC34063 BYV10-20 1,5K
0,330
DC/DC CONVERTE
VCCAPP
ST626x-EMU2 ANNEX
33/38
IC55 -12V -12V AINB 10uF IC50A TL072A +12V 74HC244 IC59 4066EC 10uF +12V 4066EC IC58
34/38
IC30 74HC244 IC31 2.2nF 4066EC VICLKR EOCN VREF INTR AGND ADC0802C AIND VSREF 4066EC IC47 IC36 74HC244 IC37 EOCADC 4066EC 4066EC IC44 VR02091C
PA[0.7]
PA[0.7]
PACAD0 PACAD1 PACAD2 PACAD3 PACAD4 PACAD5 PACAD6 PACAD7
PACAD[0.7]
PACAD[0.7]
ST626x-EMU2 ANNEX
Figure Analog Digital Converter
PB[0.7]
PB[0.7]
PBCAD0 PBCAD1 PBCAD2 PBCAD3 PBCAD4 PBCAD5 PBCAD6 PBCAD7
PBCAD[0.7]
PBCAD[0.7]
PC[0.7]
PC[0.7]
PCCAD0 PCCAD1 PCCAD2 PCCAD3 PCCAD4 PCCAD5 PCCAD6 PCCAD7
PCCAD[0.7]
PCCAD[0.7]
D[0.7]
D[0.7]
NADCRRR NSTARTADC ADCCLOCK ADCCLOCK VSREF VSREF
PA[0.7]
PA[0.7]
ST2626X ST629X PROBE CONNECTORS
PB[0.7] Number component's
PB[0.7]
PC[0.7]
PC[0.7]
VCCAPP
Figure Application connectors
XTAL EXTAL
VCCAPP XTAL EXTAL
CKNMI NRES CKNMI
NRES
NRES
HE1034DM
HE1034DM
VSREF
VSREF VSREF
VCCAPP XTAL EXTAL CKNMI
NRES
HE1034DM ST2621X PROBE CONNECTORS
HE1034DM
VR02091D
ST626x-EMU2 ANNEX
35/38
470PF
100NF
VSREF
36/38
VCCAPP XTAL EXTAL CKNM NRES HE10-34DM HE10-34DM VCCAPP OSCIN OSCOUT CKNMI VCCAPP OSCOUT OSCIN OSCOUT NRES VPP/TEST RESET DIL20 OSCIN OSCOUT VPP/TEST ESET DIL28 74HC04 74HC04 OSCIN 100K EXTAL 100NF 100PF 74HC04 OSCOUT 100PF MW1X1C MW1X1C 2X1C XTAL MW3X1C
PROBE
VCCAPP
ST626x-EMU2 ANNEX
Figure Probe ST620x, ST621x, ST622x
VCCAPP OSCIN OSCOUT
OSCIN OSCOUT
VPP/TEST ESET PB7/AIN3 PB6/AIN2
PB5/AIN1
DIL16
74HC04
8MHZ-XT-P
esonnat
XTAL EXTAL 2X1C UTTEC TACT 2X1C
PB6/TIM PB7/TIM PA0/ADC VCCAPP VSREF PA1/ADC PA2/ADC
DIL28 HE10-34DM
CONN PC0/ADC PC1/TIM 1/ADC PC2/SI/ADC PC3/SO/ADC PC4/SK/ADC SCIN PA7/ADC PA6/ADC PA5/ADC PA4/ADC PA3/ADC
E10-34D
Figure Probe ST625x, ST626x, ST629x
PB6/TIM PB7/TIM PA0/ADC VCCAPP VSREF
DIL20
CONN PC2/SI/ADC PC3/SO/ADC PC4/SK/ADC PA3/ADC PA2/ADC PA1/ADC
PB6/TIM PB7/TIM VCCAPP VSREF
DIL16
2X1C 74HC04 XTAL 100PF
EXTAL 100N 100PF
74HC04
3X1C
74HC
Z-XT-P
470PF
reso
ST626x-EMU2 ANNEX
37/38
ST626x-EMU2 ANNEX
Notes:
38/38
APPLICATION NOTE
TRIAC MICROCONTROLLER SAFETY PRECAUTIONS DEVELOPMENT TOOL
Rabier
goal this paper analyse different ways configure micro-controller development tool during debbugging phase. major problem direct connection computer lines with mains power. Some precautions have taken during emulation order avoid destruction. COST POWER SUPPLY most cost applications step down transformer used power supply delivers current, shown example figure Figure Uninsulated power supply
consequence that there insulation, microcontroller connected directly line When software emulated application board, output port (RS232 port) computer connected line emulator. some precaution taken "something" will destroyed Figure gives example application using triac microcontroller. Figure Triac microcontroller line
UNINSULATED
LINE
POWER SUPPLY
LINE
BZX55C5V6 220nF 400V 1N4148 100u 6.3V
LOAD
1/2W
domestic appliance applications, most important power switches triac. function driving triac becomes more more complex. this reason, microcontrollers becoming more more common. Furthermore, sensitive triacs with high commutation parameters, example LOGIC LEVEL triacs triggered directly microcontroller without buffer. Sensitive triacs microcontrollers allow decrease power consumption. this power supply optimized reduce cost. Optimisation achieved removing transformer.
this case micro-controller supplied uninsulated power supply connected directly line, level (0V) output ports micro-controller needed trigger triac. DEVELOPMENT TOOL During debbuging phase, micro-controller removed replaced emulation probe. circuit corresponding emulation phase previous example shown figure line connected directly emulator high (destructive) current flow through emulator and/or computer.
1996
This advance information from SGS-THOMSON. Details subject change without notice.
APPLICATION NOTE
Figure Circuit without protection (Beware this circuit dangerous)
Figure Optotriac drive
PROBE
LINE LOAD
POWE
SUPPLY
LATO
RS232 PUTE
LINE LOAD
(HIGH DESTRUCTIVE CURRENT)
INSULATED SYSTEM avoid destruction development tool necessary have insulation between line probe. This insulation achieved optocouplers, pulse transformers, insulation transformers. Figure shows topology most common insulation. Figure Conventional insulation
main advantage such system cost optotriac, needs isolated auxiliary power supply. zero crossing optotriac, triac triggering with gate current equal gate trigger current with very dIG/dt. This does allow high turn That control high current resistive load recommended with this method. pulse transformer Figure shows circuit with triac pulse transformer. triac working quadrants. Figure Pulse transformer insulation
PROBE INSULATION LINE LOAD (From external insulated power supply)
LATOR PUTE
LINE
Pulse transformer
LINE
POWER DRIVE
LOAD
Optotriac Figure shows circuit with triac optotriac. triac working quadrants.
APPLICATION NOTE
This system simple when triac initially driven buffer transistor, needs external power supply. high dIG/dt through gate allows high current resistive loads driven. saturation magnetic material, this system cannot drive small loads because gate current cancelled before latching current been reached. more information refer application note "Triac control pulse transformer". line insulation transformer previous examples, insulation between triac microcontroller. SUMMARY LOGIC LEVEL SNUBBERLESS triacs connected directly microcontroller without buffers insulation. Furthermore, cost power supplies without transformer becoming more common. There increasing number applications supplied directly from mains, microcontroller directly connected During debbuging phase when connecting development tool, galvanic insulation absolutely necessary. Figure Insulation with transformers
This insulation done ways Another solution supply each equipment connected board from mains through insulation transformer. oscilloscope used, also separately insulated. main advantage this system that need modify target system during debbuging phase used with microcontroller. When transformer used between line triac should noted that line impedance modified then behaviour triac, load line different (waveform current). With optotriacs Need modifications target system Need external power supply With pulse transformer Need modifications (transistor drive pulse transformer) Need external power supply Cannot drive small loads With insulation transformer modification application board. Modification line impedance transformer between line load. Therefore microcontroller operating mains with triac directly connected line.
PROBE LINE LOAD POWER SUPPLY
RS232 LATO
PUTER LINE
Oscilloscope
LINE INSULATED SYSTEM
APPLICATION NOTE
Notes:
Information furnished believed accurate reliable. However, SGS-THOMSON Microelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights SGS-THOMSON Microelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. SGS-THOMSON Microelectronics products authorized critical components life support devices systems without express written approval SGS-THOMSON Microelectronics. ©1998 SGS-THOMSON Microelectronics rights reserved. Purchase Components SGS-THOMSON Microelectronics conveys license under Philips Patent. Rights these components system granted provided that system conforms Standard Specification defined Philips. SGS-THOMSON Microelectronics Group Companies Australia Brazil Canada China France Germany Italy Japan Korea Malaysia Malta Morocco Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U.S.A.

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