M48T559Y SOFTWARE HARDWARE RESET WATCHDOG TIMER REGISTER COMPATIB
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Kbit (8Kb TIMEKEEPER® SRAM with ADDRESS/DATA MULTIPLEXED
M48T559Y
SOFTWARE HARDWARE RESET WATCHDOG TIMER REGISTER COMPATIBLE with M48T59 TIMEKEEPER SRAM ADDRESS/DATA MULTIPLEXED PINS WATCHDOG TIMER MONITORS CONTROL PROCESSOR HUNG ALARM with WAKE-UP BATTERY MODE INTEGRATED ULTRA POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT BATTERY FREQUENCY TEST OUTPUT REAL TIME CLOCK AUTOMATIC POWER-FAIL CHIP DESELECT WRITE PROTECTION WRITE PROTECT VOLTAGE (VPFD Power-fail Deselect Voltage): M48T559Y: 4.2V VPFD 4.5V PACKAGING INCLUDES 28-LEAD SOIC SNAPHAT® Ordered Separately) SOIC PACKAGE PROVIDES DIRECT CONNECTION SNAPHAT CONTAINS BATTERY CRYSTAL MICROPROCESSOR POWER-ON RESET (Valid even during battery back-up mode) PROGRAMMABLE ALARM OUTPUT ACTIVE BATTERY BACK-UP MODE
RSTIN1 RSTIN2
SNAPHAT (SH) Battery/Crystal
SOH28 (MH)
Figure Logic Diagram
AD0-AD7 M48T559Y IRQ/FT
DESCRIPTION M48T559Y TIMEKEEPER non-volatile static real time clock. monolithic chip available SNAPHAT package provide highly integrated battery backedup memory real time clock solution. 330mil SOIC provides sockets with gold plated contacts both ends direct connection separate SNAPHAT housing containing battery crystal. unique design allows SNAPHAT battery package mounted SOIC package after completion surface mount process.
February 2000
AI01674B
1/18
M48T559Y
Figure SOIC Connections Table Signal NameAD0-AD7 AS0-AS1 Address/Data Address Strobes Write Enable Read Enable Chip Enable Watchdog Input Reset Input Power Fail Reset Output (Open Drain) Interrupt Frequency Test Output (Open Drain) Supply Voltage Ground Connected Internally Don't must connected
RSTIN1 RSTIN2
M48T559Y
AI01675B
IRQ/FT
RSTIN1-RSTIN2 IRQ/FT
Table Absolute Maximum RatingSymbol Parameter Ambient Operating Temperature Storage Temperature Off, Oscillator Off) Input Output Voltages Supply Voltage Output Current Power Dissipation Value -0.3 -0.3 Unit
Note: Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods time affect reliability.
CAUTION: Negative undershoots below -0.3V allowed while Battery Back-up mode. CAUTION: wave solder SOIC avoid damaging SNAPH sockets.
Insertion SNAPHAT housing after reflow prevents potential battery crystal damage high temperatures required device surface-mounting. SNAPHAT housing keyed prevent reverse insertion. SOIC battery/crystal packages shipped separately plastic anti-static tubes Tape Reel form. lead SOIC, battery/crystal package (i.e. SNAPHAT) part number "M4T28-BR12SH1". Caution: place SNAPHAT battery/crystal conductive foam, this will drain lithium button-cell battery. Figure shows, static memory array quartz controlled clock oscillator M48T559Y integrated silicon chip.
circuits interconnected upper eight memory locations provide user accessible BYTEWIDEclock information bytes with addresses 1FF8h-1FFFh. clock locations contain year, month, date, day, hour, minute, second hour format. Corrections (leap year), months made automatically. Byte 1FF8h clock control register. This byte controls user access clock information also stores clock calibration setting. eight clock bytes actual clock counters themselves; they memory locations consisting BiPORTread/write memory cells. M48T559Y includes clock control circuit which updates clock bytes with current infor-
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M48T559Y
Figure Block Diagram
IRQ/FT
OSCILLATOR CLOCK CHAIN 32,768 CRYSTAL POWER
BiPORT SRAM ARRAY DATA TRANSCEIVER
LITHIUM CELL VOLTAGE SENSE SWITCHING CIRCUITRY VPFD
8176 SRAM ARRAY
UPPER ADDRESS LATCH
AD0-AD7
LOWER ADDRESS LATCH
RSTIN1 RSTIN2
AI01676B
Table Operating Modes
Mode Deselect Write Read Read Deselect Deselect VPFD (min) 4.5V 5.5V AD0-AD7 High DOUT High High High Power Standby Active Active Active CMOS Standby Battery Back-up Mode
Note: VIL; Battery Back-up Switchover Voltage. Table details. AD0-AD7, AS0, active when high VPFD
mation once second. information accessed user same manner other location static memory array. M48T559Y also Power-fail Detect circuit. control circuitry constantly monitors single supply tolerance condition.
When tolerance, circuit write protects SRAM, providing high degree data security midst unpredictable system operation brought VCC. falls below approximately control circuitry connects battery which maintains data clock operation until valid power returns.
3/18
M48T559Y
Table Measurement ConditionInput Rise Fall Times Input Pulse Voltages Input Output Timing Ref. Voltages 1.5V
1.9k DEVICE UNDER TEST
Figure Testing Load Circuit
Note that Output Hi-Z defined point where data longer driven.
100pF
includes capacitance
AI01673
Table Capacitance MHz)
Symbol Parameter Input Capacitance Input Output Capacitance Test Condit VOUT Unit
Note: Effective capacitance measured with power supply Sampled only, 100% tested. Outputs deselected.
Table Characteristics 4.5V 5.5V)
Symbol ILRST ICC1
Note:
Parameter Input Leakage Current Output Leakage Current Input Leakage Current Supply Current Supply Current (Standby) Supply Current (Standby) CMOS Input Voltage Input High Voltage Output Voltage Output Voltage (IRQ/FT) Output High Voltage
Test Condit VOUT Outputs open 0.2V
Unit
-0.3 2.1mA 10mA -1mA
Outputs deselected. Input leakage current input RESET pins. AD0-AD7, AS0, active when high VPFD Negative spikes allowed 10ns once cycle. pins Open Drain. Measured with Control Bits follows: '1'; '0'.
4/18
M48T559Y
Table Power Down/Up Trip Points Characteristics
Symbol VPFD Parameter Power-fail Deselect Voltage Battery Back-up Switchover Voltage Expected Data Retention Time 4.35 Unit YEARS
Note: voltages referenced VSS. 25°C.
Table Power Down/Up Characteristics
Symbol tREC Parameter before Power Down VPFD (max) VPFD (min) Fall Time VPFD (min) Fall Time VPFD (min) VPFD (max) Rise Time VPFD (min) Rise Time VPFD (max) High Unit
Note: VPFD (max) VPFD (min) fall time less than result deselection/write protection occurring until 200µs after passes VPFD (min). VPFD (min) fall time less than cause corruption data.
Figure Power Down/Up Mode Waveform
VPFD (max) VPFD (min) tREC
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01384D
5/18
M48T559Y
Table Characteristics 4.5V 5.5V)
M48T559Y Symbol tRLDV RLRH tRHDZ tWLWH tELEH tASLASH ASHRL tASHWL tELRL EHDZ tELWL Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Enable Access Time Pulse Width Read Enable High Output High Pulse Width Pulse Width AS0, Pulse Width AS0, High AS0, High Chip Enable Read Enable Chip Enable High Data Output Hi-Z Chip Enable Write Enable Parameter Unit
OPERATION Four control signals, AS0, AS1, used access M48T559Y. address latches loaded from address/data response rising edge signals applied Address Strobe (AS0) Address Strobe (AS1) signals. used latch lower bits address, used latch upper bits address. however necessary follow particular order. inputs parallel address bytes (upper lower) latched order long correct strobe used. necessary meet set-up hold times given specifications with valid address information order properly latch address. upper and/or lower order addresses correct from prior cycle, necessary repeat address latching sequence. write operation requires valid data placed (AD0-AD7), followed activation Write Enable line. Data will written RAM, provided that write timing specifications met. During read cycle, Read Enable signal driven active. Data from will become valid provided that read access timing specifications met.
signals should never active same time. addition, must active before control line recognized (except AD0-AD7 AS0, AS1). RESET INPUT M48T559Y provides debounced inputs which generate output Reset. duration function Reset output identical Reset generated power cycle. Pulses shorter than will generate Reset condition (see Table Figure 13). DATA RETENTION MODE Should supply voltage decay, will automatically power-fail deselect, write protecting itself when falls within VPFD (max), VPFD (min) window. outputs become high impedance, inputs treated "don't care." Note: power failure during write cycle corrupt data currently addressed location, does jeopardize rest RAM's content. voltages below VPFD (min), user assured memory will write protected state, provided fall time less than
6/18
M48T559Y
Figure Read Mode Waveform
tELEH tELRL tASLASH tASLASH tASHRL tRLDV AD0-AD7
DATA VALID
tEHDZ
tRLRH
tRHDZ
ADDRESS VALID
UPPER ADDRESS VALID
AI01671B
Note: AD5-AD7 don't care when latching upper address.
Figure Write Mode Waveform
tELEH tELWL tASLASH tASLASH tASHWL AD0-AD7
DATA VALID
tEHDZ
tWLWH
ADDRESS VALID
UPPER ADDRESS VALID
AI01672B
Note: AD5-AD7 don't care when latching upper address.
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M48T559Y
Table Register
Data Address 1FFFh 1FFEh 1FFDh 1FFCh 1FFBh 1FFAh 1FF9h 1FF8h 1FF7h 1FF6h 1FF5h 1FF4h 1FF3h 1FF2h 1FF1h 1FF0h
Keys:
Year
Function/Rang Format Year Month Date 00-99 01-12 01-31 01-07 00-23 00-59 00-59
Years RPT4 RPT3 RPT2 RPT1 BMB4
Month Date Hours Minutes Seconds Calibration
Date
Hour Minutes Seconds Control
Hours Minutes Seconds BMB3 BMB2 BMB1
BMB0
Watchdog Interrupts Alarm Date Alarm Hours Alarm Minutes Alarm Seconds 01-31 00-23 00-59 00-59
Date Hour
Alarm Date Alarm Hours Alarm Minutes Alarm Seconds
Alarm Minutes Alarm Seconds
Unused Flag
SIGN FREQUENCY TEST READ WRITE STOP Must zero Read only Alarm Flag
Battery Watchdog Steering BMB0-BMB4 Watchdog Multiplier Bits RB0-RB1 Watchdog Resolution Bits Alarm Flag Enable Alarm Battery Back-up Mode Enable RPT1-RPT4 Alarm Repeat Mode Bits Watchdog Flag
M48T559Y respond transient noise spikes that reach into deselect window during time device sampling VCC. Therefore, decoupling power supply lines recommended. When drops below VSO, control circuit switches power internal battery which preserves data powers clock. internal button cell will maintain data M48T559Y accumulated period least years when less than VSO. system power returns rises above VSO, battery disconnected, power supply switched exter-
Write protection continues until reaches VPFD (max) plus tREC. more information Battery Storage Life refer Application Note AN1012. POWER-ON RESET M48T559Y continuously monitors VCC. When falls power fail detect trip point, pulls (open drain) remains powerup 40ms 200ms after passes VPFD. external pull-up resistor required resistor recommended). reset pulse remains active with VSS.
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M48T559Y
CLOCK OPERATIONS Reading Clock Updates TIMEKEEPER registers should halted before clock data read prevent reading data transition. Because BiPORT TIMEKEEPER cells array only data registers, actual clock counters, updating registers halted without disturbing clock itself. Updating halted when written READ bit, Control register (1FF8h). long remains that position, updating halted. After halt issued, registers reflect count; that day, date, time that were current moment halt command issued. TIMEKEEPER registers updated simultaneously. halt will interrupt update progress. Updating within second after reset '0'. Setting Clock Control register (1FF8h) WRITE bit. Setting WRITE '1', like READ bit, halts updates TIMEKEEPER registers. user then load them with correct day, date, time data hour format (see Table Resetting WRITE then transfers values time registers (1FF9h-1FFFh) actual TIMEKEEPER counters allows normal operation resume. After WRITE reset, next clock update will occur second. Application Note AN923 "TIMEKEEPER rolling into 21st century" information Century Rollover. Figure Clock Calibration Stopping Starting Oscillator oscillator stopped time. device going spend significant amount time shelf, oscillator turned minimize current drain battery. STOP seconds register. Setting stops oscillator. M48T559Y shipped from STMicroelectronics with STOP '1'. When reset '0', M48T559Y oscillator starts within second. Calibrating Clock M48T559Y driven quartz controlled oscillator with nominal frequency 32,768Hz. devices tested exceed (parts million) oscillator frequency error 25°C, which equates about ±1.53 minutes month. With calibration bits properly set, accuracy each M48T559Y improves better than 25°C. oscillation rate crystal changes with temperature (see Figure 10). Most clock chips compensate crystal frequency temperature shift error with cumbersome trim capacitors. M48T559Y design, however, employs periodic counter correction. calibration circuit adds subtracts counts from oscillator divider circuit divide stage, shown Figure number times pulses blanked (subtracted, negative calibration) split (added, positive calibration) depends upon value loaded into five Calibration byte found Control Register. Adding counts speeds clock subtracting counts slows clock down.
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
9/18
M48T559Y
Figure Crystal Accuracy Across Temperature
-0.038
-100
AI02124
Calibration byte occupies five lower order bits (D4-D0) Control register (1FF8h). These bits represent value between binary form. Sign bit; indicates positive calibration, indicates negative calibration. Calibration occurs within minute cycle. first minutes cycle may, once minute, have second either shortened lengthened oscillator cycles. binary loaded into register, only first minutes minute cycle will modified; binary loaded, first will affected, Therefore, each calibration step effect adding subtracting oscillator cycles every 125,829,120 actual oscillator cycles, that +4.068 -2.034 adjustment calibration step calibration register. Assuming that oscillator fact running exactly 32,768Hz, each increments Calibration byte would represent +10.7 -5.35 seconds month which corresponds total range +5.5 2.75 minutes month. methods available ascertaining much calibration given M48T559Y require.
first involves simply setting clock, letting month comparing known accurate reference (like broadcasts). While that seem crude, allows designer give user ability calibrate clock environment require, even after final product packaged non-user serviceable enclosure. designer provide simple utility that accesses Calibration byte. second approach better suited manufacturing environment, involves IRQ/FT pin. will toggle 512Hz when Stop 1FF9h) '0', 1FFCh) '1', 1FF6h) '0', Watchdog Steering 1FF7h) Watchdog Register reset (1FF7h deviation from 512Hz indicates degree direction oscillator frequency shift test temperature. example, reading 512.01024 would indicate oscillator frequency error, requiring (WR001010) loaded into Calibration Byte correction. Note that setting changing Calibration Byte does affect Frequency test output frequency. cleared power-down.
10/18
M48T559Y
more information calibration, Application Note AN934 "TIMEKEEPER Calibration". IRQ/FT open drain output which requires pull-up resistor proper operation. 500-10k resistor recommended order control rise time. SETTING ALARM CLOCK Registers 1FF5h-1FF2h contain alarm settings. alarm configured prescribed time specific month repeat every day, hour, minute, second. also programmed while M48T559Y battery back-up mode operation serve system wake-up call. RPT1-RPT4 alarm repeat mode operation. Table shows possible configurations. Codes listed table default once second mode quickly alert user incorrect alarm setting. Note: User must transition address toggle chip enable) Flag change. When clock information matches alarm clock settings based match criteria defined RPT1-RPT4, (Alarm Flag) set. (Alarm Flag Enable) also set, alarm condition activates IRQ/FT pin. disable alarm, write Alarm Date registers RPT1-4. alarm flag IRQ/FT output cleared read Flags register shown Figure Note: alarm condition occurs while flags register address latched into address buffer, alarm flag will until address other than flags register (1FF0h) latched into address buffer. This will insure that alarm flag will inadvertently reset while reading flag register. properly check alarm condition occurred while reading flag register, user required latch, read write alternate address then re-read alarm flag. IRQ/FT also activated battery back-up mode. IRQ/FT will alarm occurs both (Alarm Battery Back-up Mode Enable) set. bits reset during power-up, therefore alarm generated during power-up will only user read Flag Register system boot-up determine alarm generated while M48T559Y deselect mode during power-up. Figure illustrates back-up mode alarm timing. Table Alarm Repeat Mode
RPT4 RPT3 RPT2 RPT1 Alarm Activated Once Second Once Minute Once Hour Once Once Month
Figure Interrupt Reset Waveform
AD0-AD7
ADDRESS 1FF0h
ACTIVE FLAG
IRQ/FT
AI01677B
11/18
M48T559Y
Figure Back-up Mode Alarm Waveform
tREC VPFD (max) VPFD (min)
Interrupt Register
Flags Register
IRQ/FT HIGH-Z HIGH-Z
AI01678C
WATCHDOG TIMER watchdog timer used detect outof-control microprocessor. user programs watchdog timer setting desired amount time-out into eight Watchdog Register (Address 1FF7h). five bits (BMB4-BMB0) store binary multiplier lower order bits (RB1RB0) select resolution, where 1/16 second, second, second, seconds. amount time-out then determined multiplication five multiplier value with resolution. (For example: writing 00001110 Watchdog Register seconds). Note: Accuracy timer within selected resolution. processor does reset timer within specified period, M48T559Y sets (Watchdog Flag) generates watchdog interrupt microprocessor reset. reset reading Flags Register (Address 1FF0h). most significant Watchdog Register Watchdog Steering Bit. When '0', watchdog will activate IRQ/FT when timedout. When '1', watchdog will output negative pulse duration 40ms 200ms. Watchdog register will reset watchdog time-out when '1'.
12/18
watchdog timer reset methods: transition (high-to-low low-to-high) applied Watchdog input (WDI) microprocessor perform write Watchdog Register. time-out period then starts over contains pull-up resistor therefore left unconnected used. watchdog timer will reset each transition (edge) seen pin. order perform software reset Watchdog timer, original time-out period written into Watchdog Register, effectively restarting count-down cycle. Should watchdog timer time-out, programmed output interrupt, value needs written Watchdog Register order clear IRQ/FT pin. This will also disable watchdog function until again programmed correctly. read Flags Register will reset Watchdog Flag (D7; Register MSB15). watchdog function automatically disabled upon power-down Watchdog Register cleared. watchdog function output IRQ/FT frequency test function activated, watchdog alarm function prevails frequency test function denied.
M48T559Y
Figure Reset Timing Waveform
RSTIN1
RSTIN2 Hi-Z tR1HRZ tR2HRZ
AI01679
Hi-Z
Table Reset Characteristics 70°C; 4.5V 5.5V)
Symbol tR1HRZ tR2HRZ RSTIN1 RSTIN2 RSTIN1 High Hi-Z RSTIN2 High Hi-Z Parameter Unit
BATTERY WARNING M48T559Y checks battery voltage power-up. (Battery Low) 1FF0h) will power-up battery voltage less than 2.5V (typical). POWER-ON DEFAULTS Upon application power device, following register bits state: WDS; BMB0-BMB4; RB0-RB1; AFE; ABE; POWER SUPPLY DECOUPLING UNDERSHOOT PROTECTION transients, including those produced output switching, produce voltage fluctuations, resulting spikes bus. These transients reduced capacitors used store energy, which stabilizes bus. energy stored bypass capacitors will released going spikes generated energy will absorbed when overshoots occur. ceramic bypass capacitor value 0.1µF shown Figure recommended order provide needed filtering. addition transients that caused normal SRAM operation, power cycling generate neg-
ative voltage spikes that drive values below much Volt. These negative spikes cause data corruption SRAM while battery backup mode. protect from these voltage spikes, recommended connect schottky diode from (cathode connected VCC, anode VSS). Schottky diode 1N5817 recommended through hole MBRS120T3 recommended surface mount. Figure Supply Voltage Protection
0.1µF
DEVICE
AI02169
13/18
M48T559Y
Table Ordering Information Scheme
Example: Device Type M48T Supply Voltage Write Protect Voltage 559Y 4.5V 5.5V; VPFD 4.2V 4.5V Package SOH28 Temperature Range Shipping Method SOIC blank Tubes Tape Reel M48T559Y
Note: SOIC package (SOH28) requires battery/crystal package (SNAPHAT) which ordered separately under part number "M48T28-BR12SH1" plastic tube "M4T28-BR12SH1TR" Tape Reel form. Caution: place SNAPHAT battery/crystal package "M4T28-BR12SH1" conductive foam since will drain lithium button-cell battery.
list available options (Speed, Package, etc.) further information aspect this device, please contact Sales Office nearest you.
Table Revision History
Date June 1998 First Issue Description Paragraph changed Setting Alarm Clock paragraph changed M4T28-BR12SH SNAPHAT Housing 48mAh Battery Crystal Package added (Table Power Down/Up Mode Waveforms changed (Figure Back-up Mode Alarm Waveforms changed (Figure Revision Detail
02/07/00
14/18
M48T559Y
Table SOH28 lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Mechanical Data
Symb 1.27 0.05 2.34 0.36 0.15 17.71 8.23 3.20 11.51 0.41 0.10 3.05 0.36 2.69 0.51 0.32 18.49 8.89 3.61 12.70 1.27 0.050 0.002 0.092 0.014 0.006 0.697 0.324 0.126 0.453 0.016 0.004 0.120 0.014 0.106 0.020 0.012 0.728 0.350 0.142 0.500 0.050 inche
Figure SOH28 lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline
SOH-A
Drawing scale.
15/18
M48T559Y
Table M4T28-BR12SH SNAPHAT Housing 48mAh Battery Crystal, Package Mechanical Data
Symb 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 0.612 0.126 0.080 0.265 0.255 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090 inche
Figure M4T28-BR12SH SNAPHAT Housing 48mAh Battery Crystal, Package Outline
SHTK-A
Drawing scale.
16/18
M48T559Y
Table M4T28-BR12SH SNAPHAT Housing 120mAh Battery Crystal, Package Mechanical Data
Symb 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 0.415 0.335 0.315 0.015 0.022 0.860 0.710 0.628 0.142 0.090 inche
Figure M4T28-BR12SH SNAPHAT Housing 120mAh Battery Crystal, Package Outline
SHTK-A
Drawing scale.
17/18
M48T559Y
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics 1998 STMicroelectronics Rights Reserved other names property their respective owners. STMicroelectronics GROUP COMPANIES Australia Brazil China Finland France Germany Hong Kong India Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom U.S.A http://w ww.st.com
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