PORTS 8-Bit CORE Accu Index Index Program Data bytes Data EEprom
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INTRODUCTION CORE ADRESSING MODES PERIPHERALS SOFTWARE TOOLS HARDWARE TOOLS STVD7
PORTS
8-Bit CORE Accu Index Index Program Data bytes Data EEprom
PORT 16-bit timer Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
Optional features:
converter 16-bit Timer 8-bit Auto Reload Timer EEPROM Programmable OpAmp
Interrupt Controller Test/Vpp Reset Oscillator Power Supply
Watchdog Timer
Optional
That show block diagram ST7, have seen core, memory, power supply/reset watchdog block which present ST7. There also least timer ports input ouput electrical signals. difference maily memory size peripherals. Find listed peripherals described this presentation.
PORTS
Overview
I/Os individually software configurable using different registers:
DDR: Data Direction Register Data Register Option Register
ST72254: multifunction bidirectional lines
Standard I/Os (sink 5mA) High Current I/Os (PA0-PA7 sink 20mA) Analog Inputs (PC0-PC5) alternate Functions pins (for Timers, I2C) I/Os set-up Interrupt inputs
Most port made PINS. PA0,.PA7) Each registers made PADR[0:7]), each these registers linked dedicated PA0.PA7). driven port register (DDR,OR peripheral, last case used port alternate porpertie.
Safe transition
PORT
Mode Floating input Input pull- with/without interrupt Output Open-Drain Output Push-Pull
Reset State
When correspondig INPUT mode When corresponding OUTPUT mode. reset state most cases, DDR,OR (0,0) that floating input (without pull-up pull-down) switch from reset state ouput push-pull, recommended first bits then bits that case, input with interrupt avoided. Transitions including this state generate spurius interrupts.
PORT Basic structure
Read Write DDRi
Data Direction Register
Write
Latch Data Output Input
Ouput
Read Input
Software selectable configuration HIGH FLEXIBILITY software board layout
When data direction register (the ouput), read action data register return data previously written electrical level applied pin. When data direction register reset (the input), read action data register return electrical value applied whatever value loaded latch data Ouput
Settings electrical behaviour Configuration given when external Hardware connected pins
Input Floating Written Read
Floating Floating
PORT
Input Pull_up
Ouput Open Drain
Floating
Ouput Push-Pull
This table gives logical electrical levels present according configuration. represent logical logical assume that external connected floating state also called High Impedance state connection VSS).
EXTERNAL INTERRUPTS
Edge/level selection Edge/level selection Interrupt generation Interrupt source Negative edge only Positive edge only Negative edge level Positive Negative edge Latched Latched Latched Latched Interrupt Source Interrupt Controller Interrupt Source
Miscellaneous Register
Several >I/O pins with interrupt capability linked same interrupt vector. signals issued from several pins configured Input with interrupt belonging same vector logically ANDED befor entering edge/level selection block. This block able generate interrupt request according several stimulus, configuration done through Miscellaneous register, could Negative edge Positive edge Negative edge loww level Both negative positive edge. signals ANDED, level applied (configured input with interrupt) masked events occuring other pins also cofigured input with interrupt) belonging same interrupt vector
PORT Block Diagram
OUTPUT STAGE
INPUT STAGE
block diagram show that input stage output stage pin. input stage: analog signal directly send from pin. logical send alternate input through Cmos schmitt trigger input with interrupt onfiguration set, input signals send polarity selection block trough gate. clamping diode connected manage current injection. output stage: bits combination between control directly buffer. also controlled alternate enable command, buffer controlled Alternate Output value Whatever values. Alternate enable Alternate Ouput signals come from peripherals.
PROGRAMMING TIPS
Port
convertion
Each used cell must configured floating input (i.e. without pull-up resistors) before activating analog input mode
Alternate function
signal coming from on-chip peripheral output port. this case, automatically configured output mode. signal coming from input on-chip peripheral. this case, must configured Input without interrupt (Floating Input).
PROGRAMMING TIPS
Port
Open Drain Outputs used driving where several devices connected same line. They wired together increase current drive capability Voltages driving Analog Input should always stay within absolute maximum ratings (Vss-0.3V Vdd+0.3V) Pull-up resistors typically deliver 50µA under toggling time output will approximately 30ns 50pF load
First Bullet: typically case connections.
Ports Configuration Example
Fill dedicated port registers order have following configuration: PB0:PB2
Push-Pull Output (high level)
PBDR7
PBDRO
PBDR
PBDDR7 PBDDRO
PB3,PB4
Floating Input
Input with Interrupt
PBDDR
PBOR7 PBORO
Push-Pull Output (low level)
Ouput (High Impedance)
PBOR
EEPROM Data
8-Bit CORE Accu Index Index Program Data bytes Data EEprom
PORT 16-bit timer Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
Optional features:
converter 16-bit Timer 8-bit Auto Reload Timer EEPROM Programmable OpAmp
Interrupt Controller Test/Vpp Reset Oscillator Power Supply
Watchdog Timer
Optional
Data EEPROM contains bytes. This memory type used sore volatile data (variable able keep their value even after power off).
EEPROM
Overview
Eeprom feature:
Used store volatile data multi-cycle read access, EEPROM cannot execute code
parallel writing allows program bytes
Write cycle Write Erase cycles cycles Data retention years
bytes belonging same programmed 8ms. guarantees programming cycles byte.
EEPROM Block Diagram
INTERRUPT REQUEST
FALLING EDGE DETECTOR
HIGH VOLTAGE PUMP
EEPCR RESERVED E2ITE E2LAT E2PGM DECODER
EEPROM MEMORY MATRIX BITS
ADDRESS
ADDRESS DECODER
16*8 BITS DATA LATCHES
E2ITE disabled enabled E2LAT read mode write mode E2PGM prog finished started start programming
DATA MULTIPLEXER
BUFFER DATA
EEPROM memory matrix made rows (each made bytes). cell built around byte latch, first byte copied latch (using lSbit their address) Then selected (using Msbit last write access latch) previously written byte loaded from latch EEPROM memory matrix. Interrupt generated programming cycle (according value E2ITE conrol register) bits E2L1T E2PGM operation EEPROM cell.
EEPROM Programming Cycle
Read operation possible INTERNAL PROGRAMMING VOLTAGE
Write data latches
Read operation allowed
Erase cycle
Write cycle
Tprog
E2LAT
E2PGM
INTERRUPT REQUEST
Interrupt vector fetch
read access EEPROM location allowed till E2LAT reset. Once set, read access more allowed write access will updated byte latch. When E2PGM programming cycle starts, first erase cycle then write cycles. erase write cycles only bytes updated bytes latch. programming cycle, bits E2LAT E2PGM reset interrupt request generated E2ITE generated. interrupt request reset soon EE2PROM interrupt vector fetched (loaded PC).
PROGRAMMING TIPS
EEPROM
write done programming e2prom control register:
Step E2LAT order select write mode Step write bytes with MSBit common Step E2PGM start programming cycle Step wait E2LAT reset programming cycle
read performed read only memory: software overhead required halt instruction reset immediatly stop eeprom operation. wait mode effect
Programming mode read memory location, ELAT must cleared program EEPROM:
BSET with EEPCR, #E2LAT VARIABLE_i, ELAT Write locations same address
EEPROM
BSET EEPCR, #E2ITE Enable interrupts needed BSET EEPCR, #E2PGM Start programming .wait BTJT EEPCR, #E2PGM, wait Wait write cycle
16-bit TIMER
8-Bit CORE Accu Index Index Program Data bytes Data EEprom
PORT 16-bit timer Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
Optional features:
converter 16-bit Timer 8-bit Auto Reload Timer EEPROM Programmable OpAmp
Interrupt Controlle Test/Vpp Reset Oscillator Power Supply
Watchdog Timer
Optional
timer implemented except light familly. most common timer. also oldest.
16-bit TIMER
Overview
16-bit free running counter driven software configurable prescaler different modes:
Input capture pins): latch value counter after transition ICAPi Output compares pins): control output waveform indicate when period time over pulse: generation pulse when external event occurs PWM: generation signal with frequency pulse length software (OCR1 OCR2)
Free running means timer starts counting just after reset phase never stoped. configurable prescaler used timer frequency. OCR1 OCR2 means output compare
16-bit TIMER
Overview
timer clock provided
internal clock with configurable ratio external source: Fext must times slower than internal clock Fmax=2Mhz)
Timer clock Fcpu/4 Fcpu/2 Fcpu/8 External
When timer used, timer frequency must set. timer frequency could synchronous division frequency external clock. with freq 8MHz CC1:CC0 timer frequency will Mhz, Timer tick 1µsec.
16-bit TIMER
Block diagram
INTERNAL
MCU-PERIPHERAL INTERFACE HIGH BYTE HIGH BYTE HIGH BYTE HIGH BYTE BYTE BYTE BYTE BYTE CLOCK 8-BIT BUFFER BYTE
EXEDG
EXCLK
16-BIT FREE RUNNING COUNTER COUNTER ALTERNATE REGISTER
OUTPUT COMPARE REGISTER
OUTPUT COMPARE REGISTER
INPUT CAPTURE REGISTER
INPUT CAPTURE REGISTER
16-Bit INTERNAL TIMER OUTPUT COMPARE CIRCUIT
EDGE DETECT CIRCUIT EDGE DETECT CIRCUIT LATCH
ICAP
OVERFLOW DETECT CIRCUIT
ICAP2
OCMP
STATUS REGISTER
ICF2
OCF2
LATCH
OCMP2
ICIE
OCIE
TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL2
OC1E OC2E
IEDG2 EXEDG
CONTROL REGISTER
CONTROL REGISTER
TIMER INTERNAL INTERRUPT
When timer used, timer frequency must set. timer frequency could synchronous division frequency external clock. with freq 8MHz CC1:CC0 timer frequency will Mhz, Timer tick 1µsec.
Input capture Captures counter value upon input signal edge detection Allows external pulse length measurement Internal safety process case critical interrupts timing
16-bit TIMER
Timer Counter Register
ICAP1A
Edge Detector
Input Capture Register Software Maskable Interrupt Request
purpose input capture assign external event, internal timing value. edge sensitivity selectable. input capture process inhibited when byte input capture read until read. This internal propertie allow keep safe value during input capture register read (done steps) event occurs between time read read, input capture registers modified capture taken into account.
Input capture
16-bit TIMER
This diagramm show 16-bit timer ressources used input capture timer freq selected trough CC0, edge sensitvity selected through IEDG1 ICAP1 IEDG2 ICAP2 falling edge, rising edege). that works When event occurs (lets take example ICAP1), content free running counter automatically loaded input capture register flag ICF1 generate interrupt ICIE also set. clear ICF1 have perform software sequence, read status register (BTJT BTJF instructions performed read acces). read byte IC1R. ICIE means input Capture Interrupt Enable. This bits allows interrupt generation both input capture description, alternate input directly connected peripheral. That means ICAP1 ICAP2 used output registers, every toglling that pins activate input capture process. only disable input read corresponding high byte
Ouput compare Event generation (Interrupt request/bit toggling) whenever compare register matches counter Indicates period time elapsed controls output waveform Internal safety process case critical interrupts timing
16-bit TIMER
Timer Counter Register Match? Output Compare Register Software Maskable Interrupt Request Pulse generation
outpout compare system able generate kind events when timer matches output comprare register content: internal event: flag interrupt generated. external event: OCMP take defined value. internal safety procces activate soon write Output compare register until write output compare register LSB. During that time output compare function inhibited. transition value (new MSB, generate matching).
Output compare
16-bit TIMER
This diagramm show 16-bit timer ressources used input capture freee running counter clock driven CC0-CC1 bits control register. that works When free running matches value located OC1R (for ex), OCF1 flag set, interrupt request generated ICIE set, ICIE means Input Capture Interrupt Enable. same time logical level OLVL1 applied OCMP1 OC1E (Output Compare Alternate Enable) set. clear OCF1 flag sequence need performed: read status register (BTJT BTJF instructions performed read acces). Read write byte OC1R register. timer free running counter wich rolls over FFFF 0000 automatically, flag able time, only disable function write byte Output Compare register without writting High byte.
Real Time Clock each Interrupt Routine Register content updated. There shift time (the counter never reset externally).
FREE RUNNING COUNTER VALUE
16-bit TIMER
FFFFh
OCR+T
0000h
Timer
Timer
time
built themost precise real time clock. timer without reseting (the only value that user load tiler reset value (FFFC). When timer reach OC1R value, interrupt generated. Inside interrupt user Time variables updated OC1R register reloaded with vallue. This value added time increment.
pulse mode Generation pulse synchronized with external event Allows Phase Locked Loop Generation Input Capture event
counter reset timer output toggled
16-bit TIMER
Output compare event
timer output toggled timer waits next Input Capture event
Pulse Mode uses whole Output compare ressources (register pin, flags), input capture (pin, flags) OLVL2 belonging ressources. pulse width software, external event could rising edge falling edge.
pulse mode
16-bit TIMER
When external event occurs ICAP1
Free running counter initialized FFFCh
OLVL2 level applied OCMP1 When free running counter reaches OC1R register value
OLVL1 level applied OCMP1
first state when micro waits external event detection. counter rest automatically value FFFC ICF1 level applied OCMP1 H/W. When Pulse Mode selected different registers correctly set, pulse generation done automatically without load.
pulse mode
FREE RUNNING COUNTER VALUE FFFFh FFFCh
16-bit TIMER
Compare 0000h time
ICAPInput Capture Timer input
time
OCMPOuput Compare Timer output
time
diag shows pulse mode synchronized rising edge ICAP1. When event occurs timer rest FFFC OCMP1 take OLVL2 value When timer reach compare1 value OCMP1 take OLVL1 value this OLVL1=0 OLVL2
16-bit TIMER
mode
Automatic generation Pulse Width Modulated signal Period &pulse lenght software:
first Output Compare Register OC1R contains length pulse second Output Compare Register OCR2 contains period pulse
Resolution steps (fCPU MHz): accuracy duty cycle
Pulse Mode uses whole Output compare ressources (register pin, flags) Output Compare2 (register pin, flags) input capture (flags).
mode
TIMER
When free running counter reaches OC2R register value
Free running counter initialized FFFCh
OLVL2 level applied OCMP1 ICF1
When free running counter reaches OC1R register value
OLVL1 level applied OCMP1
mode usses same mechanism than pulse mode: external event replaced maching OC2R free running counter. These events generate same actions than pulse mode one.
mode
FREE RUNNING COUNTER VALUE
TIMER
Tmax Ttimer 65535
FFFFh FFFCh
Compare Compare 0000h
time
OCMPOuput Compare Timer output
time
OLVL1 OLVL2 must different order have signal OCMP1 pin, forget also OC1E (this Ouput Compare alternate Enable pin).
PROGRAMMING TIPS
16-bit timer
Define Input capture pins inputs through corresponding Data Direction Register Read first then
counter buffered during read counter read accesses buffered value access high byte disables corresponding timer function until byte accessed Disable interrupts during word access
Writing counter resets timer FFFCh
Last Bullet: write acces valide TACLR, TACLR,
PROGRAMMING TIPS 16-bit timer
Clearing status performed read access status register followed access (read write) byte corresponding register alternate counter register always matching counter alternate counter register when want clear Timer Overflow Flag interrupt generated compare when active, ICF1 every period generates interrupt aware that implicit reading performed emulator might clear status flags
Last Bullet: emulator based real silicon read access peripheral registers intrusive. STVD7 takes care that.
PROGRAMMING TIPS
16-bit timer
Read
ACHR
buffered ACLR buffered
others Instructions
Read
ACLR ACLR
Returns buffered value Clear Returns ACLR buffered value Reset counter FFFCh Clear Reset counter FFFCh
Write
Timer Configuration Example
ICIE
OCIE
TOIE
FOLVL2
FOLVL1 OLVL2 IEDG
OLVL
TACROC1E OC2E IEDG2 EXED
TACR2
Fill Timer registers order generate real time clock using interrupt strategy timer clock (fCPU 8MHz).
interrupt generated every using Output compare1. OCMP1 toggled every period
What value TAOC1HR TAOC1LR every period?
8-bit Auto Reload Timer
Optional features:
converter 16-bit Timer 8-bit Auto Reload Timer EEPROM Programmable OpAmp
8-Bit CORE Accu Index Index Program Data bytes Data EEprom
PORT 16-bit timer Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
Interrupt Controller Test/Vpp Reset Oscillator Power Supply
Watchdog Timer
Optional
8-bit ARTimer Programmable Timer frequency (Fcounter) External Clock counter event capability independant signals (same frequency) Output compare timebase Interrupts Input capture Channels with Interrupts Timer implemented ST72171, ST72511R, ST72311R
Overview
This timeris auto reload timer. When counter reach rolls over value located registers.
Fcounter definition Finput could Fcpu Fext. Fext Fcpu/2. Counter incremented rising edge Finput. Fcounter division Finput, acccording prescaler driven CC2-CC0 bits Control Register.
Fcounter Finput Finput Finput Finput Finput Finput Finput Finput /128 Finput= 8MHz 8MHz 4MHz 2MHz 1MHz 500KHz 250KHz 125KHZ 62.5KHZ
8-bit ARTimer
wide range prescaler allow timer ticks from 125ns 16µs.
Autoreload Ouputs
set, Interrupt generation
8-bit ARTimer
Counter value
DCRx Duty Cycle Register
Auto Reload Register
PWMx Output
bit=1 bit=
Time
Time DCRx Value ARR-1 PWMx (OPx=1) Level 1pulse Tcounter High Level
Double buffering changes both DCRX taken into account only when counter overflow. Resolution 1/(256-ARR) autoreload register contains value that load timer after overflow Duty Cycle Register (DCR) value must between value
8-bit ARTimer
Input Capture
Interrupt generation CIEx Fcounter Counter Register ARTICx Input Capture ICRx Input Capture Register
bit=
This slide describes input capture examples: conter changes rising edge Fcounter. value Input capture sampled evry falling edge Fcounter. event occurs (rising edge this example), Input capture reister loaded with Counter value next falling edge Fcounter, this also flag that able generate interrupt.
Programming Tips Clearing OVF(Overflow) performed reading register. Clearing (Capture Flag performed reading ICRx register. HALT mode, Input capture Interrupt used wake ST7. HALT mode, Overflow Interrupt used wake ST7, external clock (Fext) used. (external event detector mode). aware that implicit reading performed emulator might clear status flags.
8-bit ARTimer
Serial Peripheral Interface
Optional features:
converter 16-bit Timer 8-bit Auto Reload Timer EEPROM Programmable OpAmp
8-Bit CORE Accu Index Index
PORT 16-bit timer Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
Program Interrupt Controller Test/Vpp Reset Oscillator Power Supply Watchdog Timer Data bytes Data EEprom
Optional
stand Serial Peripheral Interface
Overview
cell allows full duplex synchronous serial communication between devices Main feature:
Full duplex, wire synchronous transfers Master: frequency available. rates Slave mode: rates
clock programmable: polarity phase Different status flag:
Data transfer: data transfer completed Write collision: access SPIDR during transmission Fault flag: fault master mode detected
very fast protocol, Used implemement communication betwen microcontrolers more connecte external memory ST7. (see 970)
Master-Slave communication
Master
8-bit Shift Register MISO MISO
Slave
8-bit Shift Register
MOSI
MOSI
Clock Generator
This shows tipycal connection between master slave. clock alwys send master slave. only master Clock configuration). based shift registers that ouput bytes first. MOSI (Master Slave must connected together pins MISO (Master Slave Out) must also conneted together. When byte been loaded shift register master, communication starts count clock later contents shift register have been inverted. external condition used specify master (5V) tyhe slave (0V) mode.This condition also done internally S/W) order save I/O.
Block diagram
SPIDR
SPISR
MISCR2
SPICR
This slides show organized Cell. Data register made 8-bit shift register 8bit read buffer. When read acces performed SPIDR value located 8bit read buffer returned. When write acces performed SPIDR shift register updated transfert starts case master mode. SPICR controls clock speed also clock polarity (level after transfert) cock phase (sampling time even edges).It contains some bits anable interrupt (SPIE) enable Cell pins (SPE) allows interrupt (SPIE). SPISR contains flags: SPIF each transfer. user want pin, able bits MISCR2 registers Future flash devices this bits will included SPISR regsiter.
Single master configuration
MOSI MISO
MOSI
MOSI MISO
MISO
MOSI MISO
This slides show organized Cell. Data register made 8-bit shift register 8bit read buffer. When read acces performed SPIDR value located 8bit read buffer returned. When write acces performed SPIDR shift register updated transfert starts case master mode. SPICR controls clock speed also clock polarity (level after transfert) cock phase (sampling time even edges).It contains some bits anable interrupt (SPIE) enable Cell pins (SPE) allows interrupt (SPIE). SPISR contains flags: SPIF each transfer. user want pin, able bits MISCR2 registers Future flash devices this bits will included SPISR regsiter.
MOSI MISO
Configuration Example
SPIE
SPR2
MSTR
CPOL
CPHA
SPRO
SPICR
Fill SPICR register order configure cell
Master mode Serial clock 5OOKHz (fCPU=8MHz) Sampling edge High level after clock signal interrupt generation
8-Bit CORE Accu Index Index Program Data bytes Data EEprom
PORT 16-bit timer Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
Optional features:
converter 16-bit Timer 8-bit Auto Reload Timer EEPROM Programmable OpAmp
Interrupt Controller Test/Vpp Reset Oscillator Power Supply
Watchdog Timer
Optional
UART
Overview Full duplex, asynchronous communication Dual baud rate generator (maximum speed 250kHz)
Fcpu Fcpu
Programmable word length
bits bits bits data plus parity bit)
Noise, overrun frame error detection
mainly establish communication between several devices betwen serial port (RS232 protocol). 969. Fuuln duplex: means emision reception same time. Asynchronous: clock send line, ecah devices have clock running same frequency. Security bits test integrity frame.
Overview FLAGS
Buffer full Transmit buffer empty transmission
Muting functions multiprocessor configurations Receiver wake function most significant idle line Interrupt sources with flags
Flags indicates frame ongoing reception transmission cell placed mute mode: enable receive frames, when example frame dedicated device. cell ouput mute mode methods (the value most significant idle line).
Serial data format
Previous frame idle line
data
Following frame idle line Optionnal parity
Start
Stop
Each frame starts start (Low level) ends stop (High level)? data byte send between start stop significant byte first. IDLE line high level, also pending state.
Sampling Data Format
Time
Data Sampled values
Received value
Flag
Sampling Time
Each time
Divided clock Sampled times 8th, 10th count clock
flag sampling equal reception still available
Each time divided external level sampled times: count clock, samples have same value thereis problem this value placed corresponding shift register. samples have same value noise eflag receive value will place shift register receive byte could accepted user.
Block Diagram
Data Register
Transmit data register
Receive data register
Transmit shift register
Receive shift register
Transmit rate Control Transmit Control Wake-Up Unit Receive Control
Receive rate Control
Control register
Status Register
fcpu
Control Register Interrupt Control
connected through pins (TDO (Transmit Data Output) (Receive Data Input). data register made transmit register (one buffer shift register) start transmission user write data register. first time shift register empty byte goes directly transmission starts. flag indicate that buffer free byte frame will placed buffer. When transmission byte ended goes directly transmit register transmission byte starts. flag indicate that buffer free byte loaded waiting ened byte transmit. receive part data register also made shift register buffer. When byte completely received goes automatically buffer read, other byte loaded buffer while flag indicated that byte been received cleared.
Clock selection
order reach industry standard baud rate, extended baud rate prescaler been added. This extended prescaler used when clock division 8MHz.
Configurable Baud Rate
SCT2:SCT0 SCR2:SCR0
SCP1,SCP0
ETPR /ERPR
Baud Rate
1200 2400 4800 9600 10400 19000 38000
Values given fCPU =8MHz selected SCP1& SCP0 bits SCIBRR Register selected SCT2,SCT1 SCT0 bits SCIBRR Register selected SCR2,SCR1 SCR0 bits SCIBRR Register Reach industry standard requirement
table shows baud rates that reach using baud rates their configuration bits.
Configuration Example
WAKE
SCICRTIE TCIE ILIE
SCICR2
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
SCIBRR
Fill registers order configure cell
word reception 9600 Bauds word transmission 1200 Bauds Interrupt generation when RDRF (reception flag)
fCPU 8MHz
8-Bit CORE Accu Index Index Program Data bytes Data EEprom
PORT 16-bit timer Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
Optional features:
converter 16-bit Timer 8-bit Auto Reload Timer EEPROM Programmable OpAmp
Interrupt Controller Test/Vpp Reset Oscillator Power Supply
Watchdog Timer
Optional
protocol been developed Philip, oftenly used limited number connections safety.
Overview
cell provides specific sequencing, protocol, arbitration timing order reduce much possible software overhead Polling Management Interrupt Driven Cell Main feature:
Multi Master capability Interrupt generation Standard mode 100kHz) Fast mode 400kHz) 7-bit 10-bit addressing
Multi master means that cell able connected network where several devices master. support that able arbitration line, only master talk time. Each devices connected address, this addres bits bits.
Protocol
based wires. This Wires bidirectionnal (input output) based open drain system. When generated line, will seen devices. will seen only applied. Every fram starts sart condition ends Stop condition. Each byte transfered count clock line first data from emmitter recepter, last thie acknoledge from receiver emmitter).
Transfer Sequencing
Master Mode
7-bit Master Transmitter
Address DATA1 DATA2 DATA
7-bit Master Receiver
Address DATA1 DATA2 DATA
EV5: EVF=1, SB=1, cleared reading register followed writing register. EV6: EVF=1, cleared reading register followed writing register (for example PE=1). EV7: EVF=1, BTF=1, cleared reading register followed reading register. EV8: EVF=1, BTF=1, cleared reading register followed writing register.
Send master Send slave
Find example frames: After Start condition master send address device wants talk with. Then devices recognize address acknoledge that. Then master send datas slaves acknoledge till stop condition. master receiver configuration. After starts condition master send address {slave +1}. slave addressis coded dedicated emitter receiver configuration. Then slave recognize address+1 acknoledges. Then slaves send datas master acknoledges till ackonledge stop condition. these events toset flags order synchronize frame.
Transfer Sequencing
Slave Mode
7-bit Slave Receiver
Address DATA1 DATA2 DATA
7-bit Slave Transmitter
Address DATA1 DATA2 DATA
EV1: EVF=1, ADSL=1, cleared reading register. EV2: EVF=1, BTF=1, cleared reading register followed reading register. EV3: EVF=1, BTF=1, cleared reading register followed writing register. EV4: EVF=1, STOPF=1, cleared reading register.
Send master Send slave
That shown same thing than previous slides from slave point view. that case fram events does same flags.
Clock Control
CLOCK CONTROL REGISTER (CCR)
FM/SM
FM/SM :Fast standard mode Standard mode Fast mode CC6-CC0 7bit clock divider
Standard Mode
Fast Mode
Fscl
Fcpu (2x[CC6.CC0]+2)
Fscl=
Fcpu (3x[CC6.CC0]+2)
clock speed (only master) using register. different formula used calculate clock rate according standard fast mode have been selected.
Block Diagram
DATA REGISTER (DR)
DATA CONTROL
DATA SHIFT REGISTER
COMPARATOR
ADDRESS REGISTER (OAR1) ADDRESS REGISTER (OAR2)
CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR) STATUS REGISTER (SR1) STATUS REGISTER (SR2)
CONTROL LOGIC
INTERRUPT
line connected data control (checking arbitration) shift register data register. There address register, after start condition first received data compared value registers.
Software Programable Gain Amplifier
8-Bit CORE Accu Index Index Program Data bytes Data EEprom
SPGA
PORT 16-bit timer Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
Optional features:
converter 16-bit Timer 8-bit Auto Reload Timer EEPROM Programmable OpAmp
Interrupt Controller Test/Vpp Reset Oscillator Power Supply
Watchdog Timer
Optional
Software Programable Gain Amplifier OVERVIEW Integrated RAIL RAIL OpAmp Internal programmable Gain Integrated reference voltage sources, dependent independent (Band-Gap). OpAmp Outputs internally connected input Interupt flag comparator mode Power on/off active power modes capability with PWM/ART output
ST72C171, SPGA (Software Programmable Gain Amplifier) embedded. Gain from Advantage Integration: Prog gain Direct links resistive output connected SPGA input
Block Diagram SPGANS1[2:0] bits OA1NIN AGND
R=2K
SPGA
Programmable gain Op-Amp
G1[2:0] bits
/16R
VR1E, PS1[1:0] bits OA1PIN
R3=2K
Channel
OA1O
VR1[2:0] bits
Band Reference Voltage
(1.2V)
8-Step Reference Voltage
OA1V
OA1IE
Interrupt
Reference voltages: *1.2V, independant steps, dependant
Analog (Amplifier digital (Comparator) output
lood feedback resistive network used SPGA gain. Every OpAmp inputs connected multiplexor, that allow have several configuration software. Positive input multiplexor send references voltage. OpAmp output isend directly input analog pin. external loop feedback also implemented.
SPGA MODES
NS1[2:0] bits
OA1NIN
AGND R=2K VR1E, PS1[1:0] bits
G1[2:0] bits
Programmable gain Value
AVCL
Channel
Inverter Inverter
OA1PIN
R3=2K VR1[2:0] bits
OA1O
OA1V OA1IE
Band Reference Voltage (1.2V)
8-Step Reference
Voltage
Interrupt
NS1[2:0] bits
OA1NIN
AGND R=2K VR1E, PS1[1:0] bits
G1[2:0] bits /16R
AVCL
Channel
OA1PIN
R3=2K VR1[2:0] bits
OA1O
OA1V OA1IE
Band Reference Voltage (1.2V)
8-Step Reference Voltage
Interrupt
inverter modes input signal connected OA1NIN (non inverting input) reference selected thank Positive input selector. Non-Inverter mode input signal connectede Positive input Negative input connected ground (internally). There gain selected software because easily configure SPGA follower mode.
OPAMP MODES
Comparator mode
NS1[2:0] bits OA1NIN AGND /16R R=2K VR1E, PS1[1:0] bits OA1PIN R3=2K OA1O Band Reference Voltage (1.2V) VR1[2:0] bits 8-Step Reference Voltage OA1IE G1[2:0] bits
Channel
selectables positive input
Interrupt
comparator mode interrupt request active when output equal value control register. Most time selectable positive input used reference (thank divider).
SPGA MODES
NS1[2:0] bits OA1NIN AGND R=2K PWM0R OA1PIN VR1E, PS1[1:0] bits R3=2K VR1[2:0] bits DDA/8 8-Step Reference Voltage G1[2:0] bits /16R AVCL=1
Channel Analog output sink
OA1IE Interrupt
External Capacitor
Band Reference Voltage (1.2V) Internal Resistor
PWM0
Channel
8-bit PWM/ARTimer
Channel
8-Bit Digital Analog Converter
most interesting mode SPGA. Combined with ART/pwm timer output, SPGA output able DAC. signal issued from timer send through serila resistor, signal filtered capacitor connected OA1PIN. analog value connected SPGA input configured follower configuration. analog output value sink 40ma.
Op-Amps characteristics comparison
general purpose Rail Rail Consumption (mA) Output current (mA) Noise(nv*sqr(Hz)) Offset voltage (mV) Slow rate (v/us) Power supply range(v)
ST72C171 (I/O)
TS922 audio performance (I/O)
CONVERTER
8-Bit CORE Accu Index Index Program Data bytes Data EEprom
PORT 16-bit timer Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
Optional features:
converter 16-bit Timer 8-bit Auto Reload Timer EEPROM Programmable OpAmp
Interrupt Controller Test/Vpp Reset Oscillator Power Supply
Watchdog Timer
Optional
Microcontrollers have sometimes control analog process, used bridge between analog world (sensors, analog board) digital world. described this part 8bit ADC, also find brand (ST72521 ST72321)
CONVERTER
Overview
8-BIT successive approximations converter with analog channels:
ST72254: inputs ST72334 ST725xx: inputs ST72171: external inputs internal inputs
FEATURE:
Accuracy: Total Unajusted Error MAX: Conversion time: cycle full speed (8MHz)
FLAGS:
COCO: conversion (Status flag) ADON: on/off reduce power consumption)
internal inputs ST72171 OpAmp Outputs, connections done inside chip. This based sample hold. analog value sampled during half conversion time (the Hold capacitance loaded with analog value), then hold capacitance compared array capacitors using successive approximation methods.
CONVERTER
Overview
consumption modes
Wait mode doesn't affect Halt mode stops ADC.
HARDWARE
ST72334 ST725xx: Vdda Vssa must connected externally respectivelly through decoupling capacitors. ST72254: connection done internally
RATIONETRIC Functionnal Range
analog voltage input Vdd: converted result overflow indication) analog voltage input Vss: converted result underflow indication)
decoupling capacitors connected VDDA VSSA reduced digital noise induced micro application.
CONVERTER
Block diagram
analog Multiplexor driven Bits [CH2:CH0] Control status register. This selects which analog input will converted. Then analog signal send sample hold thevalue converted. conversion COCO result placed data register. interupt generation speed conversion (only cycles, compre cycles needed switch context case interrupts).
PROGRAMMING TIPS
Converter
PROCEDURE
Step analog input pins must set-up Input pull-up interrupt Step assign channel conversion (bit CH0, register) ADON Step Wait until COCO set. continuous conversion performed. reach best accuracy, impedance seen analog input must lower than 10Kohm.
ADON
Continuous
init config -Channel selected
Write CSR: Stop conversion ADON still conversion Else stop
Beginning conversion writing (select analog channel)
Configuration Example
COCO
ADON
ADCDR
Fill ADCCSR register order have analog conversion AIN4. What tested know conversion
Configuration Example
COCO
ADON
ADCDR
Fill ADCCSR register order have analog conversion AIN4. What tested know conversion
8-Bit CORE Accu Index Index Program Data bytes Data EEprom
PORT 16-bit timer Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
Optional features:
converter 16-bit Timer 8-bit Auto Reload Timer EEPROM Programmable OpAmp
Interrupt Controller Test/Vpp Reset Oscillator Power Supply
Watchdog Timer
Optional
High Networks
ENTERTAINMENT
AUDIO VIDEO speed 2.0B kbps
Radio Audio Power TVModule Car-Phone Navigation Video-Box
BODY
COMFORT ACCESS
POWER-TRAIN
TRACTION STABILITY
Door Module Door Module Trunk Module Cond DoomControl Contr. Pannel. Light Front
Door Module Door Module Driver-Seat
Dashboard Gateway
Sensor Gearbox
Pass.-Seat Backseat Central Airbag Light Rear Immobiliser
Very high speed 100M
DIAGNOSIS ISO9141 10kbps
Traction
High speed CAN2.0B kbps 1Mbps
Wiper Left UART Node Node
Wiper
High Lights
Asynchronous Serial Communication Protocol Based
Multi-master concept
CSMA/CA (Carrier Sense Multiple Access Collision Avoid) Message priority
Object oriented communication
node addressing, content identification
Realtime capability
message transfer latency
System wide message consistence
Error detection management mechanism
Topology
Sensor Actuator Signals Signals
Node Node Node
Controller differential voltage twisted wire Mbps
Transceiver
CANH
CANL
Standard Extended Frames
bits Arbitration Field Identifier Control Field
0.64 bits Data Field Data, bytes Field bits
bits Interframe space bits Idle
bits
IDE=0
delimiter slot
delimiter
2.0A (standard format: identifier)
bits Arbitration Field Identifier Identifier Data, bytes bits bits bits Control Field 0.64 bits Data Field Field bits Interframe space
IDE=
delimiter slot
delimiter
2.0B (extended format: identifier)
Standard Extended Implementations
Implementation Standard send receive Extended check acknowledge Extended send receive
2.0B Passive
2.0B Active
(destructive (destructive
(compliant)
2.0B passive active nodes cohabit same network
Characteristics
Wired-AND
Levels
Recessive Dominant
Dominant Prevail
node node node recessive dominant
Access Arbitration
Node Node Node Node
Arbitration Phase Remainder Transmit Request
Node Node Node recessive dominant
Error Detection Transmitter
Error
Based "write verify" principle each sent read back transmitter
values differ error detected Except during arbitration phase
Acknowledge Error
receiver considering frame correct acknowledge otherwise signal detected error with Error Frame transmitter missing acknowledge supposes only active node network
Error Detection Receiver
Error
transmitter
Stuff Error
More than identical bits detected
Error
received calculated values different
Form Error
fixed format bits correct
delimiter delimiter Frame
Fault Confinement
Reset configuration Error Active blocks successive recessive bits
Error Passive
Basic Full
Full controller
Many buffers (e.g. Sophisticated message filtering Dedicated Larger silicon (buffer size, filtering)
Basic controller
Tx/Rx buffers (e.g. Simple identifier filtering More overhead Less silicon
Typical: body
Typical: Engine management
Filters Possible Implementations
FULL
Buffer allocation static based message Messages copied (automatic reply capability) Interesting great number buffers
BASIC
Buffer allocation dynamic based avalaibility Messages must copied (more load)
Buffer
Match Filter
Buffer
Decreasing Priority
Buffer
Match Filter
Buffer
Buffer
Match Filters
Buffer
Cell Block Diagram
INTERNAL INTERFACE
Buffer Buffer Buffer Bytes Bytes Bytes
Filter Filter Bytes Bytes
PAGE CKDIV
BCDL
8-bit Shift Reg. CTRL
STAT
passive Engine
Features
Comply with 2.0B passive specification Speed: 1MBits/s Basic capability with:
prioritized object messages data bytes each) acceptance filters match don't care)
Flexibility Full baud rate timing control
Buffers useable transmit receive buffers
Other Features
Optimized buffer flip-flopping capability transmission
Real-time performance minimum load Deterministic transfers Solves inner priority inversion problem with extra hardware
power mode Extensive interrupt scheme
Separate signalling successful transfers errors maskable sources: Rx123, error, error, overrun
Buffer Pagination
Saves address space
registers mapped onto addresses
Interrupt Status Interrupt Control Control Status Baud Rate Prescaler Timing Page Selection
Allows more efficient addressing mode
memory indirection
PAGED PAGES REGS PAGED REGS REGISTERS PAGED REGS PAGED REGS DIAGNOSIS, MESSAGE BUFFERS, ACCEPTANCE FILTERS
Page Mapping
Page LAST
Page
Page
Page
Page FILTER
10-BYTE BUFFER RESERVED RESERVED
CTRL STATUS
10-BYTE BUFFER
10-BYTE BUFFER
FILTER
TEST REG.
ERROR COUNTERS
RESERVED
CTRL STATUS
RESERVED
CTRL STATUS
RESERVED
Buffer-dedicated Control Status Register (BCSR)
Reduces requirements reactiveness
Dual mapping interupt flags BCSR
same code handles buffer
Sleep Mode Wake
Software controlled power mode (RUN cleared)
Prescaler protocol engine stopped Need resynchronization
Automatic power mode after recessive bits
Protocol engine stopped need resynchronization (idle mode)
Wake-up upon reception dominant Possible wake pulse generation when leaving stand-by
Cell Certification
Validated with Bosch model patterns Certification going with expert third party (c&s)
Protocol compliance test according Bosch specifications interface test Cell robustness behaviour
Final silicon certification targeted 1Q99
ST725xx Kits
Development ST7MDT2-DVP2
Available User software development debugging Easy connection high speed node/network Compatible widespread Vector tools
Demonstration Board
Available Software functions controlled Visual
Visual
Intuitive discover exercice passive cell Existing network traffic monitoring messages generator function
VisualCAN Snapshot
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