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ST486DX4V

75, 100 & 120 MHz Clock Tripled 3.45 Volt 486 CPU

ST486DX4V
75, 100 & 120 MHz Clock Tripled 3.45 Volt 486 CPU
PRELIMINARY DATA
ON-CHIP 8-KBYTE WRITE-BACK CACHE - Industry-wide write-back chipset support - Burst-mode write capability - Configurable as write-back or write-through ADVANCED POWER MANAGEMENT - Fast SMI interrupt with separate memory space - Fully static design permits dynamic clock control - Software or hardware initiated low power suspend
De coder Control ROM Address S e que nce r Control Bra nch Control Limit Unit Microcode ROM Imme diate Imme diate
16-byte Instruction Que ue
- Automatic FPU power-down mode These processors are designed to meet the power management requirements in the newest generation of low-power desktops and notebooks. Power is saved by taking advantage of advanced power management features such as static circuitry, SMM, and automatic FPU power-down. Fast entry and exit of SMM allows frequent use of the SMM feature without noticeable performance degradation. This CPU family maintains compatibility with the installed base of x86 software and provides essential socket compatibility with the 486DX / DX2 / DX4
SUS P # Core Clock P refetch Da ta Bus 32 Bus Clock S MM, S us pe nd Mode a nd Clock Control S USP A# CLK S MI# S MADS#
Execution P ipeline
Exe cution Unit 3-Input S hift Re gister Multiplier Adde r File Unit Unit Unit Line a r Addres s Bus
Memory Da ta Bus
Byte Muxes &I / O Re gs
8 Write Buffers Data Buffers
D31-D0
Ca che a nd Me mory Mana ge me nt
Memory Mana ge ment Unit
P refetch Unit
8 KByte Instr / Data Ca che
Control
Bus Control
Control
Instruction Address Bus Da ta Addres s Bus
A31-A2 Addres s BE3#-BE0# Buffers 486DX Compa tible Bus Interface
October 1995
This is preliminary infor mationon a new product undergoing evaluation. Details are subject to change withou t not ice.
ST486DX4V
added to the 486 instruction set that permit software entry into SMM, as well as saving and restoring the total CPU state when in SMM mode. 1.5 Power Management The ST486DX4 power management features allow for a dramatic improvement in battery life over systems designed with non-static 486 processors. During suspend mode the typical current consumption is less than 1 percent of the full operation current. Suspend mode is entered by either a hardware or a software initiated action. Using the hardware method to initiate suspend mode involves a two-pin handshake between the SUSP# and SUSPA# signals. The software can initiate suspend mode through the execution of the HALT instruction. Once in suspend mode, the ST486DX4 power consumption is further reduced by stopping the external clock input. The resulting current draw is typically 450 µA. Since the ST486DX4 is static, no internal data is lost when the clock is stopped. 1.6 Signal Summary The ST486DX4 signal set includes ten cache interface signals, two coprocessor interface signals, two power management signals, two system management mode signals, one power supply voltage control signal and one clock multiplier control signal. Figure 1-1. ST486 DX4 Input & Output Signals.
ADS# 1 BE3#-BE0# BLAST# BREQ
ST486DX4 CPU
D31-D0 D / C# DP3-DP 0 FERR# HITM# HLDA LOCK#
M / IO# PCD PCHK# PLOCK# PWT RPLSET(1-0) RP LVAL# SMADS# S USPA# W / R# VOLDET
ST486DX4V
ST MODE SMI#: Bidirectional System management Interrupt pin. Asserted by the system logic to request an SMI interrupt. Sampled by the CPU on each rising clock edge. Causes I / O trap to occur if sampled asserted at least two clocks prior to RDY# sampled asserted for an I / O cycle. Asserted by the CPU during execution of an SMI service routine or in response to SMINT if SMAC is set. SMADS#: SMI Address Strobe output used to indicate that SMIACT#: SMI Active output asserted by the CPU during the current bus cycle is an SMM memory access. execution of an SMI service routine. SL-COMPATIBLE MODE SMI#: System Management Interrupt input pin. Asserted by the system logic to request an SMI interrupt. Sampled by the CPU on each rising clock edge. SMI# is falling edge sensitive and causes an I / O trap to occur if s amp led as ser ted a t least three c lo cks prior to RDY# / BRDY# sampled for any I / O cycle.
ST486DX4V
PARAMETER Case Temperature Storage Temperature Supply Voltage, VCC Voltage On Any Pin Input Clamp Current, IIK Output Clamp Current, IOK ST486DX4V MIN MAX -65° +110° -65° +150° -0.5 4.6 -0.5 6.0 10 25 UNITS C C V V mA mA NOTES Power Applied No Bias With Respect to VSS With Respect to VSS Power Applied Power Applied
2.2 Absolute Maximum Ratings The following table lists absolute maximum ratings for the ST486DX4 microprocessors. Stresses beyond those listed under Table 2-3 limits may cause permanent damage to the device. These are stress ratings only and do not imply that operation under any conditions other than those listed under "Recommended Operating Conditions"Table 2-4 is possible. Exposure to conditions beyond Table 2-3 may (1) reduce device reliability and (2) result in premature failure even when there is no immediately apparent sign of failure. Prolonged exposure to conditions at or near the absolute maximum ratings (Table 2-3) may also result in reduced useful life and reliability. Table 2-1. Pins Connected to Internal Pull-Up and Pull-Down Resistors
Table 2-2. Pins Requiring External Pull-Up Resistors
SIGNAL ADS# LOCK# EXTERNAL RESISTOR 20-k pull-up 20-k pull-up
ST486DX4V
2.3 Recommended Operating Conditions Table 2-4 presents the recommended operating conditions for the ST486DX4V device. Table 2-4. Recommended Operating Conditions
PARAMETER TC Case Temperature VCC Supply Voltage VIH High Level Input VIL Low Level Input IOH Output Current (High) IOL Output Current (Low)
ST486DX4V
MIN 0° 3.3 2 -0.3 MAX +85° 3.6 5.5 0.8 -1 3
UNITS
NOTES
Power Applied With Respect to Vss
2.4 DC Characteristics Table 2-5. DC Characteristics (at Recommended Operating Conditions)
Note 1
Note 1, 3
ST486DX4V
2.5 AC Characteristics Tables 2-6 through 2-9 list the AC characteristics including output delays, input setup requirements, input hold requirements and output float delays. These measurements are based on the measurement points identified in Figure 2-1 and Figure 2-2. The rising clock edge reference level VREF, and other reference levels are shown in Table 2-6 below for the ST486DX4 Input or output signals must Figure 2-1 shows output delay (A and B) and input setup and hold times (C and D). Input setup and hold times (C and D) are specified minimums, defining the smallest acceptable sampling window a synchronous input signal must be stable for correct operation.
Table 2-6. Drive Level and Measurement Points for Switching Characteristics
SYMBOL VREF VIHD VILD
Note: Refer to Figure 2-1.
ST486DX4V 1.5 2.3 0
ST486DX4V
Figure 2-1. Drive Level and Measurement Points for Switching Characteristics
OUTP UTS :
Valid V Output n REF
Valid Output n+1
INP UTS :
Valid V REF Input
LEGEND:
A - Maximum Outpu t De lay S pe cification B - Minimum Ou tput De lay S pecification C - Minimum Inpu t S etup S pecification D - Minimum Input Hold Spe cification
Figure 2-2. CLK Timing Measurement Points
VIH(MIN) VREF V IL(MAX)
ST486DX4V
Figure 2-3 . Input Setup and Hold Timing
Tx CLK Tx Tx Tx
T12 EADS#
T12A INVAL
T14 BS8#, BS 16#, KEN# T18 AHOLD, HOLD
T22 A31-A4 (CACHE INQUIRY CYCLE)
ST486DX4V
Figure 2-4 Input Setup and Hold Timing
BRDY#, RDY#
D31-D0, DP3-DP0 (READ)
Figure 2-5. PCHK# Valid Delay Timing
T2 CLK
BRDY#, RDY#
D31-D0,
DP3-DP0
VALID MIN
P CHK#
VALID
ST486DX4V
Figure 2-6 Output Valid Delay Timing.
Tx CLK
A31-A2, ADS #, BE3-BE0#, BREQ , D / C#, HLDA, LOCK#, M / IO#, P CD, P WT, W / R#
VALID n+1
VALID n
VALID n+1
S MADS #, S MI#
VALID n
VALID n+1
BLAST#, P LOCK#
VALID n
VALID n+1
HITM#, RP LSET(1-0), RP LVAL#, S US P A# D31-D0, DP 3-DP 0 (WRITE)
VALID n
VALID n+1
VALID n
Figure 2-7. Output Valid Delay Timing
Tx CLK
A31-A2, ADS# , BE3-BE0#, BREQ, D / C#, P WT, P CD, HLDA, LOCK#, M / IO#, W / R#
VALID
S MADS# , S MI#
VALID
BLAST#, P LOCK#
VALID
RP LSET(1-0), RPLVAL#
VALID
D31-D0, DP 3-DP0 (WRITE)
VALID
ST486DX4V
3.0 MECHANICAL SPECIFICATIONS 3.1 168-Pin Ceramic PGA & Plastic PGA Packages The pin assignments for the ST486DX4V 168-pin PGA packages are shown in Figure 3-1. The pins are listed by signal name and pin number in Table 3-1.
Figure 3 - 1. 168-Pin Plastic & Ceramic PGA Packages Pin Assignments
A26 A25
A17 A30
DP0 D4 D7 D14 D16 DP 2 D12 D15 D10 D17
VOLDET
A14 A18 A21
A12 A15 A22
S T486 3.45Volt S TANDARD P INOUT
D27 D25 D24
D28 D31 D29
168-P in PGA
(Top View)
INVAL
A11 A5
S MADS# RP LS ET1
HITM#
A10 A8 A7 TEST RP LVAL# SUS P A#
FERR# RPLS ET0 TDI
HLDA LOCK# D / C#
BRDY# S US P # KEN#
HO LD A20M# FLUS H# NMI
IGNNE#
A4 BLAST# PLOCK# Vcc
Vcc Vcc Vcc
RES ET
ADS# CLKMUL P CHK#
BOFF#
BS16# EADS# AHOLD
ST486DX4V
Table 3 - 1. ST486DX4 168-Pin PGA Packages Signal Names Sorted by Pin Number
Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
Signal Name D20 D22 TCK D23 DP3 D24 VSS D29 VSS INVAL VSS HITM# SUSPA# TDI IGNNE# INTR AHOLD D19 D21 VSS VSS VSS D25 VCC D31 VCC SMI# VCC
Pin No. B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D15 D16
Pin No. D17 E1 E2 E3 E15 E16 E17 F1 F2 F3 F15 F16 F17 G1 G2 G3 G15 G16 G17 H1 H2 H3 H15 H16 H17 J1 J2 J3
Signal Name BOFF# VSS VCC D10 HOLD VCC VSS DP1 D8 D15 KEN# RDY# BE3# VSS VCC D12 SUSP# VCC VSS VSS D3 DP2 BRDY# VCC VSS NC D5 D16
Pin No. J15 J16 J17 K1 K2 K3 K15 K16 K17 L1 L2 L3 L15 L16 L17 M1 M2 M3 M15 M16 M17 N1 N2 N3 N15 N16 N17 P1
Signal Name BE2# BE1# PCD VSS VCC D14 BE0# VCC VSS VSS D6 D7 PWT VCC VSS VSS VCC D4 D / C# VCC VSS D2 D1 DP0 LOCK# M / IO# W / R# D0
Pin No. P2 P3 P15 P16 P17 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 R1 R2 R3 R4 R5 R6
Signal Name A29 A30 HLDA VCC VSS A31 VSS A17 A19 A21 A24 A22 A20 A16 A13 A9 A5 A7 A2 BREQ
Pin No. R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 S1 S2 S3 S4 S5 S6 S7 S8 S9
Signal Name A15 VCC VCC VCC VCC A11 A8 VCC A3 BLAST# CLKMUL A27 A26 A23 VOLDET A14 VSS A12 VSS VSS VSS VSS VSS A10 VSS A6 A4 ADS#
PLOCK# S10 PCHK# A28 A25 VCC VSS A18 VCC S11 S12 S13 S14 S15 S16 S17
ST486DX4V
Figure 3 -2. 168 pin Ceramic or Plastic PGA package
1.65 DIA REF
SE ATING P LANE A
S T486
B DIA (ALL P INS)
45 DEG. CHAMFER INDEX CORNER SWAGGED PIN 4 PLACES
SE ATING P LANE
SWAGGED PIN DETAIL
Table 3 - 2. 168 Pin PGA Packages Dimensions
SYMBOL A A1 B D D1 e1 L MILLIMETERS MIN 3.65 1.14 0.43 44.07 40.51 2.29 2.54 MAX 4.57 1.40 0.51 44.83 40.77 2.79 3.30 MIN 0.140 0.045 0.017 1.735 1.595 0.090 0.110 INCHES MAX 0.180 0.055 0.020 1.765 1.605 0.110 0.120
ST486DX4V
3.2 208 Lead QFP(Quad Flat Package) The pin assignments for the ST486DX4 208 lead QFP package are shown in Figure 3-2. The pins are listed by signal name and pin number in Table 3-2.
Figure 3 - 3. 208-Lead QFP Package Pin Assignments
Vss LOCK# PLOCK# Vcc BLAST# ADS# A2 Vss Vcc Vss Vcc A3 A4 A5 UP# A6 A7 Vcc A8 Vss Vcc A9 A10 Vcc Vss Vcc A11 Vss A12 Vcc A13 A14 Vcc Vss A15 A16 Vcc A17 Vss Vcc TDI TMS A18 A19 A20 Vcc Vcc A21 A22 A23 A24 Vss
Vss Vcc NC P CHK# BRDY# BOFF# BS16# BS8# Vcc Vss CLKMUL RDY# KEN# Vcc Vss HOLD AHOLD TCK Vcc Vcc Vss Vcc Vcc CLK Vcc HLDA W / R# Vss Vcc BREQ BE0# BE1# BE2# BE3# Vcc Vss M / IO# Vcc D / C# P WT P CD Vcc Vss Vcc Vcc EADS# A20M# RESET FLUSH# INTR NMI Vss
S T486DX4
208-Le a d P QFP
(To p Vie w)
Vss Vcc A25 A26 A27 A28 Vcc A29 A30 A31 Vss DP0 D0 D1 D2 D3 D4 Vcc Vss Vcc Vcc Vss Vcc Vcc Vss Vcc D5 D6 Vcc TES T D7 DP1 D8 D9 Vss Vcc Vss D10 D11 D12 D13 Vss Vcc D14 D15 Vcc Vss DP2 D16 Vss Vcc Vss
ST486DX4V
Table 3 - 3. ST486DX4 208 Lead QFP Package Signal Names Sorted by Pin Number
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Signal Vss Vcc NC PCHK# BRDY# BOFF# BS16# BS8# Vcc Vss CLKMUL RDY# KEN# Vcc Vss HOLD AHOLD TCK Vcc Vcc Vss Vcc Vcc CLK Vcc HLDA W / R# Vss Vcc BREQ BE0# BE1# BE2# BE3# Vcc Pin 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Signal Vss M / IO# Vcc D / C# PWT PCD Vcc Vss Vcc Vcc EADS# A20M# RESET FLUSH# INTR NMI Vss Vss Vcc Vss Vcc Vss SMADS# Vcc Vss Vcc HITM# SMI# FERR# SUSPA# TDO Vcc RPLVAL# Pin 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 94 95 96 97 98 100 101 102 103 104 105 Signal INVAL IGNNE# SUSP# D31 D30 Vss Vcc D29 D28 Vcc Vss Vcc D27 D26 D25 Vcc D24 Vss Vcc DP3 D23 D22 D21 Vss Vcc Vss Vcc D20 D19 D18 Vcc D17 Vss Vss Pin 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 132 133 134 135 136 137 138 139 140 Signal Vcc Vss D16 DP2 Vss Vcc D15 D14 Vcc Vss D13 D12 D11 D10 Vss Vcc Vss D9 D8 DP1 D7 TEST Vcc D6 D5 Vcc Vss Vcc Vcc Vss Vcc Vcc Vss Vcc D4 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 Signal D3 D2 D1 D0 DP0 Vss A31 A30 A29 Vcc A28 A27 A26 A25 Vcc Vss Vss A24 A23 A22 A21 Vcc Vcc A20 A19 A18 TMS TDI Vcc Vss A17 Vcc A16 A15 Vss Pin 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Signal Vcc A14 A13 Vcc A12 Vss A11 Vcc Vss Vcc A10 A9 Vcc Vss A8 Vcc A7 A6 UP# A5 A4 A3 Vcc Vss Vcc Vss A2 ADS# BLAST# Vcc PLOCK# LOCK# Vss
RPLSET0 131
RPLSET1 99
ST486DX4V
Figure 3 - 4. 208 Lead Plastic QFP Package
VIEW A
ST486DX 208-Le a d QFP
Table 3 - 4. 208 Lead Plastic QFP Package Dimensions
SYMBOL A1 A2 D D1 L MILLIMETERS MIN 0.13 3.27 30.45 27.9 0.4 0° MAX 0.33 3.47 30.75 28.1 0.6 7° MIN 0.005 0.129 1.198 1.098 0.015 0° INCHES MAX 0.013 0.137 1.21 1.106 0.023 7°
ST486DX4V
Table 3 - 5. Ceramic & Plastic PGA Packages Thermal Resistance and Airflow
AIRFLOW (m / sec) CERAMIC PGA THERMAL RESISTANCE (C / W) WITH HEATSINK ja 0 1 2 3 4 15 12 10 9.5 8.5 jc 2.5 2.5 2.5 2.5 2.5 WITHOUT HEATSINK ja 19 15 13 12 11 jc 2.5 2.5 2.5 2.5 2.5 PLASTIC PGA THERMAL RESISTANCE (C / W) WITH HEATSINK ja 12 8 6.5 5.5 5 jc 1.5 1.5 1.5 1.5 1.5 WITHOUT HEATSINK ja 15 11.5 9.5 8.5 8 jc 1.5 1.5 1.5 1.5 1.5
PACKAGE CPU INTERNAL CLOCK FREQUENCY 66 MHz Ceramic Pin Grid Array 75 or 80 MHz 100 MHz 100 MHz 120 MHz 66 MHz Plastic Pin Grid Array 75 or 80 MHz 100 MHz 120 MHz 120 MHz HEATSINK (Yes / No) No No No Yes Yes No No No No Yes AIRFLOW (m / sec) 0 51 °C 51 °C 47 °C 57 °C 52 °C 60 °C 60 °C 57 °C 52 °C 60 °C 1 60 °C 60° C 57° C 65° C 60 °C 68 °C 68 °C 66 °C 62 °C 72 °C 2 65° C 65° C 62 °C 70 °C 66 °C 73° C 73 °C 71 °C 68 °C 76 °C 3 67 °C 67 °C 65 °C 72° C 68° C 75° C 75 °C 74 °C 71 °C 79 °C 4 69° C 69° C 67 °C 74 °C 71 °C 76 °C 76° C 75 °C 72 °C 81 °C 21 / 23
ST486DX4V
Figure 3 - 5. Typical Heatsink for PGA Packages
Table 3 - 7. Typical PGA Heatsink Dimensions
SYMBOL A B C D MILLIMETERS 6.1 1.3 4.8 39.1 INCHES 0.24 0.05 0.19 1.54
QFP Package Table 3-8 lists the junction-to-ambient and junctionto-case thermal resistances for the QFP package without a heat sink. Table 3-9 lists the maximum ambient temperatures permitted for various clock frequencies and airflows for the QFP Package for VCC equalto 3.6 volts. These QFP package thermal characteristics assume that the package is soldered to a four-layer printed circuit board. Table 3 - 8.
AIRFLOW QFP THERMAL RESISTANCE (°C / W) ja 0 m / sec 1 m / sec 21 17 jc 3.5 3.5
Table 3 - 9.
CPU INTERNAL CLOCK FREQUENCY 66 MHz 75 MHz 100 MHz AIRFLOW 0 (m / sec) 40° C 34 °C 30 °C 1 (m / sec) 53 °C 47 °C 45 °C
ST486DX4V
Ordering Information.
486DX
Please contact your nearest SGS-THOMSON sales office to confirm availability of specific valid combinations and to check on newly released combinations.