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CORE ADRESSING MODES PERIPHERALS SOFTWARE TOOLS HARDWARE TOOLS


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MICROCONTROLLER TRAINING
CORE
ADRESSING MODES PERIPHERALS SOFTWARE TOOLS HARDWARE TOOLS
CORE General
Purpose Microcontroller Training CORE
CORE PRESENTATION
LLER
CORE General
Purpose Microcontroller Training CORE
CORE General Description
CORE BUILT AROUND 8-bit Arithmetic Logic Unit (ALU) internal registers Accumulator (A), index registers, Program Counter (PC), Stack Pointer (SP) Code Condition register (CC) controller block INTERFACES WITH on-chip oscillator reset block address data buses access memories peripherals interrupt controller
CORE General
Purpose Microcontroller Training CORE
CORE Block Diagram
OSCin OSCout TEST/VPP CONTROL RESET Mutli oscillator Clock controller
Internal CLOCK
Watchdog Enhanced Reset
ADDRESS
-BIT DATA
Accu Index Index
Program memory
CORE General
Purpose Microcontroller Training CORE
CORE Internal Registers
ACCUMULATOR 8-BIT GENERAL PURPOSE REGISTER USED HOLD Operands Results arithmetic logic operation REGISTERS 8-BIT REGISTERS USED Create effective addresses Store temporary data automatically stacked. needed, must done using PUSH instructions Instructions using faster than ones using
CORE General
Purpose Microcontroller Training CORE
CORE Internal Registers
PROGRAM COUNTER 16-BIT REGISTER USED STORE ADDRESS NEXT INSTRUCTION EXECUTED CPU. RESULT, ADDRESS PROGRAM MEMORY STACK POINTER 16-BIT REGISTER. FIXED HARDWARE CODE CONDITION 5-BIT REGISTER
CORE General
NAME Half carry Interrupt mask Negative Zero Carry/Borrow
DESCRIPTION when carry occurs during instructions disabled interrupt result last operation negative result last operation zero affected when carry borrow occur some inst. executed
Purpose Microcontroller Training CORE
CORE Internal Registers
ACCUMULATOR
RESET VALUES
INDEX REGISTER
RESET VALUES
INDEX REGISTER
RESET VALUES RESET VECTOR FFFEh-FFFFh Fixed RESET VALUES
PROGRAM COUNTER
RESET VALUES
STACK POINTER
CONDITION CODE REGISTER
CORE General
Purpose Microcontroller Training CORE
CORE Stack manipulation
PURPOSE Save context during subroutine calls interrupts Save temporary user's data (PUSH instructions) CASE OVERFLOW (LOWER LIMIT EXCEEDED) rolls over higher address Previous value overwritten lost Stack overflow indicated return from subroutines interrupt
CORE General
Lower Address
Higher Address
Push call subroutines interrupt
Purpose Microcontroller Training CORE
CORE Stack manipulation
CALL subroutine
$0100
Interrupt event
PUSH
IRET
$017F
Stack size position device dependent ST72254 bytes ($0100 $017F) ST72334 bytes ($0100 $01FF)
CORE General
Purpose Microcontroller Training CORE
CORE memory space
MEMORY MADE DIFFERENT BLOCKS Peripherals hardware register Short Addressing Ports, TIM, ADC, WDG,SPI, I2C, EEPROM Mode first page Location Stack from bytes (device dependent) EEPROM Data bytes) Program memory Interrupt Reset vectors
PERIPHERALS HARDWARE REGISTERS Bytes STACK Bytes
$0100 $0180
RESERVED $E000 ROM/EPROM 8KBytes INTERRUPTS RESET VECTORS $FFE0
$FFFF
CORE General
Purpose Microcontroller Training CORE
IN-SITU PROGRAMING Remote
What PROGRAM REPROGRAM (flash devices) Program Memory when micro soldered application board. Main features: Only wires used (including VSS). need double voltage application board. Supported window eepromer tools. Performances: program 8Kbytes.
CORE General
Purpose Microcontroller Training CORE
IN-SITU PROGRAMING (ISP) Remote mode
Boot-ROM
ISPCLK ISPDATA ISPCLK RESET/ISPSEL VCC/VSS ISPDATA
I/Os
Periphs.
Boot-ROM allows executable software dowloaded through ISPCLK ISPDATA
PROG MEMORY
RESET/ISPSEL VCC/VSS
Software executed programs prog memory
PROG MEMORY
Software executed runs applicative software with I/Os peripherals access In-Situ Programming uses wires only
CORE General
Purpose Microcontroller Training CORE
IN-SITU PROGRAMING ROADMAP
28,32 pins
ST72104G1 ST72215G2 ST72216G1 ST72254G1/2 ST72314J2/4 ST72314N2/4 ST72334J2/4 ST72334N2/4
42,44,56,64 pins
wires Parallel JTAG wires Remote mode
wires Parallel JTAG wires Remote mode
Auto 42,44,56,64 pins
ST72532R4 ST72311R6/7/9 ST72512R4 ST72511R6/7/9 ST72171K2 ST72411R1
Dedicated Solutions
wires Parallel JTAG wires Remote mode wires Parallel JTAG
wires Parallel JTAG
ST72141K2
CORE General
Purpose Microcontroller Training CORE
INTERRUPTS Overview
EXCEPT SOFTWARE INTERRUPT, INTERRUPTS MASKED SETTING WHEN INTERRUPT OCCURS context saved stack (CC, other interrupts masked (the H/W) interrupt vector loaded Program Counter WHEN RETURN FROM INTERRUPT EXECUTED original context automatically restored (CC, Interrupts enabled reset) PRIORITY BETWEEN INTERRUPTS GIVEN INTERRUPT ADDRESS VECTOR
CORE General
Purpose Microcontroller Training CORE
INTERRUPTS ST72254 Interrupt mapping
INTERRUPT Reset Trap (instruction) External Interrupt External Interrupt Timer INTERRUPTS Reset Software Port Port Port Clock Filter Interrupt Transfer Complete Mode Fault Input Capture Output Compare Input Capture Output Compare Timer Overflow Input Capture Output Compare Input Capture Output Compare Timer Overflow Byte Transmission finished Error STOP Detection REGISTER CRSR Status Timer Status FLAG NAME CCSD SPIF MODF ICF1_A OCF1_A ICF2_A OCF2_A TOF_A ICF1_B OCF1_B ICF2_B OCF2_B TOF_B BERR SSTOP INTERRUPT SOURCE VECTOR ADDRESS FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h
Timer
Timer Status
FFEEh-FFEFh
Status
FFE4h-FFE5h
CORE General
Purpose Microcontroller Training CORE
INTERRUPTS Peripheral management
Periph Status Register Periph Control Register Condition Code Register
Interrupt flag Interrupt Enable Interrupt Mask Context switch takes clock cycles
Interrupt generation
CORE General
Purpose Microcontroller Training CORE
INTERRUPT Peripheral management
SOFTWARE EXAMPLE .Main BSET Control_reg, #IT_enable Enable Periph interrupt Clear register interrupt enabled .Int_routine BRES Status_reg, #IT_flag IRET
Avoid process same interrupt forever Return from interrupt
CORE General
Purpose Microcontroller Training CORE
Interrupt Summary
Interrupt Vector Number: Vectors Priority: levels hardwired Priority levels user configurable Interrupt Reaction Time: 1.250µs 2.750 (end current instruction cycles) Automatic register pushed: Program Counter, Accumulator,
Software levels allows nested interrupt process (only ST72511R subsets) least Interrupt Vector Peripheral
CORE General
Purpose Microcontroller Training CORE
Concurent Interrupt Management
Software Priority
Hardware Priority
main
main
CORE General
Purpose Microcontroller Training CORE
Nested Interrupt
interrupt levels thanks pair bits
Interrupt Software Priority Level (main) Level Level Level (=interrupt disable) Level
High
pair bits interrupt vector stored ISPR registers pair bits copied register when corresponding activated.
CORE General
Purpose Microcontroller Training CORE
Nested Interrupt Management
Software Priority
Hardware Priority
main
main
CORE General
Purpose Microcontroller Training CORE
Interrupt Roadmap
28,32 pins
ST72104G1 ST72215G2 ST72216G1 ST72254G1/2 ST72314J2/4 ST72314N2/4 ST72334J2/4 ST72334N2/4
42,44,56,64 pins
Concurent Interrupts
Concurent Interrupts
Auto 42,44,56,64 pins
ST72532R4 ST72311R6/7/9 ST72512R4 ST72511R6/7/9 ST72171K2 ST72411R1
Dedicated Solutions
Nested Interrupts
ST72141K2
Concurent Interrupts
CORE General
Purpose Microcontroller Training CORE
Multi oscillator
ADVANCED CLOCK SYSTEM
OSC1
OSC2
OSC1
OSC2
OSC1
OSC2
OSC1
OSC2
QUARTZ/CERAMIC
EXTERNAL SOURCE
INTERNAL 4Mhz
EXTERNAL
frequency backup safety oscillator Implemented Reprogrammable devices only
CORE General
Purpose Microcontroller Training CORE
Multi Oscillator
Crystal Ceramic Oscillators Designed reduce consumption speed speed high speed High speed External Oscillator Internal Oscillator Internal Safe Oscillator Oscillator selected option byte
CORE General
Frequency range
250KHz
Purpose Microcontroller Training CORE
Main Clock Controller
OSC1 OSC2
Multi Oscillator (MO)
Clock Security System (CSS)
Clock Filter Safe Oscillator
fOSC
Main Clock Controller (MCC)
CLKOUT
Alternate Function
MCCSR Register
Clock Divider
fCPU
Clock divider Values: 2,4,8,16,32
CORE General
CORE PERIPHERALS
Purpose Microcontroller Training CORE
Clock Security System
Clock Filter Function
Main Oscillator Clock Internal Clock
Safe Oscillator 250KHz)
Main Oscillator Clock Safe Oscillator Clock Internal Clock
CSSD safety function activated generate maskable interrupt request
CORE General
Purpose Microcontroller Training CORE
CLOCK POWER MODES
MODES: Fcpu=Fosc/2 Core periph. running except WAIT (Core stopped) selected SLOW MODES: Division ratio from software Core periph. running except WAIT (Core stopped) selected ACTIVE HALT: Division ratio from 32000 400000 software Core periph. stopped periodic wake-up through interrupts HALT MODE: Oscillator stopped Core periph. stopped
CORE General
Purpose Microcontroller Training CORE
Clock System Roadmap
28,32 pins
ST72104G1 ST72215G2 ST72216G1 ST72254G1/2
42,44,56,64 pins
Multi oscillator ext. 4Mhz int. Safety oscillator SLOW: 4/8/16/32 ACTIVE HALT
Multi oscillator ext. 4Mhz int. Safety oscillator SLOW: 4/8/16/32
ST72314J2/4 ST72314N2/4 ST72334J2/4 ST72334N2/4
Auto 42,44,56,64 pins
ST72171K2 ST72532R4 ST72311R6/7/9 ST72512R4 ST72511R6/7/9
Dedicated Solutions
Idem 28,32 pins
Quartz/Ceramic/Ext.clock 4Mhz SLOW:4/8/16/32 ACTIVE HALT
ST72411R1 ST72141K2
7.16Mhz Ext.Clock SLOW:/32 Quartz/Ceramic/Ext.clock SLOW:4/8/16/32
CORE General
Purpose Microcontroller Training CORE
CORE Reset diagram
EXTERNAL RESET USING RESET Purpose allow generate external reset Condition reset pull POWER SUPPLY DEPENDEND RESET USING Purpose ensure known state whatever Condition internal reset when reaches WATCHDOG RESET USING WATCHDOG TIMER Purpose guarantee safety case software trouble Condition internal reset when register refreshed
CORE General
Purpose Microcontroller Training CORE
ENHANCED RESET SYSTEM
RESET SOURCES Watchdog Voltage Detection (LVD) External RESET COMPLETE RESET MANAGEMENT Flags Reset sources Internal Reset externally issued reset whole application
COMPLETE RESET SEQUENCE Phase with RESET grounded Internal Reset 4096 clock cycles
Fetch Vector
From internal Watchdog Reset: Phase 30µs From internal Reset: 30µs<Phase<Low voltage duration From external RESET pin: 30µs<Phase<Ext RESET pulse width
CORE General
Purpose Microcontroller Training CORE
CORE Reset diagram
OSCILLATOR
Internal Reset
SIGNAL COUNTER
NRESET (ACTIVE LOW)
RESET
30µs Delay
RESET WATCHDOG RESET
CORE
GENERATION
supply
Safe behaviour despite starting current sunk
250mV hysteresis
VLVDr VLVDf
working
Internal RESET
Selectable levels Activation Flag
CORE
consumption RESET tied
General Purpose Microcontroller Training CORE
LEVELS OPTIMIZE SAFE AREA
Freq.
16Mhz
med. high
Absolute working window
8Mhz Safe 8Mhz area 3.0V 3.5V
Safe 16MHz area. 3.5V Reset issued
Safe 16Mhz area 3.8V Reset issued Vsupply
4.0V
CORE General
Purpose Microcontroller Training CORE
PART COMPLETE RESET MANAGEMENT
LVDRF WDGRF
supply
Software clearance
Reset ensures stable cleared state WDGRF when starts
Reset
Reset
Reset
External Reset
Reset
Ext. Reset
LVDRF cleared upon another Reset, flag remains keep trace original failure.
Original RESET source External RESET Watchdog
CORE General
LVDRF
Voltage Reset Flag
WDGRF
Voltage Reset Flag
Purpose Microcontroller Training CORE
ROADMAP
28,32 pins
levels option byte:
ST72104G1 ST72215G2 ST72216G1 ST72254G1/2
42,44,56,64 pins
levels option byte:
ST72314J2/4 ST72314N2/4 ST72334J2/4 ST72334N2/4
4.00V/4.25V 3.60V/3.85V 3.10V/3.35V Reset Flags
4.00V/4.25V 3.60V/3.85V 3.10V/3.35V Reset Flags
Auto 42,44,56,64 pins
ST72171K2 ST72532R4 ST72311R6/7/9 ST72512R4 ST72511R6/7/9
Dedicated Solutions
Idem 28,32 pins
device reference 4.25V/4.50V
ST72411R1 ST72141K2
CORE General
Purpose Microcontroller Training CORE
WATCHDOG Overview
PURPOSE DETECT OCCURENCE SOFTWARE FAULT. MUST REGULARLY REFRESHED PROGRAM WDCR, #$FF Reload DIFFERENT WATCHDOG SELECTED OPTION MASK Hardware Watchdog automatically activated upon reset Software watchdog activated software (bit Once activated, cannot disabled
CORE General
Purpose Microcontroller Training CORE
WATCHDOG Overview
RESET WATCHDOG HALT instruction generate reset watchdog activated option byte allows Watchdog used generate software reset (bit WDCR, #$80 Reset WDCR 12288 12288 clock cycles 1.54 Fcpu 8MHz WDCR 12288 786432 clock cycles 98.30 Fcpu 8MHz
CORE General
Purpose Microcontroller Training CORE
WATCHDOG Block diagram
Activation Reset active set)
WDGF
Watchdog Status Register
WDGA
7-bit Down Counter
Watchdog Control Register
Fcpu
Clock Divider ÷12288
CORE General
Purpose Microcontroller Training CORE
CONSUMPTION MODES Overview
MAXIMUM CONSUMPTION WITH FOSC REACH LOWEST POWER CONSUMPTION Switch unused peripherals Configure I/Os output level connect them lowest oscillator frequency possible Slow mode, Wait mode better Halt mode DATA RETENTION VOLTAGE HALT MODE
CORE General
Purpose Microcontroller Training CORE
CONSUMPTION MODES Slow mode
GOAL reduce comsumption reduing clock speed keeping same Oscillator frequency ENTER configuring miscellaneous register CAUSES clock slows down Fosc divided rather than EXIT configuring miscellaneous register
CORE General
Purpose Microcontroller Training CORE
CONSUMPTION MODES Wait mode
GOAL Reduce consumption while monitoring external events ENTER execution instruction CAUSES micro software frozen Program execution stopped Memory registers remain unchanged oscillator still provides clock peripherals EXIT Reset (Watchdog, reset pin) Internal interrupts (timer timer A/D, etc) External interrupts (I/O ports)
CORE General
Purpose Microcontroller Training CORE
CONSUMPTION MODES Active Halt mode
GOAL Reduce consumption lowest value while monitoring real time clock. ENTER execution HALT instruction while (Oscillator Interrupt Enable) set. CAUSES micro frozen, peripherals stopped, only Oscillator Main Oscillator Counter running. EXIT External Reset Interrupts with exit from halt capability (External IT,.) Time Base Interrupt (32000,64000,160000,400000 *Tcpu) From 25ms with fOSC=16MHZ
CORE General
Purpose Microcontroller Training CORE
CONSUMPTION MODES Halt mode
GOAL Reduce consumption lowest value ENTER execution HALT instruction CAUSES micro frozen Program execution stopped Memory registers remain unchanged oscillator stopped EXIT External Reset External interrupts (I/O ports)
CORE General
Purpose Microcontroller Training CORE
PROGRAMMING TIPS Consumption Modes
DURING WAIT MODE HALT MODE, (INTERRUPT BIT) REGISTER AUTOMATICALLY RESET ENABLE INTERRUPT TYPICAL CONSUMPTION
ST72254 ST72334 20µA
mode (Vdd=5V, Fcpu=8MHz)
Slow mode (Vdd=5V, Fcpu=500KHz) Wait mode (Vdd=5V, Fcpu=8MHz) Wait minimun mode (Vdd=5V,Fcpu=500KHz) Active Halt mode (Vdd=5V,Fosc=16MHz) Halt mode (Vdd=5V)
CORE General
Purpose Microcontroller Training CORE
PROGRAMMING TIPS Consumption Modes
AFTER EXITING FROM HALT MODE WAIT MODE AFTER RESET, MICRO WAITS 4096 CLOCK CYCLE (STABILIZATION TIME) BEFORE BEING OPERATIONAL SOURCE THAT ALLOWS EXIT FROM HALT MODE
Reset
ST72254 ST72334 ST725xx
Wfi-Halt Wfi-Halt Wfi-Halt
Timer
Timer
E2prom
Wfi-Halt Wfi-Halt Wfi-Halt
CORE General
Purpose Microcontroller Training CORE

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