LZ95D42/M U95D42/M CMOS timing generator which provides timing pu

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LZ95D42/M U95D42/M CMOS timing generator which provides timing pu

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U95D42/M
LZ95D42/M
U95D42/M CMOS timing generator which provides timing pulses used drive area sensor, combination with (LZ95D52/M).
Timing Pulse Generator
CONNECTIONS
48-PIN
mN._ooomm. za~knzuunm
L~O>k~O SMDI SMD2 SMD3 DATA DCLK PBLK CPPR CPOB CPEN S211 MCK. MCKI SII1
VIEW
FEATURES
Switchable between 410000 pixels
470000 pixels Switchable between NTSC (EIA) (CCIR) systems Internal electronic shutter: Shutter speed selectable from 1/60 (PAL /50), /250, /500, 000, 1/10 addition this, (PAL 1/125 Flicker-less mode using serial parallel code. Shutter speed also controlled periods using serial code Single power supply Packages 48-pin QFP(QFP048-P-101 LZ95D42 LZ95D42M 48-pin QFP(QFP048-P-0707)
1121\31141] 5116117116 ]]9]l10]lll][12] c))g~zsclse?? (J(.)~
data Wka, GIntact SHARP cider obmfn latest verc(on device wficafionshaeh ~fcfe using SHARP device."
abs?nce confimat)m dev)ce s~lflcahon
sheets WARP takes rewslblllw defwb that Ecur qulpment using SHARPS devices, shovir c8QIws.
U95D42/M
MCK4 MCKI
S212
SPSW TEST
DECODER
PNSW
SHUTTER CONTROL
'11,
V-COUNTER
SMD, SMDZ SMD3 DATA DCLK PBLK CPPR CPOB CPEN
U95D42/M ABSOLUTE MAXIMUM RATINGS
PARAMHER Power voltage lnDut voltaae
output voltage
SYMBOL
RATING -0.3 +0.3 -0.3
Topr Tsta
VCC+O.3
Operating temperature Storaoe temperature
+150
CHARACTERISTICS
PARAMHER level input voltage High level input voltage level input current High level input current level output voltage High level output voltage level output voltage High level output voltage level output voltage High level output voltage NOTES Applied inputs (IC, ICD, ICU, OSCI) Applied inputs (IC, ICD, OSCI). Applled input (ICU). Applied inputs (IC, ICU, OSCI). Applied input (lCD). Applied outputs OR1, OSCO). Applied output (OR1 Applied output (OR1 SYMBOL IIL1 IILz Vl=o Vl=o
(VCC=+5 V*1O%, +75C) CON~lONS MIN.
TYP.
MAX.
UNIT
NOTE
IIL1 IIL2
VOL1
vOL2 vOH2
IoH=-1.6
12.8
VOL3 VOH3
U95D42/M
SYMBOL
POIARITY
NAME
FUNCTION
output dividing pulse reference clink (pin 37). connected clwkinput
CLKO
Delay-line clock.
SSG-LSI. NTSC mode 14.31818 (910 mode 14.18750 (908 input Horizontal reference pulse. connected SSG-LSI. input vertical reference pulse. connected SSG-LSI. Vertical transfer pulse. connected LR36663N vertical driver LSI. Vertical transfer pulse. connected LR36663N vertical driver LSI. Vertical transfer pulse. connected LR36683N vertical driver LSI. grounding pin, connected level. Vertical transfer pulse. connected LR36663N vertical driver LSI. output transfer photo diode charge
Horizontal drive pulse
Vertical drive pulse
Vertical transfer pulse Vertical transfer pulse Vertical transfer pulse Ground Vertical transfer pulse
Read pulse
vertical shift register. connected LR36663N vertical driver LSI. output transfer photo diode charge
Read pulse
vertical shift register. connected LR36~N vertical driver LSI. output sweep photo diode charge
pulse output
CCD. When electrical shutter Normal mode, this output becomes High level. output reset output signals.
0R12
Reset pulse
connected through DCoffset circuit.
Width control input
input width reset pulse (pin 12). output width reset pulse (pin 12). input (pin through integral circuit. Horizontal transfer pulse last-gate CCD. area without inverting driver.
Width control output
Horizontal transfer last pulse
LZ95D42/M
SYMBOL POLARITY NAME Power supply FUNCTION connected Horizontal transfer pulse CCD. connected area sensor without inverting driver. Horizontal transfer pulse CCD. connected
OR14
Horizontal transfer pulse
OR14
Horizontal transfer
pulse
Ground
area sensor without inverting
driver. grounding pin. connected level. input phase (pin pulse
SII1
Phase
control input
output. inputs signal from MCK4 (pin output
through integral circuit. input width (pin pulse output. inputs signal from MCKI (pin output through integral circuit. output dividing pulse referem clock (pin 37). same with (pin 17). output dividing pulse referen~ clwk
SI12
Phase control input
MCKI
Clock output
MCK4
Clwk output
(pin 37). delayed approximately phase with respect (pin 18), input phase (pin pulse output. inms signal MCK4 (pin outPut through integral circuit. input phase (pin pulse output. inputs signal frofn MCKI (pin output through integral circuit. pulse clamp signals from CCD. pulse sample-hold signals from CCD. input switch (pin (pin 35), details, "TIMING DIAGRAM (HIGH SPEED PULSE TIMING)" Testing pin. open level Normal
S211
Phase control input
S212
Phase control input
pulse pulse
SPSW
Phase SPI, select input
TEST
Test terminal
mode. Typically connected level.
connected grounding pin. connected level.
Power supply Ground
Phase SPI, control output
output pulse phase (pin (pin 35).
LZ95D42/M
SYMBOL
POIARITY
NAME Phase SPI, control input
FUNCTION input pulse (pin (pin 35). inputs signal from (pin output through integral circuit. output sampling pulse color demodulation based upon output signal from CCD. details, "TIMING DIAGRAM (HORIZONTAL TIMING)" output sampling pulse color demodulation based upon output signal from CCD. details, "TIMING DIAGRAM (HORIZONTAL TIMING)" input select standards. level NTSC mode High level mode oscillation inverter input. frequencies follows NTSC mode 28.63636 (1820 mode 28.37500 (1816 Horizontal frequency)
oscillation inverter output.
Color sampling pulse
Color sampling pulse
PNSW
mode select
Oscl
Clock input
SMDI
Osco
Uuuu
Clock output Shutter control
input select Shutter mode. details, "NOTES (Shutter Speed Control
input select Shutter mode. details, "NOTES (Shutter Speed Control
SMD2
Shutter control
SMD3
Shutter control Shutter speed switching input Shutter speed
switching input
input select Shutter mode. details, "NOTES (Shutter Speed Control input control Shutter Speed, details, "NOTES (Shutter Speed Control
input control Shutter Speed. details, "NOTES (Shutter Speed Control output color separate pulse. sig-
DATA
DCLK
Line index pulse
switches between High every line. resets 273th line when NTSC mode, 326th line when mode. Equivalent CBLK pulse except shorter pulse
PBLK
Pre-Blanking pulse
width with cut-off falling edge. details, "TIMING DIAGRAM",
CPPR
Dummy clamp pulse
output clamp pulse dummy signals. details, "TIMING DIAGRAM".
LZ95D42/M
SYMBOL CPOB POIARITY
NAME
FUNCTION pulse clamp optical black signals, details, "TIMING DIAGRAM" output clamp pulse recovering level. repetition horizontal frequency, details, "TIMING DIAGRAM".
Optical Black clamp
CPEN
clamp pulse
Input (CMOS level). Input (CMOS level with pull-up resistor). Input (CMOS level with pull-down resistor) Output pin. OR1, OR12, 0R14 Output (Through rate controlled buffer) Oscl Input oscillation. Osco Output oscillation.
NOTES
Shutter Speed Control Pararell data input
SMDI SMD2 SMD3 (Pin (Pin (Pin 111-1I
SHU~ER SPEED NTsc SERIAL CONTROL SERIAL CONTROL 1/100 1/120 /250 /250 /500 /500 I+non 1/1000 -.,, /2000
/4000
/2000
/4000
Serial data input
calculate method shutier speed. NTSC (261 n)x63.56 (O<n5130) (311 -2xn)x64.~ [gs] (Osns155)
LZ95D42/M TIMING DAIGRAM
VERTICAL TIMING NTSC
(ODD FIELD)
HNo. CBLK PBLK 522523524525
CH1,2
~1~3~50:7~9WJi~: CS2~4B6CS603101
11,13
output
CPOB CPEN CPPR
2B-G 2B.G 2R-G 2B-G
Z4~2ffi2S4
SUB(1 /60s) SUB(1 /2000s)
(EVEN FIELD)
HNo. CBLK PBLK 2622~ 2672W 269270271272273274275 276277278 2792W 281282 2832W ?YYY4YY0B2 4s'467
C61C630B5CS7
~2~4~6~6CS$6;3 M906112:4
~::l; 8:~012
output
CPOB CPEN CPPR
2&G: 2R-G 2f-G
2B4:2R4
SUB(1 /60s) SUB(1 /2000s)
U95D42/M
VERTICAL TIMING
(Ist, FIELD)
HNo. CBLK PBLK
621622623624625
output CPOB CPEN CPPR SUB(1 /50s) SUB(1 /2000s)
(2nd, FIELD)
HNo. CBLK PBLK
308309310311
312313314315316317318319320321
322323324325326327328329330W1
332333324335336337
~2~6~8[W101 035:@7 C89;B;1
577579581 output CPOB CPEN CPPR SUB(1 /50s) SUB(I /2000s) 28-G
2B-G
K95D42/M
HORIZONTAL TIMING NTSC
1812 1820,0
CBLK CLKO output *SPI (Ye)
*SP2 (Cy) 78911
131416182C12224 %2g30 3Z3436284~
nflnnnfl nnflnnmnnflnnn flnnnnn wnflnnnflnnnn~ Innnfinnnnr
PBLK
CPOB
CPEN CPPR
*SPSW=L level
1820fH
106110
180182
CBLK CLKO output (Ye)
(Cy)
mhnlnnn nnnnnnnnnnnn~nnh nnnnnnn nnnnnnnnlnnnnnnn~n Uhflflflhflnnn
nnninnnfln~
PBLK CPOB CPEN CPPR
*SPSW=L level
U95D42/M
HORIZONTAL TIMING NTSC (cent'd)
1820fH CBLK CLKO
Z81O 1214 DAMMY 161820221231234567810 M36W 4042 OM~CrYe@Ye CYYe@YeCYYeCYYeCY YeCYYeCYYeCYYe CYYqCYYeCYYeCYYeQYeCYYe QYe@Ye QYqCYYe CYYe
output
(Ye) (Cy)
nhnnnnn nwnnnnnnnnnn nfllnfl fl~flfl flflflf lflflflf lllflflflfl nnnnnnnnnnnhnnnn nnnnn~nnnnn~
Iflnnnn nnnnnnnflnnnnnnn nnnnfln nnflnnnnnnnnnnn flnn~nnnnnnflnnn
PBLK CPOB CPEN CPPR *SPSW=L level
HORIZONTAL TIMING
1816fH CBLK CLKO 323436W4~ nnnnhnnnnnnnnnnnn 1808 1816,0 142230=4654
output
131416182022242628W
nnnnnnnnnnhn~nnnnn nnnnnnn nfinnnnnnnnnn
nnnnnnn hnnnhnnnnnnnnnnn nmnnnnn flnnnflnnnnnnn
(Ye) (Cy) PBLK CPOB CPEN CPPR
mnnnnnn flnnnnnunnnnn
*SPSW=L level
U95D42/M
HORIZONTAL TIMING (cent'd)
1816fH
CBLK CLKO output (Ye) (Cy)
PBLK CPOB CPEN CPPR
*SPSW=L level
1816fH
CBLK CLKO output
123456769 OAMMY
1820:2212312345678910 2&30
nnnnnnn nnnnnnnnnnnnnnnn nnhnnnn nnnnnnnnnnnnnnnn nnnnnnnonnnhw ~nnnnnnn~ flnnnnr
*SPI (Ye)
*SP2 (Cy)
PBLK CPOB CPEN CPPR
*SPSW=L level
U95D42/M
CHARGE READ TIMING
(ODD lst, FIELD)
Oflz 1494 1816)
1208
(EVEN 2nd, FIELD)
1062 1062 1206
1816
U95D42/M
HIGH SPEED PULSE TIMING
NTSC 209T 237T
215T 243T
247T 275T
253T
259T 287T
[1/T :34,921 [1/T :35.242
output
FH2=L Ft12=H GtcmYGtcmYw MGtYMtc GtYM
[SPSW
[SPSW <FH2=L> <FH2=I-1> PELK

LZ95D42/M U95D42/M CMOS timing generator which provides timing pu

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