Acapella Optical Modem ACS5010CS Main Features Full duplex s
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Acapella Optical Modem
ACS5010CS Main Features
Full duplex serial transmission through twin optical fiber. Configurable parallel microprocessor interface. independent synchronous data channels. (STS1) 51.840Mbps E3/T3 E1/T1
Link lengths 25km.
General Description
ACS5010CS complete controller, driver receiver chipset supporting full-duplex synchronous transmission 51.840Mbps over single/twin optical fiber. designer share available bandwidth over main channels over link lengths 25km. addition main channels, ACS5010CS provides single independent maintenance channel with data rate selectable between 8kbps 256kbps. There also separate framing signal channel maintenance channel. This allows user frame bandwidth maintenance channel into several channels, 16kbps. electrical side ACS5010CS selectable interface either pseudo bipolar data coding types HDB3/AMI/B3ZS/B6ZS/B8ZS. ACS5010CS configurable parallel microprocessor interface. This used device set-up, control status analysis. Additional flags data status, data status alarm indication both near receive fail accessible interface. Communicating modems automatically maintain synchronization with each other.
Incorporates 256kbps maintenance channel with separate framing signal. Error Rate (BER) Latency 0.50ms 25km.
Twin fiber full duplex system using ACS5010CS chip with external T1/E1 Framer microprocessor.
Select between pseudo-bipolar HDB3/AMI/B3ZS/ B6ZS/B8ZS input data coding types.
Acapella Optical Modem
ACS5010CS comprises chip two/three (link budget dependent) highly integrated devices, ACS9020 ACS5010. ACS9020 analogue device ACS5010 predominately digital device. ACS9020 contains Laser/LED driver well receiver circuitry. Since devices transmitting receiving concurrently (half duplex fiber), long haul applications ACS9020 devices required, configured transmitter other configured receiver. ACS5010 comprises logic necessary time compress decompress data, plus logic associated with valid data transmission reception locking status. ACS5010 also configurable parallel microprocessor interface device configuration (control) status analysis. device setup alternatively possible (remote control) directly pins basic device setup. purpose this specification chip-set will referred ACS5010CS individual devices ACS9020 ACS5010.
ACS5010CS
PORB
Power Reset (PORB) resets device forced more. normal operation PORB should held High. recommended that PORB connected 100K resistor 100nF capacitor.
System Clock
system clock ACS5010CS derived locally using on-chip crystal oscillator. oscillator (XTO/I) requires fundamental parallel resonance crystal with appropriate padding capacitors. crystal specification should
Calibration tolerance: 20ppm Temp. tolerance: +/-20ppm
Temperature range:
Load condition: Mode
Padding capacitor:
applications requiring higher link budget 30dB) three chip solution used, where laser driver receiver circuitry separated.
link budget applications 10dB) chips, ACS9020 analogue (including laser driver receiver circuitry) ACS5010 sufficient.
system clock defines burst frequency which data transmitted over optical link optical interface. receive circuitry within ACS5010 recovers clock from received data Rxdat inputs produces clock that synchronised incoming data stream. system clock must have maximum tolerance +/50ppm over desired temperature range.
Inter-Modem Coding
Optical Operational Modes
ACS5010CS four optical operational modes, supporting twin fiber, controlled pins LASER, LASRX PINRX ACS9020 device. ACS9020 also utilise components with internal Trans-Impedence Amplifier (TIA). twin fiber modes Table converted single fiber operation simply interfacing Wave Division Multiplexer (WDM) device.
inter-IC coding between communication modems 8B10B. Whilst transparent user, 8B10B encoding ensures that there component signal, provides frequent data transitions, factors which ease task data recovery clock extraction. coding rules continuously checked ensure integrity link, errors indicated ERRL ERRC pins (see section headed ERRC ERRL Error Detection
Transmit Receive functions
Data presented near-end TPOS/TNEG timecompressed, encoded 8B10B format transmitted over fiber link receiver. Similarly, data presented far-end TPOS/TNEG time-compressed, encoded 8B10B format transmitted over other fiber link near end.
Table Optical modes
parallel load 15pF Optical Device
18-22pF (tune desired tolerance)
Laser separate without TIA. Laser separate with internal TIA. separate without TIA. separate with internal TIA.
ACS5010CS PRE-RELEASE Issue BETA January 1999.
Mode Laser separate without internal mode device configured with Laser separate without TIA. this configuration, output from optical receiver will directed into chip pre-amplifier ACS9020 This will realise long haul twin fiber link. Mode Laser separate with internal mode device configured with Laser separate with internal TIA. this configuration, output from optical input directly post amplifier ACS9020 device will bypass pre-amplifier. This will realise long haul twin fiber link. Mode separate without internal mode device configured with separate without internal TIA. this configuration, output from optical receiver will directed into chip pre-amplifier ACS9020 This will realise long haul twin fiber link.
There internal resistor value connected between RxMN which converts current into voltage. RxMN compared with 1.25V. RxMN exceeds 1.25V, then output RxFLG otherwise RxFLG With internal resistor 50K. adding external parallel resistor between RxMN GND, this threshold increased.
Link Receive Clock CLKR
link receive clock recovery (RPLL) extracts clock clkr from data received over fiberoptic link. This clock used drive link receive circuitry synchronized incoming data stream.
Line Transmit Receive Clocks TxCLK
There independent Transmit clocks TxCLK(16:1) independent Receive clocks RxCLK(16:1) ACS5010. purpose this specification, these signals will referred collectively TCLK RCLK. lower frequency data rates T1/E1/T2/E2 generated on-chip line Transmit clocks (TxCLK1 TxCLK16 TmCLK) internal transmit clock generation mode (CKC reference clock clock recovery de-jittering PLLs that generate line Receive clocks (RxCLK1 RxCLK16 RmCLK) derived digitally from system clock clkx. line Receive clocks RxCLK1-RxCLK16 RmCLK recovered de-jittered digital-only algorithmic PLLs (DPLL). higher data rates E3/T3/OC1, multiplying (MPLL) provides line Transmit clock TxCLK1 reference clock that generates RxCLK1 they cannot generated digitally. line Receive clock RxCLK1 recovered dejittered mixed digital/analog (RXCPLL) using digital algorithm control analog lock rate far-end bit-rate. analog circuitry channel disabled lower data rates. Both mixed digital PLLs comply jitter tolerance jitter transfer specifications selected data rates. algorithm that determines transfer function response PLLs modified (shaped) according selected data rate.
Mode separate with internal
TxMN TxFLG
TxMN used monitor current delivered Laser. TxMN current source that proportionally mirrors current flow through Laser. placing appropriate resistor (Rtxmn) between TxMN GND, voltage developed (referenced GND), will proportional transmit current. During Laser setup procedure TxMN should monitored ensure that Laser manufacturer's maximum current specification exceeded. TxMN also employed during normal operation continuously check Laser current. voltage developed across Rtxmn compared within internally generated reference voltage 1.25V. event that reference voltage exceeded, TxFLG High, otherwise Low.
Receive Monitor
ACS9020 incorporates power meter which generates current source which proportional received optical current.
ACS5010CS PRE-RELEASE Issue BETA January 1999.
mode device configured with separate with internal TIA. this configuration, output from optical input directly post amplifier ACS9020 device will bypass pre-amplifier. This will realise long haul twin fiber link.
System Frequencies Clock Generation
crystal clock frequency multiplying factors MPLL fully determined choice data rates. Table lists required frequencies system. Mode Data Rate
1.544 2.048 6.312 8.448 34.368 44.736 51.840
anticipated that most users ACS5010CS will interface directly with E1/T1 framers. popular framers provide POS/NEG bipolar interfaces which will directly connect ACS5010. required, detailed description AMI/HDB3/ BxZS coding rules available from Acapella.
XTAL
23.160 22.528 23.144 22.528 22.912 22.368 25.920
Fsys
69.480 67.584 69.432 67.584 68.736 67.104 77.760
Data Rate Selection
purpose this specification TPN1 represents signals TPOS1 TNEG1, RPN1 represents signals RPOS1 RNEG1. section headed, Data Coding description coding types. maximum recommended crystal (XTAL) 25.920MHz. internal multiplier factors XTAL frequency maximum bandwidth 51.840MHz (OC1). This bandwidth utilised various ways, divided over channels. main channels completely independent. channel consists following signals: Transmit side: TPOS bipolar signal data TNEG bipolar signal TPOS TCLK transmit clock (internal external) Receive side: RPOS bipolar signal data RNEG bipolar signal data RCLK receive clock data rate selected data rate selection bits DR(4:1), either directly pins microprocessor interface. selection determines number active channels combination with selected crystal frequency line data rate accordance with Table
Pins TCLK (MHz) 1.544 2.048 6.312 8.448 34.368 44.736 51.840 Nos. channels Tmode
Data Coding HDB3 B8ZS B6ZS B3ZS
POL3
POL2
Table Line coding selection
Non-Return-to-Zero (NRZ) coding, data applied directly TPOS inputs, output data appears only RPOS output pins (except 8-channel mode, section headed, Multi-Channel Operation). When using code, unconnected TNEG input pins will automatically pull-up VD+. addition, ACS5010CS will assert continuous redundant RNEG output pins.
POL1
main synchronous channels following coding methods: NRZ, AMI, HDB3, B3ZS, B6ZS B8ZS. desired mode selected POL(3:1) input pins, shown Table
Data Coding
Table System frequencies
AMI, B3ZS, B6ZS, B8ZS HDB3 coding normally bipolar. However, possible interface with ACS5010CS using inputs outputs rather than single bipolar interface. Data equivalent positive excursions bipolar AMI/BxZS/HDB3 signal applied logic High TPOS, while data equivalent negative excursions applied logic High TNEG. Similarly, AMI/BxZS/HDB3 positive excursions will appear logic High RPOS negative excursions will appear logic High RNEG.
Table Data rate channel selection
Channels used specific mode disabled. example mode channels carrying data rates, channels disabled. channels disabled individually microprocessor interface, alternatively far-end remote control.
ACS5010CS PRE-RELEASE Issue BETA January 1999.
Diagnostic modes
ACS5010 four diagnostic/configuration modes implemented main channels, configured DM(3:1) shown Table
Diagnostic Mode Local loopback Remote loopback Full-duplex master Full-duplex slave Full-duplex Lock Drift Active Drift Active Active
Local Loopback
local loopback mode, data looped back inside near-end modem output outputs. Data received from far-end device ignored, except maintain lock. concurrent requests occur local remote loopback, local loopback selected. local loopback diagnostic mode used test data flow back from, local ACS405CS does test integrity link itself. Therefore, local loopback operates independently synchronisation with second modem (i.e. High Low). local loopback test initiated microprocessor interface microprocessor modes), giving independent control each channel. channels simultaneously initiated into local loopback when microprocessor mode disabled DM(3:1) pins.
Table Selection diagnostic modes
Full-Duplex
full-duplex configuration, RCLK clock both devices track average frequency corresponding TCLK clock opposite link. receiving Digital-Phase-Lock Loop (DPLL) system makes periodic adjustments RCLK clock ensure that average frequency exactly same far-end TCLK clock. summary, each TCLK independent master clock each RCLK slave far-end TCLK clock. relationship between TmCLK RmCLK treated similarly.
Remote Loopback
Full-Duplex Slave
relationship between TmCLK RmCLK treated similarly. should forced GND, that TmCLK always configured output.
slave mode, TCLK RCLK clock derived from TCLK clock far-end modem, such that their average frequencies identical. Clearly, essential that only modem within communicating pair configured slave mode. should forced GND, that TCLK always configured output.
Full-Duplex Master
master mode, local RCLK clock internally generated from local TCLK clock. local TCLK clock internally externally generated. Master mode only valid far-end device configured slave mode far-end TCLK clock derived from far-end RCLK clock. Only modem within communicating pair configured master. relationship between TmCLK RmCLK treated similarly.
DM(3:1) Slave
remote loopback mode, near-end modem sends request far-end modem loopback received data, thus returning data that appears initiating modem. Both modems exercised completely, well Lasers/LEDs fiber optic link. remote loopback test normally used check integrity entire link from near-end (initiating modem). Whilst device responding request remote loopback from far-end, requests from nearend initiate remote loopback will ignored. remote loopback test initiated microprocessor interface microprocessor modes), giving independent control each channel. channels simultaneously initiated into remote loopback when microprocessor mode disabled DM(3:1) pins.
chip Line Transmit Clocks
on-chip line transmit clock selection specific channel depending selection clock direction (CKC) diagnostic/configuration mode DM(3:1) given below. Selected on-chip TxCLK Selected chip RxCLK Selected chip RxCLK
TxCLK will generated internally MPLL channel T3/E3/OC1 data rates, otherwise digitally system clock division. TxCLK will generated externally.
ACS5010CS PRE-RELEASE Issue BETA January 1999.
modes selectable DM(3:1) either directly pins microprocessor interface. diagnostic modes Remote Loop-back (RL) Local Loop-back (LL) selectable individually each channel microprocessor interface.
chip Line Receive Clocks
on-chip line receive clock selection specific channel depending selection diagnostic/ configuration mode DM(3:1) given below. DM(3:1) Master Selected on-chip RxCLK Selected chip TxCLK Selected chip TxCLK
same clock, therefore increasing total available maintenance bandwidth 512kbps.
Diagnostic Modes Configuration
diagnostic configuration modes available main channels also available maintenance channel. DM(3:1) also controls maintenance channel, while Remote Loop-back (RL) Local Loop-back (LL) also selectable individually microprocessor interface.
RxCLK will generated internally RXCLK channel T3/E3/OC1 data rates, otherwise digitally system clock division digital PLLs (DPLLs). polarity clocks (data being latched/valid either rising falling clock edge) selected TRSEL RESEL signals.
Transmit Receive Clock
same clock selection applies maintenance channel main channels, with being used external/internal TmCLK selection. onchip transmit clock (TmCLK) reference clock (digital) clock recovery de-jittering PLLs (DPLL) RmCLK derived digitally from system clock clkx 256kbps division factors shown Table Note that non-integer values, some additional jitter will introduced into maintenance path. lower data rates than 256kbps selected, 256kbps clock will divided further down factor 2/4/8/16/32.
Maintenance channel
synchronous maintenance channel consists following signals: Transmit Side TMCLK transmit data framing input transmit clock (internal external)
uPSEL(3:1)
Receive Side RMCLK
receive data framing output receive clock
Data Rate (kbps)
Maintenance Data Rate Selection
MSEL(3:1)
data rate selected maintenance data rate selection bits MSEL(3:1), either directly pins microprocessor interface. data rates shown Table
Microprocessor Interface Interface Mode Selection
ACS5010 incorporates 8-bit parallel microprocessor interface, which configured following modes interface mode control pins uPSEL(3:1) defined Table
Mode MOTOROLA INTEL MULTIPLEXED EPROM Description Interface disabled Motorola interface Intel compatible interface multiplexed interface EPROM read mode
Table Maintenance Channel Data Rate Selection
framing signal, together with specific data rate selection, used divide maintenance channel into sub-channels with certain data rate. Example: Required: 16kbps maintenance data: select MSEL(3:1) 001, 64kbps frame every bit. framing channel locked data channel RMD. alternatively used implement 256kbps channels running
Note: least significant modes used here, byte structure complies little endian format (byte least significant stored lowest address).
Mode
Table System Clock Division Factors Maintenance Clock Generation (256kbps)
Table Microprocessor Interface Mode Selection
FSys/256 kbps 271.40625 271.21875 268.5 262.125 303.75
ACS5010CS PRE-RELEASE Issue BETA January 1999.
Mode (uPSEL interface disabled. Control device solely pins. This will result limited functionality, example individual set-ups remote loop-back local loop-back each channel possible, only common one. this mode, pins tri-stated. Alternatively, possible unused interface pins other functions, such additional control setup. This might become necessary functionality ACS5010 expanded future modifications specification.
A(3:0) AD(7:0)
Description Active chip select Active read enable Active write enable Address Data Ready
Table Interface Pins INTEL mode.
EPROM mode
EPROM mode (uPSEL enables device read set-up from memory device. internal state machine controls access memory. addresses memory read, device according corresponding data. access time scaled interface with EPROMs type AM27C020 lowest speed (250ns) specification (TAcc 64/FSys). Read-only addresses interface ignored, with exception device (address which used check memory device actually attached device. memory attached, interface reverts default mode. interface pins used EPROM mode defined Table
A(3:0) AD(7:0) Description
MOTOROLA mode
MOTOROLA mode (uPSEL enables ACS5010 interface with Motorola 680x0 type microprocessor bus. interface pins used defined Table
A(3:0) AD(7:0)
Description Active chip select Address latch enable Active read enable Active write enable Address Data Ready
Active chip select/output enable Address output EPROM Data input from EPROM
Name ch_enb(16:1) DR(3:1) POL(3:1) DM(2:1) TRSEL RESEL MSEL(3:1)
Remote Control
device setup control signals controllable far-end when remote control enabled (ENRSB These defined Table
Description Channel enable(active low)for individual channels Data rate select Line code polarity select Configuration mode(full-duplex/master/slave) Clock edge select transmit clocks Clock edge select receive clocks Clock direction select maintenance channel Clock direction select main channels(combined) Maintenance channel data rate select
Table Interface Pins EPROM mode.
MULTIPLEXED mode
MULTIPLEXED mode (uPSEL enables ACS5010 interface with microprocessor using combined multiplexed address/data bus. interface pins defined Table
AD(7:0)
Table Interface Pins MULTIPLEXED mode.
INTEL mode
INTEL mode (uPSEL enables ACS5010 interface with Intel 80x86 type microprocessor bus. interface pins used defined Table
Table Interface Pins MOTOROLA mode.
Table Remote Control Device Setup
Description
Active chip select Read write select Address Data Active data transfer acknowledge (DTACK)
ACS5010CS PRE-RELEASE Issue BETA January 1999.
Memory
Table shows memory ACS5010. location names chosen match corresponding names. Signals directly equivalent pins lower case. device identification number id(7:0) address used EPROM mode check external memory device connected. value programmed will advised. Remote loop-back, local loop-back clock direction select (CKC) controlled individually each channel. error counter errc(7:0) (address 0xA) 8-bit saturating counter ERRC error pulse. write 0x00 mask this address clears counter 0x00. status signals ERRL, fail_ne, fail_fe also cleared writing specific address. example, writing mask 0xDF address clears ERRL signal, leaves other status signals unchanged.
Address
Access
Name
id(7:0) ch_enb(8:1) ch_enb(8:1) ENRSB DR(3:1)
rl_det ll_det
POL(3:1) TRSEL RESEL MSEL(3:1) rl(8:1) rl(16:9) ll(8:1) ll(16:9) ckc(8:1) ckc(16:9) DM_FE(2:1) DM(2:1) LOSS ERRL fail_ne fail_fe resync_ne resync_fe errc(7:0) RESERVED Table Memory
Line code polarity select. Clock edge select transmit clocks. Clock edge select receive clocks. Remote loop-back maintenance channel. Remote loop-back maintenance channel. Clock direction select maintenance channel. Maintenance channel data rate select. Remote loop-back main channels Remote loop-back main channels Local loop-back main channels Local loop-back main channels Clock direction select main channels Clock direction select main channels Configuration (full-duplex/master/slave) far-end. Configuration (full-duplex/master/slave). Data carrier detect status. Loss signal status. Error latch. Alarm indication near-end receive fail. Alarm indication far-end receive fail. Near-end device entered re-synchronization. Far-end device entered re-synchronization. Near-end remote loop-back detect (any channel). Far-end local loop-back detect (any channel). 8-bit saturating error counter (reset write).
Description
Device identification number. Channel enable (active low) channels Channel enable (active low) channels Enable remote control. Data rate select.
ACS5010CS PRE-RELEASE Issue BETA January 1999.
ERRC ERRL Error Detection
These signals used give indication quality optical link. Even when signal applied data, maintenance TCLK inputs, ACS5010CS modem transmits data over link each direction Fsys system frequency. This transmit control data used maintain timing synchronisation. transmit control data constantly monitored make sure compatible with 8B10B format. coding error detected ERRL will High will remain High until reset. ERRL reset asserting PORB, removing fiber optic cable from side link thereby forcing device temporarily lock.
Latency system calculated delay RAMs (until read-out RAMs activated), max. time between slots frame dTmax, fiber delay Assuming:
Max. delay RAMS: buffer size
dTRAM [us] [bytes] [Mbps] Max. time between slots frame (see section 4.7.4): dTmax [us] ((Td TRunin Tfhc) nr_of_channels) [cycles] FLink [MHz]
Fiber Delay:
[us] [us/km] [km] Max. Latency relation Fiber Length: [us] dTRAM dTmax [us/km] [km]
maximum latency possible fiber length depend final FIFO implementation, shown that even with conservative values specification values 500us 25km more than fulfilled. therefore expected that link budget, determined maximum Laser transmit power receiver sensitivity, will limit maximum possible fiber length.
ACS5010CS PRE-RELEASE Issue BETA January 1999.
Latency Fiber Length
Please note that ERRL ERRC detect 8B10B coding errors data errors, nevertheless because complexity coding rules employed ACS5010CS, absence detected errors these pins will give good indication high quality link.
ERRC produces pulse detection each coding error. These pulses accumulated means external electronic counter.
Description
Table indicates descriptions ACS5010. numbers given correspond physical order final package.
Name TPOS1 TPOS16 TNEG1 TNEG16 TCLK1 TCLK16 RPOS1 RPOS16 RNEG1 RNEG16 RCLK1 RCLK16 TMCLK RMCLK uPSEL1 uPSEL3 Txdat+ TxdatRxdat+ RxdatENTX IREF PORB LOSS ERRL ERRC POL1 POL3 RESEL TRSEL Description Transmit channels corresponds bipolar signal data signal. Transmit channels corresponds bipolar signal. Transmit clocks Samples TPOS/TNEG edge selected TRSEL control. Receive channels corresponds bipolar signal data signal. Receive channels corresponds bipolar signal. Receive clocks to16. RPOS/RNEG data valid edge selected RESEL control. Transmit data maintenance channel. Framing input maintenance channel. Bit-locked TMD. Transmit clock maintenance channel. Samples TMD/TMF edge selected TRSEL control. Receive data maintenance channel. Framing output maintenance channel. Receive clock maintenance channel. RMD/RMF data valid edge selected RESEL control. address data. address. chip select (active low). address latch enable. read (active low). write (active low). ready data acknowledge. interface mode control. Positive differential transmit data out. Negative differential transmit data slicing level Txdat+) Positive differential receive data Negative differential receive data slicing level Rxdat+) Enable transmitter Crystal oscillator input Crystal oscillator output Current reference Power-on reset
MSEL1 MSEL3 ENRSB VDDA1 VDDA2 GNDC1 GNDC4 VDDC1 VDDC2 GNDP1 GNDP6 VDDP1 VDDP6
Notes: Test pins, visible user (VDD, IC). Full custom analog
Analog supply. Digital core ground, Digital core supply, Digital peripheral ground, Digital peripheral supply, Table
Data carrier detect Loss signal Error latch Error count pulse Data rate select Diagnostic configuration mode select Line code polarity select Clock edge select receive clocks. When RESEL=0, data valid falling edge RCLK1-16 RMCLK Clock edge select transmit clocks. When TRSEL=0, data latched falling edge TCLK1-16 TMCLK Clock select main channels. When CKC=0, TCLK1-16 configured outputs (internal clocks). When CKC=1, TCLK1-16 configured inputs (external clocks). Clock select maintenance channel. When CKM=0, TMCLK configured output (internal clock). When CKM=1, TMCLK configured input (external clock). Maintenance Channel Data Rate Select. Enable remote control setup from far-end.
ACS5010CS PRE-RELEASE Issue BETA January 1999.
XTAL
iref
porb
rclk1 rpos1 LINE CODER rneg1
MULT CLOCK RESET GENERATION FIFO rxdatp rxdatn DATA SLICER 8B10B LOCK CONTROL
rclk16 rpos16 LINE CODER rneg16 rmclk tclk1 tpos1 LINE tneg1 tclk16 tpos16 LINE tneg16 tmclk
entx
CONTROL
FIFO
txdatp txdatn DIFF. DRIVER 8B10B CODER
MEMORY INTERFACE
upsel<2:1> ad<7:0> a<3:0>
Figure Block diagram ACS5010
MODE CONTROL STATUS loss errl errc
ACS5010CS PRE-RELEASE Issue BETA January 1999.
Figure System diagram ACS5010CS with Laser
ACS5010CS PRE-RELEASE Issue BETA January 1999.
Thin Quad Flat Pack
dimensions
E1/D1
0.05 14.00 1.60 0.15 0.05 24.00 1.60 0.15 1.45 1.45 1.35 0.50 0.27 0.75
1.35 0.80 0.45 0.17 0.75 0.45 26.00 0.10
0.30
0.45
Copl.
TQFP64
16.00 0.10
TQFP176
Figure Package information TQFP package
ACS5010CS PRE-RELEASE Issue BETA January 1999.
ACAPELLA ACS9020
2-Fiber Modem
Reserved, Internally Connected
Figure view TQFP package
ACS5010CS PRE-RELEASE Issue BETA January 1999.
2-Fiber Modem
ACAPELLA ACS5010
Reserved, Internally Connected
Figure view TQFP package
ACS5010CS PRE-RELEASE Issue BETA January 1999.
Acapella Ltd. Delta House Chilworth Research Centre Southampton S016 United Kingdom
Tel. Fax. Intn'l. Tel. Intn'l. Fax. 01703 01703 (0)1703 (0)1703 Email: sales@acapella.co.uk Web: www.acapella.co.uk Acapella wholly owned subsidiary
This pre-released version specification. Since specification likely change response customer feedback, please check with Acapella that have latest version specification.
interest further product development Acapella reserve right change this specification without further notice.
Copyright, Acapella Ltd. 1999
ACS5010CS PRE-RELEASE Issue BETA January 1999.
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