Introduction This application note presents circuit which implements d

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Introduction This application note presents circuit which implements d

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Pulse Width Modulated `Linear' Graph Display
Introduction This application note presents circuit which implements design programming techniques virtual peripherals. first technique reading value potentiometer measuring time takes partially charge capacitor through potentiometer. second technique displaying eight result simulated linear manner using pulse width modulation proportionally vary brightness adjacent LEDs graph composed sixteen LEDs. result signal that 'slides' smoothly down graph potentiometer rotated instead hopping from next.
LED16
LED15
LED14
X18AC
MCLR pot.
LED13
LED12
LED11
LED10
LED9
.047uF
LED8
LED7
LED6
LED5
text
LED4
LED3
R1-4
LED2
LED1
Figure Tested circuit pulse width modulated graph display.
circuit program work Both sections circuit virtual peripherals which take advantage SX's internal interrupts simplify programming timing issues. interrupt triggered each time RTCC rolls over (counts past restarts loading OPTION register with appropriate value, RTCC count rate equal oscillator frequency, which internal 4MHz oscillator this case. close interrupt sequence, predefined value loaded into register using RETIW instruction which determines period interrupt RTCC cycles. Reading potentiometer read value potentiometer, measure partial charging time (until port input triggers high) simple circuit, which directly proportional potentiometer value. begins timing measurement discharging capacitor through port setting port output driving low, thereby essentially shorting capacitor ground through current-limiting resistor which prevents damage1 port. program code leaves port RA.0 long enough assure that capacitor discharged enough affect next reading more than 1/256th 0.4% maintain resolution order bits. then clears charge time counter register switches port RA.0 input begin charging capacitor through potentiometer. increments charge time register until capacitor charges enough trigger input reading high port. reduce power consumption avoid high current draws through potentiometer when near lower limit, program waits specified time between potentiometer samples before clearing taking another reading. capacitor potentiometer values chosen that potentiometer maximum value, time charge capacitor enough trigger input high provide timing resolution will just slightly above 256) interrupt cycles since each interrupt cycle corresponds pass through count loop. using `RETIW int_period' instruction interrupt, RTCC rolls over interrupt triggered every int_period2 RTCC cycles3. With running internal 4MHz oscillator turbo mode (i.e. RTCC count/hardware clock count), interrupt timing tinterrupt int_period 4MHz µsec, t256 loops 12.8 msec Starting with potentiometer knowing that port input triggers high about 0.25Vcc, formula V=Vcc(1-e-t/RC) charging voltage capacitor after time calculate required capacitor value:
limits maximum discharge current through port under 30mA (i.e. Rdischarge Imax 30mA 167). practice, small capacitor values order 0.01µF less), probably even omitted, since total charge stored capacitor minimal shouldn't damage
value int_period variable controls interrupt period. suggested that minimum value this variable kept longer than longest possible interrupt routine duration (converted RTCC counts), maximum value should 256, which case int_period=0. Values less than execution time interrupt routine will cause interrupt periods longer than RTCC counts.
Actual cycle count multiples int_period RTCC operating with prescaler other than
0.25Vdd e-t/RC) hence: ln(1 0.25)) 12.8 10-3 ln(0.75)) 0.044
want sure whole counter range, choose little large order that charge time extends slightly beyond iterations count loop when potentiometer maximum, hence value 0.047uF4. Then, within capacitor charge counting loop, also watch charge time counter overflow skip ahead with charge time value maximum when this occurs that graph doesn't loop around display values again potentiometer near maximum). allow tolerance values capacitor potentiometer, final adjustments made int_period variable assure that whole 0-255 range properly spanned potentiometer. graph output pulse-width modulation often desirable minimize number pins used while maximizing number devices accessed. effective cost-efficient manner doing this pins matrix read devices such switch/keypad inputs this case, outputs access array LEDs. While LEDs physically positioned after another line graph, circuit connections made matrix using only port pins rather than program code then controls which column active which then lights corresponding LED. Here have used high bits port source output rows LEDs lower bits sink (output=low) input columns. Since have LEDs value potentiometer input 0-255 bits), create smooth linear signal 'slide' effect using pulse width modulation partially proportionally light adjacent LEDs when output value lies between them. example, assume read potentiometer value Since there LEDs, this value would correspond number 44/16=2.75. Normally this case, we'd have choose between LEDs, using pulse width modulation resolve fraction after decimal point sending duty cycle second duty cycle third one, providing visual effect that signal somewhere between LEDs, closer (3/4 way) one. higher nibble potentiometer reading select which LED(s) will lit, lower nibble pulse width modulation duty cycle calculation, which makes possible levels brightness. During each interrupt cycle, pulse width modulation duty cycle count incremented, with lookup table, matrix port light appropriate LED. this way, each reading value from 0-255 given unique output pattern graph. Resistors R1-4 limit current LEDs, which 100% duty cycle draw ILED Vdd/R 5V/220 23mA. values R1-4 adjusted reduce/increase overall brightness, though source/sink maximum port current limit should kept mind.
value changed, clear_time constant discharging should also adjusted appropriately.
Program Listing
Pulse Width Modulated 'Linear' Graph Display Copyright 1998 Length: bytes Author: Craig Webb Written: 97/02/26 This program implements virtual peripherals using interrupts. shows read potentiometer value pulse width modulate bar-graph LEDs arranged matrix port order provide smooth 'sliding' signal effect varying brightness adjacent LEDs when potentiometer value lies somewhere between them. ;****** Assembler directives DEVICE DEVICE osc4mhz,turbo LEDs' RESET Start ;set reset/boot address Program Variables *************************** ;****** Register definitions (bank ;global variables 08-0Fh reading ;potentiometer reading display ;LED output display flags ;program flags variables interrupt routine ;bank variables mainbank LED_bank ;(can other than bank ;holds which light cycle_count ;pwm cycle count pot_count ;temporary timing count clear_delay ;delay period clear cap. sample_delay ;delay period sample (reduces power consumption) ;****** variable definitions RA.0 ;potentiometer (input) triggered flags.0 ;status pot. reading clearing flags.1 while cap. clearing ;****** Constants sample_time ;time between pot. readings clear_time ;delay value clearing capacitor (>=2) int_period ;interrupt period (based RTCC counts) IO_portA 00001111b ;Port input/output setup LEDs_off value LEDs=off ;************************* Interrupt Routines ****************************
;***** Virtual Peripheral Read potentiometer This routine reads value potentiometer clearing capacitor timing circuit then measuring time takes capacitor charge until port input goes high. avoid high current draws potentiometer values, routine only resamples after (256*sample_time) interrupt cycles. maximum potentiometer reading 255. Input variable(s) none Output variable(s) reading Variable(s) affected pot_count, clear_delay, sample_delay Flag(s) affected clearing, triggered Timing cycles (turbo) 12-charging, 14-triggered, 14-clearing clearing,:charge ;are clearing cap.? W,#11111111b ;get port mask (=done) DECSZ clear_delay count done? W,#11111110b ;no, port mask (=clearing) TEST clear_delay count done? not, skip ahead CLRB clearing ;yes, reset clearing flag W,#IO_portA ;get port setup byte !RA,W ;adjust port status pot_count ;clear timing count :done_pot ;jump past checking routine :charge pot,:adjust_count ;triggered yet? W,pot_count ;get timing count triggered this first trigger cycle? reading,W ;yes, store result SETB triggered ;set trigger flag :adjust_count INCSZ pot_count ;adjust reading counter :done_pot ;was counter maximum? W,#255 ;no, store max. value triggered ;did already reading? reading,W ;no, max. SETB triggered flag that value DECSZ sample_delay ;time sample? :done_pot not, keep cycling :trig CLRB triggered ;yes, reset trigger flag SETB clearing ;set flag clear cap. sample_delay,#sample_time ;load sample clear_delay,#clear_time clear delay time counts :done_pot ;end pot. reading routine ;***** Virtual Peripheral driver This routine drives bar-graph array, providing levels brightness allow output slide effect between adjacent LEDs must called fairly often, otherwise pulsing effect will become noticeable. Input variable(s) display Output variable(s) none Variable(s) affected cycle_count, Timing cycles (turbo) ;next instruction needed only multiple variable banks used W,<>display ;get input (nibble-swapped) W,#0Fh ;keep high bits (which LED) LED,W ;save W,display ;get input reading again W,#00001111b ;keep lower bits W,cycle_count-W ;calculate which have :zero_point ;adjust zero baseline one* ;next skip ahead
CALL
W,LED LED_Table RB,W cycle_count cycle_count.4 cycle_count
;yes, increment next ;get number ;fetch value ;light ;adjust cycle ;time reset cycles)? ;yes, start cycle
;*this instruction shifts whole display range one, thus making first dimly reading last fully reading 255. it's preferable that LEDs reading this instruction removed commented out. W,#-int_period ;interrupt again after RETIW 'int_period' RTCC counts Subroutines ;***** Subroutine LED_Table This look-up table that returns output port value light contained register. holds then LEDs turned off. LED_Table PCL,W ;get value LED1-16 RETW ;LEDs RETW ;LED1 RETW ;LED2 RETW ;LED3 RETW ;LED4 RETW ;LED5 RETW ;LED6 RETW ;LED7 RETW ;LED8 RETW ;LED9 RETW ;LED10 RETW ;LED11 RETW ;LED12 RETW ;LED13 RETW ;LED14 RETW ;LED15 RETW ;LED16 Main Program ******************************* ;***** Initialization routine Start ;clear port !RA,#IO_portA ;set port RB,#LEDs_off ;set LEDs !RB,#0 ;configure port outputs ;reset starting :zero_ram FSR.4 ;are half bank? SETB FSR.3 don't touch regs ;clear using indirect addressing IJNZ FSR,:zero_ram ;repeat until done !OPTION,#10001000b ;enable interrupt rtcc=xtal/1 sample_delay,#sample_time ;load sampling period ;***** Main program loop Mainloop display,reading ;copy pot. output display <program code goes here>
Mainloop
;keep looping

Introduction This application note presents circuit which implements d

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