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34COM/100SEG DRIVER CONTROLLER MATRIX KS0075 matrix driver contro


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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
KS0075 matrix driver controller which fabricated power CMOS technology. display lines with dots format.
FUNCTIONS
Character type matrix driver controller Internal driver common segment signal output Easy interface with 4-bit 8-bit Clock synchronized serial Interface matrix possible matrix possible Bi-directional shift function character reverse display Display shift line Voltage converter drive voltage times times) Various instruction functions Automatic power reset
FEATURES
Internal Memory Character Generator (CGROM) 9,600 bits (240 characters dot) Character Generator (CGRAM) bits characters dot) Segment Icon (SEGRAM) bits icons max.) Display Data (DDRAM) bits characters max.) power operation Power supply voltage range (VDD) Drive voltage range 13.0 (VDD CMOS process Programmable duty cycle 1/17, 1/33 (refer Table Internal oscillator with external resistor Bare chip available
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34COM/100SEG DRIVER CONTROLLER MATRIX
Table Programmable duty cycles 5-dot font width Display Line Numbers 1/17 1/33 1/33 Duty Ratio Single-chip Operation Displayable characters line characters lines characters line characters Possible icons
6-dot font width Display Line Numbers 1/17 1/33 1/33 Duty Ratio Single-chip Operation Displayable characters line characters lines characters line characters Possible icons
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BLOCK DIAGRAM
OSC1 OSC2
Oscillator Power Reset (POR) RESET System Interface Serial Instruct Register (IR) Instruction Decoder
Timing Generator
Display Data (DDRAM) Address Counter bits
Shift Register
Common Driver
COM0 COM33
Input/ Output Buffer
Data Register (DR)
Shift Latch Segment Driver SEG1 SEG100
Register Circuit
Busy Flag DB0/
Segment (SEGRAM) bytes
Character Generator RAM(CGRAM) bytes
Character Generator Cursor ROM(CGROM) Blink 9600 bits Controller
Driver Voltage Selector
V5OUT2 V5OUT3
Voltage Converter
Parallel Serial Converter Smooth Scroll Circuit
(VSS)
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CONFIGURATION
SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33
SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34
chip size 7450 5340 size unit
SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24
OSC2 OSC1 RESET VSS1 RS/CS RW/SID E/SCLK DB0/SOD VSS2 V5OUT2 V5OUT3
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LOCATION
NUMBER
NAME
SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 COM9 COM10 COM11 COM12 COM13 COM14 COM15
COORDINATE
-2975 -2850 -2725 -2600 -2475 -2350 -2225 -2100 -1975 -1850 -1725 -1600 -1475 -1350 -1225 -1100 -975 -850 -725 -600 -475 -350 -225 -100 1024 1262 1387 1512 1637 1762 1887 2012 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504
NUMBER
NAME
COM16 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 OSC2 OSC1 RESET VSS1 RS/CS RW/SID E/SCLK DB0/SOD VSS2 V5OUT2 V5OUT3 COM24
COORDINATE
2137 2262 2387 2512 2637 2762 2887 3012 3137 3262 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3262 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -1750 -1625 -1500 -1375 -1250 -1125 -1000 -875 -750 -625 -500 -375 -250 -125 1000 1125 1250 1375 1500 1625 1750 2504
NUMBER
NAME
COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24
COORDINATE
3137 3012 2887 2762 2637 2512 2387 2262 2137 2012 1887 1762 1637 1512 1387 1262 1024 -100 -225 -350 -475 -600 -725 -850 -975 -1100 -1225 -1350 -1475 -1600 -1725 -1850 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504
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NUMBER
NAME
SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64
COORDINATE
-1975 -2100 -2225 -2350 -2475 -2600 -2725 -2850 -2975 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 2504 2504 2504 2504 2504 2504 2504 2504 2504 2062 1937 1812 1687 1562 1437 1312 1187 1062 -187 -312 -437 -562 -687 -812 -937 -1062 -1187 -1312 -1437 -1562 -1687
NUMBER
NAME
SEG65 SEG66 SEG67
COORDINATE
-3559 -3559 -3559 -1812 -1937 -2062
NUMBER
NAME
COORDINATE
"KS0075" Marking easy find No.115
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DESCRIPTION
(NO) INPUT/ OUTPUT (51) VSS1,VSS2 (57,72) (69) SEG1 SEG100 163, COM0 COM33 OSC1,OSC2 (53,52) Input (OSC1), Output (OSC2) C1,C2 (71,70) Input External capacitance input RESET (54) (56) Input Input Reset Select instruction V5OUT2(73) Output times converter output V5OUT3(74) Three times converter output voltage converter(2 times times), these pins must connected external capacitance. Initialized When "High", selected Instruction External capacitance Oscillator When internal oscillator, connect external External resistor. resistor/oscillator external clock used, connect OSC1. (OSC1) Input Output Input voltage voltage converter generate drive voltage(Vci 1.0-4.5V). Segment output Segment signal output drive. Power supply Bias voltage level driving. Power supply logical circuit(+3V,+5V) 0V(GND) NAME DESCRIPTION INTERFACE
Output
Common output Common signal output drive.
Table
When "Low", Instruction selected Table value converted times. three times converter, same capacitance that C1-C2 should connected here. value converted three times. capacitance
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DESCRIPTION (continued)
(NO) INPUT/ OUTPUT (55) Input Interface mode selection Register select/ Chip select Select Interface mode with MPU. When "Low" Serial mode, When "High" 4-bit/8-bit mode. RS/CS (58) Input mode, used register selection input. When RS/CS "High", Data register selected. When RS/CS "Low", Instruction register selected. serial mode, used chip selection input. When RS/CS "Low", selected. When RS/CS "High", selected.(Low access enable) RW/SID (59) Input mode, used read/write selection input. When RW/SID "High", read operation. When Serial input data RW/SID "Low", write operation. Read_write/ serial mode, used data input pin. E/SCLK (60) Input Read_write enable/Serial clock Data bit/Serial output data Data mode, used read_write enable signal. serial mode, used serial clock input pin. 8-bit mode, used lowest bi-directional data bit. During 4-bit mode, Open this pin. serial mode, used serial data output pin. read operation, open this pin. 8-bit mode, used order bidirectional data bus. During 4-bit mode serial mode, open these pins. 8-bit mode, used high order bidirectional data bus. case 4-bit mode, used both high order. used Busy Flag output. During serial mode, open these pins. NAME DESCRIPTION INTERFACE
DB0/SOD (61)
Input_Output/ Output
Input. Output
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FUNCTION DESCRIPTION
System Interface This chip three kinds interface type with serial, 4-bit 8-bit bus. Serial bus(4-bit/8-bit) selected input, 4-bit 8-bit selected instruction register. During read write operation, 8-bit registers used. data register (DR), other instruction register(IR). data register(DR) used temporary data storage place being written into read from DDRAM/CGRAM/SEGRAM, target selected address setting instruction. Each internal operation, reading from writing into RAM, done automatically. Hence, after reads data, data next DDRAM/CGRAM/SEGRAM address transferred into automatically. Also after writes data data transferred into DDRAM/CGRAM/SEGRAM automatically. Instruction register(IR) used only store instruction code transferred from MPU. cannot read instruction data. select register, RS/CS input 4-bit/8-bit mode(IM "High") serial mode(IM "Low").
Table Various kinds operations according bits. Operation Instruction Write operation (MPU writes Instruction code into Read Busy flag(DB7) address counter (DB0 DB6) Data Write operation (MPU writes data into Data Read operation (MPU reads data from
Busy Flag (BF) When "High", indicates that internal operation being processed. during this time next instruction cannot accepted. read, when High(Read Instruction Operation), through port Before executing next instruction, sure that High.
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Display
Data (DDRAM)
DDRAM stores display data maximum bits characters). DDRAM address address counter (AC) hexadecimal number. (refer Fig-1.)
Fig-1. DDRAM Address
Display 5-dot font width character 5-dot line display case line display with 5-dot font, address range DDRAM 4FH. (Refer Fig-2)
COM1 COM8
SEG1
SEG100
Display position
COM9
KS0075
SEG1
DDRAM addresss KS0075
COM16 SEG100
COM1 COM8
COM9 COM16
(After Shift Left)
COM1 COM8
COM9 COM16
(After Shift Right)
Fig-2. 1-line 40ch. display
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5-dot line display case line display with 5-dot font, address range DDRAM 27H, 67H. (Refer Fig-3)
COM1 COM8 COM17 COM24
SEG1
SEG100
Display position
COM9 COM16 COM25 COM32
KS0075
SEG1
DDRAM addresss KS0075
SEG100
COM1 COM8 COM17 COM24
COM9
COM16
COM25 COM32
(After Shift Left)
COM1 COM8 COM17 COM24
COM9 COM16 COM25 COM32
(After Shift Right)
Fig-3. 2-line 40ch. display (5-dot font width)
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5-dot line display case line display with 5-dot font, address range DDARM 13H, 33H, 53H, 73H. (Refer Fig-4)
COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32
Display position DDRAM addresss
SEG100
SEG1
KS0075
COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32
(After Shift Left)
COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32
(After Shift Right)
Fig-4. 4-line 20ch. display (5-dot font width)
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Display 6-dot font width character When this device used 6-dot font width mode, SEG97,SEG98,SEG99 SEG100 must open. 6-dot line display case line display with 6-dot font, address range DDRAM 4FH. (Refer Fig-5)
Display position
COM1 COM8 COM9 COM16
SEG1
SEG96
KS0075
SEG96 SEG1
DDRAM addresss KS0075
COM1 COM8
COM9 COM16
(After Shift Left)
COM1 COM8 COM9 COM16
(After Shift Right)
Fig-5. 1-line 32ch. display
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6-dot line display case line display with 6-dot font, address range DDRAM 27H, 67H. (refer Fig-6)
Display
COM1 COM8 COM17 COM24
COM9 COM16
COM25
KS0075
SEG96
DDRAM addresss KS0075
SEG96
COM1 COM8 COM17 COM24
COM9 COM16 COM25 COM32
(After
Left)
COM1 COM8 COM17 COM24
COM9 COM16 COM25 COM32
(After Shift Right)
Fig-6. 2-line 32ch. display (6-dot font width)
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6-dot line display case line display with 6-dot font, address range DDARM 13H, 33H, 53H, 73H. (refer Fig-7)
COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32
SEG96
Display position DDRAM addresss
SEG1
KS0075
COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32
(After Shift Left)
COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32
(After Shift Right)
Fig-7. 4-line 16ch. display (6-dot font width)
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Timing Generation Circuit Timing generation circuit generates clock signals internal operations. Address Counter (AC) Address Counter(AC) stores DDRAM/CGRAM/SEGRAM address, transferred from After writing into (reading from) DDRAM/CGRAM/SEGRAM, automatically increased (decreased) When "Low" "High", read through ports Cursor/Blink Control Circuit controls cursor/blink ON/OFF black/white inversion cursor position. Driver Circuit Driver circuit common segment signals driving. Data from SEGRAM/CGRAM/CGROM transferred 100-bit segment latch serially, which stored 100-bit shift latch. When each common selected 34-bit common register, segment data also output through segment driver from 100-bit segment latch. 1-line display mode, COM0 COM17 have 1/17 duty, 2-line 4-line mode, COM0-COM33 have 1/33 duty ratio.
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CGROM (Character Generator ROM) CGROM 8-dot character pattern. (refer Table Table CGROM Character Code Table
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CGRAM (Character Generator RAM) CGRAM 8-dot characters. writing font data CGRAM, user defined character used. (Refer Table
Table Relationship between Character Code(DDRAM) Character Pattern(CGRAM) Character pattern
Character Code(DDRAM data)
CGRAM address
CGRAM data
Pattern number pattern
pattern
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Character pattern
Character Code(DDRAM data)
CGRAM address
CGRAM data
Pattern number pattern
pattern
When BE(Blink Enable bit) "HIGH", blink controlled bit. displaying 5-dot font width, when "1", enabled dots will blink, when "1", enabled dots will blink, when "0", blink will happen. displaying 6-dot font width, when "1", enabled dots will blink, when "1", enabled dots will blink, when "0", blink will happen. Don't care
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SEGRAM (Segment Icon RAM) SEGRAM segment control data segment pattern data. During 1-line display mode, COM0(COM17) makes data SEGRAM enable display icons. When used 2/4-line display mode COM0(COM33) does that. higher 2-bits blinking control data, lower 6-bits pattern data. (refer Table Fig-8) Table Relationship between SEGRAM address display pattern
SEGRAM address
SEGRAM data display pattern 5-dot font width 6-dot font width
Blinking control Control Blinking Port 5-dot font width blink blink 6-dot font width blink blink
S1~S80 Icon pattern ON/OFF 5-dot font width S1~S96 Icon pattern ON/OFF 6-dot font width Don't care
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5-dot font width
S100
6-dot font width
Fig-8. Relationship between SEGRAM segment display
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INSTRUCTION DESCRIPTION
OUTLINE overcome speed difference between internal clock KS0075 clock, KS0075performs internal operation storing control information internal operation determined according signal from MPU, composed read/write data bus. (refer Table 6/10) Instruction divided largely four kinds, KS0075 function instructions display methods, data length, etc.) address instructions internal data transfer instructions with internal others address internal automatically increased decreased When "High", KS0075 operated according Instruction 1(Table when "Low", KS0075 operated according Instruction 2(Table 10).
Note During internal operation, Busy Flag (DB7) read High. Busy Flag check must precede next instruction. When program with Busy Flag(DB7) checking made, fosc necessary) executing next instruction falling edge signal after Busy Flag(DB7) goes "Low".
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INSTRUCTION DESCRIPTION "High")
Table Instruction
Instruction
Instruction Code
Description
Execution Time (fosc kHz)
Clear Display Return Home
Write "20H" DDRAM. DDRAM address "00H" from DDRAM address "00H" from return cursor original position shifted. contents DDRAM changed. power down mode bit. :power down mode set, :power down mode disable Assign cursor moving direction. increment, decrement
1.53ms
1.53ms
Power Down Mode
39µs
Entry Mode
display shift enable bit. make display shift enabled lines bits Shift Enable instruction. "0":display shift disable Segment bi-direction function.
Seg100 Seg1, Seg1 Seg100. display/cursor/blink on/off display
Display ON/OFF Control
display off, cursor cursor off, blink blink off. Assign font width, black/white inverting cursor, 4-line display mode control bit. 6-dot font width, 5-dot font width, black/white inverting cursor enable, black/white inverting cursor disable 4-line display mode, 1-line 2-line display mode.
Extended function
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(Table continued) Instruction Instruction Code Cursor Display Shift Cursor display shift. display shift, cursor shift, shift right, shift left. (when "1") Determine line display shift "1/0": line display shift enable/disable "1/0": line display shift enable/disable "1/0": line display shift enable/disable "1/0": line display shift enable/disable. (when "0") Determine line horizontal smooth scroll. "1/0" line scroll enable/disable "1/0" line scroll enable/disable "1/0" line scroll enable/disable "1/0" line scroll enable/disable. interface data length 8-bit, 4-bit), numbers display line when "0", 2-line, 1-line), extension register, RE("0"), shift/scroll enable display shift enable scroll enable. reverse reverse display, normal display. RE("1") CGRAM/SEGRAM blink enable (BE) 1/0" CGRAM/SEGRAM blink enable/disable Execution Description Time (fosc kHz)
Shift Enable
Scroll Enable
Function
RE(0)
RE(1)
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(Table continued) Instruction Instruction Code CGRAM Address SEGRAM Address DDRAM Address Scroll Quantity Read Busy flag Address Write Data Read Data known whether during internal operation reading contents address counter also read. busy state, ready state. Write data into internal (DDRAM CGRAM SEGRAM). Read data from internal (DDRAM CGRAM SEGRAM). quantity horizontal scroll. DDRAM address address counter. SEGRAM address address counter. CGRAM address address counter. Execution Description Time (fosc kHz)
Note When program with Busy Flag(DB7) checking made, fosc necessary) executing next instruction signal after Busy Flag (DB7) goes "Low". Don't care
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Display Clear
Clear display data writing "20H" (space code) DDRAM address, DDRAM address "00H" into (address counter). Return cursor original status, hence, bring cursor left edge first line display. Make entry mode increment (I/D "1").
Return Home
Return Home cursor return home instruction. DDRAM address "00H" into address counter. Return cursor original site return display original status, shifted. Contents DDRAM does change.
Power Down Mode
Power down mode enable instruction. "High", makes KS0075 suppress current consumption except current needed data storage executing next three functions. make output value COM/SEG ports make COM/SEG output value extension driver setting output "High" output "Low" disable voltage converter remove current through divide resistor power supply. This instruction used power sleep mode. When "Low", power down mode becomes disabled.
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Entry Mode
moving direction cursor display. Increment decrement DDRAM address (cursor blink) When "High", cursor/blink moves right DDRAM address increased When "Low", cursor/blink moves left DDRAM address decreased CGRAM/SEGRAM operates same DDRAM, when read from write CGRAM/SEGRAM. When "High", after DDRAM write, display enabled line bits Shift Enable instruction shifted right (I/D "0") left(I/D "1"). will seem cursor does move. When "Low", DDRAM read, CGRAM/SEGRAM read/write operation, shift display like this function performed.
data shift direction segment application set. Data Shift Direction Segment When "Low", segment data shift direction normal order from SEG1 SEG100. When "High", segment data shift direction reverse from SEG100 SEG1. using this instruction, efficiency application board area raised. setting instruction recommended same time level function instruction. must "1".
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Display ON/OFF Control
Control display/cursor/blink ON/OFF register. Display ON/OFF control When "High", entire display turned When "Low", display turned off, display data remained DDRAM. Cursor ON/OFF control When "High", cursor turned When "Low", cursor disappeared current display, register remains data. Cursor Blink ON/OFF control When "High", cursor blink that performs alternate between high data display character cursor position. fosc frequency, blinking interval. When "Low", blink off.
Extended Function
Font Width control When "High", display character font width assigned 6-dot execution time becomes times than that 5-dot font width. user font, specified CGRAM, displayed into 6-dot font width, bit-5 bit-0,including leftmost space CGRAM.(refer Fig-9) When "Low", 5-dot font width set. Black/White Inversion enable When "High", black/white inversion cursor position set. this case display ON/OFF control instruction becomes don't care condition. fosc frequency kHz, inversion intervals. Line mode enable When "High", line display mode set. this case function instruction becomes don't care condition.
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6-bit
CGROM character (5-dot)
6-bit
CGRAM character font (6-dot
(CGROM)
(CGRAM)
Fig-9. 6-dot font width CGROM/CGRAM
Cursor Display Shift
Shift right/left cursor position display, with writing reading display data, This instruction used correct search display data.(refer Table During 2-line mode display, cursor moves line after 40th digit line. 4-line mode, cursor moves next line, only after every 20th digit current line. Note that display shift performed simultaneously line enabled Shift Enable instruction. When displayed data shifted repeatedly, each line shifted individually. When display shift performed, contents address counter changed. During power consumption mode, display shift performed normally.
Table Shift patterns according bits Operation Shift cursor left, ADDRESS COUNTER decreased Shift cursor right, ADDRESS COUNTER increased Shift display left, cursor moves according display Shift display right, cursor moves according display
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Shift/Scroll Enable
Horizontal Scroll Line Enable This instruction makes valid shift display line unit. HS1, HS2, indicate each line scrolled, each scroll performed individually each line. line 1-line display mode line 2-line display mode, scrolled "High". line scroll needed 2-line mode, "High". (refer Table
Display Shift Line Enable This instruction selects shifting line shifted according each line mode display shift right/left instruction. DS1, DS2, indicate each line shifted, each shift performed individually each line. "High" (enable) line mode, only line shifted line shifted. When only "High", only half line shifted. bits (DS1 DS4) "Low" (disable), display shifted.
Table Relationship between signal Enable HS1/DS1 HS2/DS2 HS3/DS3 HS4/DS4 Enabled common signals during shift COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32 part display line that corresponds enabled common signal shifted. Description
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Function
Interface data length control When "High", means 8-bit mode with MPU. When "Low", means 4-bit mode with MPU. Hence, signal select 8-bit 4-bit mode. 4-bit mode, required transfer 4-bit data twice. Display line number control variable only when extended function instruction Low. When "Low", means 1-line display mode. When "High", 2-line display mode set. When "High", invalid, means 4-line mode independent bit. Extended function registers enable this instruction, must "Low". Display shift enable selection bit. When "High", enable display shift line. When "Low", enable smooth scroll. This accessed only when input "High". Reverse enable When "High", display data reversed. I.e., black black dots become white. When "Low", display mode normal display.
white dots become
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Interface data length control When "High", means 8-bit mode with MPU. When "Low", means 4-bit mode with MPU. Hence, signal select 8-bit 4-bit mode. When 4-bit mode, required transfer 4-bit data twice. Display line number control variable only when extended function instruction Low. When "Low", 1-line display mode set. When "High", 2-line display mode set. When "High", invalid, means 4-line mode independent bit. Extended function registers enable When "High", extended function registers, SEGRAM address registers, bit, HS/DS bits shift/scroll enable instruction bits function register accessed. CGRAM/SEGRAM data blink enable ="High", makes user font CGRAM segment SEGRAM blinking. quantity blink assigned highest CGRAM/SEGRAM.
CGRAM Address
CGRAM address This instruction makes CGRAM data available from MPU.
SEGRAM Address
CGRAM address This instruction makes CGRAM data available from MPU.
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DDRAM Address
DDRAM address This instruction makes DDRAM data available from MPU. 1-line display mode DDRAM address from "00H" "4FH". 2-line display mode DDRAM address line from "00H" "27H", DDRAM address line from "40H" "67H". 4-line display mode DDRAM address from "00H" "13H" line, from "20H" "33H" line, from "40H" "53H" line from "60H" "73H" line.
Scroll Quantity
Setting SQ0, horizontal scroll quantity controlled units. (Refer Table this case KS0075 show hidden areas DDRAM executing smooth scroll from dots.
Table Scroll quantity according bits Function shift shift left 1-dot shift left 2-dot shift left 3-dot shift left 47-dot shift left 48-dot
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Read Busy Flag Address
This instruction shows whether KS0075 internal operation not. resultant High, internal operation progress have wait until Low, which then next instruction performed. this instruction value address counter also read.
Write data
Write binary 8-bit data DDRAM/CGRAM/SEGRAM. selection from DDRAM, CGRAM, SEGRAM, previous address instruction DDRAM address set, CGRAM address set, SEGRAM address set. instruction also determines direction RAM. After write operation, address automatically increased/decreased according entry mode.
Read data from
Read binary 8-bit data from DDRAM/CGRAM/SEGRAM. selection previous address instruction. address instruction performed before this instruction, data that read first invalid, direction determined. data read several times without address instruction before read operation, correct data obtained from second, first data would incorrect, there time margin transfer data. DDRAM read operation, cursor shift instruction plays same role DDRAM address instruction also transfer data output data register. After read operation address counter automatically increased/decreased according entry mode. After CGRAM/SEGRAM read operation, display shift executed correctly. case write operation, increased/decreased read operation after this. this time, indicates next address position, previous data only read read instruction.
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34COM/100SEG DRIVER CONTROLLER MATRIX
INSTRUCTION DESCRIPTION "LOW")
Table Instruction
Instruction
Instruction Code
Execution Description Time (fosc kHz) Write "20H" DDRAM. DDRAM address "00H" from DDRAM address "00H" from return cursor original position shifted. contents DDRAM changed. Assign cursor moving direction. increment, 1.53ms
Clear Display Return Home
1.53ms
Entry Mode
decrement. display shift enable bit. :make entire display shift lines during DDRAM write, "0":display shift disable display/cursor/blink on/off display
39µs
Display ON/OFF Control
display off, cursor cursor off, blink blink off. Assign font width, black/white inverting cursor, 4-line display mode control bit. 6-dot font width, 5-dot font width, 39µs
Extended function
black/white inverting cursor enable, black/white inverting cursor disable 4-line display mode, 1-line 2-line display mode Cursor display shift. display shift, cursor shift, shift right, shift left 39µs 39µs
Cursor Display Shift
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
(Table continued) Execution Instruction Instruction Code Determine line horizontal smooth scroll. "1/0" line scroll enable/disable "1/0" line scroll enable/disable "1/0" line scroll enable/disable "1/0" line scroll enable/disable interface data length 8-bit, 4-bit numbers display line when "0", 2-line, 1-line extension register, RE("0"), RE("1") CGRAM/SEGRAM blink enable (BE) 1/0" CGRAM/SEGRAM blink enable/disable CGRAM address address counter. Description Time (fosc kHz)
Scroll Enable
39µs
Function
RE(0)
39µs
RE(1)
39µs
CGRAM Address SEGRAM Address DDRAM Address Scroll Quantity Read Busy flag Address Write Data Read Data known whether during internal operation reading contents address counter also read. busy state, ready state. Write data into internal (DDRAM CGRAM SEGRAM). Read data from internal (DDRAM CGRAM SEGRAM). quantity horizontal scroll. 39µs DDRAM address address counter. 39µs SEGRAM address address counter. 39µs 39µs
43µs 43µs
Note When program with Busy Flag(DB7) checking made, fosc necessary) executing next instruction falling edge signal after Busy Flag(DB7) goes "Low" don't care
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34COM/100SEG DRIVER CONTROLLER MATRIX
Display Clear
Clear display data writing "20H" (space code) DDRAM address, DDRAM address "00H" into (address counter). Return cursor original status, hence, bring cursor left edge first line display. entry mode increment mode (I/D "1").
Return Home
Return Home cursor return home instruction. DDRAM address "00H" into address counter. site return display original status, shifted. Contents DDRAM does change.
Return cursor original
Entry Mode
moving direction cursor display. Increment decrement DDRAM address (cursor blink) When "High", cursor/blink moves right DDRAM address increased When "Low", cursor/blink moves left DDRAM address decreased CGRAM/SEGRAM operates identically DDRAM, when reading from writing CGRAM/SEGRAM. When "High", after DDRAM write, entire display lines shifted right (I/D "0") left(I/D "1"). will seem cursor does moving. When "Low", DDRAM read, CGRAM/SEGRAM read/write operation, shift entire display performed.
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34COM/100SEG DRIVER CONTROLLER MATRIX
Display ON/OFF Control
Control display/cursor/blink ON/OFF register. Display ON/OFF control When "High", entire display turned When "Low", display turned off, display data remained DDRAM. Cursor ON/OFF control When "High", cursor turned When "Low", cursor disappeared current display, register remains data. Cursor Blink ON/OFF control When "High", cursor blink that performs alternate between high data display character cursor position. fosc frequency, blinking interval. When "Low", blink off.
Extended Function
Font Width control When "High", display character font width assigned 6-dot execution time becomes times than that 5-dot font width. user font, specified CGRAM, displayed into 6-dot font width, bit-5 bit-0,including leftmost space CGRAM.(Refer Fig-10) When "Low", 5-dot font width set. Black/White Inversion enable When "High", black/white inversion cursor position set. this case display ON/OFF control instruction becomes don't care condition. fosc frequency kHz, inversion intervals. Line mode enable When "High", line display mode set. this case function instruction becomes don't care condition.
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
6-bit
CGROM character (5-dot)
6-bit
CGRAM character font (6-dot
(CGROM)
(CGRAM)
Fig-10. 6-dot font width CGROM/CGRAM
Cursor Display Shift
Shift right/left cursor position display, without writing reading display data This instruction used correct search display data.(Refer Table During 2-line mode display, cursor moves line after 40th digit line. 4-line mode, cursor moves next line, only after every 20th digit current line. Note that display shift performed simultaneously line. When displayed data shifted repeatedly, each line shifted individually. When display shift performed, contents address counter changed.
Table Shift patterns according bits Operation Shift cursor left, ADDRESS COUNTER decreased Shift cursor right, ADDRESS COUNTER increased Shift display left, cursor moves according display Shift display right, cursor moves according display
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34COM/100SEG DRIVER CONTROLLER MATRIX
Scroll Enable
Horizontal Scroll Line Enable This instruction makes valid shift display line unit. HS1, HS2, indicate each line scrolled, each scroll performed individually each line. line 1-line display mode line 2-line display mode scrolled, "High". line scroll needed 2-line mode, "High". (refer Table
Function
Interface data length control When "High", means 8-bit mode with MPU. When "Low", means 4-bit mode with MPU. speak, signal select 8-bit 4-bit mode. 4-bit mode, required transfer 4-bit data. Display line number control variable only when extended function instruction Low. When "Low", 1-line display mode set. When "High", 2-line display mode set. When "High", invalid, means 4-line mode independent bit. Extended function registers enable this instruction, must "Low".
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34COM/100SEG DRIVER CONTROLLER MATRIX
Interface data length control When "High", means 8-bit mode with MPU. When "Low", means 4-bit mode with MPU. Hence, signal select 8-bit 4-bit mode. 4-bit mode, required transfer 4-bit data twice. Display line number control variable only when extended function instruction Low. When "Low", 1-line set. When "High", 2-line display mode set. When "High", invalid, 4-line mode independent bit. Extended function registers enable When "High", extended function registers, SEGRAM address registers, bits scroll enable instruction bits function register accessed. CGRAM/SEGRAM data blink enable "High", makes user font CGRAM segment SEGRAM blinking. quantity blink assigned highest CGRAM/SEGRAM.
CGRAM Address
CGRAM address This instruction makes CGRAM data available from MPU. SEGRAM Address
SEGRAM address This instruction makes SEGRAM data available from MPU.
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34COM/100SEG DRIVER CONTROLLER MATRIX
DDRAM Address
DDRAM address This instruction makes DDRAM data available from MPU. 1-line display mode DDRAM address from "00H" "4FH". 2-line display mode DDRAM address line from "00H" "27H", DDRAM address line from "40H" "67H". 4-line display mode DDRAM address from "00H" "13H" line, from "20H" "33H" line, from "40H" "53H" line from "60H" "73H" line.
Scroll Quantity
Setting SQ0, horizontal scroll quantity controlled units. (Refer Table 12). this case KS0075 execute smooth scroll from dots.
Table Scroll quantity according bits Function shift shift left 1-dot shift left 2-dot shift left 3-dot shift left 47-dot shift left 48-dot
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
Read Busy Flag Address
This instruction shows whether KS0075 internal operation not. resultant High, means internal operation progress should wait until become "Low". Which then next instruction performed. this instruction value address counter also read.
Write data
Write binary 8-bit data DDRAM/CGRAM/SEGRAM. selection from DDRAM, CGRAM, SEGRAM, previous address instruction DDRAM address set, CGRAM address set, SEGRAM address set. instruction also determines direction RAM. After write operation, address automatically increased/decreased according entry mode.
Read data from
Read binary 8-bit data from DDRAM/CGRAM/SEGRAM. selection previous address instruction. address instruction performed before this instruction, data that read first invalid, direction determined. data read several times without address instruction before read operation, correct data from second, first data would incorrect, there time margin transfer data. case DDRAM read operation, cursor shift instruction plays same role DDRAM address instruction also transfer data output data register. After read operation address counter automatically increased/decreased according entry mode. After CGRAM/SEGRAM read operation, display shift executed correctly. case write operation, increased/decreased like read operation after this. this time, indicates next address position, previous data only read read instruction.
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
INTERFACE WITH
KS0075 transfer data mode (4-bit 8-bit) serial mode with MPU. Hence, both types 8-bit used. case 4-bit mode, data transfer performed twice transfer byte data. When interfacing data length 4-bit, only ports, from DB7, used data bus. first higher 4-bit case 8-bit mode, contents DB7) transferred, then lower 4-bit case 8-bit mode, contents DB3) transferred. transfer performed twice. Busy Flag outputs "High" after second transfer ended. When interfacing data length 8-bit, transfer performed time through ports, from DB7. "Low", serial transfer mode set.
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
Interface with Mode Interface with 8-bits 8-bits used, KS0075 connect directly with that. this case, port need interface each other. Example timing sequence shown below.
Internal signal
Internal operation
DATA
Busy
Busy
Busy
DATA
INSTRUCTION
Busy Flag Check
Busy Flag Check
Busy Flag Check
INSTRUCTION
Example 8-bit Mode Timing Sequence
Interface with 4-bits 4-bits used, KS0075 connect directly with this. this case, port need interface each other. transfer performed twice. Example timing sequence shown below.
Internal signal
Internal operation Busy
Busy
INSTRUCTION
Busy Flag Check
Busy Flag Check
INSTRUCTION
Example 4-bit Mode Timing Sequence
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
Interface with Serial Mode When port input "Low", serial interface mode started. this time, three ports, SCLK (synchronizing transfer clock), (serial input data), (serial output data), used. KS0075 used with other chips, chip select port (cs) used. setting "Low", KS0075 receive SCLK input. "High", KS0075 reset internal transfer counter. Before transfer real data, start byte transferred. composed succeeding "High" bits, read write control (R/W), register selection (RS), that indicates start byte. Whenever succeeding "High" bits detected KS0075, resets serial transfer counter prepares receive next information. next input data register selection which determine which register used, read write control that determine direction data. Then transferred, which must have "Low" value show start byte. (Refer Write Operation (R/W After start byte transferred from KS0075, 8-bit data transferred which divided into bytes, each byte bit's real data bit's partition token data. example, real data "10110001" D7), then serially transferred data becomes "1011 0000 0001 0000" where bits must "0000" safe transfer. transfer several bytes continuously without changing bit, start byte transfer needed only first starting time. I.e., after first start byte transferred, real data succeeding transferred. Read Operation (R/W After start byte transferred KS0075, receive 8-bit data through port time from LSB. Wait time needed insert between start byte data reading, internal reading from requires some delay. Continuous data reading possible such serial write operation. also needs only start bytes, only some delay between reading operations each byte inserted. During reading operation, KS0075 observes succeeding "High" from MPU. detected, KS0075 restarts serial operation once prepares receive bit. continuous reading operation, port must "Low".
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
Serial rite Operati
(Input)
(Input) (Input)
"R/W ""RS"
Starting Byte Synchroni zing tring Serial Read Operati Lower Data 1'st Byte
Instruction Upper Data 2'nd Byte
(Input) SCLK (Input)
(Input)
"RS""0"
utput)
Invalid Data
Starting Byte Synchronizing string Lower Data
Busy Flag/ Read Data Upper Data
Timing Diagram Serial Data Transfer
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
Continuous Operati
SCLK
Start byte byte
byte
byte
byte
byte
byte
(Ins tructi on1)
(Instruction2) Instruction1 execution time Instruction2 execution time
(Instruc tion3) Instruc tion3 executi time
Continuous Read Operati
SCLK
Wait
Wait
Wait
Start byte
Data read1
Data read2
Data read3
Instruction1 execution time
Instruc tion2 executi
truction3 execution time
Timing Diagram Continuous Data Transfer
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
APPLICATION INFORMATION ACCORDING PANEL
Panel character line format (5-dot font,1/17 duty)
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 (COM0) SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SSG7 SEG8 SEG9 SEG10 SEG98 SEG99 SEG100 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9
KS0075
Panel character line format (5-dot font, 1/33 duty)
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM33 (COM0)
KS0075
SEG1 SEG2 SEG3 SEG4 SEG5 SEG98 SEG99 SEG100 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9
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34COM/100SEG DRIVER CONTROLLER MATRIX
Panel character line format (5-dot font, 1/33 bias)
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24
KS0075
COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 (COM0) SEG1 SEG2 SEG3 SEG4 SEG5 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG98 SEG99 SEG100
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34COM/100SEG DRIVER CONTROLLER MATRIX
Panel character line format (6-dot font, 1/33 bias)
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 (COM0) SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100
KS0075
OPEN OPEN OPEN OPEN
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
INITIALIZING
Initializing Internal Reset Circuit When power turned KS0075 initialized automatically power reset circuit. During initialization, following instructions executed, BF(Busy Flag) kept "High"(busy state) initialization. Display Clear instruction Write "20H" DDRAM Functions instruction 8-bit mode 2-line display mode Extension register disable CGRAM/SEGRAM blink Horizontal scroll enable Normal display (Not reversed display) iii) Control Display ON/OFF instruction Display Cursor Blink Entry Mode instruction Increment entire display shift Normal direction segment port Extension Function instruction 5-dot font width character display Normal cursor (8th line) 4-line display mode, 2-line mode because N("1") Enable Shift instruction 0000 Scroll line disable 0000 Shift line disable vii) scroll Quantity instruction 000000 scroll
Initializing Hardware RESET input When RESET "Low", KS0075 initialized like case power reset. During power reset operation, this ignored.
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
INITIALIZING INSTRUCTION
8-bit interface mode
Power Wait more than after rises 4.5V (DL="1") Function 4-bit interface 8-bit interface 1-line mode 2-line mode Condition:
Wait more than Dsplay ON/OFF Control Wait more than Clear Dsplay display display cursor cursor blink blink
Wait more than 1.53ms Entry Mode decrement mode increment mode entire shift entire shift
Initialization
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
4-bit interface mode
Power
Wait more than after rises 4.5V (DL="0") Function
Condition:
4-bit interface 8-bit interface 1-line mode 2-line mode
Wait more than 39µs
Function
Wait more than 39µs Dsplay ON/OFF Control display display cursor cursor blink blink
Wait more than 39µs
Clear Dsplay
Wait more than 1.53ms
Entry ModeSet
decrement mode increment mode entire shift entire shift
Initialization
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
EXAMPLE INSTRUCTION DISPLAY CORRESPONDENCE
"Low"
1.Power Supply Initialized internal power reset circuit. DISPLAY
2.Function 8-bit, 1-line, RE(0)
3.Display ON/OFF Control Display/Cursor
4.Entry Mode Increment
5.Write Data DDRAM Write
6.Write Data DDRAM Write
7.Write Data DDRAM Write
SAM_
Write data DDRAM Write
SAMS_
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
Write data DDRAM Write
SAMSU_
Write data DDRAM Write
SAMSUN_
Write data DDRAM Write
SAMSUNG_
Cursor Display Shift Cursor shift right
SAMSUNG
Entry Mode Entire display shift enable
SAMSUNG
Write data DDRAM Write
AMSUNG
Write data DDRAM Write
MSUNG
Write data DDRAM Write
SUNG KS0_
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
Write data DDRAM Write
KS00_
Write data DDRAM Write
KS007_
Write data DDRAM Write
KS0073_
Cursor Display Shift Cursor shift left
KS0073
Write Data DDRAM Write
KS0075_
Return Home
SAMSUNG KS0075
Clear Display
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
"High"
Power Supply Initialized internal power reset circuit.
Function 8-bit, RE(1)
Extended Function 5-font, 4-line
Function RE(0)
Display ON/OFF Control Display/Cursoron
Write data DDRAM Write
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
Write data DDRAM Write
Write data DDRAM Write
SAMSUNG_
Address
SAMSUNG
Write data DDRAM Write
SAMSUNG
Write data DDRAM Write
SAMSUNG KS0075_
Address
SAMSUNG KS0075
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
Write data Write
SAMSUNG KS0075
Write data DDRAM Write
SAMSUNG KS0075 DRIVER_
Address
SAMSUNG KS0075 DRIVER
Write data DDRAM Write
SAMSUNG KS0075 DRIVER CONTROLLER_
Function RE("0"), DH("1")
SAMSUNG KS0075 DRIVER CONTROLLER_
Function RE("1")
SAMSUNG KS0075 DRIVER CONTROLLER_
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
Shift/Scroll Enable DS4("1"),DS3/2/1("0")
SAMSUNG KS0075 DRIVER CONTROLLER_
Function RE("0")
SAMSUNG KS0075 DRIVER CONTROLLER_
Cursor Display Shift Display shift left
SAMSUNG KS0075 DRIVER CONTROLLER_
Cursor Display Shift Display shift left
SAMSUNG KS0075 DRIVER CONTROLLER_
Cursor Display Shift Display shift left
SAMSUNG KS0075 DRIVER ONTROLLER_
Cursor Display Shift Display shift left
SAMSUNG KS0075 DRIVER NTROLLER_
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
Return Home
SAMSUNG KS0075 LCDDRIVER CONTROLLER
Function
RE("0"),REV("1")
SAMSUNG KS0075 LCDDRIVER CONTROLLER
Cursor Display
Shift
Display
shift
right
SAMSUNG KS0075 LCDDRIVER CONTROLLER
Cursor Display
Shift
Display
shift
right
SAMSUNG KS0075 LCDDRIVER CONTROLLER
Return Home
SAMSUNG KS0075 LCDDRIVER CONTROLLER
Function
RE("0"),REV("0")
SAMSUNG KS0075 LCDDRIVER CONTROLLER
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
Function RE("1")
SAMSUNG KS0075 DRIVER CONTROLLER
Entry Mode BID("1")
Write Data DDRAM Write
Write Data DDRAM Write
Write Data DDRAM Write
Clear Display
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
FRAME FREQUENCY
1/17 duty cycle
1-line selection period
COM1 Frame Frame
Item 5-dot font width 1-line selection period Frame frequency clocks 79.4Hz
Display Font Width 6-dot font width clocks 66.2Hz fosc clock 3.7µs)
1/33 duty cycle
1-line election period
COM1 Frame Frame
Item 5-dot font width 1-line selection period Frame frequency clocks 81.8Hz
Display Font Width 6-dot font width clocks 68.2Hz fosc clock
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
POWER SUPPLY DRIVING PANEL
When external power supply used
When internal booster used
(Boosting twice) V5OUT2 V5OUT3
(Boosting three times)
V5OUT2 V5OUT3
detached using powr down mode
detached using powr down mode
Boosted output voltage should exceed maximum value driving voltage. Especially, voltage over 4.3V should input reference voltage (Vci) when boosting three times. voltage over 5.5V should input reference voltage (Vci) when boosting twice. value resistance, according number lines, duty ratio bias, shown below. (Refer Table
Table Duty Ratio Power Supply Driving Item Number lines Duty ratio Bias Divided resistance 1/17 Data 1/33 1/6.7 2.7R
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
MAXIMUM ABSOLUTE RATE
Characteristic Power Supply Voltage Power Supply Voltage Input Voltage Operating Temperature Storage Temperature Symbol VLCD Value -0.3 +7.0 -15.0 +0.3 -0.3 +0.3 +125 Unit
Voltage greater than above damage circuit (VDDV1V2V3V4V5)
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
ELECTRICAL CHARACTERISTICS
Characteristics (VDD 2.7V 5.5V, Ta=-30 Characteristic Operating Voltage Supply Current Symbol Condition Internal oscillation external clock. (VDD=3.0V,fosc=270KHz) Input Voltage (Except OSC1) VIH1 VIL1 VDD=2.7 VDD=3.0 Input Voltage (Osc1) Output Voltage (DB0 DB7) Output Voltage(2) (Except Db7) Voltage Drop VIH2 VIL2 VOH1 VOL1 VOH2 VOL1 VdCOM VdSEG Input Leakage Current Input Current ILKG VIN=0V VIN=0V, VDD=3V (PULL Internal Clock (external External Clock duty Voltage Converter Out2 (Vci 4.5V) Voltage Converter Out3 (Vci 2.7V) Voltage Converter Input Driving Voltage VLCD VDD-V5 Bias 1/6.7 Bias 13.0 13.0 VOUT3 VOUT2 C=1µF, IOUT 0.25mA, fOSC=270KHz -4.3 -5.1 fOSC Rf=91[k] (VDD=5V) -3.0 -4.2 IOH= -0.1 IOL= 0.1mA 0.7VDD -0.3 -0.3 0.7VDD 0.75VDD 0.8VDD 0.2VDD 0.2VDD 0.2VDD 0.2VDD -120 0.15 Unit
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
Characteristics
(VDD=4.5~ 5.5V, Ta=-30 Mode Item Cycle Time Rise Fall Time Pulse Width (High, Low) Write Mode (refer Fig-15) Setup Time Hold Time Data Setup Time Data Hold Time Cycle Time Rise Fall Time Pulse Width (High, Low) Read Mode (refer Fig-16) Setup Time Hold Time Data Output Delay Time Data Hold Time Serial Clock Cycle Time Serial Clock Rise/Fall Time Serial Clock Width (High, Low) Serial Interface Mode (refer Fig-17) Chip Select Setup Time Chip Select Hold Time Serial Input Data Setup Time Serial Input Data Hold Time Serial Output Data Delay Time Serial Output Data Hold Time Symbol tsu1 tsu2 tR,tF tR,tF tsu1 tsu2 Unit
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
Characteristics contnued)
(VDD=2.7 5.5V, Ta=-30 Mode Item Cycle Time Rise Fall Time Pulse Width (High, Low) Write Mode (refer Fig-15) Setup Time Hold Time Data Setup Time Data Hold Time Cycle Time Rise Fall Time Pulse Width (High, Low) Read Mode (refer Fig-16) Setup Time Hold Time Data Output Delay Time Data Hold Time Serial Clock Cycle Time Serial Clock Rise/Fall Time Serial Clock Width (High, Low) Serial Interface Mode (refer Fig-17) Chip Select Setup Time Chip Select Hold Time Serial Input Data Setup Time Serial Input Data Hold Time Serial Output Data Delay Time Serial Output Data Hold Time Symbol tsu1 tsu2 tR,tF tR,tF tsu1 tsu2 1000 1000 Unit
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
tSU1
VIH1 VIL1 tSU2 VIH1 VIL1 VIH1 VIL1
VIL1
VIL1
Valid Data
Fig-15. Write Mode
VIH1 VIL1 VIH1 VIH1 VIL1 VIH1 VIL1 Valid Data VIH1 VIL1 VIH1
Fig-16. Read Mode
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KS0075
34COM/100SEG DRIVER CONTROLLER MATRIX
VIL1 tSU1 VIL1 tSU2 VIH1 VIL1 VIH1 VIL1 VIL1 VIL1
SCLK
VOH1 VOL1
Fig-17. Serial Interface Mode
Reset Timing (VDD 5.5V, Item Reset level width (refer Fig-18) Symbol tRES Unit
tRES
RESET
Fig-18. Reset Timing Diagram
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