The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.    


Datasheet Search Engine   
 
Part # or Description: • 5V RS232 Driver • 2SC5066* • "Real Time Clock" • "USB connector" • "blue led" 5mm • 10 watt zener diode • 2N3055* motorola
 
Search Tip: Try entering the part number only. Include a wildcard (eg. lm317* or 1n4148*)

 

 

16COM 40SEG DRIVER CONTROLLER MATRIX INTRODUCTION QFP-1420C KS006


Datasheet Thumbnail

   

Download PDF

Top Searches for this datasheet



KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
INTRODUCTION QFP-1420C KS0066U matrix driver controller whichis fabricated power CMOS technology. display lines with dots format line with dots format.
FUNCTIONS Character type matrix driver controller. Internal driver: common segment signal output. Easy interface with 4-bit 8-bit MPU. Display character pattern: dots format (208 kinds) dots format kinds). Special character pattern directly programmable Character Generator RAM. customer character pattern programmable mask option. Programmable Driving Method same character font mask option: Display Waveform A-type B-type drive maximum characters using KS0065B KS0063B externally. Various instruction functions. Built-in automatic power reset.
FEATURES Internal Memory Character Generator (CGROM): 10,080 bits (204 dots) dots) Character Generator (CGRAM): bits dots) Display Data (DDRAM): bits characters max.) power operation Power supply voltage range (VDD): Drive voltage range (VDD-V5): 13.0 CMOS process Programmable duty cycle: 1/8, 1/11, 1/16 Internal oscillator with external resistor power consumption bare chip available
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
BLOCK DIAGRAM
Busy Flag Parallel Serial Data Conversion Circuit
Character Generator (CGROM) 10080 bits
Character Generator (CGRAM) bits
Cursor Blink Controller
DB0- DB4- Input /Output Buffer Instruction register (IR) Data Register (DR)
40-bit Shift Register 40-bit Latch Circuit Segment Driver S1-S40
Instruction Decoder (ID) Display Data RAM) 80x8 bits
Address Counter 16-bit Shift Register Common Driver C1-C16
OSC1 OSC2
Timing Generator Circuit
CLK1 CLK2
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
CONFIGURATION
CLK2 CLK1 OSC2
KS0066U
OSC1
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
DIAGRAM
OSC1
KS0066U
(0,0)
CHIP SIZE: SIZE: UNIT:
OSC2
CLK1
CLK2
NOTE: "KS0066U" marking make easy find.
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
LOCATION Table Location
Name Coordinate -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 1465 1340 1215 1090 -160 -285 -410 -535 -660 -785 -910 Name OSC1 OSC2 CLK1 CLK2 Coordinate -1864 -1864 -1864 -1864 -1120 -970 -820 -670 -520 -370 -220 1018 -1034 -1159 -1285 -1414 -1754 -1754 -1754 -1754 -1754 -1754 -1754 -1754 -1754 -1754 -1754 -1754 -1754 -1754 -1754 -1754 Name Coordinate 1864 1864 1864 1864 1864 1864 1864 1864 1864 1864 1864 1864 1864 1864 1864 1864 1864 1864 1864 1864 -1488 -1362 -1238 -1112 -988 -862 -665 -540 -415 -290 -165 Name
(Unit:
Coordinate 1864 1864 1864 1864 -114 -240 -364 -490 -614 -740 -864 -989 1085 1210 1341 1466 1754 1754 1754 1754 1754 1754 1754 1754 1754 1754 1754 1754 1754 1754 1754 1754
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
DESCRIPTION Table Description V1-V5 S1-S40 C1-C16 OSC1 OSC2 26-30 1-22, 63-80 47-62 Segment output Common output Oscillator Oscillator Name Supply Voltage Description Supply Voltage logical circuit (+3V 10%,+5V 10%) Ground (0V) Bias voltage level driving Segment signal output drive Common signal output drive Oscillator. When using internal oscillator, connect external resistor. external clock used, connect OSC1. Extension driver latch clock Extension driver shift clock Outputs alternating signal convert driver waveform Outputs extension driver data (the 41st dot's data) Used register selection input. When "High", Data register selected. When "Low", Instruction register selected. Used read/write selection input. When "High", read operation. When "Low", write operation. Extension driver External resistor/oscillator (OSC1) Extension driver Interface Power Supply
CLK1 CLK2
Extension driver Latch clock Extension driver Shift clock Alternated signal driver output Display data interface Register select
Extension driver
Read/Write
DB0-DB3
39-42
Read/Write enable Used read/write enable signal. 8-bit mode, used order bidirectional data bus. 4-bit mode, open these pins. 8-bit mode, used high order bidirectional data bus. 4-bit mode, used both high order. used Busy Flag output.
Data
DB4-DB7
43-46
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
FUNCTION DESCRIPTION System Interface This chip both kinds interface type with MPU: 4-bit 8-bit bus. 4-bit 8-bit selected instruction register. During read write operation, 8-bit registers used. data register (DR), other instruction register (IR). data register (DR) used temporary data storage place being written into read from DDRAM/CGRAM. target selected address setting instruction. Each internal operation, reading from writing into RAM, done automatically. Thus, after reads data, data next DDRAM/CGRAM address transferred into automatically. Also, after writes data data transferred into DDRAM/CGRAM automatically. Instruction register(IR) used only store instruction codes transferred from MPU. cannot read instruction data. select register, input 4-bit/8-bit mode. Table Various kinds Operations according bits Operation Instruction Write operation (MPU writes Instruction code into Read Busy flag(DB7) address counter (DB0 DB6) Data Write operation (MPU writes data into Data Read operation (MPU reads data from
Busy Flag (BF) "High", indicates that internal operation being processed. during this time next instruction cannot accepted. read through port when "Low" "High" (Read Instruction Operation). Before executing next instruction, sure that "High".
Address Counter (AC) address Counter (AC) stores DDRAM/CGRAM addresses, transferred from After writing into (reading from) DDRAM/CGRAM, automatically increased (decreased) When "Low" "High", read through ports DB6.
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
Display Data (DDRAM) DDRAM stores display data maximum bits characters). DDRAM address address counter(AC) hexadecimal number (Refer Fig-1.)
Figure DDRAM Address 1-line display case 1-line display, address range DDRAM 00H-4FH. extension driver will used. Fig-2 shows example with segment extension driver added.
Display position
COM1 COM8 SEG1 KS0066U SEG40 SEG1 Extension Driver (40SEG) SEG40 SEG1 Extension Driver (40SEG) SEG40
DDRAM address
COM1 COM8 SEG1
KS0066U
SEG40
SEG1 Extension Driver (40SEG) SEG40
SEG1 Extension Driver (40SEG) SEG40
(After Shift Left)
COM1 COM8 SEG1
KS0066U
SEG40
SEG1 Extension Driver (40SEG) SEG40
SEG1 Extension Driver (40SEG) SEG40
(After Shift Right)
Figure 1-line char. display with SEG. extension driver
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
2-line display case 2-line display, address range DDRAM 00H-27H 40H-67H. extension driver will used. Fig-3 shows example with segment extension driver added.
Display position
COM1 COM8
DDRAM address
COM9 COM16
SEG1
KS0066U
SEG40
SEG1 Extension Driver (40SEG) SEG40
SEG1 Extension Driver (40SEG) SEG40
COM1 COM8 COM9 COM16
SEG1
KS0066U
SEG40
SEG1 Extension Driver (40SEG) SEG40
SEG1 Extension Driver (40SEG) SEG40
(After Shift Left)
COM1 COM8 COM9 COM16
SEG1
KS0066U
SEG40
SEG1 Extension Driver (40SEG) SEG40
SEG1 Extension Driver (40SEG) SEG40
(After Shift Right) Figure 2-line char. display with SEG. extension driver
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
CGROM(Character Generator ROM) CGROM dots characters pattern dots characters pattern (Refer Table CGROM character patterns dots, character patterns dots.
CGRAM(Character Generator RAM) CGRAM dots characters. writing font data CGRAM, user defined characters used (Refer Table
Timing Generation Circuit Timing generation circuit generates clock signals internal operations.
Driver Circuit Driver circuit common segment signals driving. Data from CGRAM/CGROM transferred 40-bit segment latch serially, then stored 40-bit shift latch. When each common selected 16-bit common register, segment data also output through segment driver from 40-bit segment latch. case 1-line display mode, COM1 COM8 have duty COM1 COM11 have 1/11 duty, 2-line mode, COM1 COM16 have 1/16 duty ratio.
Cursor/Blink Control Circuit controls cursor/blink ON/OFF cursor position.
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
Table CGROM Character Code Table
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
Table Relationship between Character Code (DDRAM) Character Pattern (CGRAM) Character Code (DDRAM data) CGRAM Address CGRAM Data pattern Pattern number pattern
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
INSTRUCTION DESCRIPTION Outline overcome speed difference between internal clock KS0066U clock, KS0066U performs internal operations storing control informations internal operation determined according signal from MPU, composed read/write data (Refer Table Instructions divided largely into four groups: KS0066U function instructions (set display methods, data length, etc.) address instructions internal data transfer instructions with internal others address internal automatically increased decreased Note: During internal operation, Busy Flag (DB7) read "High". Busy Flag check must preceded next instruction. When program with checking Busy Flag (DB7) made, must necessary fosc executing next instruction falling edge signal after Busy Flag (DB7) goes "Low".
Contents Clear Display
Clear display data writing "20H" (space code) DDRAM address, DDRAM address "00H" into (address counter). Return cursor original status, namely, bring cursor left edge first line display. Make entry mode increment (I/D "High").
Return Home
don' care Return Home cursor return home instruction. DDRAM address "00H" into address counter. Return cursor original site return display original status, shifted. Contents DDRAM does change.
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
Entry Mode
moving direction cursor display. I/D: Increment decrement DDRAM address (cursor blink) When "High", cursor/blink moves right DDRAM address increased When "Low", cursor/blink moves left DDRAM address decreased CGRAM operates same DDRAM, when reading from writing CGRAM. Shift entire display When DDRAM read (CGRAM read/write) operation "Low", shifting entire display performed. "High" DDRAM write operation, shift entire display performed according value (I/D "High": shift left, "Low": shift right). Display ON/OFF Control
Control display/cursor/blink ON/OFF register. Display ON/OFF control When "High", entire display turned When "Low", display turned off, display data remains DDRAM. Cursor ON/OFF control When "High", cursor turned When "Low", cursor disappeared current display, register preserves data. Cursor Blink ON/OFF control When "High", cursor blink which performs alternately between "High" data display characters cursor position. When "Low", blink off.
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
Cursor Display Shift
Shifting right/left cursor position display without writing reading display data. This instruction used correct search display data.(Refer Table During 2-line mode display, cursor moves line after 40th digit line. Note that display shift performed simultaneously lines. When displayed data shifted repeatedly, each line shifted individually. When display shift performed, contents address counter changed.
Table Shift Patterns According Bits Operation Shift cursor left, decreased Shift cursor right, increased Shift display left, cursor moves according display Shift display right, cursor moves according display
Function
Interface data length control When "High", means 8-bit mode with MPU. When "Low", means 4-bit mode with MPU. Hence, signal select 8-bit 4-bit mode. When 4-bit mode, needs transfer 4-bit data twice. Display line number control When "Low", 1-line display mode set. When "High", 2-line display mode set. Display font type control When "Low", dots format display mode set. When "High", dots format display mode.
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
CGRAM Address
CGRAM address This instruction makes CGRAM data available from MPU.
DDRAM Address
DDRAM address This instruction makes DDRAM data available from MPU. When 1-line display mode Low), DDRAM address from "00H" "4FH". 2-line display mode High), DDRAM address line from "00H" "27H", DDRAM address line from "40H" "67H".
Read Busy Flag Address
This instruction shows whether KS0066U internal operation not. resultant "High", internal operation progress should wait until Low, which then next instruction performed. this instruction also read value address counter.
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
Write data
Write binary 8-bit data DDRAM/CGRAM. selection from DDRAM, CGRAM, previous address instruction (DRAM address set, CGRAM address set). instruction also determine direction RAM. After write operation, address automatically increased/decreased according entry mode.
Read data from
Read binary 8-bit data from DDRAM/CGRAM. selection previous address instruction. address instruction performed before this instruction, data that been read first invalid, direction determined. data read several times without address instructions before read operation, correct data obtained from second. first data would incorrect, there time margin transfer data. case DDRAM read operation, cursor shift instruction plays same role DDRAM address instruction, also transfers data output data register. After read operation, address counter automatically increased/decreased according entry mode. After CGRAM read operation, display shift executed correctly. NOTE: case write operation, increased/decreased read operation. this time, indicates next address position, only previous data read read instruction.
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
Table Instruction Table Instruction Code Instruction
Description
Execution time (fosc= kHz) 1.53
Clear Display
Write "20H" DDRAM DDRAM address "00H" from DDRAM address "00H" from return cursor original position shifted. contents DDRAM changed. Assign cursor moving direction enable shift entire display. display(D), cursor(C), blinking cursor(B) on/off control bit. cursor moving display shift control bit, direction, without changing DDRAM data. interface data length (DL: 8-bit/4-bit), numbers display line 2-line/1-line) and, display font type dots) CGRAM address address counter. DDRAM address address counter.
Return Home
1.53
Entry Mode Display Control Cursor Display Shift
Function
CGRAM Address DDRAM Address Read Busy Flag Address Write Data Read Data from
Whether during internal operation known reading contents address counter also read.
Write data into internal (DDRAM/CGRAM). Read data from internal (DDRAM/CGRAM).
"-": don' care
NOTE: When program with checking Busy Flag(DB7) made, must necessary 1/2Fosc necessary executing next instruction falling edge signal after Busy Flag (DB7) goes "Low".
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
INTERFACE WITH Interface with 8-bit When interfacing data length 8-bit, transfer performed time through ports, from DB7. Example timing sequence shown below.
Internal
signal
Internal Operation Busy
DATA
Busy
Busy
DATA
Instruction
Busy Flag Check
Busy Flag Check
Busy Flag Check
Instruction
Figure Example 8-bit Mode Timing Diagram Interface with 4-bit When interfacing data length 4-bit, only ports, from DB7, used data bus. First, higher 4-bit case 8-bit mode, contents DB7), then lower 4-bit case 8-bit mode, contents DB3) transferred. transfer performed twice Busy Flag outputs "High" after second transfer ended. Example timing sequence shown below.
Internal signal
Internal Operation
Busy
Busy
Instruction
Busy Flag Check
Busy Flag Check
Instruction
Figure Example 4-bit Mode Timing Diagram
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
APPLICATION INFORMATION ACCORDING PANEL Panel: characters format dots 1cursor line, bias, duty)
KS0066U
Panel: characters format dots 1cursor line, bias, 1/11 duty)
KS0066U
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
Panel: characters -line format dots line, bias, 1/16 duty)
KS0066U
Panel: characters format dots 1cursor line, bias, 1/16 duty)
KS0066U
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
Panel: characters format dots 1cursor line, bias, duty)
KS0066U
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
APPLICATION CIRCUIT
Panel
SC40 SC40 SC40 SHL1 SHL2
KS0065B
KS0065B
OSC1 OSC2
SHL1 SHL2
SHL1 SHL2
KS0066U
CLK1 CLK2
KS0065B
VLCD (1/5 bias)
Other voltage
NOTE: When KS0065B externally connected KS0066U, increase number display digits characters. BIAS VOLTAGE DIVIDE CIRCUIT bias, 1/11 duty bias, 1/16 duty
KS0066U
KS0066U
Other voltage
Other voltage
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
INITIALIZING When power turned KS0066U initialized automatically power reset circuit. During initialization, following instructions executed, (Busy Flag) kept "High" (busy state) initialization. Display Clear instruction: Write "20H" DDRAM Functions instruction: "High": 8-bit mode "Low": 1-line display mode "Low": font type Control Display ON/OFF instruction: "Low": Display "Low": Cursor "Low": Blink Entry Mode instruction: "High": Increment "Low": entire display shift FRAME FREQUENCY Programmable Driving Method same font mask option: Display waveform A-Type, B-Type duty cycle A-type Waveform 1-Line selection period
B-type Waveform
COM1
COM1
FRAME FRAME
1-Line selection period clocks Frame 11850 11.9 clock=3.7 fosc=270 kHz) Frame frequency 11.9 84.4
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
1/11 duty cycle A-type Waveform
1-Line selection period
B-type Waveform
COM1
COM1
FRAME FRAME
1-Line selection period clocks Frame 16300 16.3 clock=3.7 fosc=270 kHz) Frame frequency 16.3 61.4 1/16 duty cycle A-type Waveform
1-Line selection period
B-type Waveform
COM1
COM1
FRAME FRAME
1-Line selection period clocks Frame 11850 11.9 clock=3.7 fosc=270 kHz) Frame frequency 11.9 84.3
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
INITIALIZING INSTRUCTION 8-bit interface mode (Condition: fosc 270KHZ)
Power
Wait more than after rises
Function
1-line mode 2-line mode display display
Wait more than
Display ON/OFF Control
display display cursor cursor blink blink
Wait more than
Display Clear
Wait more than 1.53
Entry Mode
decrement mode increment mode entire shift entire shift
Initialization
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
4-bit interface mode (Condition: fosc 270KHZ)
Power
Wait more than after rises
Function
1-line mode 2-line mode display display
Wait more than
Display ON/OFF Control
display display cursor cursor blink blink
Wait more than
Display Clear
Wait more than 1.53
Entry Mode
decrement mode increment mode entire shift entire shift
Initialization
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
MAXIMUM ABSOLUTE LIMIT Table Maximum Absolute Power Ratings Characteristic Power Supply Voltage(1) Power Supply Voltage(2) Input Voltage Symbol VLCD Unit Value -0.3 +7.0 VDD-15.0 VDD+0.3 -0.3 VDD+0.3
NOTE: Voltage greater than above damage circuit.
Table Temperature characteristics Characteristic Operating Temperature Storage Temperature Symbol TOPR TSTG Unit Value +125
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
ELECTRICAL CHARACTERISTICS Characteristics Table Characteristics (VDD 4.5V 5.5V, +85oC) Characteristic Operating Voltage Supply Current Symbol VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VdCOM VdSEG Input Leakage Current Input Current Internal Clock (external IIKG fOSC1 fOSC External Clock duty Driving Voltage VLCD VDD-V5 (1/5, Bias) Condition Internal oscillation external clock. (VDD=5.0 fosc kHz) -0.205 (PULL (VDD Min. -0.3 VDD-1.0 -0.2 0.9VDD Typ. 0.35 -125 Max. 0.1VDD -250 13.0 Unit
Input Voltage (except OSC1) Input Voltage (OSC1) Output Voltage (DB0 DB7) Output Voltage (except DB7) Voltage Drop
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
Table Characteristic (VDD =2.7V 4.5V, +85oC) Characteristic Operating Voltage Supply Current Input Voltage (except OSC1) Input Voltage (OSC1) Output Voltage (DB0 DB7) Output Voltage (except DB7) Voltage Drop Input Leakage Current Input Current Internal Clock (external Symbol VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VdCOM VdSEG IIKG fOSC1 fOSC2 External Clock duty tR,tF Driving Voltage NOTE: Driving Voltage Power Duty Bias 1/8, 1/11 Duty Bias VDD-VLCD/4 VDD-VLCD/2 VDD-VLCD/2 VDD-3VLCD/4 VDD-VLCD 1/16 Duty Bias VDD-VLCD/5 VDD-2VLCD/5 VDD-3VLCD/5 VDD-4VLCD/5 VDD-VLCD VLCD VDD-V5 (1/5, Bias) Condition Internal oscillation external clock. (VDD=3.0 fosc kHz) -0.1 (PULL (VDD Min. 0.7VDD -0.3 0.7VDD 0.75VDD 0.8VDD Typ. 0.15 Max. 0.55 0.2VDD 0.2VDD 0.2VDD -120 13.0 Unit
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
Characteristics Table Characteristics (VDD 4.5V 5.5V, +85oC) Mode Characteristic Cycle Time Rise Fall Time Pulse Width (High, Low) Write Mode (Refer Fig-6) Setup Time Hold Time Data Setup Time Data Hold Time Cycle Time Rise Fall Time Pulse Width (High, Low) Read Mode (Refer Fig-7) Setup Time Hold Time Data Output Delay Time Data Hold Time Symbol tR,tF tsu1 tsu2 tR,tF Min. Typ. Max. Unit
Table Characteristics (VDD =2.7V 4.5V, +85oC) Mode Characteristic Cycle Time Rise Fall Time Pulse Width (High, Low) Write Mode (Refer Fig-6) Setup Time Hold Time Data Setup Time Data Hold Time Cycle Time Rise Fall Time Pulse Width (High, Low) Read Mode (Refer Fig-7) Setup Time Hold Time Data Output Delay Time Data Hold Time Symbol tsu1 tsu2 tR,tF Min. 1000 1000 Typ. Max. Unit
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
Table Characteristics (VDD =2.7V 4.5V, +85oC) Mode Characteristic Clock Pulse Width (High, Low) Clock Rise Fall Time Interface Mode with Extension Driver (Refer Fig-8) Clock Setup Time Data Setup Time Data Hold Time Delay Time Symbol tR,tF tsu1 tsu2 Min. -1000 Typ. Max. 1000 Unit
VIL1 tSU1
VIL1 VIL1 tSU2 Valid Data
VIL1
Figure Write Mode Timing Diagram
Figure Read Mode Timing Diagram
KS0066U
16COM 40SEG DRIVER CONTROLLER MATRIX
CLK1
tSU1 tSU2
CLK2
Figure Interface Mode With Extension Driver Timing Diagram

Other recent searches


SPX2954 - SPX2954   SPX2954 Datasheet
SPX2954A - SPX2954A   SPX2954A Datasheet
Si9150 - Si9150   Si9150 Datasheet
RFSP5030 - RFSP5030   RFSP5030 Datasheet
LA-2244A-1 - LA-2244A-1   LA-2244A-1 Datasheet
LA-1244A-1 - LA-1244A-1   LA-1244A-1 Datasheet
LA-044A-1 - LA-044A-1   LA-044A-1 Datasheet
HHM1534 - HHM1534   HHM1534 Datasheet
ADS8343 - ADS8343   ADS8343 Datasheet

 

Privacy Policy | Disclaimer
© 2012 Datasheet Archive