CMOS SDRAM Revision History Revision .3(November 1997) tRDL chang

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CMOS SDRAM Revision History Revision .3(November 1997) tRDL chang

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KM48S8020B
CMOS SDRAM
Revision History Revision .3(November 1997) tRDL changed 10ns 12ns. Binning does meet PC100 characteristics parameter/Characteristics have changed values. Revision (February 1998) Input leakage Currents (Inputs changed. IIL(Inputs) 1uA, IIL(DQ) 1.5uA. measuring condition tR/tF clearly defined each VSS/VDD, 50pF VSS/VDD measured 3.3V, 23°C, 1MHz, VREF =1.4V Operating Condition changed defined VIH(max) 5.6V overshoot voltage duration 3ns. VIL(min) -2.0V undershoot voltage duration 3ns. ICC3PS changed 2mA. ICC6 power changed 400uA 450uA. Revision (March 1998) ICC2N, ICC2NS, ICC3N ICC3NS values changed. Revision (June 1998) (-10 binning) revised. Revision (July 1998) Simplified Truth Table revised.
July 1998
KM48S8020B
8Bit Banks Synchronous DRAM
FEATURES
standard 3.3V power supply LVTTL compatible with multiplexed address Dual banks operation cycle with address programs latency Burst length Full page) Burst type (Sequential Interleave) inputs sampled positive going edge system clock read single-bit write operation masking self refresh refresh period Cycle)
CMOS SDRAM
GENERAL DESCRIPTION
KM48S8020B 67,108,864 bits synchronous high data rate Dynamic organized 4,194,304 words bits, fabricated with SAMSUNG high performance CMOS technology. Synchronous design allows precise cycle control with system clock transactions possible every clock cycle. Range operating frequencies, programmable burst length programmable latencies allow same device useful variety high bandwidth, high performance memory system applications.
ORDERING INFORMATION
Part KM48S8020BT-G/F8 KM48S8020BT-G/FH KM48S8020BT-G/FL KM48S8020BT-G/F10 Freq. 125MHz 100MHz 100MHz 100MHz LVTTL TSOP(II) Interface Package
FUNCTIONAL BLOCK DIAGRAM
Control
Data Input Register
LDQM
Bank Select Refresh Counter
Output Buffer
Decoder
Sense
Buffer
Address Register
Column Decoder Col. Buffer Latency Burst Length
LRAS
LCBR
LCKE LRAS LCBR LCAS
Programming Register LWCBR LDQM
Timing Register
Samsung Electronics reserves right change products specification without notice.
July 1998
KM48S8020B
CONFIGURATION (Top view)
VDDQ VSSQ VDDQ VSSQ A10/AP VSSQ VDDQ VSSQ VDDQ N.C/RFU
CMOS SDRAM
54Pin TSOP (II) (400mil 875mil) (0.8 pitch)
FUNCTION DESCRIPTION
Name System clock Chip select Input Function Active positive going edge sample inputs. Disables enables device operation masking enabling inputs except CLK, Masks system clock freeze operation from next clock cycle. should enabled least cycle prior command. Disable input buffers power down standby. Row/column addresses multiplexed same pins. address RA12, Column address Selects bank activated during address latch time. Selects bank read/write during column address latch time. Latches addresses positive going edge with low. Enables access precharge. Latches column addresses positive going edge with low. Enables column access. Enables write operation precharge. Latches data starting from CAS, active. Makes data output Hi-Z, after clock masks output. Blocks data input when active. Data inputs/outputs multiplexed same pins. Power ground input buffers core logic. Isolated power supply ground output buffers provide improved noise immunity. This recommended left Connection device.
Clock enable
VDD/VSS VDDQ /VSSQ N.C/RFU
Address Bank select address address strobe Column address strobe Write Enable Data input/output mask Data input/output Power supply/ground Data output power/ground connection /reserved future
July 1998
KM48S8020B
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage relative Voltage supply relative Storage temperature Power dissipation Short circuit current Symbol VOUT VDDQ TSTG Value -1.0 -1.0 +150
CMOS SDRAM
Unit
Note Permanent device damage occur "ABSOLUTE MAXIMUM RATINGS" exceeded. Functional operation should restricted recommended operating condition. Exposure higher than recommended voltage extended periods time could affect device reliability.
OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced Parameter Supply voltage Input logic high voltage Input logic voltage Output logic high voltage Output logic voltage Input leakage current (Inputs) Input leakage current (I/O pins) Symbol VDDQ -0.3 -1.5
70°C) VDDQ +0.3 Unit -2mA Note
Notes (max) 5.6V overshoot voltage duration 3ns. (min) -2.0V undershoot voltage duration 3ns. input VDDQ Input leakage currents include Hi-Z output leakage bi-directional buffers with Tri-State outputs. Dout disabled, VOUT VDDQ.
CAPACITANCE
Clock
(VDD 3.3V, 23°C, 1MHz, 1.4V Symbol CCLK CADD COUT Unit
RAS, CAS, CKE, Address
July 1998
KM48S8020B
CHARACTERISTICS
(Recommended operating condition unless otherwise noted, Parameter Symbol
CMOS SDRAM
70°C) Latency Version Unit Note
Test Condition Burst length (min) VIL(max), 15ns VIL(max),
Operating current (One bank active) Precharge standby current power-down mode
ICC1 ICC2 ICC2 ICC2
Precharge standby current power-down mode ICC2 Active standby current power-down mode ICC3 ICC3 ICC3 ICC3
VIH(min), VIH(min), 15ns Input signals changed time during 30ns VIH(min), VIL(max), Input signals stable VIL(max), 15ns VIL(max), VIH(min), VIH(min), 15ns Input signals changed time during 30ns VIH(min), VIL(max), Input signals stable Page burst 2Banks activated tCCD 2CLKs (min) 0.2V
Active standby current power-down mode (One bank active)
Operating current (Burst mode) Refresh current Self refresh current
ICC4
ICC5 ICC6
Notes Measured with outputs open. Refresh period 64ms. KM48S8020BT-G** KM48S8020BT-F**
July 1998
KM48S8020B
OPERATING TEST CONDITIONS
Parameter Input levels (Vih/Vil) Input timing measurement reference level Input rise fall time Output timing measurement reference level Output load condition
3.3V
CMOS SDRAM
(VDD 3.3V 0.3V, 70°C) Value 2.4/0.4 tr/tf Fig.
1.4V
Unit
1200 Output 50pF (DC) 2.4V, -2mA (DC) 0.4V, Output
50pF
(Fig. output load circuit
(Fig. output load circuit
OPERATING PARAMETER
operating conditions unless otherwise noted) Parameter Active Active Delay delay precharge time active time cycle time Last data precharge Last data col. address delay Last data burst stop Col. address col. address delay Number valid output data Symbol tRRD (min) tRCD (min) (min) tRAS (min) tRAS (max) (min) tRDL (min) tCDL (min) tBDL (min) tCCD (min) latency=3 latency=2 Version Unit Note
Notes minimum number clock cycles determined dividing minimum time required with clock cycle time then rounding next higher integer. Minimum delay required complete write. parts allow every cycle column address change. case precharge interrupt, auto precharge read burst stop.
July 1998
KM48S8020B
CHARACTERISTICS
Parameter latency=3 latency=2 valid output delay Output data hold time latency=3 latency=2 latency=3 latency=2 tSLZ tSHZ tSAC operating conditions unless otherwise noted) Symbol cycle time 1000 1000 1000
CMOS SDRAM
1000
Unit
Note
high pulse width pulse width Input setup time Input hold time output Low-Z output Hi-Z latency=3 latency=2
Notes Parameters depend programmed latency. clock rising time longer than 1ns, (tr/2-0.5)ns should added parameter. Assumed input rise fall time 1ns. longer than 1ns, transient time compensation should considered, i.e., [(tr tf)/2-1]ns should added parameter.
BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter Output rise time Output fall time Output rise time Output fall time Symbol Condition Measure linear region 1.2V ~1.8V Measure linear region 1.2V ~1.8V Measure linear region 1.2V ~1.8V Measure linear region 1.2V ~1.8V 1.37 1.30 4.37 Unit Volts/ns Volts/ns Volts/ns Volts/ns Notes 1,2,3 1,2,3
Notes Output rise fall time must guaranteed across process range. Rise time specification based Ohms these values design Fall time specification based Ohms these values design Measured into 50pF only, these values characterize measurements done with respect
July 1998
KM48S8020B
IBIS SPECIFICATION
Characteristics (Pull-up)
Voltage 3.45 1.65 100MHz (mA) 100MHz (mA) -2.4 -27.3 -74.1 -129.2 -153.3 -197.0 -226.2 -248.0 -269.7 -284.3 -344.5 -502.4 66MHz (mA) -100 -200 -300 -400 -500 -600 Voltage
CMOS SDRAM
66MHz 100MHz Pull-up
-21.1 -34.1 -58.7 -67.3 -73.0 -77.9 -80.8 -88.6 -93.0
-0.7 -7.5 -13.3 -27.5 -35.5 -41.1 -47.9 -52.4 -72.5 -93.0
(100MHz) (66MHz) 100MHz)
66MHz 100MHz Pull-down
Characteristics (Pull-down)
Voltage 0.65 0.85 1.65 1.95 3.45 100MHz (mA) 27.5 41.8 51.6 58.0 70.7 72.9 75.4 77.0 77.6 80.3 81.4 100MHz (mA) 70.2 107.5 133.8 151.2 187.7 194.4 202.5 208.6 212.0 219.6 222.6 66MHz (mA) 17.7 26.9 33.3 37.6 46.6 48.0 49.5 50.7 51.5 54.2 54.9
Voltage
(100MHz) (66MHz) (100MHz)
July 1998
KM48S8020B
CMOS SDRAM
Minimum clamp current (Referenced
Clamp CLK, CKE,
(mA) 0.23 1.34 3.02 5.06 7.35 9.83 12.48 15.30 18.31
Voltage
(mA)
Minimum clamp current
Clamp CLK, CKE,
-2.6 -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.9 -0.8 -0.7 -0.6 -0.4 -0.2 (mA) -57.23 -45.77 -38.26 -31.22 -24.58 -18.37 -12.56 -7.57 -3.37 -1.75 -0.58 -0.05
Voltage
(mA)
July 1998
KM48S8020B
FREQUENCY PARAMETER RELATIONSHIP TABLE
KM48S8020BT-8
Frequency 125MHz (8.0ns) 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) Latency 68ns tRAS 48ns 20ns tRRD 16ns tRCD 20ns
CMOS SDRAM
(Unit Number clock) tCCD tCDL tRDL
KM48S8020BT-H
Frequency 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) 60MHz (16.7ns) Latency 70ns tRAS 50ns 20ns tRRD 20ns tRCD 20ns tCCD 10ns
(Unit Number clock) tCDL 10ns tRDL 10ns
KM48S8020BT-L
Frequency 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) 60MHz (16.7ns) Latency 70ns tRAS 50ns 20ns tRRD 20ns tRCD 20ns tCCD 10ns
(Unit Number clock) tCDL 10ns tRDL 10ns
KM48S8020BT-10
Frequency 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) 60MHz (16.7ns) Latency 80ns tRAS 50ns 24ns tRRD 20ns tRCD 24ns tCCD 10ns
(Unit Number clock) tCDL 10ns tRDL 12ns
July 1998
KM48S8020B
SIMPLIFIED TRUTH TABLE
Command Register Mode register Auto refresh Refresh Entry Self refresh Exit
CKEn-1 CKEn
CMOS SDRAM
A10/AP
Note
code
address
Column address Column address
Bank active addr. Read column address Write column address Burst stop Precharge Bank selection banks Clock suspend active power down Entry Exit Entry Precharge power down mode Exit Operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable
(V=Valid, X=Don care, H=Logic high, L=Logic low) Notes Code Operand code Program keys. MRS) issued only banks precharge state. command issued after cycles MRS. Auto refresh functions same refresh DRAM. automatical precharge without precharge command meant "Auto". Auto/self refresh issued only banks precharge state. Bank select addresses. "Low" read, write, active precharge, bank selected. "High" read, write, active precharge, bank selected. "High" precharge, ignored banks selected. During burst read write with auto precharge, read/write command issued. Another bank read/write command issued after burst. active associated bank issued after burst. Burst stop command valid every burst length. sampled positive going edge masks data-in very (Write latency makes Hi-Z state data-out cycles after. (Read latency
July 1998
DEVICE OPERATIONS
MODE REGISTER FIELD TABLE PROGRAM MODES
Register Programmed with Address Function 10/AP W.B.L Latency
CMOS SDRAM
Burst Length
Test Mode Type Mode Register Reserved Reserved Reserved Length Burst Single
Latency Latency Reserved Reserved Reserved Reserved Reserved Reserved
Burst Type Type Sequential Interleave
Burst Length
Write Burst Length
Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved
Full Page Length (1024), (512), (256)
POWER SEQUENCE
Apply power start clock, Attempt maintain CKE= "H", DQM= other pins condition inputs. Maintain stable power, stable clock input condition minimum 200us. Issue precharge commands banks devices. Issue more auto-refresh commands. Issue mode register command initialize mode register. cf.) Sequence regardless order.
device ready normal operation.
Note high during cycle, "Burst Read Single Write" function will enabled. (Reserved future use) should stay during cycle.
REV. Feb.
ELECTRONICS
DEVICE OPERATIONS
BURST SEQUENCE (BURST LENGTH
Initial Address Sequential
CMOS SDRAM
Interleave
BURST SEQUENCE (BURST LENGTH
Initial Address Sequential Interleave
REV. Feb.
ELECTRONICS
DEVICE OPERATIONS
DEVICE OPERATIONS
CLOCK (CLK)
clock input used reference SDRAM operations. operations synchronized positive going edge clock. clock transitions must monotonic between During operation with high inputs assumed valid state (low high) duration set-up hold time around positive edge clock order function well perform specifications.
CMOS SDRAM
ADDRESS INPUTS A12)
case
address bits required decode 8,388,608 word locations multiplexed into address input pins 12). addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
CLOCK ENABLE (CKE)
clock enable(CKE) gates clock onto SDRAM. goes synchronously with clock (set-up hold time same other inputs), internal clock suspended from next clock cycle state output burst address frozen long remains low. other inputs ignored from next clock cycle after goes low. When banks idle state goes synchronously with clock, SDRAM enters power down mode from next clock cycle. SDRAM remains power down mode ignoring other inputs long remains low. power down exit synchronous internal clock suspended. When goes high least "1CLK before high going edge clock, then SDRAM becomes active from same clock edge accepting input commands.
case
address bits required decode 4,194,304 word locations multiplexed into address input pins 12). addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
case
address bits required decode 2,097,152 word locations multiplexed into address input pins 12). addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
BANK ADDRESS (BA)
case
This SDRAM organized independent banks 8,388,608 words bits memory arrays. input latched time assertion select bank used operation. bank address latched bank active, read, write, mode register precharge operations.
DEVICE DESELECT
When RAS, high, SDRAM performs operation (NOP). does initiate operation, needed complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. device deselect also entered asserting high. high disables command decoder that RAS, CAS, address inputs ignored.
case
This SDRAM organized independent banks 4,194,304 words bits memory arrays. input latched time assertion select bank used operation. bank address latched bank active, read, write, mode register precharge operations.
POWER-UP
Apply power start clock, Attempt maintain CKE= "H", DQM= other pins condition inputs. Maintain stable power, stable clock input condition minimum 200us. Issue precharge commands both banks devices. Issue more auto-refresh commands. Issue mode register command initialize mode register. cf.) Sequence regardless order.
case
This SDRAM organized independent banks 2,097,152 words bits memory arrays. input latched time assertion select bank used operation. bank address latched bank active, read, write, mode register precharge operations.
device ready normal operation.
REV. Feb.
ELECTRONICS
DEVICE OPERATIONS
DEVICE OPERATIONS (Continued)
MODE REGISTER (MRS)
mode register stores data controlling various operating modes SDRAM. programs latency, burst type, burst length, test mode various vendor specific options make SDRAM useful variety different applications. default value mode register defined, therefore mode register must written after power operate SDRAM. mode register written asserting RAS, (The SDRAM should active mode with already high prior writing mode register). state address pins same cycle RAS, going data written mode register. clock cycles required complete write mode register. mode register contents changed using same command clock cycle requirements during operation long banks idle state. mode register divided into various fields depending fields functions. burst length field uses
CMOS SDRAM
active initiate sensing restoring complete dynamic cells determined
RAS(min).
Every SDRAM bank
activate command must satisfy RAS(min) specification before precharge command that active bank asserted. maximum time bank active state determined RAS(max). number cycles both RAS(min) tRAS(max) calculated similar
specification.
BURST READ
burst read command used access burst data consecutive clock cycles from active active bank. burst read command issued asserting must active least
RCD(min)
with being high positive edge clock. bank before burst read command issued. first output appears latency number clock cycles after issue burst read command. burst length, burst sequence latency from burst read command determined mode register which already programmed. burst read initiated column address active row. address wraps around initial address does start from boundary such that number outputs from each equal burst length programmed mode register. output goes into high-impedance burst, unless burst read initiated keep data output gapless. burst read terminated issuing another burst read burst write same bank other active bank precharge command same bank. burst stop command valid every page burst length.
burst type uses
latency (read latency from column address) specific options test mode
vendor
10/AP
write burst length programmed using
A10/AP
must normal SDRAM operation. Refer table specific codes various burst length, burst type latencies.
BANK ACTIVATE
bank activate command used select random idle bank. asserting with desired bank address, access initiated. read write operation occur after time delay
RCD(min)
BURST WRITE
burst write command similar burst read command used write data into SDRAM consecutive clock cycles adjacent addresses depending burst length burst sequence. asserting with valid column address, write burst initiated. data inputs provided initial address same clock cycle burst write command. input buffer deselected burst length, even though internal writing completed yet. writing completed issuing burst read blocking data inputs burst write same another active bank. burst stop command valid every burst length. write burst also terminated using blocking data procreating bank last data input written into active row. OPERATION also.
from time
bank activation. internal timing parameter SDRAM, therefore dependent operating clock frequency. minimum number clock cycles required between bank activate read write command should calculated dividing RCD(min) with cycle time clock then rounding result next higher integer. SDRAM internal banks same chip shares part internal circuitry reduce chip area, therefore restricts activation banks simultaneously. Also noise generated during sensing each bank SDRAM high, requiring some time power supplies recover before other bank sensed reliably. RRD(min) specifies minimum time required between activating different bank. number clock cycles required between different bank activation must calculated similar tRCD specification. minimum time required bank
after
REV. Feb.
ELECTRONICS
DEVICE OPERATIONS
DEVICE OPERATIONS (Continued)
OPERATION
used mask input output operations. works similar during read operation inhibits writing during write operation. read latency cycles from zero cycle write, which means masking occurs cycles later read cycle occurs same cycle during write cycle. operation synchronous with clock. signal important during burst interruptions write with read precharge SDRAM. asynchronous nature internal write, operation critical avoid unwanted incomplete writes when complete burst write required. Please refer timing diagram also.
CMOS SDRAM
AUTO REFRESH
storage cells SDRAM need refreshed every 64ms maintain data. auto refresh cycle accomplishes refresh single storage cells. internal counter increments automatically every auto refresh cycle refresh rows. auto refresh command issued asserting with high auto refresh command only asserted with both banks being idle state device power down mode (CKE high previous cycle). time required complete auto refresh operation specified
RFC(min).
minimum number
clock cycles required calculated driving
with
PRECHARGE
precharge operation performed active bank asserting RAS, 10/AP with valid bank precharged. precharge command asserted anytime after
RAS(min)
clock cycle time them rounding next higher integer. auto refresh command must followed NOP's until auto refresh operation completed. Both banks will idle state auto refresh operation. auto refresh preferred refresh mode when SDRAM being used normal data transactions. auto refresh cycle performed once 15.6us burst 4096 auto refresh cycles once 64ms.
satisfied from bank active
command desired bank. calculated dividing
defined minimum
number clock cycles required complete precharge with clock cycle time rounding next higher integer. Care should taken make sure that burst write completed used inhibit writing before precharge command asserted. maximum time bank active specified
RAS(max).
SELF REFRESH
self refresh another refresh mode available SDRAM. self refresh preferred refresh mode data retention power operation SDRAM. self refresh mode, SDRAM disables internal clock input buffers except CKE. refresh addressing timing internally generated reduce power consumption. self refresh mode entered from both banks idle state asserting RAS, with high Once self refresh mode entered, only state being matters, other inputs including clock ignored order remain self refresh mode. self refresh exited restarting external clock then asserting high CKE. This must followed NOP's minimum time before SDRAM reaches idle state begin normal operation. system uses burst auto refresh during normal operation, recommended burst 4096 auto refresh cycles immediately after exiting self refresh mode.
Therefore, each
bank activate command. precharge, bank enters idle state ready activated again. Entry Power down, Auto refresh, Self refresh Mode register etc. possible only when both banks idle state.
AUTO PRECHARGE
precharge operation also performed using auto precharge. SDRAM internally generates timing satisfy tRAS(min) programmed burst length latency. auto precharge command issued same time burst read burst write asserting high 10/AP. burst read burst write asserting high 10/AP, bank left active until command asserted. Once auto precahrge command given, commands possible that particular bank until bank achieves idle state.
BOTH BANKS PRECHARGE
Both banks precharged same time using Precharge command. Asserting RAS, with high 10/AP after both banks have satisfied RAS(min) requirement, performs precharge both banks. after performing precharge banks, both banks idle state.
REV. Feb.
ELECTRONICS
DEVICE OPERATIONS
BASIC FEATURE FUNCTION DESCRIPTIONS
CLOCK Suspend
Clock Suspended During Write (BL=4
Masked
CMOS SDRAM
Clock Suspended During Read (BL=4)
Masked
Internal DQ(CL2) DQ(CL3) Written
Suspended Dout
Operation
Write Mask (BL=4)
Masked
Read Mask (BL=4)
DQ(CL2) DQ(CL3)
Masked Hi-Z
Hi-Z
Data-in Mask
Data-out Mask
with Clock Suspended (Full Page Read) DQ(CL2) DQ(CL3)
Hi-Z Hi-Z
Note
Hi-Z Hi-Z
Hi-Z Hi-Z
*Note disable/enable 1CLK. makes data Hi-Z after 2CLKs which should masked masks both data-in data-out.
REV. Feb.
ELECTRONICS
DEVICE OPERATIONS
Interrupt
Note
CMOS SDRAM
Read interrupted Read (BL=4) DQ(CL2) DQ(CL3)
tCCD Note
Write interrupted Write (BL=2)
Note
Write interrupted Read (BL=2)
tCCD
Note
tCCD
DQ(CL2) DQ(CL3)
tCDL Note
tCDL Note
*Note Interrupt", meant stop burst read/write external command before burst. Interrupt", stop burst read/write access read write. delay. (=1CLK) Last data column address delay. (=1CLK)
REV. Feb.
ELECTRONICS
DEVICE OPERATIONS
Interrupt (II) Read Interrupted Write
CL=2, BL=4 iii) CL=3, BL=4 iii) iii)
Hi-Z
Note
CMOS SDRAM
Hi-Z
Hi-Z
Hi-Z
Note
Hi-Z
*Note prevent contention, there should least between data data out.
REV. Feb.
ELECTRONICS
DEVICE OPERATIONS
Write Interrupted Precharge
Masked
CMOS SDRAM
Note
Note
*Note prevent contention, should issued which makes least between data data out. inhibit invalid write, should issued. This precharge command burst write command should same bank, otherwise precharge interrupt only other bank precharge dual banks operation.
Precharge
Normal Write (BL=4)
tRDL Note
Normal Read (BL=4) DQ(CL2) DQ(CL3)
Auto Precharge
Normal Write (BL=4)
Note Auto Precharge Starts
Normal Read (BL=4) DQ(CL2) DQ(CL3)
Note Auto Precharge Starts
*Note Last data precharge delay Number valid output data after precharge Latency respectively. active command precharge bank issued after from this point. read/write command other activated bank issued from this point. burst read/write with auto precharge, interrupt same/other bank illegal.
REV. Feb.
ELECTRONICS
DEVICE OPERATIONS
Burst Stop Interrupted Precharge
Normal Write (BL=4)
tRDL
CMOS SDRAM
Write Burst Stop (BL=8)
STOP
Note
tBDL
Note
Read Interrupted Precharge (BL=4) DQ(CL2) DQ(CL3)
Read Burst Stop (BL=4) DQ(CL2)
STOP
DQ(CL3)
Mode Register
Note
2CLK
*Note Last data burst stop delay. Read write burst stop command valid every burst length. Number valid output data after precharge burst stop latency= respectiviely. Both banks precharge necessary. issued only both banks precharge state.
REV. Feb.
ELECTRONICS
DEVICE OPERATIONS
Clock Suspend Exit Power Down Exit
Clock Suspend (=Active Power Down) Exit
CMOS SDRAM
Power Down (=Precharge Power Down) Internal
Note
Internal
Note
Auto Refresh Self Refresh
Auto Refresh Self Refresh
Note Note Note
tRFC
Self Refresh
Note
Note
tRFC
*Note Active power down both banks active state. Precharge power down both banks precharge state. auto refresh same refresh conventional DRAM. precharge commands required after auto refresh command. During from auto refresh command, other command accepted. Before executing auto/self refresh command, both banks must idle state. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry. During self refresh mode, refresh interval refresh operation perfomed internally. After self refresh entry, self refresh mode kept while low. During self refresh mode, inputs expect will don't cared, outputs will Hi-Z state. time interval from self refresh exit command, other command accepted. Before/After self refresh mode, burst auto refresh cycle (4096 cycles) recommended.
REV. Feb.
ELECTRONICS
DEVICE OPERATIONS
About Burst Type Control
Sequential Counting Basic MODE Interleave Counting Random column Access tCCD
CMOS SDRAM
"0". BURST SEQUENCE TABLE. (BL=4, BL=1, full page. "1". BURST SEQUENCE TABLE. (BL=4, BL=4, BL=1, Interleave Counting Sequential Counting Every cycle Read/Write Command with random column address realize Random Column Access. That similar Extended Data (EDO) Operation conventional DRAM.
Random MODE
About Burst Length Control
Basic MODE Full Page Special MODE Random MODE BRSW Burst Stop 2,1,0 "000". auto precharge, should violated. 2,1,0 "001". auto precharge, should violated. 2,1,0 "010". 2,1,0 "011". 2,1,0 "111". burst length, burst will stop automatically. "1". Read burst full page write Burst auto precharge write, should violated. BDL= Valid after burst stop latency respectively Using burst stop command, burst length control possible. Before burst, precharge command same bank stops read/write burst with precharge. tRDL= with DQM, valid after burst stop latency respectively. During read/write burst with auto precharge, interrupt issued. Before burst, read/write stops read/write burst starts read/write burst. During read/write burst with auto precharge, interrupt issued.
Interrupt MODE
Interrupt (Interrupted Precharge)
Interrupt
REV. Feb.
ELECTRONICS
DEVICE OPERATIONS
FUNCTION TRUTH TABLE (TABLE
Current State IDLE Active Read Write Read with Auto Precharge Write with Auto Precharge Precharging code ADDR 10/AP A10/AP code 10/AP 10/AP A10/AP 10/AP 10/AP A10/AP 10/AP 10/AP A10/AP 10/AP 10/AP A10/AP ILLEGAL ILLEGAL Bank) Active Latch Auto Refresh Self Refresh Mode Register Access ILLEGAL ACTION
CMOS SDRAM
Note
Begin Read latch determine Begin Write latch determine ILLEGAL Precharge ILLEGAL (Continue Burst Active) (Continue Burst Active) Term burst active Term burst, Read, Determine Term burst, Write, Determine ILLEGAL Term burst, Precharge timing Reads ILLEGAL (Continue Burst Active) (Continue Burst Active) Term burst active Term burst, read, Determine Term burst, Write, Determine ILLEGAL Term burst, precharge timing Writes ILLEGAL (Continue Burst Precharge) (Continue Burst Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL (Continue Burst Precharge) (Continue Burst Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL Idle after Idle after ILLEGAL ILLEGAL ILLEGAL Idle after
REV. Feb.
ELECTRONICS
DEVICE OPERATIONS
FUNCTION TRUTH TABLE (TABLE
Current State Activating Refreshing Mode Register Accessing Bank Address Column Address ADDR A10/AP ILLEGAL Active after Active after ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Idle after Idle after ILLEGAL ILLEGAL ILLEGAL Idle after clocks Idle after clocks ILLEGAL ILLEGAL ILLEGAL
CMOS SDRAM
ACTION
Note
Abbreviations Address Operation Command
Auto Precharge
*Note entries assume active (High) during precharge clcok current clock cycle. Illegal bank specified state Function Iegal bank indicated depending state that bank. Must satisfy contention, turn around, and/or write recovery requirements. bank precharging idle state. precharge bank indicated (and 10/AP). Illegal bank idle.
REV. Feb.
ELECTRONICS
DEVICE OPERATIONS
FUNCTION TRUTH TABLE (TABLE
Current State (n-1) Self Refresh Banks Precharge Power Down Banks Idle State other than Listed above ADDR Code INVALID ACTION
CMOS SDRAM
Note
Exit Self Refresh Idle after Exit Self Refresh Idle after ILLEGAL ILLEGAL ILLEGAL (Maintain Self Refresh) INVALID Exit Power Down Exit Power Down ILLEGAL ILLEGAL ILLEGAL
(ABI) (ABI)
(Maintain Power Mode) Refer Table Enter Power Down Enter Power Down ILLEGAL ILLEGAL Bank) Active Enter Self Refresh Mode Register Access Refer Operations Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clcok Suspend
Abbreviations Banks Idle, Address *Note high transition asynchronous. high transition asynchronous restarts internal clock. minimum setup time 1CLK must satisfied before command other than exit. Power down self refresh entered only from both banks idle state. Must legal command.
REV. Feb.
ELECTRONICS
TIMING DIAGRAM
Single Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1
CMOS SDRAM
CLOCK
*Note
HIGH tRAS
tRCD
tCCD
*Note *Note *Note *Note *Note
ADDR
*Note
A10/AP
*Note
*Note
*Note *Note
tRAC tSAC
tSLZ
Active
Read
Write
Read Precharge
Active
Don't care
REV. Mar.
ELECTRONICS
TIMING DIAGRAM
CMOS SDRAM
*Note inputs expect care when high high going edge. Bank active read/write controlled
Active Read/Write Bank Bank
Enable disable auto precharge function controlled A10/AP read/write command. A10/AP Operation Disable auto precharge, leave bank active burst. Disable auto precharge, leave bank active burst. Enable auto precharge, precharge bank burst. Enable auto precharge, precharge bank burst.
A10/AP control bank precharge when precharge command asserted. A10/AP Precharge Bank Bank Both Banks
REV. Mar.
ELECTRONICS
TIMING DIAGRAM
Power Sequence
CLOCK
CMOS SDRAM
High level necessary
tRFC tRFC
ADDR
A10/AP
High-Z
High level necessary
Precharge (All Banks)
Auto Refresh
Auto Refresh
Mode Register Active (A-Bank)
Don't care
REV. Mar.
ELECTRONICS
TIMING DIAGRAM
Read Write Cycle Same Bank @Burst Length=4
CLOCK
CMOS SDRAM
HIGH
*Note
tRCD
*Note
ADDR
A10/AP
CL=2
tRAC
*Note
tSAC
tSHZ
*Note
tRDL
CL=3
tRAC
*Note
tSAC
tSHZ
*Note
tRDL
Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Active (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
Don't care *Note Minimum cycle times required complete internal DRAM operation. precharge interrupt burst cycle. [CAS Latency number valid output data available after precharge. Last valid output will Hi-Z(t SHZ) after clcok. Access time from active command. latency Ouput will Hi-Z after burst. Full page burst)
REV. Mar.
ELECTRONICS
TIMING DIAGRAM
Page Read Write Cycle Same Bank @Burst Length=4
CLOCK
tRCD
CMOS SDRAM
HIGH
*Note
ADDR
A10/AP
tRDL
CL=2
CL=3
tCDL
*Note *Note
Active (A-Bank)
Read (A-Bank)
Read (A-Bank)
Write (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
Don't care
*Note
write data before burst read ends, should asserted three cycle prior write command avoid contention. precharge will interrupt writing. Last data input, before precharge, will written. should mask invalid input data precharge command cycle when asserting precharge before burst. Input data after precharge cycle will masked internally.
REV. Mar.
ELECTRONICS
TIMING DIAGRAM
Page Read Cycle Different Bank @Burst Length=4
CLOCK
*Note
CMOS SDRAM
HIGH
*Note
ADDR
A10/AP
CL=2
QAa0 QAa1
QAa2 QAa3
QBb0
QBb1 QBb2 QBb3
QAc0
QAc1
QBd0 QBd1
QAe0 QAe1
CL=3
QAa0 QAa1
QAa2
QAa3
QBb0 QBb1 QBb2 QBb3
QAc0
QAc1
QBd0
QBd1 QAe0 QAe1
Active (A-Bank)
Active (B-Bank) Read (A-Bank)
Read (B-Bank)
Read (A-Bank)
Read (B-Bank)
Read (A-Bank)
Precharge (A-Bank)
Don't care
*Note
don't cared when RAS, high clock high going dege. interrupt burst read precharge, both read precharge banks must same.
REV. Mar.
ELECTRONICS
TIMING DIAGRAM
Page Write Cycle Different Bank @Burst Length=4
CLOCK HIGH
CMOS SDRAM
*Note
ADDR
A10/AP
DAa0
DAa1 DAa2
DAa3
DBb0
DBb1
DBb2 DBb3
DAc0
DAc1
DBd0
DBd1
tCDL
tRDL
*Note
Active (A-Bank)
Active (B-Bank) Write (A-Bank)
Write (B-Bank)
Write (A-Bank) Write (B-Bank)
Precharge (Both Banks)
Don't care
*Note
interrupt burst write precharge, should asserted mask invalid input data. interrupt burst write precharge, both write precharge banks must same.
REV. Mar.
ELECTRONICS
TIMING DIAGRAM
Read Write Cycle Different Bank @Burst Length=4
CLOCK HIGH
CMOS SDRAM
ADDR
A10/AP
tCDL
*Note
CL=2
QAa0
QAa1
QAa2 QAa3
DBb0
DBb1
DBb2 DBb3
QAc0
QAc1
QAc2
CL=3
QAa0 QAa1
QAa2 QAa3
DBb0
DBb1
DBb2 DBb3
QAc0
QAc1
Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank) Active (B-Bank)
Write (B-Bank) Active (A-Bank)
Read (A-Bank)
Don't care
*Note
should complete write.
REV. Mar.
ELECTRONICS
TIMING DIAGRAM
Read Write Cycle with Auto Precharge @Burst Length=4
CLOCK HIGH
CMOS SDRAM
ADDR
A10/AP
CL=2
CL=3
Active (A-Bank)
Read with Auto charge (A-Bank) Active (B-Bank)
Read without Auto precharge(B-Bank) Auto Precharge Start Point (A-Bank)*
Precharge (B-Bank)
Active (A-Bank)
Write with Auto Precharge (A-Bank)
Don't care *Note: When Read(Write) command with auto precharge issued A-Bank after Bank activation. Read(Write) command without auto precharge issued B-Bank before Bank auto precharge starts, Bank auto precharge will start Bank read command input point command issued Bank during after Bank auto precharge starts.
REV. Mar.
ELECTRONICS
TIMING DIAGRAM
Read Write Cycle with Auto Precharge @Burst Length=4
CLOCK HIGH
CMOS SDRAM
ADDR
A10/AP
CL=2
CL=3
Active (A-Bank) Read with Auto Precharge (A-Bank) Auto Precharge Start Point (A-Bank) Active (B-Bank) Read with Auto Precharge (B-Bank) Auto Precharge Start Point (B-Bank)
Don't care *Note command A-bank allowed this period. determined from auto precharge start point
REV. Mar.
ELECTRONICS
TIMING DIAGRAM
Clock Suspension Operation Cycle @CAS Latency=2, Burst Length=4
CLOCK
CMOS SDRAM
ADDR
A10/AP
tSHZ
tSHZ
*Note
Active
Read
Clock Suspension
Read
Read Write
Write Clock Suspension
Write
Don't care
*Note
needed prevent contention.
REV. Mar.
ELECTRONICS
TIMING DIAGRAM
CMOS SDRAM
Read Interrupted Precharge Command Read Burst Stop Cycle @Burst Length=Full page
CLOCK HIGH
ADDR
A10/AP
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
*Note
CL=2
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
CL=3
QAa0
QAa1 QAa2
QAa3 QAa4
Active (A-Bank)
Read (A-Bank)
Burst Stop
Read (A-Bank)
Precharge (A-Bank)
Don't care
*Note
full page mode, burst burst. auto precharge possible. About valid after burst stop, same case interrupt. Both cases illustrated above timing diagram. label them. burst write, Burst stop interrupt should compared carefully. Refer timing diagram "Full page write burst stop cycle". Burst stop valid every burst length.
REV. Mar.
ELECTRONICS
TIMING DIAGRAM
CMOS SDRAM
Write Interrupted Precharge Command Write Burst Stop Cycle Burst Length=Full page
CLOCK
HIGH
ADDR
A10/AP
tBDL
*Note
tRDL
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
DAa0
DAa1
DAa2
DAa3 DAa4
Active (A-Bank)
Write (A-Bank)
Burst Stop
Write (A-Bank)
Precharge (A-Bank)
Don't care
*Note
full page mode, burst burst. auto precharge possible. Data-in cycle interrupted precharge written into corresponding memory cell. defined parameter RDL. write interrupted precharge command needed prevent invalid write. should mask invalid input data precharge command cycle when asserting precharge before burst. Input data after precharge cycle will masked internally. Burst stop valid every burst length.
REV. Mar.
ELECTRONICS
TIMING DIAGRAM
Burst Read Single Write Cycle @Burst Length=2
CLOCK
*Note
CMOS SDRAM
HIGH
*Note
ADDR
A10/AP
CL=2
DAa0
QAb0
QAb1
DBc0
QAd0
QAd1
CL=3
DAa0
QAb0
QAb1
DBc0
QAd0
QAd1
Active (A-Bank)
Active (B-Bank) Write (A-Bank)
Active (A-Bank) Write with Auto Precharge (B-Bank)
Read (A-Bank)
Precharge (A-Bank)
Read with Auto Precharge (A-Bank)
Don't care
*Note
BRSW modes enabled setting "High" (Mode Register Set). BRSW Mode, burst length write fixed regaredless programmed burst length. When BRSW write command with auto precharge executed, keep mind that should violated. Auto precharge executed burst-end cycle, case BRSW write command, next cycle starts precharge.
REV. Mar.
ELECTRONICS
TIMING DIAGRAM
Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4
CLOCK
CMOS SDRAM
*Note
*Note
*Note
ADDR
A10/AP
tSHZ
Precharge Power-down Entry
Active
Read
Precharge
Precharge Active Power-down Power-down Exit Entry
Active Power-down Exit
Don't care
*Note
Both banks should idle state prior entering precharge power down mode. should high least 1CLK prior active command. violate minimum refresh specification. (64ms)
REV. Mar.
ELECTRONICS
TIMING DIAGRAM
Self Refresh Entry Exit Cycle
CLOCK
*Note *Note
CMOS SDRAM
*Note
tRFCmin
*Note
*Note
*Note
*Note
ADDR
A10/AP
Hi-Z
Hi-Z
Self Refresh Entry
Self Refresh Exit
Auto Refresh Don't care
*Note
ENTER SELF REFRESH MODE with should same clcok cycle. After clock cycle, inputs including system clock don't care except CKE. device remains self refresh mode long stays "Low". cf.) Once device enters self refresh mode, minimum required before exit from self refresh. EXIT SELF REFRESH MODE System colck restart stable before returning high. starts from high. Minimum required after going high complete self refresh exit. cycle burst auto refresh required before self refresh entry after self refresh exit system uses burst
resh.
REV. Mar.
ELECTRONICS
TIMING DIAGRAM
Mode Register Cycle
CLOCK
*Note
CMOS SDRAM
Auto Refresh Cycle
HIGH
HIGH
tRFC
*Note
*Note
ADDR
Hi-Z
Hi-Z
Command
Auto Refresh
Command
Don't care
Both banks precharge should completed before Mode Register cycle auto refresh cycle.
MODE REGISTER CYCLE *Note RAS, CAS, activation same clock cycle with address will internal mode register. Minimum clock cycles should before activation. Please refer Mode Register table.
REV. Mar.
ELECTRONICS

CMOS SDRAM Revision History Revision .3(November 1997) tRDL chang

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