24L32F Memory Cell Density RecommendedOperating Condition Operating Ti
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Sirial Wire CBUS Type EEPROM"L"Ver.vs "E"Ver.
24L32F Memory Cell Density RecommendedOperating Condition Operating Time Supply Voltage Clock Frequency Write Time Noise suppression time Hold Time Setup Time Effective Time Effective Period P.O.R Feature LVCC Feature Power Reset Voltage Data retention Erase/Write Cycles HDWP SUWP HIGHWP VLVCC year cycle W-cell 32Kbit 1.8-5.5 Vcc=2.5-5.5V Vcc=1.8-2.5V rising edge clock which take 0.3R= Below 10ms 0.2R=Below 100ms 1.2V (Typ.) 1,000,000 24E16F Single-Cell 16Kbit 2.7-5.5 Vcc=4.5-5.5V Vcc=2.7-3.3V 0.05 down edge clock which take 0.2R=Below 10ms 0.1R=Below 100ms 1.8V (Typ.) 100,000 Fig.1 Fig.2 Attention.1
Copyright 2007 ROHM Co., Ltd. rights reserved.
Caution1. Address timing
DATA DATA
SLAVE ADDRESS
a)BR24E16F ADDRESS TIMING(ex; PAGE WRITE
WA12="L"
DATA DATA
SLAVE ADDRESS
b)BR24L32F-W ADDRESS TIMING(ex; PAGE WRITE
Copyright 2007 ROHM Co., Ltd. rights reserved.
"C"Ver down edge
"L"Ver rising edge
rising edge
SLAVE ADDRESS
WORD ADDRESS
Data
cancellation invalid period
cancellation effective Stop write operation period
data will written Data guaranteed
FigWP EFFECTIVE
Copyright 2007 ROHM Co., Ltd. rights reserved.
"L"Ver
Recommended Operating Condition tR,tOFF,Vbot
Below 10ms Below 100ms tOFF Above 10ms Above 10ms Vbot Below 0.3V Below 0.2V
"C"Ver
Recommended Operating Condition tR,tOFF,Vbot
Below 10ms Below 100ms tOFF Above 10ms Above 10ms Vbot Below 0.2V Below 0.1V
tOFF
Vbot
Fig2. Wave Profile
Copyright 2007 ROHM Co., Ltd. rights reserved.
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