Multistandard Digital Video Encoder Features All-digital vid
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TMC22290
Multistandard Digital Video Encoder
Features
All-digital video encoding Internal digital subcarrier synthesizer 8-bit parallel CCIR-601/CCIR-656/ANSI/SMPTE 125M input iormat CCIR-624/SMPTE-170M compliant output Switchable chrominance bandwidth Switchable pedestal with gain compensation Pre-programmed horizontal vertical timing 13.5 Mpps pixel rate Synchronizes incoming data stream Subcarrier phase frequency values input through ancillary data packet video stream Internal interpolation simplify output reconstruction 9-bit converters video reconstruction Supports NTSC standards Output encoding Macrovision copy protection (Revision available (TMC22291) Simultaneous S-Video (Y/C) output Controlled edge rates (IEEE 1149.1-1990) test interface Single power supply lead PLCC package Parallel serial control interface
Applications
Settop Digital Cable Television Receivers Settop Digital Satellite Television Receivers Studio Parallel CCIR-601 Analog Conversion
Description
TMC22290 video encoder converts digital component video 8-bit parallel CCIR-601/656 ANSI/SMPTE 125M format) into standard analog baseband television (NTSC, NTSC-EIA, standards) signal with modulated color subcarrier. Both composite (single lead) S-Video (separate chroma luma) formats active simultaneously three analog outputs. Each video output generates standard video-level signal capable driving singly- doubly-terminated load. TMC22290 fabricated submicron CMOS process packaged 44-lead PLCC. Performance guaranteed over full 70°C operating temperature range.
Block Diagram
PD7-0 Pixel Data Demux Sync Extract Interpolator 4:2:2 4:4:4 Digital Sync Generator Subcarrier Synthesizer 9-bit LUMA Chroma Modulator Interpolation Filter 9-bit CHROMA S-VIDEO COMPOSITE VREF CBYP RREF
65-3721-01
PXCK
Sync Blank Inserter Interpolation Filter
9-bit
Serial/Parallel Control
Global Control
JTAG
Serial Parallel
RESET D7-0
Rev. 1.0.0
This document created with FrameMaker
PRODUCT SPECIFICATION
TMC22290
General Description
TMC22290 fully-integrated digital video encoder with simultaneous composite (S-Video) outputs. TMC22290 video outputs compatible with NTSC, NTSC-EIA, television standards. external component selection tuning required. prevent unauthorized video taping, output data stream Macrovision copy protection system (Revision This feature available TMC22291 only Macrovision licensees. Consult factory information. encoder accepts digital component video port 8-bit parallel CCIR-601/656 format. demultiplexed into luminance chrominance components. chrominance components modulate digitally synthesized subcarrier. luminance chrominance signals separately interpolated twice input pixel rate converted analog levels 9-bit converters. They also digitally combined resulting composite signal output third 9-bit converter. encoder operates from single clock MHz, twice system pixel rate. Programmable control registers allow software control subcarrier frequency phase parameters. Incoming YCBCR422 digital video interpolated YCBCR444 format encoding. Internal control registers accessed over standard 8-bit parallel microprocessor port 2-pin (clock data) serial port.
PD7-0 PXCK RESET SA0/ADR TMC22290 CHROMA LUMA COMPOSITE VREF CBYP RREF
65-3721-02
Sync Generator
TMC22290 operates slave mode, extracting horizontal vertical sync timing information from CCIR-656 (End Active Video) signal incoming data stream. Horizontal vertical synchronization pulses analog output digitally generated TMC22290 with controlled rise fall times sync edges, beginning active video, burst envelope.
Chroma Modulator
digital subcarrier synthesizer drives quadrature modulator, producing digital chrominance signal. chroma bandwidth programmed 650kHz MHz. relative phases burst active video portions subcarrier adjusted with respect falling edge horizontal sync. This sets phasing TMC22290. phase adjustment accomplished through parallel serial ports well ancillary data prior each line incoming video.
Interpolation Filters
Interpolation luminance chrominance signals double pixel rate preparation conversion. This low-pass oversampling process greatly output required after converters dramatically reduces sin(x)/x distortion.
Converters
analog outputs TMC22290 driven three 9-bit converters, operating MHz. outputs drive standard video levels into loads. internal voltage reference used provide reference current converters. more accurate video levels, external variable voltage reference source accommodated. video signal levels from TMC22290 adjusted overcome insertion loss analog low-pass output varying RREF VREF.
Multistandard Digital Video Encoder
Parallel Serial Microprocessor Interfaces
parallel microprocessor interface employs pins. These shared with serial interface, single pin, SER, selects between interface modes. parallel interface mode, address line decoded access internal control register pointer. Controls reached loading desired address through 8bit D7-0 port, followed desired data (read write) that address. control register address pointer auto-increments address then remains there. 2-line serial interface also provided TMC22290 initialization control. same registers accessed parallel port available serial port.
D7-0 SCL/CS SDA/R/W
Figure Logic Symbol
(n+1)
Figure Pixel Data Format
Samples CB(n), Y(n), CR(n) cosited.
TMC22290
PRODUCT SPECIFICATION
RESET sets internal state machines their initialized conditions, disables analog outputs, places encoder power-down mode. register data maintained while power-down mode. power-up. encoder automatically initialized NTSC-M format.
JTAG Test Interface
TMC22290 includes standard 4-line JTAG (IEEE 1149.1-1990) test interface port, providing access digital input/output data pins. This provided facilitate component board-level testing.
Assignments
SA0/ADR SDA/R/W
SCL/CS
CHROMA CBYP LUMA COMPOSITE
RESET
PXCK
VREF
RREF
65-3721-21
Descriptions
Name Clock PXCK Pixel Clock Input. This 27.0 clock internally divided generate internal pixel clock. PXCK drives entire TMC22290, except asynchronous microprocessor interface. internal registers strobed rising edge PXCK. Pixel Data Inputs. Video data enter TMC22290 PD7-0 (Figure Master Reset Input. Bringing RESET forces internal state machines their starting states, sets control registers their default values, disables outputs. Data Port. Parallel control port. When HIGH, control parameters loaded into read back over this 8-bit port. When LOW, serves composite sync output, outputs burst flag during back porch, D2-5 General Purpose Outputs, D6-7 General Purpose Inputs. Serial Address Select. When LOW, conjunction with selects one-of-four addresses TMC22290. Number Value Function Description
Data Input PD7-0 Proc RESET 38-44,
D7-0
9-12, 14-17
PRODUCT SPECIFICATION
TMC22290
Descriptions (continued)
Name Number Value Function Description Serial/Parallel Port Select. When LOW, 2-line serial interface activated. Pins function SA0, SDA, respectively. When HIGH, parallel interface port active pins function ADR, R/W, respectively. Serial/Parallel Port Address. When LOW, conjunction with selects one-of-four addresses TMC22290. When HIGH, this control governs whether parallel microprocessor interface selects table address reads/ writes table contents. also governs setting verification TMC22290's internal operating modes, also over port D7-0.
SA0/ADR
SDA/R/W
R-Bus/TTL Serial Data/Read/Write Control. When LOW, data line serial interface. When HIGH, read/write control parallel interface. When LOW, microprocessor write control registers over D70. When HIGH LOW, read contents selected control register over D7-0. R-Bus/TTL Serial Clock/Chip Select. When LOW, clock line serial interface. When HIGH, chip select control parallel interface. When HIGH, microprocessor interface port, D7-0, HIGH impedance ignored. When LOW, microprocessor read write parameters over D7-0. 1.35 Composite NTSC/PAL Video. Analog output composite converter, nominally 1.35 volt peak-to-peak into doubly terminated load. 1.35 Luminance-only Video. Analog output luminance converter, nominally 1.35 volt peak-to-peak into doubly terminated load. 1.35 Chrominance-only Video. Analog output chrominance converter, nominally 1.35 volt peak-to-peak into doubly terminated load. +1.23 787W Voltage Reference Input. External voltage reference input, internal voltage reference output, nominally 1.235 Reference Bypass Capacitor. Connection point decoupling capacitor. Current-setting Resistor. Connection point external currentsetting resistor converters. resistor connected between RREF GND. Output video levels inversely proportional value RREF. Data Input Port. Boundary scan data input port. Scan Select Input. Boundary scan (HIGH) normal operation (LOW) selector. Scan Clock Input. Boundary scan clock. Data Output Port. Boundary scan data output port.
SCL/CS
Analog Outputs COMPOSITE
LUMA
CHROMA
Reference VREF CBYP RREF
JTAG
TMC22290
PRODUCT SPECIFICATION
Descriptions (continued)
Name Power Power Supply. Positive power supply circuits. Ground. Ground analog circuits, Number Value Function Description
Control Registers
TMC22290 initialized controlled registers which determine operating modes. external controller employed write read Control Registers through either 8-bit parallel 2-line serial interface port. parallel port, D7-0, governed pins R/W, ADR. serial port controlled SCL.
Name ANCFREN ANCPHEN ANCTREN
Function Ancillary FREQ enable Ancillary SCHPH enable Ancillary timing ref. enable Ancillary identification Subcarrier frequency Subcarrier freq. byte Subcarrier freq. byte Subcarrier frequency Subcarrier phase MSBs Subcarrier phase LSBs General Purpose Inputs General Purpose Outputs Burst Flag Output Composite Sync Output
Ancillary Data Register ANCID FREQ3 FREQ2 FREQ1 FREQ0 SCHPHM SCHPHL PORT7-6 PORT5-2 BURSTF CSYNC reserved Subcarrier Frequency Register
Table Control Register
Name PARTID2 PARTID1 PARTID0 REVID reserved YCDELAY RAMPEN YCDIS COMPDIS FORMAT reserved BURSTF CHRBW SYNCDIS BURDIS LUMDIS CHRDIS PEDEN reserved FIELD Field (Read only) Burst flag disable Chroma bandwidth select Sync pulse disable Color burst disable Luminance disable Chrominance disable Pedestal enable Luma chroma delay Modulated ramp enable LUMA, CHROMA disable COMPOSITE disable Television standard select Function TMC22290 Identification Registers (Read only 7Fh) (Read only 3Ah) (Read only 95h) (Read only Revision
0FFF
Subcarrier Phase Offset Register
Global Control Register
General Purpose Port (when SER=LOW)
Reserved Registers
Video Output Control Register
Notes: Functions listed order reading writing. each register listed above, bits specified reserved should zero ensure proper operation.
Table Power-Up Default Register Values
Dflt Dflt Dflt Dflt
Horizontal Ancillary Data Control Register
PRODUCT SPECIFICATION
TMC22290
Control Register Definitions
TMC22290 Identification Registers (read only)
Name PARTID2 PARTID1 PARTID0 REVID Description Reads back Reads back Reads back Reads back value corresponding revision letter silicon.
Global Control Register (04)
Reserved YCDELAY Name YCDELAY RAMPEN YCDIS COMPDIS FORMAT
Description Reserved. When HIGH, luminance path within TMC22290 delayed PXCK period. delay applies only LUMA output used compensate group delay variation external filters. When LOW, luminance chrominance have same latency. COMPOSITE output always equal luminance chrominance latencies. When HIGH, TMC22290 outputs modulated ramp test signal. When LOW, incoming digital video encoded. When HIGH, LUMA CHROMA outputs disabled, reducing power consumption. normal enabled operation. When HIGH, COMPOSITE output disabled. normal enabled operation. Output video format select. Subcarrier frequency, pedestal level, chrominance bandwidth independently programmed. NTSC PAL-B,G,H,I,N PAL-M Reserved
RAMPEN YCDIS COMPDIS FORMAT
TMC22290
PRODUCT SPECIFICATION
Control Register Definitions (continued)
VIdeo Output Control Register (05)
Reserved BURSTF CHRBW SYNCDIS Name BURSTF Description Reserved. When BURSTF LOW, clamp gate signal produced output register When LOW, chrominance bandwidth ±650 kHz. When HIGH, chrominance bandwidth ±1.3 MHz. When HIGH, horizontal vertical sync pulses COMPOSITE video output suppressed (blanking level). Color burst, active video, COMPSYNC output remain active. normal composite video operation. When HIGH, color burst suppressed (blanking level). normal operation. When HIGH, incoming values forced black level. Color burst, CHROMA, sync affected. normal operation. When HIGH, incoming color components suppressed enabling monochrome operation. Output color burst affected. normal color operation. When LOW, black blanking same level lines. When HIGH, pedestal inserted into output video NTSC PAL-M lines 23262 286-525 only. Chrominance luminance gain factors adjusted appropriately. PEDEN valid NTSC PAL-M only should other formats. CHRBW SYNCDIS BURDIS CHRDIS PEDEN
BURDIS LUMDIS CHRDIS
PEDEN
Horizontal Ancillary Data Control Register (06)
Reserved FIELD ANCFREN Name Description Reserved. Digital field identification. read-only value corresponds field corresponds field When HIGH, TMC22290 gets subcarrier frequency data (FREQ3-0) from incoming ancillary data accordance with bit). When LOW, FREQ3-0 registers contain subcarrier frequency data. When HIGH, TMC22290 gets subcarrier phase offset data (SCHPHL SCHPHM) from incoming ancillary data accordance with bit). When LOW, default value 0000h used subcarrier phase. When HIGH, TMC22290 decodes incoming ancillary data determine video timing (FIELD SVF). When LOW, ancillary timing reference data ignored. FIELD ANCFREN ANCPHEN ANCTREN
ANCPHEN
ANCTREN
PRODUCT SPECIFICATION
TMC22290
Control Register Definitions (continued)
Ancillary Data Register (07)
Name ANCID Description Bits determine ancillary data identification. parity bit, TMC22090 does check parity. value this register must match that incoming ancillary data.
Subcarrier Frequency Registers
Name FREQ3 FREQ2 FREQ1 FREQ0 Description Eight MSBs (bits 31-24) 32-bit subcarrier frequency value. Bits 23-16 32-bit subcarrier frequency value. Bits 15-8 32-bit subcarrier frequency value. Eight LSBs (bits 7-0) 32-bit subcarrier frequency value.
Subcarrier Phase Offset Registers
Name SCHPHM SCHPHL Description Eight MSBs (bits 15-8) 16-bit subcarrier phase offset value. Values other than used adjust phase TMC22290. Eight LSBs (bits 7-0) 16-bit subcarrier phase offset value. Values other than used adjust phase TMC22290.
General Purpose Port Register (0E)
PORT7 PORT6 Name PORT7-6 PORT5-2 PORT5 Description D7-6 input pins. When serial control mode, these register read-only bits indicate state present data port pins D5-2 output pins. When serial control mode when reading register parallel control mode, these register read/write bits drive data pins D5-D2 state contained respective register bits. output pin. Produces Burst Flag when serial control mode, when reading register output pin. Produces Composite Sync when serial control mode, when reading register PORT4 PORT3 PORT2 BURSTF CSYNC
BURSTF CSYNC
Reserved Registers
0FFF Name Description Reserved. left unwritten.
TMC22290
PRODUCT SPECIFICATION
General Purpose Port
TMC22290 provides general purpose port system utility functions. Input, output, sync functions implemented. Register General Purpose Register. Full functionality provided when encoder Serial control mode (SER LOW). Most functions available parallel interface mode (SER HIGH).
These register bits read time over either serial parallel control port. they dynamic, their states will change appropriate during parallel port read. fact, parallel control port commanded read register continually, pins associated with these bits behave burst composite sync timing outputs. serial control mode, these same data output pins (D1-0) always burst composite sync outputs, conditions serial control notwithstanding. states read over serial port, frequency serial interface, meaningful information.
General Purpose Input (serial mode only)
Bits Register general purpose inputs. When encoder serial control mode, data bits connected these register locations. When Register read, states bits levels present respectively, time read command execution. Writing these bits effect. This function available when encoder parallel control mode.
Horizontal Vertical Timing
Horizontal vertical video timing TMC22290 preprogrammed line-locked systems with pixel clock 27.0 MHz. Table Table show timing parameters NTSC standards well actual expected timing TMC22290. Exactly pixels active video provided user 525/60 standards, pixels 625/50 systems. TMC22290 precisely controls duration activity other segments horizontal line vertical group. vertical group comprises several different line types based upon Horizontal line time. [Vertical sync pulses] [Equalization pulses] SMPTE 170M NTSC Report video standards call rise fall times critical portions video waveform. chip does this automatically, requiring user intervention. TMC22290 digitally slopes compatible with SMPTE 170M NTSC CCIR Report vital edges: Sync leading trailing edges. Burst envelope. Active video leading trailing edges. vertical interval equalization pulse sync edges.
General Purpose Output
Register read/write bits connected pins D5-2, respectively, when encoder serial control mode. output pins continually values most recently written into register HIGH, LOW). Note that these pins always driven outputs when encoder serial control mode. When register read, these pins report values previously stored corresponding register bits, i.e., acts read/write register. When encoder parallel control mode, this reading produces output values corresponding data pins, just serial control mode. However, values only present when reading register controller command continuous read this register produce continuous outputs from these pins.
Burst Flag Composite Sync (output/ read-only)
Register associated with encoder burst (HIGH) from just before start colorburst just after burst. (LOW) other times. internally delayed match internal encoder latency, synchronous with LUMA COMPOSITE outputs. Register reports encoder composite sync. (LOW) during horizontal vertical sync tips. (HIGH) other times.
PRODUCT SPECIFICATION
TMC22290
Table Horizontal Timing Standards Actual Values Video Standards (ms)
NTSC (SMPTE 170M) Parameter Front porch Horiz. Sync Breezeway Color Burst Color Back porch Blanking Active Video Line Time Equalization HIGH Equalization Sync HIGH Sync Sync rise fall times 0.508 2.235 0.998 10.5 52.56 0.608 2.514 1.378 10.7 52.86 63.556 29.5 27.1 140±20 0.809 2.794 1.857 11.0 53.06 PAL-M (CCIR 624) 1.27 2.237 0.503 10.7 52.46 10.9 52.66 63.556 29.5 27.1 <250 2.517 2.22 2.797 2.363 11.1 52.86 TMC22290 1.48 4.74 0.59 (NTSC) 1.04 (PAL-M) 2.37 1.63 (NTSC) 1.19 (PAL-M) 10.81 52.74 63.56 29.41 2.37 4.74 27.04
Table Horizontal Timing Standards Actual Values Video Standards (ms)
PAL-B,G,H,I (CCIR 624) Parameter Front porch Horiz. Sync Breezeway Color Burst Color Back porch Blanking Active Video Line Time Equalization HIGH Equalization Sync HIGH Sync Sync rise fall times 11.7 51.7 2.030 2.255 2.654 12.0 52.0 29.65 2.35 27.3 250±50 12.3 52.3 11.7 51.7 2.481 PAL-N (CCIR 624) 2.233 2.513 2.387 12.0 52.0 29.65 2.35 27.3 200±100 12.3 52.3 2.792 TMC22290 1.41 4.74 0.89 2.37 2.15 11.56 52.44 64.0 29.63 2.37 4.74 27.26
TMC22290
PRODUCT SPECIFICATION
Burst
65-3721-03
65-3721-04
Figure Horizontal Blanking Interval Timing
Figure Vertical Sync Equalization Pulse Detail
FIELDS
COMPOSITE SYNC
FIELDS
COMPOSITE SYNC
65-3721-05
Figure NTSC Vertical Interval
Table NTSC Field/Line Sequence Identification
Field Line
Field Line Line
Field Line
Field
Equalization pulse Vertical sync pulse Equalization broad pulse Half-line video, half-line equalization pulse
Half-line vertical sync pulse, half-line equalization pulse Half-line equalization pulse, half-line vertical sync pulse Active video
PRODUCT SPECIFICATION
TMC22290
1247
1248 1249 1260
COMPOSITE SYNC
FIELDS
COMPOSITE SYNC
FIELDS
COMPOSITE SYNC
FIELDS
COMPOSITE SYNC
65-3721-06
Figure PAL-B, Vertical Interval
TMC22290
PRODUCT SPECIFICATION
Table PAL-B, Field/Line Sequence Identification
Fields 000, Line
Fields 001, Line
Fields 011, Line
Fields 011, Line 1246 1247 1248 1249 1250
Equalization pulse Half-line vertical sync pulse, half-line equalization pulse Vertical sync pulse Half-line equalization pulse, half-line vertical sync pulse Equalization broad pulse Active video Active video with color burst suppressed Half-line video, half-line equalization pulse, color burst suppressed
PRODUCT SPECIFICATION
TMC22290
FIELDS
COMPOSITE SYNC
FIELDS
COMPOSITE SYNC
FIELDS
COMPOSITE SYNC
FIELDS
COMPOSITE SYNC
65-3721-07
Figure PAL-M Vertical Interval
TMC22290
PRODUCT SPECIFICATION
Table PAL-M Field/Line Sequence Identification
Field 000, Line
Field 001, Line
Field 010, Line
Field 011, Line
Equalization pulse Half-line vertical sync pulse, half-line equalization pulse Vertical sync pulse Half-line equalization pulse, half-line vertical sync pulse Equalization broad pulse Active video Active video with color burst suppressed Half-line video, half-line equalization pulse, color burst suppressed half-line black, half-line video
Subcarrier Generation Synchronization
color subcarrier produced internal digital frequency synthesizer with programmable frequency phase. subcarrier synthesizer gets frequency phase values from control registers ancillary data packet. subcarrier internally synchronized establish maintain relationship between leading edge horizontal sync color burst phase (SCH). NTSC PAL, synchronization performed every eight sequence. Proper subcarrier phase maintained through entire eight set, including offset PAL-N,B,I systems subcarrier synthesizer seed value (stored FREQ3, FREQ2, FREQ1, FREQ0) depends upon desired subcarrier frequency pixel rate: FREQ10 (Subcarrier frequency 13.5 MHz) (Subcarrier cycles line pixels line) Converting FREQ10 hexadecimal yields values FREQ3, FREQ2, FREQ1, FREQ0 registers.
Phase Error Correction
refers timing relationship between point leading edge horizontal sync positive negative zero-crossing color burst subcarrier reference. PAL, line since there color burst line usually measured line need specify relative particular line offset subcarrier frequency. Since NTSC such offset, applies lines. Based upon operating mode TMC22290, subcarrier phase reset once every eight lineby-line basis, (free run). resetting subcarrier phase always synchronized with point falling edge horizontal sync. When eight reset employed, subcarrier reset phase values found Table
PRODUCT SPECIFICATION
TMC22290
Table Subcarrier Color Burst Reset Values
NTSC Digital field: Line number: Subcarrier phase reset value: Resultant color burst phase: 180° PAL-M PAL-B,G,H,I,N +135° +135°
SCHPH control register used compensate subcarrier phase group delay variation external analog This register adds constant phase shift subcarrier. This phase offset adjustable from 360° SCHPH value 0000h equals offset while SCHPH value 8000h equal 180°. 13-bit subcarrier phase value from ancillary data packet will absolute phase subcarrier synthesizer line-by-line basis. phase values from ancillary data used, absolute phase synthesizer zero. SCHPH phase value phase offset added subcarrier phase after synthesizer.
Note: Line numbering accordance with Figure Figure Figure Subcarrier color burst phase relative horizontal reference line specified above.
Table Standard Subcarrier Parameters
Standard NTSC B,G,H,I PAL-M PAL-N Horizontal Frequency (MHz) 15.734266 15.625000 15.734266 15.625000 Subcarrier FREQ Registers PHASE Register SCHPH Register Frequency (MHz) (hex) (hex) (hex) 3.579545455 4.43361875 3.57561189 3.58205625 43E0F83E 54131596 43CDDFC7 43ED288D 0000 0000 0000 0000 0000 0000 0000 0000
Note: PHASE Register accessed ancillary data packet only.
Luminance Processing
During horizontal vertical blanking, luma processor generates blanking levels properly timed shaped sync equalization pulses. During active video, captures rescales incoming components adds results blank level complete proper monochrome television waveform, which then upsampled drive luma composite adder. NTSC-EIA (5:2 white:sync, black pedestal), overall luma input-to-output transfer function 0<Y<255 luma (IRE, relative blank) 100/219
NTSC PAL-M (5:2, with pedestal), equation becomes: luma (IRE, relative blank) 92.5/219 common 625-line standards (7:3, pedestal), equation becomes: luma (mV, relative blank) (Y-16) 700/219 Since Y=255 reserved values CCIR-601, trap causes them output black, i.e., without pedestal, with pedestal.
Table Luminance Input Codes
PD7-0 Input reserved 100% white Black Luma Level (CCIR-601) reserved NTSC, PAL-M Luma Level (IRE) PEDEN 108.7 -6.9 PEDEN PAL-B, Luma Level (mV)
TMC22290
PRODUCT SPECIFICATION
Table Converter Analog Levels
NTSC, PAL-M Video Level Maximum Output 100% white Black Blank Sync White-to-blank White-to- sync Color burst 137.2 7.37 NTSC Setup 137.2 PAL-B, 977.5 -300 1000
Filtering Within TMC22290
TMC22290 incorporates internal digital establish appropriate bandwidths simplify external analog designs. chroma portion incoming digital video bandlimited reduce edge effect other distortions image compression process. Chrominance bandwidth selected CHRBW (control register When LOW, chrominance passband attenuation ±650 from fSC. stopband rejection outside MHz. When HIGH, chrominance passband attenuation ±1.3 from fSC. stopband rejection outside MHz.
Attenuation (dB)
65-3721-08
Attenuation (dB)
65-3721-09
Frequency (MHz) 13.5 Mpps
Figure Chrominance Luminance Interpolation Filter Full Spectrum Response
CCIR Specification
Virtually digital-to-analog reconstruction systems exhibit high frequency roll-off result zero-order hold characteristic classic converters. This response commonly referred sin(x)/x response. function sampling rate output D/A.
Attenuation (dB)
65-3721-10
Frequency (MHz) 13.5 Mpps
Figure Color-Difference Low-Pass Filter Response
Chroma Modulator output luminance data path digitally with sharp-cutoff low-pass interpolation These ensure that aliased subcarrier, chrominance, luminance frequencies suppressed frequency band above base-band video below pixel frequency (fS/4 fS/4, where PXCK frequency).
Figure Chrominance Luminance Interpolation Filter Passband Detail
TMC22290's digital interpolation convert data stream sample rate twice pixel rate. This results much less high frequency sin(x)/x rolloff output spectrum between fS/4 fS/4 contains very little energy. Since there little signal energy this frequency band, demands placed output reconstruction
PRODUCT SPECIFICATION
TMC22290
greatly reduced. output needs fS/4 have good rejection fS/4. relaxed requirements greatly simplify design with good phase response group delay distortion. small amount peaking used compensate residual sin(x)/x rolloff.
Attenuation (dB)
65-3721-11
three words ancillary data comprise signal (ANC2-0) which indicates active video. Also known Ancillary Data Header, signal 00h, FFh, sequence. Except words, ancillary data (B0, LSB) parity B7-1. data type word (TT) used specify ancillary data type. TMC22290 compare this 7-bit value with contents ANCID control register. there match, ancillary data will processed. there match, TMC22290 ignores ancillary data. word count data (D11-0 ancillary data packet ignored. Ancillary data that matches programmed Data Type assumed bytes long. Ancillary phase data used program MSBs PHASE register. ANCPHEN determine ancillary phase data used. When ancillary data present, TMC22290 assumes LOW.
Frequency (MHz) 13.5 Mpps
Figure Sin(x)/x Response Pixel-Rate Conversion
Table ANCPHEN function
ANCPHEN Description Ignore ancillary phase data, PHASE Ignore ancillary phase data, change PHASE Load ancillary phase data into PHASE registers
Attenuation (dB)
65-3721-12
Frequency (MHz) 13.5 Mpps 27.0 Mpps
Ancillary frequency data used program 32-bits FREQ3-0 registers. ANCFREN determine ancillary frequency data used. When ancillary data present, TMC22290 assumes LOW.
Figure Sin(x)/x Response Pixel-Rate Conversion
Table ANCFREN function
ANCFREN Description Ignore ancillary frequency data Ignore ancillary frequency data Load ancillary frequency data into FREQ3-0 registers
Ancillary Data
TMC22290 designed accept words ancillary data after active video pixels each horizontal line. Ancillary data occur once line, once once eight random lines, all. TMC22290 does assume ancillary data present regular basis.
TMC22290
PRODUCT SPECIFICATION
Table Ancillary Data Sequence
Word ANC2 ANC1 ANC0 FIELD Description Ancillary Data Header (Timing Reference Signal) Data Type Word Count Field Synchronous Video Flag reserved
parity bit, reserved
FR27 FR20 FR13
PH12 FR26 FR19 FR12
PH11 FR25 FR18 FR11
PH10 FR31 FR24 FR17 FR10
FR30 FR23 FR16
FR29 FR22 FR15
FR28 FR21 FR14
Subcarrier Phase Subcarrier Frequency
Table Field Identification Subcarrier Reset Modes
ANCTREN (EAV) Field Subcarrier Reset Mode field, reset subcarrier every fields even field field, subcarrier free even field Field reset subcarrier field Field Field Field Field Field Field Field Basic Mode
Genlocking Mode
Field Sequence Mode
part timing reference code tracks
PRODUCT SPECIFICATION
TMC22290
Operating Modes
number bits (F2-0) from ancillary data packet FIELD word, used program counter depending upon state synchronous video (SVF) ANCTREN control register. basic operating mode (ANCTREN LOW), timing found EAV. F2-0 ignored encoder subcarrier synthesizer reset PHASE value every eight (when counter transitions from basic mode, ANCFREN ANCPHEN typically LOW, ignoring ancillary frequency phase data. ANCFREN ANCPHEN HIGH, TMC22290 uses incoming ancillary frequency phase data lineby-line basis. genlocking mode (ANCTREN HIGH), subcarrier synthesizer allowed free run, with phase frequency being from ancillary data packet PH12-0 FR31-0 data. counter increments just like does basic mode. Field sequence mode (ANCTREN HIGH SVF=LOW), same basic mode except that counter F2-0 bits FIELD word ancillary data. ancillary data present line, counter will continue count does basic mode. When ancillary data present, contents counter loaded with data (F2-0). this way, TMC22290 synchronized with external source sending data only once.
Parallel Microprocessor Interface
parallel microprocessor interface, active when HIGH, employs 14-line interface, with 8-bit data address bit: addresses required device programming pointer-register management. Address selects between reading/writing register addresses reading/writing register data. When writing, address presented along with during falling edge Eight bits data presented D7-0 during subsequent rising edge additional falling edge needed move input data assigned working registers. read mode, address accompanied HIGH during falling edge data output pins low-impedance state tDOZ after falls. Valid data present D7-0 tDOM after falling edge Because this port operates asynchronously with pixel timing, there uncertainty this data valid output delay PXCK period. This uncertainty does apply tDOZ.
Table Parallel Port Control
R/W\ Action Load D7-0 into Control Register pointer. Read Control Register pointer D7-0. Write D7-0 addressed Control Register. Read addressed Control Register D7-0.
tPWLCS SCL/CS SDA/R/W
tPWHCS
SA0/ADR D7-0
65-3721-13
Figure Microprocessor Parallel Port Write Timing
TMC22290
PRODUCT SPECIFICATION
tPWLCS SCL/CS SDA/R/W
tPWHCS
SA0/ADR tDOM D7-0 tDOZ
65-3721-14
tHOM
Figure Microprocessor Parallel Port Read Timing
Serial Control Port (R-Bus)
addition 14-wire parallel port, 2-wire serial control interface also provided, active when LOW. Either port alone control entire chip. four TMC22290 devices connected 2-wire serial interface with each device having unique address. 2-wire interface comprises clock (SCL/CS) bidirectional data (SDA/R/W) pin. TMC22290 acts slave receiving transmitting data over serial interface. When serial interface active, logic levels SCL/CS SDA/R/W pulled HIGH external pullup resistors. Data received transmitted SDA/R/W line must stable duration positive-going SCL/CS pulse. Data SDA/R/W must change only when SCL/CS LOW. SDA/R/W changes state while SCL/CS HIGH, serial interface interprets that action start stop sequence. There components serial operation: Start signal Slave address byte Base register address byte Data byte read write Stop signal
TMC22290 acknowledges bringing SDA/R/W SCL/CS pulse. addresses match, TMC22290 does acknowledge.
Table Serial Port Addresses
(SA1) (SA0)
Data Transfer Serial Interface
each byte data read written, sequence. TMC22290 does acknowledge master device during write sequence, SDA/R/W remains HIGH master generate stop signal. master device does acknowledge TMC22290 during read sequence, TMC22290 interprets this SDA/R/W remains HIGH master generate stop signal. Writing data control registers TMC22290 requires that 8-bit address control register interest written after slave address been established. This control register address base address subsequent write operations. base address autoincrements each byte data written after data byte intended base address. more bytes transferred than there available addresses, address will increment remain maximum value 20h. base address higher than will produce ACKnowledge signal. ACKnowledge received from master, encoder will automatically stop sending data.
When serial interface inactive (SCL/CS SDA/R/W HIGH) communications initiated sending start signal. start signal HIGH-to-LOW transition SDA/R/W while SCL/CS HIGH. This signal alerts slaved devices that data transfer sequence coming. eight bits data transferred after start signal comprise seven slave address single bit. indicates direction data transfer, read from write slave device. transmitted slave address matches address device (set state SA0/ADR input pins Table 19.),
PRODUCT SPECIFICATION
TMC22290
SDA/R/W tBUFF tSTAH SCL/CS tDAH
65-3721-15
tDHO tDAL
tDSU
tSTASU
tSTOSU
Figure Serial Port Read/Write Timing
Data read from control registers TMC22290 similar manner. Reading requires data transfer operations: base address must written with slave address byte sequential read operation. Reading (the slave address byte HIGH) begins previously established base address. address read register autoincrements after each byte transferred. terminate read/write sequence TMC22290, stop signal must sent. stop signal comprises LOW-toHIGH transition SDA/R/W while SCL/CS HIGH. repeated start signal occurs when master device driving serial interface generates start signal without generating stop signal terminate current communication. This used change mode communication (read, write) between slave master without releasing serial interface lines.
Write four consecutive control registers Start signal Slave Address byte (R/W LOW) Base Address byte Data byte base address Data byte (base address Data byte (base address Data byte (base address Stop signal
Read from control register Start signal Slave Address byte (R/W LOW) Base Address byte Stop signal Start signal Slave Address byte (R/W HIGH) Data byte from base address Stop signal
Read from four consecutive control registers Start signal Slave Address byte (R/W LOW) Base Address byte Stop signal Start signal Slave Address byte (R/W HIGH) Data byte from base address Data byte from (base address Data byte from (base address Data byte from (base address Stop signal
Serial Interface Read/Write Examples
Write control register Start signal Slave Address byte (R/W LOW) Base Address byte Data byte base address Stop signal
SDA/R/W
STOP
START
STOP START
SCL/CS
65-3721-16
Figure Serial Interface Start/Stop Signal
TMC22290
PRODUCT SPECIFICATION
SDA/R/W
SCL/CS
65-3721-17
Figure Serial Interface Typical Byte Transfer
JTAG Test Interface
JTAG test port accesses registers every digital except JTAG test port pins. Table sequence test registers. register number (Reg) indicates order which register data loaded read (Reg loaded read therefore serial path). scan path registers long. TEST pins function JTAG registers. JTAG port 4-wire interface, following IEEE Std. 1149.1-1990 Test Data Input (TDI) Test Mode Select (TMS) inputs referred rising edge Test ClocK (TCK) input. Test Data Output (TDO) referred falling edge TCK. JTAG standard been implemented into TMC22290 without UPDATE data register treats output pins there none TMC22290). CAPTURE Instruction Register implemented with force value which allows SAMPLE PRELOAD data data path. Instruction register contains bits: (TDI shift IRM; shift IRL; shift TDO) Table There states fully implemented. general, commanding state machine puts system into JTAG states. TMC22290 operated freely because there means interrupt function. There output driver related JTAG data path. While determines state, there only events that happen: Capture this state, data pins will LOADed into data scan path only equal IRL. IRL, even though state machine this state, ACTION will take place. Shift this state, data scan path transferring data from high order order bits. always operational regardless contents IRL. Capture While captures state, TMC22290 automatically loads pre-instruction register (IRMp IRLp respectively). Shift this state, shift IRMp, IRMp IRLp, IRLp TDO. Update this state, TMC22290 LOAD contents Instruction register from PRELOADED SHIFTED) execution Instruction register (double buffered.)
DATA SCAN PATH Register serial SHIFT, parallel LOAD shift register. While Shift state, TMC22290 does SHIFT. While (instruction register) state Capture state, TMC22290 does LOAD. each input (tri-state pins included, analog pins), TMC22290 multiplexer register. multiplexer inputs other shifted data from higher order scan path.
Table JTAG Sequence
RESET PXCK SA0\ADR SDA/R/W SCL/CS
Table Function
Function EXTEST, effect while shift data keeps shifting. SAMPLE PRELOAD capture state, load input pins parallel data scan path. Same SAMPLE PRELOAD BYPASS bypass
PRODUCT SPECIFICATION
TMC22290
tPWTCK
tPWTCK
tSTP
tHTP
tHOTP
tDOTP
65-3721-18
Figure JTAG Test Port Timing
Equivalent Circuits
Substrate
RREF VREF
27012A
COMPOSITE LUMA CHROMA
27013A
Figure Equivalent Analog Input Circuit
Figure Equivalent Analog Output Circuit
Digital Input
Digital Output
27011B 27014B
Figure Equivalent Digital Input Circuit
Figure Equivalent Digital Output Circuit
tENA tDIS 0.5V 2.0V 0.8V
Three-State Outputs
High Impedance 0.5V
7048F
Figure Threshold Levels Three-State Measurement
TMC22290
PRODUCT SPECIFICATION
Absolute Maximum Ratings (beyond which device damaged)1
Parameter Power Supply Voltage Digital Inputs Applied Voltage Forced current Output Applied voltage Forced current
-0.5 -0.5 -20.0 -0.5 -3.0
+7.0 VDD+0.5 +20.0 +6.0 second infinite
Unit
Short circuit duration (single output HIGH state ground) Analog Output Short circuit duration (all outputs ground) Temperature Operating, ambient junction Lead, soldering seconds) Vapor Phase soldering minute) Storage
+140 +300 +220 +150
Notes: Absolute maximum ratings limiting values applied individually while other parameters within specified operating conditions. Functional operation under these conditions implied. Performance reliability guaranteed only Operating Conditions exceeded. Applied voltage must current limited specified range. Forcing voltage must limited specified range. Current specified conventional current flowing into device.
Operating Conditions
Parameter Power Supply Voltage Input Voltage, Logic HIGH Compatible Inputs Serial Port (SDA, SCL) Input Input Voltage, Logic Compatible Inputs Serial Port (SDA, SCL) VREF IREF RREF External Reference Voltage Converter Reference Current (IREF=VREF/RREF), flowing RREF External Reference Resistor, VREF=NOM Output Current, Logic HIGH (D7-0, TDO) Output Current, Logic (D7-0, TDO) Output Current, Logic (SDA) Ambient Temperature, Still -2.0 1.235 1.57 0.3VDD .7VDD 4.75 5.25 Units
PRODUCT SPECIFICATION
TMC22290
Operating Conditions (continued)
Parameter Pixel Interface fPXL fPXCK tPWHPX tPWLPX tPWLCS tPWHCS tDAL tDAH tSTAH tSTASU tSTOSU tBUFF tDSU tDHO fTCK tPWLTCK tPWHTCK tSTP tHTP Pixel Rate Master Clock Rate, pixel rate PXCK pulse width, HIGH PXCK pulse width, PD7-0 Setup Time PD7-0 Hold Time Pulse Width, Pulse Width, HIGH Address Setup Time Address Hold Time Data Setup Time (write) Data Hold Time (write) Reset Setup Time Reset Hold Time Pulse Width, Pulse Width, HIGH Start Hold Time Setup Time (START) Setup Time (STOP) Stop Start Hold Time Data Setup Time Hold Time Test Clock (TCK) Rate Pulse Width, Pulse Width, HIGH Test Port Setup Time, TDI, Test Port Hold Time, TDI, 13.5 27.0 Mpps Units
Parallel Microprocessor Interface
Serial Microprocessor Interface
JTAG Interface
TMC22290
PRODUCT SPECIFICATION
Electrical Characteristics
Parameter IDDQ IOZH IOZL Power Supply Current1 Power Supply Current, DACs disabled2 Voltage Reference Output VREF Output Impedance Input Current, HIGH Input Current, Hi-Z Output Leakage Current, Output HIGH Hi-Z Output Leakage Current, Output Short-Circuit Current Output Voltage, HIGH Output Voltage, D7-0, TDO, D7-0, TDO, SDA, SDA, ROUT COUT Digital Input Capacitance Digital Output Capacitance Video Output Compliance Video Output Resistance Video Output Capacitance IOUT 0mA, 1MHz -0.3 Max, Max, Max, Max, Conditions Max, fPXCK 27MHz Max, fPXCK 27MHz 0.988 1.235 1000 1.482 Unit
Notes: Maximum with MIN. Outputs loaded wtih 75W. IDDQ when YCDIS COMPDIS HIGH, disabling converters.
Switching Characteristics
Parameter tDOZ tHOM tDOM tDOT
Conditions
Units
Output Delay, low-Z Output Hold Time, high-Z Output Delay, Data Valid Output Delay, Valid Output Hold Time, Valid Output Current Risetime Output Current Falltime Analog Output Delay full scale full scale
tHOT tDOV
Note: Timing reference points level. Analog CLOAD <10pF, D7-0 load <40pF.
PRODUCT SPECIFICATION
TMC22290
System Performance Characteristics
Parameter CNLP CNLG CLIM CLGI CLDI LNLD FTWD LTWD LOTWD LOTWD LDCOFF DYNG NOISE NOISE CAMN CPMN SYRF BERF PSRR Converter Resolution Differential Phase Differential Gain Chroma Nonlinear Phase Chroma Nonlinear Gain Chroma/Luma Intermodulation Chroma/Luma Gain inequality Chroma/Luma Delay inequality Luma Nonlinear Distortion Field Time Waveform Distortion Line Time Waveform Distortion Long Time Waveform Distortion, initial peak overshoot Long Time Waveform Distortion, peak overshoot Line-by-Line Offset Dynamic Gain Noise Level (Note Noise Level (Note Chroma Noise Chroma Noise Sync Pulse Rise Fall Time Burst envelope Rise Fall Time Power Supply Rejection Ratio CBYP NTC-7 100% unmod. ramp 100% unmod. ramp field field -65.4 PXCK MHz, Ramp PXCK MHz, Ramp NTC-7 Combination NTC-7 Combination NTC-7 Combination NTC-7 Composite NTC-7 Composite NTC-7 NTC-7 NTC-7 Bounce after seconds, Bounce Conditions 97.6 ±1.25 ±1.0 Units Bits degree degree %VDD
Notes: Noise Level unified weighted, bandwidth, with Tilt Null measured using VM700 "Measure Mode." Noise Level unified weighted, bandwidth, measured using VM700 "Auto Mode."
Applications Information
circuit Figure shows connection power supply voltages, output reconstruction external voltage reference. pins should connected same power source. full-scale output voltage level, VOUT, COMPOSITE, LUMA, CHROMA pins found from: VOUT IOUT IREF (VREF/RREF) where: IOUT full-scale output current sourced TMC22290 converters. resistive load COMPOSITE, CHROMA, LUMA output pins. constant TMC22290 converters (approximately equal 10.4). IREF reference current RREF ground.
TMC22290
PRODUCT SPECIFICATION
VREF voltage measured VREF pin. RREF total resistance connected between RREF ground.
Attenuation (dB)
Analog Reconstruction Filter Frequency (MHz) -120 -160 -200
24365A
reference voltage Figure from LM185 Volt band-gap reference. resistor connected from RREF ground sets overall "gain" three converters TMC22290. Varying RREF will cause full-scale output voltage COMPOSITE, LUMA, CHROMA vary ±5%. suggested output reconstruction same used TMC2063P7C Demonstration Board. phase frequency response this shown Figure
Figure Response Recommended Output Filter
1.0µH Video From Encoder 1.0µH 100µF 0.1µF 100pF 330pF 330pF 27pF Video Output Load
DIGITAL VIDEO INPUT CLOCK PD7-0 PXCK
CHROMA
TMC22290 Multi-standard Digital Video Encoder
SAO/ADR D7-0 SCL/CS SDA/R/W
LUMA COMPOSITE CBYP 0.1µF VREF RREF IM185-1.2 0.1µF
RESET
CONTROL INTERFACE
JTAG TEST INTERFACE
65-3721-20
Figure Typical Application Circuit
Phase (deg)
PRODUCT SPECIFICATION
TMC22290
Notes:
TMC22290
PRODUCT SPECIFICATION
Mechanical Dimensions Lead PLCC Package
Symbol D1/E1 D3/E3 ND/NE Inches Min. Max. Millimeters Min. Max. Notes: Notes dimensions tolerances conform ANSI Y14.5M-1982 Corner edge chamfer Dimension include mold protrusion. Allowable protrusion .101" (.25mm)
.165 .180 .090 .120 .020 .013 .021 .026 .032 .685 .695 .650 .656 .500 .050 .042 .056 .004
4.19 4.57 2.29 3.05 17.40 17.65 16.51 16.66 12.7 1.27 1.07 1.42 0.10
D3/E3
LEAD COPLANARITY
PRODUCT SPECIFICATION
TMC22290
Ordering Information
Product Number TMC22290R2C Temperature Range 70°C Screening Commercial Package 44-Lead PLCC Package Marking 22290R2C
information contained this data sheet been carefully compiled; however, shall implication otherwise become part terms conditions subsequent sale. liability shall determined solely standard terms conditions sale. representation application that circuits either licensed free from patent infringement intended implied. Raytheon reserves right change circuitry other data time without notice assumes liability errors.
LIFE SUPPORT POLICY:
products designed life support applications, wherein failure malfunction component reasonably expected result personal injury. user Raytheon components life support applications assumes risk such Raytheon Company against damages. Raytheon Electronics Semiconductor Division 5580 Morehouse Drive Diego, 92121 1000 7074 6314 applications@lj.sd.ray.com
10/95 2.0m Stock# DS70022290 Raytheon Company 1995
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