HIGHLIGHTS QuickLogic's FPGA design tools Workstations. Open inte
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QuickToolsfor Workstations Development Solution Third Party Tools
HIGHLIGHTS
QuickLogic's FPGA design tools Workstations. Open interface third party tools QuickTools Workstations supports EDIF, IEEE standard Verilog, IEEE standard VHDL netlist formats interfacing with many workstation design entry, synthesis, simulation tools including Synopsys, Synplicity, Exemplar, Mentor Graphics, Model Technology, Viewlogic, Cadence. Fast optimization, placement, routing tools allow complete even most complicated designs time. These tools will automatically place route design even 100% logic resources used! Accurate delay modeling guaranteed timing SpDE Delay Modeler (included QuickTools Workstations) incorporates state-of-the-art Asymptotic Waveform Evaluation (AWE) technique generate precise timing estimates post-layout delays. Sophisticated timing analysis with path analyzer allows view only delays which interested using spreadsheet format.
FIGURE QuickTools Workstations Design Flow
QuickTools Workstations QuickLogic's integrated FPGA development environment workstations. QuickTools Workstations includes place route static timing analysis QuickLogic FPGAs, well interfaces many popular design entry, synthesis, simulation tools including Synopsys, Synplicity, Viewlogic, Exemplar, Model Technology, Mentor Graphics, Cadence, Veribest. complete description third party tool support library availability, please section entitled "Third Party Support Overview" later this data book.
Third Party Design Entry Synthesis Tool
Tools
QuickTools
Workstations
SpDE Place Route Path Analysis
Third Party EDIF, VHDL, Verilog Simulator
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QuickTools Workstations
Design Flow QuickTools Workstations design flow shown Figure illustrated, designers enter designs using many industry standard party schematic editors synthesis environments, such Synopsys, Viewlogic, Synplicity, Exemplar, Mentor Graphics, etc. QuickTools reads EDIF netlists generated third party development tools performs logic optimization place route. After place route complete, designers full timing simulation with Verilog VHDL netlists generated from QuickTools. tools come standard with EDIF interfaces back-annotation support industry standard VHDL, Verilog, EDIF simulators. static timing analyzer, timing driven placement other features (design optimizer compiler) also available design process. Optimization Place Route with SpDE Once design been entered, QuickLogic's Seamless pASIC Design Environment (SpDETM) performs logic optimization mapping into pASIC macrocells, places routes design specified device, extracts delay information. QuickLogic's ViaLink antifuse technology provides abundance interconnect QuickLogic's FPGAs, giving designers benefits 100% automatic place route even with 100% fixed pin-outs. SpDE functions broken down into following components: Design Verifier Logic Optimization Automatic Place Route Delay Modeler Path Analyzer Programming
Product Features
detailed description each these components functions, please section entitled "QuickWorks Optimization Place Route with SpDE" earlier this data book.
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