HIGHLIGHTS Schematic Editor provides hierarchical design environm

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HIGHLIGHTS Schematic Editor provides hierarchical design environm

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QuickWorks® Toolkit Complete Design Entry Simulation Solution
HIGHLIGHTS
Schematic Editor provides hierarchical design environment, allowing HDLs mixed with schematic blocks level design hierarchy. Integrated Synthesis Verilog VHDL delivers results comparable with schematic entry. Architecture specific logic optimization algorithms produce optimal area speed results. 100% Automatic Place Route even with 100% utilization 100% fixed pin-outs. Silos Verilog Simulator both functional gate level timing simulation. Entry display either textual graphic waveform. Productivity Focus extends editor which includes context sensitive templates automatic color coding. Interactive Cross-Probing Clicking nets schematic editor highlights corresponding physical viewer (and vice-versa!), path analyzer highlights paths schematic editor. QuickLogic's QuickWorks offers comprehensive easy development toolset QuickLogic Field Programmable Gate Arrays (FPGAs), allowing designers quickly efficiently realize their ideas silicon. QuickWorks QuickLogic's complete design entry, synthesis, place route, simulation package Windows based platforms. QuickWorks includes variety design entry, synthesis, simulation features, including: Schematic Capture Context Sensitive Entry VHDL Synthesis Verilog Synthesis Timing Driven Place Route Timing Analysis Verilog Simulation Waveform Simulation Interfaces Third Party Tools Support Windows
Tools
QuickWorks
FIGURE QuickWorks Design Flow
QuickWorks
Verilog VHDL
Sensitive Editor
Schematic
Schematic Capture
Mixed Entry
Synthesis
SpDE Place Route Analysis
Silos Simulator
Design Flow
illustrated QuickWorks design flow diagram, designers combination schematic, and/or Verilog VHDL using Synario Capture System design entry tool. Symbols within schematic editor reference VHDL Verilog files allowing mixture schematic design design. designer then simulate functionally (zero-delay) route design, then simulate with full timing information. static timing analyzer, timing driven placement other features (design optimizer compiler) also available design process. Schematic Capture Waveform Editor from Synario Design Automation easyto-use Windows schematic capture utility. robust schematic editor provides hierarchical design environment allows intermixing schematics. wide range macrofunction libraries available user, including QuickLogic optimized counters, adders, accumulators, muxes, multipliers, registers, latches. Mixed mode entry (schematic and/or Verilog/VHDL) supported, providing variety entry methods. addition, updated Waveform Editor included graphical simulation waveform entry, will export Verilog test-fixtures simulation.
Product Features
QuickWorks
Integrated VHDL Verilog Synthesis Taking only seconds run, Synplify-LiteTM, revolutionary synthesis package (from Synplicity) provides results comparable with schematic entry both performance silicon area Verilog VHDL. supports complete IEEE 1176 VHDL standard IEEE standard 1364-1995 Verilog. synthesis engine provides optimal mapping QuickLogic FPGAs, including pASIC pASIC pASIC device families. Quality results algorithms tailored QuickLogic guarantee better performance density implementations than other vendors Ease-of-Use vendor specific directives required, just IEEEcompliant Verilog VHDL. Speed fastest time synthesizer market 25,000 gate design minutes
Context-Sensitive Text Entry TurboWritereditor offers host features from emulation variety familiar text editors context sensitive color coded entry. Common editors such Epsilon, others emulated. Context sensitive editing provides variety synthesis templates language constructs, keyword-based template entry syntax generation. Automatic color coding aids readability syntax verification. addition, automatic generation test-benches speeds Verilog VHDL simulation. Optimization Place Route with SpDE Once design been synthesized, QuickLogic's Seamless pASIC Design Environment (SpDETM) performs logic optimization mapping into pASIC macrocells, places routes design specified device, calculates delay information. QuickLogic's ViaLink antifuse technology provides abundance interconnect QuickLogic's FPGAs, giving designers benefits 100% automatic place route even with 100% fixed pin-outs. SpDE functions broken down into following components Design Verifier Logic Optimization Automatic Place Route Delay Modeler Path Analyzer Programming
Tools
QuickWorks
Design Verifier carefully analyzes each netlist read into SpDE. design issues problems that detected reported user. Design Verifier detects improperly wired designs, high fanout problems, unused logic, improper placement, many other possible design problems. schematic design entry being used, then simply clicking Design Verifier's error message will highlight appropriate portion schematic design. Logic Optimizer examines logic design determine best logic into QuickLogic logic cells. Level Optimizer, also known Technology Mapper, provides most area-efficient optimization possible. However, more predictable optimization algorithm that will leave nets design intact, Level Optimizer (the Packer) chosen. Level Optimizer will automatically, optimally insert buffers high fanout paths increase performance. Placer uses internally optimized algorithms arrange locations logic cells pins device maximum performance. Alternatively, user placement pins logic cells design description desired. Placer also Timing-Driven mode order meet timing constraints entered Path Analyzer. Router fully automatic tool. QuickLogic architecture combines ample routing resources, simple routing structure, very fast interconnect element. This combination makes automatic routing design possible even when 100% logic cells pads used. Router completes successfully even designs with pins fixed early design process. Delay Modeler calculates delays throughout device after placement routing complete. Delay Modeler achieves accuracy SPICE orders magnitude less time with modern analysis technique called (Asymptotic Waveform Evaluation). Delay Modeler uses results sequencing algorithm that determines which ViaLinks will programmed what order. These accurate, guaranteed delays used Path Analyzer, when creating timing netlist simulation.
QuickWorks
Path Analyzer uses results from Delay Modeler list static path delays throughout chip. user select groups paths (e.g., register register) specific paths viewing. path delays appear spreadsheet format Path Analyzer window, allowing simple analysis. Figure demonstrates double-clicking delay path Path Analyzer highlights path Physical Viewer schematic entry tool. Delays also graphed with Path Analyzer's graphing tool copied clipboard other applications. path delays meet timing constraints, then user specify delay required; SpDE will re-run place route tools meet timing constraint. Physical Viewer shows user automatic place route tools have mapped logic design into device's resources. manual editor, analysis tool. designer inspect results optimization, placement, routing using Path Analyzer highlighting features within SpDE. FIGURE Interactive debugging using Path Analyzer with Hierarchy Navigator
Double-Clicking path Path Analyzer will highlight path Hierarchy Navigator well SpDE
Tools
QuickWorks
Silos® Verilog Simulator Silos provides Verilog simulation power demanded designers. Rated simulators industry leading magazine, this IEEE standard 1364-1995 compliant simulator both fast easy-touse. Silos supports graphical waveform entry well Verilog test benches. Designers have previously used QuickLogic's Waveform Editor enter stimulus same files Verilog simulation. Users also cross-probe nodes between waveform display their original mixed mode HDL-schematic design. Programming Once design cycle complete, QuickLogic pASIC device programmed QuickLogic's DeskFab Programmer. DeskFab Programmer capable programming QuickLogic devices package configuration. addition, DeskFab Programmer supports "gang programming" mode, where eight programmers daisy-chained together with included serial cables. Gang programming allows devices programmed same time.

HIGHLIGHTS Schematic Editor provides hierarchical design environm

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